Update .gitlab-ci.yml

48c57e9d · Konstantinos Blantos · 7084de1d · 48c57e9d
Commit 48c57e9d authored Feb 14, 2022 by Konstantinos Blantos
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.gitlab-ci.yml .gitlab-ci.yml +39 -39

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--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,52 +2,52 @@ variables:
        GIT_SUBMODULE_STRATEGY: normal

 stages:
- - sim
-# - syn
+# - sim
+ - syn

-job_scb_top_sim:
-    stage: sim
-    tags:
-     - modelsim_10.2a
-    script:
-     - /entrypoint.sh
-     - source ~/setup_modelsim.sh
-     - git submodule sync & git submodule update --init
-     - apt-get install -y python
-     - cd top/bare_top
-     - python gen_sdbsyn.py --project wr_switch
-     - cd ../../
-     - cd sim
-     - ln -s ../ip_cores/wr-cores/sim wr-hdl
-     - cd ../testbench/scb_top
-     - cp /opt/compiled_libs_ise14.7/modelsim.ini .
-     - hdlmake makefile
-     - make
-     - vsim -c -do run.do
-
-#job_scb_top_8p_syn:
-#    stage: syn
+#job_scb_top_sim:
+#    stage: sim
 #    tags:
-#     - xilinx_ISE_14.7 
+#     - modelsim_10.2a
 #    script:
 #     - /entrypoint.sh
-#     - source ~/setup_ise147.sh
-#     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+#     - source ~/setup_modelsim.sh
+#     - git submodule sync & git submodule update --init
+#     - apt-get install -y python
 #     - cd top/bare_top
 #     - python gen_sdbsyn.py --project wr_switch
-#     - cat synthesis_descriptor.vhd
-#     - cd ../../syn/scb_8ports 
-#     - hdlmake makefile 
+#     - cd ../../
+#     - cd sim
+#     - ln -s ../ip_cores/wr-cores/sim wr-hdl
+#     - cd ../testbench/scb_top
+#     - cp /opt/compiled_libs_ise14.7/modelsim.ini .
+#     - hdlmake makefile
 #     - make
-#    artifacts:
-#     name: SCB_TOP_8P_CI_$CI_JOB_ID
-#     paths:
-#     - syn/scb_8ports/*.syr
-#     - syn/scb_8ports/*.mrp
-#     - syn/scb_8ports/*.bit
-#     - syn/scb_8ports/*.bin
-#     - syn/scb_8ports/*.par
-#     - syn/scb_8ports/*.twr
+#     - vsim -c -do run.do
+
+job_scb_top_8p_syn:
+    stage: syn
+    tags:
+     - xilinx_ISE_14.7 
+    script:
+     - /entrypoint.sh
+     - source ~/setup_ise147.sh
+     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+     - cd top/bare_top
+     - python gen_sdbsyn.py --project wr_switch
+     - cat synthesis_descriptor.vhd
+     - cd ../../syn/scb_8ports 
+     - hdlmake makefile 
+     - make
+    artifacts:
+     name: SCB_TOP_8P_CI_$CI_JOB_ID
+     paths:
+     - syn/scb_8ports/*.syr
+     - syn/scb_8ports/*.mrp
+     - syn/scb_8ports/*.bit
+     - syn/scb_8ports/*.bin
+     - syn/scb_8ports/*.par
+     - syn/scb_8ports/*.twr

 #job_scb_top_18p_syn:
 #    stage: syn