Commit 1fa7b8a2 authored by Konstantinos Blantos's avatar Konstantinos Blantos

Update .gitlab-ci.yml

parent 23e440ec
......@@ -15,13 +15,14 @@ stages:
# - source ~/setup_modelsim.sh
# - cd testbench/scb_top_8p; hdlmake makefile; make clean; make
job_scb_top_8p_sim:
job_scb_top_sim:
stage: sim
tags:
- modelsim_10.2a
script:
- /entrypoint.sh
- source ~/setup_modelsim.sh
- git submodute init & git submodule update
- apt-get install -y python
- cd top/bare_top
- python gen_sdbsyn.py --project wr_switch
......@@ -29,7 +30,7 @@ job_scb_top_8p_sim:
- cd ../../
- cd sim
- ln -s ../ip_cores/wr-cores/sim wr-hdl
- cd ../testbench/scb_top_8p
- cd ../testbench/scb_top
- cp /opt/compiled_libs_ise14.7/modelsim.ini .
- hdlmake makefile
- cat Makefile
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment