diff --git a/modules/wrsw_rtu/rtu_port_new.vhd b/modules/wrsw_rtu/rtu_port_new.vhd
index 172236845f564cd321fb99762e46c6f4921dabd7..2d738e24f70d7a14adfc0b01f611ad05fae4adbf 100644
--- a/modules/wrsw_rtu/rtu_port_new.vhd
+++ b/modules/wrsw_rtu/rtu_port_new.vhd
@@ -187,7 +187,9 @@ architecture behavioral of rtu_port_new is
signal aboard_possible : std_logic;
-- VHDL -- lovn' it
signal zeros : std_logic_vector(47 downto 0);
-
+ signal dbg_force_fast_match_only : std_logic;
+ signal dbg_force_full_match_only : std_logic;
+
constant c_match_zero: t_match_response := (
valid => '0',
port_mask => (others =>'0'),
@@ -211,11 +213,21 @@ architecture behavioral of rtu_port_new is
drop => '1',
hp => '0');
+ constant c_match_override: t_match_response := (
+ valid => '1',
+ port_mask => (others =>'1'),
+ prio => (others =>'0'),
+ drop => '0',
+ nf => '0',
+ ff => '0',
+ hp => '0');
+
begin
- zeros <= (others => '0');
-
+ zeros <= (others => '0');
+ dbg_force_fast_match_only <= '1' when (rtu_str_config_i.dbg_force_fast_match_only = '1') else '0';
+ dbg_force_full_match_only <= '1' when (rtu_str_config_i.dbg_force_full_match_only = '1') else '0';
-- port_pcr_pass_bpdu <= rtu_pcr_pass_bpdu_i(g_port_index);
-- port_pcr_pass_all <= rtu_pcr_pass_all_i(g_port_index);
@@ -485,11 +497,14 @@ begin
if(fast_match_rd_valid = '1' and fast_match_wr_req_d = '1') then
-- response the current fast_match request, registered
-- fast_match <= fast_match_rd_data_i;
- if(fast_match_rd_data_i.nf = '1' or -- non-forward (link-limited) e.g.: BPDU
- fast_match_rd_data_i.ff = '1' or -- fast forward recongized
- fast_match_rd_data_i.drop = '1' or -- no point in further work (drop due to VLAN)
- full_match_aboard = '1') then -- aboard because next frame received
- -- if we recognizd special traffic or aboard request , we don't need full match
+ if(dbg_force_fast_match_only = '1') then
+ port_state <= S_FINAL_MASK;
+ elsif((dbg_force_full_match_only = '0' and
+ (fast_match_rd_data_i.nf = '1' or -- non-forward (link-limited) e.g.: BPDU
+ fast_match_rd_data_i.ff = '1' or -- fast forward recongized
+ fast_match_rd_data_i.drop = '1')) or -- no point in further work (drop due to VLAN)
+ full_match_aboard = '1') then -- aboard because next frame received
+ -- if we recognizd special traffic or aboard request , we don't need full match
port_state <= S_FINAL_MASK;
else
-- go for full match (can be abanoned any time)
@@ -640,9 +655,13 @@ begin
-- fast_and_full_mask <= fast_match.port_mask and full_match.port_mask;
-- forming final mask:
+ -- d) for debugging: forcing to have only fast match
+ forwarding_mask <= fast_match.port_mask when (dbg_force_fast_match_only = '1') else
+ -- d) for debugging: forcing to have only full match
+ full_match.port_mask when (dbg_force_full_match_only = '1') else
-- 1) full match available, full match says that we have non-forward traffic<
-- to such traffic we don't apply fast_match (TRU and stuff)
- forwarding_mask <= full_match.port_mask when (full_match.valid = '1' and full_match.nf ='1') else
+ full_match.port_mask when (full_match.valid = '1' and full_match.nf ='1') else
-- 2) full match available and it's normal traffic, so we apply both asks
fast_and_full_mask when (full_match.valid = '1') else
-- 3) we received aboard request and the setting indicates to drop ingressf rame in such case
@@ -651,22 +670,34 @@ begin
fast_match.port_mask;
-- forming final drop:
+ -- d) for debugging: forcing to have only fast match
+ drop <= fast_match.drop when (dbg_force_fast_match_only = '1') else
+ -- d) for debugging: forcing to have only full match
+ full_match.drop when (dbg_force_full_match_only = '1') else
-- 1) drop from one of two matches, don't drop if we have non-forward traffic
- drop <= (full_match.drop or fast_match.drop) and (not full_match.nf) when (full_match.valid = '1') else
+ (full_match.drop or fast_match.drop) and (not full_match.nf) when (full_match.valid = '1') else
-- 2) when aboarding and set to drop,
'1' when (full_match_aboard_d = '1' and rtu_str_config_i.dop_on_fmatch_full = '0' ) else
-- 3) if only fast match available, is it
fast_match.drop;
-- forming final prio:
+ -- d) for debugging: forcing to have only fast match
+ prio <= fast_match.prio when (dbg_force_fast_match_only = '1') else
+ -- d) for debugging: forcing to have only full match
+ full_match.prio when (dbg_force_full_match_only = '1') else
-- 1) when full match available, use it
- prio <= full_match.prio when (full_match.valid = '1') else
+ full_match.prio when (full_match.valid = '1') else
-- 2) if aboard and set to drop, set it to zero
c_rtu_rsp_drop.prio when (full_match_aboard_d = '1' and rtu_str_config_i.dop_on_fmatch_full = '0' ) else
fast_match.prio;
-- forming final hp: decided by fast match, only
- hp <= fast_match.hp;
+ hp <= fast_match.hp when (dbg_force_fast_match_only = '1') else
+ full_match.hp when (dbg_force_full_match_only = '1') else
+ fast_match.hp;
- nf <= fast_match.nf;
+ nf <= fast_match.nf when (dbg_force_fast_match_only = '1') else
+ full_match.nf when (dbg_force_full_match_only = '1') else
+ fast_match.nf;
-- to make sure that HP traffic is not disturbed due to the fact that it's fowarded to slow NIC... just not
-- foward it there... (NIC should have it's own mechanism to prevent such situation, but precautions are not bad).
diff --git a/modules/wrsw_rtu/rtu_private_pkg.vhd b/modules/wrsw_rtu/rtu_private_pkg.vhd
index 7a46d070984e97ffb90ab7435589ba85da92ac64..9a92a968932828c715849267551820a1aac9b1a4 100644
--- a/modules/wrsw_rtu/rtu_private_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_private_pkg.vhd
@@ -152,7 +152,8 @@ package rtu_private_pkg is
mirror_port_src_tx : std_logic_vector(c_rtu_max_ports-1 downto 0);
mirror_port_src_rx : std_logic_vector(c_rtu_max_ports-1 downto 0);
mirror_port_dst : std_logic_vector(c_rtu_max_ports-1 downto 0);
-
+ dbg_force_fast_match_only : std_logic;
+ dbg_force_full_match_only : std_logic;
end record;
type t_match_response is record
valid : std_logic; -- entry valid
diff --git a/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd b/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
index c0618d966411a404be65599d27b7a55a93f97193..dd07dad7a87bd3b0aec7f304e3aa11f3f424835d 100644
--- a/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : rtu_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from rtu_wishbone_slave_new.wb
--- Created : Wed Mar 27 11:21:26 2013
+-- Created : Mon Aug 5 16:03:51 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave_new.wb
@@ -119,6 +119,8 @@ package rtu_wbgen2_pkg is
rx_ctr_hp_fw_cpu_ena_o : std_logic;
rx_ctr_urec_fw_cpu_ena_o : std_logic;
rx_ctr_learn_dst_ena_o : std_logic;
+ rx_ctr_force_fast_match_ena_o : std_logic;
+ rx_ctr_force_full_match_ena_o : std_logic;
rx_ff_mac_r0_lo_o : std_logic_vector(31 downto 0);
rx_ff_mac_r1_hi_id_o : std_logic_vector(15 downto 0);
rx_ff_mac_r1_hi_id_load_o : std_logic;
@@ -176,6 +178,8 @@ package rtu_wbgen2_pkg is
rx_ctr_hp_fw_cpu_ena_o => '0',
rx_ctr_urec_fw_cpu_ena_o => '0',
rx_ctr_learn_dst_ena_o => '0',
+ rx_ctr_force_fast_match_ena_o => '0',
+ rx_ctr_force_full_match_ena_o => '0',
rx_ff_mac_r0_lo_o => (others => '0'),
rx_ff_mac_r1_hi_id_o => (others => '0'),
rx_ff_mac_r1_hi_id_load_o => '0',
diff --git a/modules/wrsw_rtu/rtu_wishbone_slave.vhd b/modules/wrsw_rtu/rtu_wishbone_slave.vhd
index 0dc8b8015f407fabc142a87f3a42154a0f0cbde5..f1b3dd1d57f19d91051257cf688bff5c602abc6e 100644
--- a/modules/wrsw_rtu/rtu_wishbone_slave.vhd
+++ b/modules/wrsw_rtu/rtu_wishbone_slave.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : rtu_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from rtu_wishbone_slave_new.wb
--- Created : Wed Mar 27 11:21:26 2013
+-- Created : Mon Aug 5 16:03:51 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave_new.wb
@@ -99,6 +99,8 @@ signal rtu_rx_ctr_prio_mask_int : std_logic_vector(7 downto 0);
signal rtu_rx_ctr_hp_fw_cpu_ena_int : std_logic ;
signal rtu_rx_ctr_urec_fw_cpu_ena_int : std_logic ;
signal rtu_rx_ctr_learn_dst_ena_int : std_logic ;
+signal rtu_rx_ctr_force_fast_match_ena_int : std_logic ;
+signal rtu_rx_ctr_force_full_match_ena_int : std_logic ;
signal rtu_rx_ff_mac_r0_lo_int : std_logic_vector(31 downto 0);
signal rtu_rx_ff_mac_r1_type_int : std_logic ;
signal rtu_rx_ff_mac_r1_valid_int : std_logic ;
@@ -185,6 +187,8 @@ begin
rtu_rx_ctr_hp_fw_cpu_ena_int <= '0';
rtu_rx_ctr_urec_fw_cpu_ena_int <= '0';
rtu_rx_ctr_learn_dst_ena_int <= '0';
+ rtu_rx_ctr_force_fast_match_ena_int <= '0';
+ rtu_rx_ctr_force_full_match_ena_int <= '0';
rtu_rx_ff_mac_r0_lo_int <= "00000000000000000000000000000000";
regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
regs_o.rx_ff_mac_r1_id_load_o <= '0';
@@ -387,6 +391,8 @@ begin
rtu_rx_ctr_hp_fw_cpu_ena_int <= wrdata_reg(16);
rtu_rx_ctr_urec_fw_cpu_ena_int <= wrdata_reg(17);
rtu_rx_ctr_learn_dst_ena_int <= wrdata_reg(18);
+ rtu_rx_ctr_force_fast_match_ena_int <= wrdata_reg(24);
+ rtu_rx_ctr_force_full_match_ena_int <= wrdata_reg(25);
end if;
rddata_reg(0) <= rtu_rx_ctr_ff_mac_br_int;
rddata_reg(1) <= rtu_rx_ctr_ff_mac_range_int;
@@ -399,14 +405,14 @@ begin
rddata_reg(16) <= rtu_rx_ctr_hp_fw_cpu_ena_int;
rddata_reg(17) <= rtu_rx_ctr_urec_fw_cpu_ena_int;
rddata_reg(18) <= rtu_rx_ctr_learn_dst_ena_int;
+ rddata_reg(24) <= rtu_rx_ctr_force_fast_match_ena_int;
+ rddata_reg(25) <= rtu_rx_ctr_force_full_match_ena_int;
rddata_reg(7) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
@@ -1081,6 +1087,10 @@ begin
regs_o.rx_ctr_urec_fw_cpu_ena_o <= rtu_rx_ctr_urec_fw_cpu_ena_int;
-- Learn Destination MAC enable
regs_o.rx_ctr_learn_dst_ena_o <= rtu_rx_ctr_learn_dst_ena_int;
+-- DBG: Force Fast Match only
+ regs_o.rx_ctr_force_fast_match_ena_o <= rtu_rx_ctr_force_fast_match_ena_int;
+-- DBG: Force Full Match only
+ regs_o.rx_ctr_force_full_match_ena_o <= rtu_rx_ctr_force_full_match_ena_int;
-- Fast Forward MAC
regs_o.rx_ff_mac_r0_lo_o <= rtu_rx_ff_mac_r0_lo_int;
-- Fast Forward MAC
diff --git a/modules/wrsw_rtu/rtu_wishbone_slave_new.wb b/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
index c6849026f92ca01a78ce84c36c336383fcc31f6a..3aa860b759f306f973e0a2f3720111ba31e9f311 100644
--- a/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
+++ b/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
@@ -517,6 +517,27 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
+ field {
+ name = "DBG: Force Fast Match only";
+ description = "Forces RTU to use only Fast Match for forwarding decisions (useful for debugging).\
+ 0: Disabled [default]\
+ 1: Enabled (use when you know what you are doing, not in normal operation)";
+ prefix = "FORCE_FAST_MATCH_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ align = 8;
+ };
+ field {
+ name = "DBG: Force Full Match only";
+ description = "Forces RTU to use only Full Match for forwarding decisions (useful for debugging).\
+ 0: Disabled [default]\
+ 1: Enabled (use when you know what you are doing, not in normal operation)";
+ prefix = "FORCE_FULL_MATCH_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
};
reg {
prefix = "RX_FF_MAC_R0";
diff --git a/modules/wrsw_rtu/xwrsw_rtu_new.vhd b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
index bc219540ed8eb1c999ea7f115c9ee8a3573c8156..2c3212c33440b9d34d6c69d12c703dd0f718d5cd 100644
--- a/modules/wrsw_rtu/xwrsw_rtu_new.vhd
+++ b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
@@ -732,6 +732,8 @@ begin
rtu_special_traffic_config.hp_fw_cpu_ena <= regs_fromwb.rx_ctr_hp_fw_cpu_ena_o;
rtu_special_traffic_config.unrec_fw_cpu_ena <= regs_fromwb.rx_ctr_urec_fw_cpu_ena_o;
regs_towb.cpu_port_mask_i <= cpu_port_mask;
+ rtu_special_traffic_config.dbg_force_fast_match_only <= regs_fromwb.rx_ctr_force_fast_match_ena_o;
+ rtu_special_traffic_config.dbg_force_full_match_only <= regs_fromwb.rx_ctr_force_full_match_ena_o;
--------------------------------------------------------------------------------------------
--| VLAN memories
--| * one used by Full Match
diff --git a/sim/regs/rtu_regs.vh b/sim/regs/rtu_regs.vh
index 50c3a04acf66792206bff9eb6fa0bcdf5803a569..c47c3b5d4879e83b5532b56d6adf3d06de6e7c75 100644
--- a/sim/regs/rtu_regs.vh
+++ b/sim/regs/rtu_regs.vh
@@ -64,6 +64,12 @@
`define RTU_RX_CTR_HP_FW_CPU_ENA 32'h00010000
`define RTU_RX_CTR_UREC_FW_CPU_ENA_OFFSET 17
`define RTU_RX_CTR_UREC_FW_CPU_ENA 32'h00020000
+`define RTU_RX_CTR_LEARN_DST_ENA_OFFSET 18
+`define RTU_RX_CTR_LEARN_DST_ENA 32'h00040000
+`define RTU_RX_CTR_FORCE_FAST_MATCH_ENA_OFFSET 24
+`define RTU_RX_CTR_FORCE_FAST_MATCH_ENA 32'h01000000
+`define RTU_RX_CTR_FORCE_FULL_MATCH_ENA_OFFSET 25
+`define RTU_RX_CTR_FORCE_FULL_MATCH_ENA 32'h02000000
`define ADDR_RTU_RX_FF_MAC_R0 11'h18
`define RTU_RX_FF_MAC_R0_LO_OFFSET 0
`define RTU_RX_FF_MAC_R0_LO 32'hffffffff
diff --git a/sim/simdrv_rtu.sv b/sim/simdrv_rtu.sv
index dbd6502f018e401fad44050fc51d8d533e8f9e8e..66ef0fa2c34a5f905e3ef79d08f226444dc49ecd 100644
--- a/sim/simdrv_rtu.sv
+++ b/sim/simdrv_rtu.sv
@@ -67,6 +67,7 @@ class CRTUSimDriver;
extern task rx_forward_on_fmatch_full();
extern task rx_drop_on_fmatch_full();
extern task rx_feature_ctrl(bit mr, bit mac_ptp, bit mac_ll, bit mac_single, bit mac_range, bit mac_br);
+ extern task rx_feature_dbg(bit f_fast_match, bit f_full_match);
extern task rx_fw_to_CPU(bit hp, bit unrec);
// extern task run();
extern protected task htab_write(int hash, int bucket, rtu_filtering_entry_t ent);
@@ -505,17 +506,8 @@ endtask // CRTUSimDriver
task CRTUSimDriver::rx_feature_ctrl(bit mr, bit mac_ptp, bit mac_ll, bit mac_single, bit mac_range, bit mac_br);
uint64_t mask;
bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
-// $display("RTU eXtension features debugging: 1: read mask: 0x%x",mask);
-// mask = !(`RTU_RX_CTR_MR_ENA |
-// `RTU_RX_CTR_FF_MAC_PTP |
-// `RTU_RX_CTR_FF_MAC_LL |
-// `RTU_RX_CTR_FF_MAC_SINGLE |
-// `RTU_RX_CTR_FF_MAC_RANGE |
-// `RTU_RX_CTR_FF_MAC_BR |
-// 32'h00000000) &
-// mask;
+
mask = 'hFFFFFFC0 & mask;
- /*$display("RTU eXtension features debugging: 2: cleared mask: 0x%x",mask);*/
mask =(((mr << `RTU_RX_CTR_MR_ENA_OFFSET) & `RTU_RX_CTR_MR_ENA) |
((mac_ptp << `RTU_RX_CTR_FF_MAC_PTP_OFFSET) & `RTU_RX_CTR_FF_MAC_PTP) |
((mac_ll << `RTU_RX_CTR_FF_MAC_LL_OFFSET) & `RTU_RX_CTR_FF_MAC_LL) |
@@ -523,7 +515,6 @@ task CRTUSimDriver::rx_feature_ctrl(bit mr, bit mac_ptp, bit mac_ll, bit mac_sin
((mac_range << `RTU_RX_CTR_FF_MAC_RANGE_OFFSET) & `RTU_RX_CTR_FF_MAC_RANGE) |
((mac_br << `RTU_RX_CTR_FF_MAC_BR_OFFSET) & `RTU_RX_CTR_FF_MAC_BR) ) |
mask;
-// $display("RTU eXtension features debugging: 1: written mask: 0x%x",mask);
bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
$display("RTU eXtension features:");
if(mr ) $display("\t Port Mirroring - enabled");
@@ -541,6 +532,35 @@ task CRTUSimDriver::rx_feature_ctrl(bit mr, bit mac_ptp, bit mac_ll, bit mac_sin
endtask // CRTUSimDriver
+task CRTUSimDriver::rx_feature_dbg(bit f_fast_match, bit f_full_match);
+ uint64_t mask = 0;
+ bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
+
+ if(f_fast_match & f_full_match)
+ begin
+ $display("RTU eXtension debugging features: FAILED (you want to sent all, cannot do that, use one feature at at time)");
+ return;
+ end
+ if(f_fast_match)
+ begin
+ mask = `RTU_RX_CTR_FORCE_FAST_MATCH_ENA | mask;
+ $display("RTU eXtension debugging features: set fast match only");
+ end
+ else if(f_full_match)
+ begin
+ mask = `RTU_RX_CTR_FORCE_FULL_MATCH_ENA | mask;
+ $display("RTU eXtension debugging features: set full match only");
+ end
+ else
+ begin
+ $display("RTU eXtension debugging features: FAILED (nothing to set)");
+ return;
+ end
+
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
+
+endtask
+
task CRTUSimDriver::rx_fw_to_CPU(bit hp, bit unrec);
uint64_t mask;
bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
diff --git a/testbench/scb_top/main.sv b/testbench/scb_top/main.sv
index 1d26ef1015a5932cdb269e2c4d89fb37085ba1a4..b0fa467ea4dbc32153f50abde624abed3fe68e97 100644
--- a/testbench/scb_top/main.sv
+++ b/testbench/scb_top/main.sv
@@ -124,6 +124,8 @@ module main;
bit mac_br = 0;
bit hp_fw_cpu = 0;
bit unrec_fw_cpu = 0;
+ bit rtu_dbg_f_fast_match = 0;
+ bit rtu_dbg_f_full_match = 0;
// vlans
// int prio_map[8] = '{7, // Class of Service masked into prioTag 0
@@ -1714,7 +1716,7 @@ module main;
*
* see the place where confgi si done (grep for "tru_config_opt == 8")
**/
-///*
+/*
initial begin
g_min_pck_gap = 50; // cycles
g_max_pck_gap = 50; // cycles
@@ -1752,7 +1754,7 @@ module main;
mc.logic2(26, 4, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
end
-//*/
+*/
/** *************************** test scenario 56 (problematic- ToDo) ************************** **/
/*
* LACP test: - trying different way of solving the problem of forwarding frames back
@@ -1797,6 +1799,26 @@ module main;
mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
end
*/
+ /** *************************** test scenario 57 ************************************* **/
+ /*
+ * testing simple RTU forwarding and stuff
+ **/
+ ///*
+ initial begin
+ portUnderTest = 18'b010101010101010101;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 700;
+ g_min_pck_gap = 100; // cycles
+ g_max_pck_gap = 100; // cycles
+ mac_single = 1;
+
+ // tx ,rx ,opt
+ rtu_dbg_f_fast_match = 0;
+ rtu_dbg_f_full_match = 1;
+ end
+ //*/
//////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////
@@ -2690,6 +2712,7 @@ module main;
rtu.rx_drop_on_fmatch_full();
rtu.rx_feature_ctrl(mr, mac_ptp , mac_ll, mac_single, mac_range, mac_br);
rtu.rx_fw_to_CPU(hp_fw_cpu,unrec_fw_cpu);
+ rtu.rx_feature_dbg(rtu_dbg_f_fast_match, rtu_dbg_f_full_match);
////////////////////////////////////////////////////////////////////////////////////////