diff --git a/modules/wrsw_rtu/rtu_port_new.vhd b/modules/wrsw_rtu/rtu_port_new.vhd
index f500bd8cadc33801bcdd2aed0c6c5308c1500407..5de327e653b46f293bf90100c7e51eb6306bc60c 100644
--- a/modules/wrsw_rtu/rtu_port_new.vhd
+++ b/modules/wrsw_rtu/rtu_port_new.vhd
@@ -627,8 +627,13 @@ begin
-- we concatenate separately Switch's ports (g_num_ports-1 downto 0) and the rest (NIC) so that
-- frames go to NIC based on any of the decisions (fast or full match)
- fast_and_full_mask <= (fast_match.port_mask(c_RTU_MAX_PORTS-1 downto g_num_ports) or full_match.port_mask(c_RTU_MAX_PORTS-1 downto g_num_ports)) &
- (fast_match.port_mask(g_num_ports-1 downto 0) and full_match.port_mask(g_num_ports-1 downto 0));
+-- fast_and_full_mask <= (fast_match.port_mask(c_RTU_MAX_PORTS-1 downto g_num_ports) or full_match.port_mask(c_RTU_MAX_PORTS-1 downto g_num_ports)) &
+-- (fast_match.port_mask(g_num_ports-1 downto 0) and full_match.port_mask(g_num_ports-1 downto 0));
+
+ -- TODO: HACK: FUCK
+ -- stupid temporary hack, the problem is that FAST MATCH does not read (for some reason) masks of VIDs different then 0...
+ -- this is only for the latency tests, later needs to be changee
+ fast_and_full_mask <= full_match.port_mask;
-- the above solution migh not be the best - eventually, we don't really want so much traffic
-- to go to NIC...(this is mainly to prevent the "unrecognized" traffic to be forwarded to NIC)
diff --git a/modules/wrsw_rtu/xwrsw_rtu_new.vhd b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
index 9936bf59d100262062e226f10e4f106e03a8e0ad..bc219540ed8eb1c999ea7f115c9ee8a3573c8156 100644
--- a/modules/wrsw_rtu/xwrsw_rtu_new.vhd
+++ b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
@@ -663,7 +663,7 @@ begin
regs_towb.rx_ff_mac_r1_id_i <= std_logic_vector(to_unsigned(c_ff_single_macs_number, 8));
regs_towb.rx_ff_mac_r1_hi_id_i <= std_logic_vector(to_unsigned(c_ff_range_macs_number, 16));
- regs_towb.gcr_rtu_version_i <= x"7";
+ regs_towb.gcr_rtu_version_i <= x"8";
-- RTU Extension index-access configration regiters for Fast Forward MACs
p_rx_registers : process(clk_sys_i)
diff --git a/sim/simdrv_rtu.sv b/sim/simdrv_rtu.sv
index c2523a5790ca6c4c4676a30701e2e6866cc7085e..dbd6502f018e401fad44050fc51d8d533e8f9e8e 100644
--- a/sim/simdrv_rtu.sv
+++ b/sim/simdrv_rtu.sv
@@ -54,7 +54,7 @@ class CRTUSimDriver;
extern task set_bus(CBusAccessor _bus, int _base_addr);
extern task add_hash_entry(rtu_filtering_entry_t ent);
extern task set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en, bit dbg = 0);
- extern task add_static_rule(bit[7:0] dmac[], bit[31:0] dpm);
+ extern task add_static_rule(bit[7:0] dmac[], bit[31:0] dpm, bit[7:0] fid=0);
extern task add_vlan_entry(int vlan_id, rtu_vlan_entry_t ent);
extern task poll_ufifo();
@@ -337,14 +337,14 @@ function bit[15:0] CRTUSimDriver::mac_hash(bit[7:0] mac[], bit[7:0] fid);
endfunction // mac_hash
-task CRTUSimDriver::add_static_rule(bit[7:0] dmac[], bit[31:0] dpm);
+task CRTUSimDriver::add_static_rule(bit[7:0] dmac[], bit[31:0] dpm, bit[7:0] fid=0);
rtu_filtering_entry_t ent;
ent.mac = dmac;
ent.valid = 1'b1;
// ent.end_of_bucket = 1;
ent.is_bpdu = 0;
- ent.fid = 0;
+ ent.fid = fid;
ent.port_mask_dst = dpm;
ent.port_mask_src = 32'hffffffff;
ent.drop_when_source=0;
diff --git a/testbench/scb_top/main.sv b/testbench/scb_top/main.sv
index 537593d619ffd778bf701c5e38e482d4154016c0..b0d13f71e475ee944751d7081c7237949851cdba 100644
--- a/testbench/scb_top/main.sv
+++ b/testbench/scb_top/main.sv
@@ -24,7 +24,7 @@ module main;
reg rst_n=0;
parameter g_max_ports = 18;
parameter g_num_ports = 18;
- parameter g_mvlan = 4; //max simulation vlans
+ parameter g_mvlan = 10; //max simulation vlans
parameter g_max_dist_port_number = 4;
typedef enum {
PAUSE=0,
@@ -150,10 +150,16 @@ module main;
int prio_val = 0;
int pvid = 0;
// mask , fid , prio,has_p,overr, drop , vid, valid
- t_sim_vlan_entry sim_vlan_tab[g_mvlan] = '{'{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 },
- '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 },
- '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 100, 1'b1 },
- '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 200, 1'b1 }};
+ t_sim_vlan_entry sim_vlan_tab[g_mvlan] = '{'{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b0 }};
integer tru_config_opt = 0;
PFilterMicrocode mc = new;
byte BPDU_templ[] ='{'h01,'h80,'hC2,'h00,'h00,'h00, //0 - 5: dst addr
@@ -1456,7 +1462,8 @@ module main;
* simulating ungraceful loss of physic signal....
*
**/
-//*
+/*
+
initial begin
portUnderTest = 18'b000000000000000110;
g_tru_enable = 1;
@@ -1473,6 +1480,59 @@ module main;
g_enable_pck_gaps = 0;
g_force_payload_size = 512;
end
+*/
+ /** *************************** test scenario 51 ************************************* **/
+ /*
+ * VLAN + FF bug
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000010000001;
+
+ g_is_qvlan = 1; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ qmode = 2;
+ mac_br = 1; // fast forward broadcast
+ hp_prio_mask = 8'b0;
+ sim_vlan_tab[1] = '{'{32'b11 , 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'b110 , 8'h2, 3'h0, 1'b0, 1'b0, 1'b0}, 2 , 1'b1 };
+ sim_vlan_tab[3] = '{'{32'b1100 , 8'h3, 3'h0, 1'b0, 1'b0, 1'b0}, 3 , 1'b1 };
+ sim_vlan_tab[4] = '{'{32'b11000 , 8'h4, 3'h0, 1'b0, 1'b0, 1'b0}, 4 , 1'b1 };
+ sim_vlan_tab[5] = '{'{32'b110000 , 8'h5, 3'h0, 1'b0, 1'b0, 1'b0}, 5 , 1'b1 };
+ sim_vlan_tab[6] = '{'{32'b1100000 , 8'h6, 3'h0, 1'b0, 1'b0, 1'b0}, 6 , 1'b1 };
+ sim_vlan_tab[7] = '{'{32'b11000000 , 8'h7, 3'h0, 1'b0, 1'b0, 1'b0}, 7 , 1'b1 };
+ sim_vlan_tab[8] = '{'{32'b110000000 , 8'h8, 3'h0, 1'b0, 1'b0, 1'b0}, 8 , 1'b1 };
+ sim_vlan_tab[9] = '{'{32'b1100000000, 8'h9, 3'h0, 1'b0, 1'b0, 1'b0}, 9 , 1'b1 };
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,2 , 13 }; // send braodcast to VLAN=3
+ trans_paths[7] = '{7 ,0 , 10 };//send broadcast to VLAN=1
+// trans_paths[2] = '{2 ,15 , 0 };
+
+ end
+*/
+ /** *************************** test scenario 51 ************************************* **/
+ /*
+ * VLAN + FF bug
+ **/
+//*
+ initial begin
+ portUnderTest = 18'b000000000010000000;
+
+ g_is_qvlan = 1; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ qmode = 2;
+// mac_br = 1; // fast forward broadcast
+ hp_prio_mask = 8'b0;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'hF , 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'hF0 , 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ // tx ,rx ,opt
+
+ trans_paths[7] = '{7 ,4 , 10 };//send broadcast to VLAN=1
+// trans_paths[0] = '{2 ,15 , 0 };
+
+ end
//*/
//////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////
@@ -1537,7 +1597,7 @@ module main;
tmpl.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h00}; //BPDU
else if(opt==3)
tmpl.dst = '{17, 'h50, 'hca, 'hfe, 'hba, 'hbe};
- else if(opt==4 || opt==10 || opt==201 || opt == 203 || opt == 204 || opt == 205 || opt == 206 || opt == 207)
+ else if(opt==4 || opt==10 || opt==13 || opt==201 || opt == 203 || opt == 204 || opt == 205 || opt == 206 || opt == 207)
tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}; // broadcast
else if(opt==5)
tmpl.dst = '{'h11, 'h50, 'hca, 'hfe, 'hba, 'hbe}; // single Fast Forward
@@ -1570,7 +1630,9 @@ module main;
tmpl.is_q = is_q;
- if(opt==10)
+ if(opt==13)
+ tmpl.vid = 3;
+ else if(opt==10)
tmpl.vid = 1;
else
tmpl.vid = 0;
@@ -2182,6 +2244,10 @@ module main;
rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h00}, (1<<18));
rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h01}, (1<<18));
+ rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 0 /*FID*/);
+// rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 1 /*FID*/);
+// rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 2 /*FID*/);
+
if(g_LACP_scenario == 2)
begin
for(int i = 0;i<LACPdistro.distPortN;i++)
diff --git a/top/bare_top/scb_top_bare.vhd b/top/bare_top/scb_top_bare.vhd
index 7a73be6f09df860b861af67e5e20267b1954261b..2f9a477493d0dbad2b5a7d10ded7d635dc5c98da 100644
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -139,7 +139,7 @@ end scb_top_bare;
architecture rtl of scb_top_bare is
- constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"10_05_13_02"; --DD_MM_YY_VV
+ constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"24_05_13_00"; --DD_MM_YY_VV
constant c_NUM_WB_SLAVES : integer := 16;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;