From daedbde4a8c25fd52e8a3db69b5dda7f8bdc9c8a Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Fri, 3 Jul 2015 16:04:44 +0200
Subject: [PATCH] testbench: adding 8p testbench with helped me debug the
swcore
---
testbench/scb_top_8p/Manifest.py | 14 +
testbench/scb_top_8p/alloc.svh | 317 ++++++++
testbench/scb_top_8p/main.sv | 856 ++++++++++++++++++++
testbench/scb_top_8p/run.do | 14 +
testbench/scb_top_8p/scb_top_sim_svwrap.svh | 329 ++++++++
testbench/scb_top_8p/simdrv_wr_endpoint.svh | 250 ++++++
testbench/scb_top_8p/wave.do | 216 +++++
7 files changed, 1996 insertions(+)
create mode 100644 testbench/scb_top_8p/Manifest.py
create mode 100644 testbench/scb_top_8p/alloc.svh
create mode 100644 testbench/scb_top_8p/main.sv
create mode 100644 testbench/scb_top_8p/run.do
create mode 100644 testbench/scb_top_8p/scb_top_sim_svwrap.svh
create mode 100644 testbench/scb_top_8p/simdrv_wr_endpoint.svh
create mode 100644 testbench/scb_top_8p/wave.do
diff --git a/testbench/scb_top_8p/Manifest.py b/testbench/scb_top_8p/Manifest.py
new file mode 100644
index 00000000..2a2ae0be
--- /dev/null
+++ b/testbench/scb_top_8p/Manifest.py
@@ -0,0 +1,14 @@
+target = "xilinx"
+action = "simulation"
+syn_device = "XC6VLX130T"
+fetchto = "../../ip_cores"
+vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
+
+files = [ "main.sv" ]
+
+modules = { "local" : ["../../top/bare_top",
+ "../../ip_cores/general-cores",
+ "../../ip_cores/wr-cores"] }
+
+
+
diff --git a/testbench/scb_top_8p/alloc.svh b/testbench/scb_top_8p/alloc.svh
new file mode 100644
index 00000000..2758051f
--- /dev/null
+++ b/testbench/scb_top_8p/alloc.svh
@@ -0,0 +1,317 @@
+
+typedef enum
+ {
+ ALLOC,
+ FREE,
+ FORCE_FREE,
+ SET_USECOUNT
+ } alloc_req_type_t ;
+
+typedef struct {
+ int is_allocated;
+ int last_page_freed;
+ int usecnt;
+ int free_cnt; //for 3 resoruces
+ int force_free_cnt; // 3 resoruces
+ int alloc_port_vec;
+ int free_port_vec;
+ int f_free_port_vec;
+} alloc_page_instance_t;
+
+
+
+`define g_alloc_pages 1024
+`define g_usecnt_width 5
+`define g_pg_addr_width 10
+`define g_num_ports 19
+`define g_res_num_width 2
+`define g_alloc_inst_num 100
+
+typedef struct {
+ int alloc_cnt; // number of allocations of that page
+ alloc_page_instance_t alloc_inst[`g_alloc_inst_num];
+} alloc_page_t;
+
+
+alloc_page_t alloc_tab[`g_alloc_pages];
+int pre_s_alloc_tab[`g_alloc_pages]; // pre-allocated start page
+int pre_i_alloc_tab[`g_alloc_pages]; // pre-allocated inter page
+
+function init_alloc_tab();
+ int i;
+ for(i=0;i<`g_alloc_pages;i++) begin
+ alloc_tab[i].alloc_cnt = -1;
+ pre_s_alloc_tab[i] = 0;
+ pre_i_alloc_tab[i] = 0;
+ end
+endfunction;
+
+function automatic alloc_check(
+ input bit alloc_done,
+ input bit set_usecnt,
+ input bit free,
+ input bit force_free,
+ input bit [`g_usecnt_width -1:0] usecnt_alloc,
+ input bit [`g_usecnt_width -1:0] usecnt_set,
+ input bit [`g_pg_addr_width-1:0] pga_f, //page address freed
+ input bit [`g_pg_addr_width-1:0] pga_u, //page address usecnt
+ input bit [`g_pg_addr_width-1:0] pga_a, //page address allocated
+ input bit [`g_num_ports -1:0] req_vec
+ );
+ int cnt=0;
+ if(alloc_done) begin
+ cnt = ++alloc_tab[pga_a].alloc_cnt;
+ if(cnt >= `g_alloc_inst_num) $fatal("not enough alloc instances [see define g_alloc_inst_num in alloc.svh]");
+ alloc_tab[pga_a].alloc_inst[cnt].is_allocated = 1;
+ alloc_tab[pga_a].alloc_inst[cnt].usecnt = usecnt_alloc;
+ alloc_tab[pga_a].alloc_inst[cnt].free_cnt = 0;
+ alloc_tab[pga_a].alloc_inst[cnt].force_free_cnt = 0;
+ alloc_tab[pga_a].alloc_inst[cnt].alloc_port_vec = req_vec;
+ alloc_tab[pga_a].alloc_inst[cnt].free_port_vec = 0;
+ alloc_tab[pga_a].alloc_inst[cnt].f_free_port_vec= 0;
+ end
+ if(set_usecnt) begin
+ cnt = alloc_tab[pga_u].alloc_cnt;
+ alloc_tab[pga_u].alloc_inst[cnt].usecnt = usecnt_set;
+ end
+ if(free) begin
+ cnt = alloc_tab[pga_f].alloc_cnt;
+ alloc_tab[pga_f].alloc_inst[cnt].free_cnt++;
+ alloc_tab[pga_f].alloc_inst[cnt].free_port_vec = req_vec | alloc_tab[pga_f].alloc_inst[cnt].free_port_vec;
+ end
+
+ if(force_free) begin
+ cnt = alloc_tab[pga_f].alloc_cnt;
+ alloc_tab[pga_f].alloc_inst[cnt].force_free_cnt++;
+ alloc_tab[pga_f].alloc_inst[cnt].f_free_port_vec = req_vec | alloc_tab[pga_f].alloc_inst[cnt].f_free_port_vec;
+ end
+endfunction // first_free
+
+
+function automatic int check_if_prealloc(
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckstart_pageaddr,
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckinter_pageaddr,
+ input int pageaddr);
+ int i;
+ int tab_s[19];
+ int tab_i[19];
+
+ tab_s[ 0] = pckstart_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)];
+ tab_s[ 1] = pckstart_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)];
+ tab_s[ 2] = pckstart_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)];
+ tab_s[ 3] = pckstart_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)];
+ tab_s[ 4] = pckstart_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)];
+ tab_s[ 5] = pckstart_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)];
+ tab_s[ 6] = pckstart_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)];
+ tab_s[ 7] = pckstart_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)];
+ tab_s[ 8] = pckstart_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)];
+ tab_s[ 9] = pckstart_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)];
+ tab_s[10] = pckstart_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)];
+ tab_s[11] = pckstart_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)];
+ tab_s[12] = pckstart_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)];
+ tab_s[13] = pckstart_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)];
+ tab_s[14] = pckstart_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)];
+ tab_s[15] = pckstart_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)];
+ tab_s[16] = pckstart_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)];
+ tab_s[17] = pckstart_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)];
+ tab_s[18] = pckstart_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)];
+
+ tab_i[ 0] = pckinter_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)];
+ tab_i[ 1] = pckinter_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)];
+ tab_i[ 2] = pckinter_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)];
+ tab_i[ 3] = pckinter_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)];
+ tab_i[ 4] = pckinter_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)];
+ tab_i[ 5] = pckinter_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)];
+ tab_i[ 6] = pckinter_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)];
+ tab_i[ 7] = pckinter_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)];
+ tab_i[ 8] = pckinter_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)];
+ tab_i[ 9] = pckinter_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)];
+ tab_i[10] = pckinter_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)];
+ tab_i[11] = pckinter_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)];
+ tab_i[12] = pckinter_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)];
+ tab_i[13] = pckinter_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)];
+ tab_i[14] = pckinter_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)];
+ tab_i[15] = pckinter_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)];
+ tab_i[16] = pckinter_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)];
+ tab_i[17] = pckinter_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)];
+ tab_i[18] = pckinter_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)];
+
+ for(i=0;i<19;i++) begin
+ if(tab_s[i] == pageaddr) begin
+ pre_s_alloc_tab[i]++;
+// $display("start pck pre-alloc page: pageaddr=%3d | %3d [port=%2d | vector: %p]", pageaddr,tab_s[i],i, pckstart_pageaddr);
+ return i;
+ end
+ if(tab_i[i] == pageaddr) begin
+ pre_i_alloc_tab[i]++;
+// $display("inter pck pre-alloc page: pageaddr=%3d | %3d [port=%2d | vector: %p]", pageaddr,tab_i[i],i, pckstart_pageaddr);
+ return i;
+ end
+ end
+
+// if(pckstart_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)] == pageaddr) return 0;
+// if(pckstart_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)] == pageaddr) return 1;
+// if(pckstart_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)] == pageaddr) return 2;
+// if(pckstart_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)] == pageaddr) return 3;
+// if(pckstart_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)] == pageaddr) return 4;
+// if(pckstart_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)] == pageaddr) return 5;
+// if(pckstart_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)] == pageaddr) return 6;
+// if(pckstart_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)] == pageaddr) return 7;
+// if(pckstart_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)] == pageaddr) return 8;
+// if(pckstart_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)] == pageaddr) return 9;
+// if(pckstart_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)] == pageaddr) return 0;
+// if(pckstart_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)] == pageaddr) return 11;
+// if(pckstart_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)] == pageaddr) return 12;
+// if(pckstart_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)] == pageaddr) return 13;
+// if(pckstart_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)] == pageaddr) return 14;
+// if(pckstart_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)] == pageaddr) return 15;
+// if(pckstart_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)] == pageaddr) return 16;
+// if(pckstart_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)] == pageaddr) return 17;
+// if(pckstart_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)] == pageaddr) return 18;
+//
+// if(pckinter_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)] == pageaddr) return 0;
+// if(pckinter_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)] == pageaddr) return 1;
+// if(pckinter_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)] == pageaddr) return 2;
+// if(pckinter_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)] == pageaddr) return 3;
+// if(pckinter_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)] == pageaddr) return 4;
+// if(pckinter_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)] == pageaddr) return 5;
+// if(pckinter_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)] == pageaddr) return 6;
+// if(pckinter_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)] == pageaddr) return 7;
+// if(pckinter_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)] == pageaddr) return 8;
+// if(pckinter_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)] == pageaddr) return 9;
+// if(pckinter_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)] == pageaddr) return 10;
+// if(pckinter_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)] == pageaddr) return 11;
+// if(pckinter_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)] == pageaddr) return 12;
+// if(pckinter_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)] == pageaddr) return 13;
+// if(pckinter_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)] == pageaddr) return 14;
+// if(pckinter_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)] == pageaddr) return 15;
+// if(pckinter_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)] == pageaddr) return 16;
+// if(pckinter_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)] == pageaddr) return 17;
+// if(pckinter_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)] == pageaddr) return 18;
+
+// for(i=0;i<`g_num_ports;i++) begin
+// pg_s = pckstart_pageaddr[((i+1)*`g_pg_addr_width):(i*`g_pg_addr_width)];
+// pg_i = pckinter_pageaddr[((i+1)*`g_pg_addr_width):(i*`g_pg_addr_width)];
+// $display("checking pre-alloc: pg_s =0x%4x | pg_s =0x%4x | pg =0x%4x",pg_s,pg_i, pageaddr);
+// if(pg_s == pageaddr && pg_i == pageaddr ) return 1;
+// end
+ return -1;
+endfunction
+
+function automatic dump_results(
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckstart_pageaddr,
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckinter_pageaddr
+ );
+
+
+ int i = 0;
+ int j = 0;
+ int chk = 0;
+ int per_alloc_cnt =0;
+ int pg_pre_alloc = 0;
+ $display("--------------------------------- dumping resutls -------------------------------------");
+ while(alloc_tab[i].alloc_cnt >=0)
+ begin
+ for(j=0;j<=alloc_tab[i].alloc_cnt;j++)
+ begin
+ chk = alloc_tab[i].alloc_inst[j].usecnt - alloc_tab[i].alloc_inst[j].free_cnt;
+ if((chk != 0 || alloc_tab[i].alloc_inst[j].usecnt == 0) &&
+ alloc_tab[i].alloc_inst[j].is_allocated == 1 && // allocated and
+ alloc_tab[i].alloc_cnt == j) // last usage and
+ pg_pre_alloc = check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i);
+ else
+ pg_pre_alloc = -1;
+
+ if(chk == 0 && alloc_tab[i].alloc_inst[j].usecnt != 0)
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | OK",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec);
+ else if(pg_pre_alloc > -1) // one of pre-allocated
+ begin
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | pre-alloc-ed page for port %2d",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec,
+ pg_pre_alloc);
+ per_alloc_cnt++;
+ end
+// else if(chk == 1 && //possible candidate for pre-allocated page
+// alloc_tab[i].alloc_cnt == j && // needs to be the last usage
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i) > -1) // needs to be preallocated in one of ports
+// begin
+// $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | pre-alloc-ed page %2d",
+// i, j,
+// alloc_tab[i].alloc_inst[j].is_allocated,
+// alloc_tab[i].alloc_inst[j].usecnt,
+// alloc_tab[i].alloc_inst[j].free_cnt,
+// alloc_tab[i].alloc_inst[j].force_free_cnt,
+// alloc_tab[i].alloc_inst[j].alloc_port_vec,
+// alloc_tab[i].alloc_inst[j].free_port_vec,
+// alloc_tab[i].alloc_inst[j].f_free_port_vec,
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i));
+// per_alloc_cnt++;
+// end
+// else if(alloc_tab[i].alloc_inst[j].is_allocated == 1 && //allocated but...
+// alloc_tab[i].alloc_inst[j].usecnt == 0 && // no usecnt set and
+// alloc_tab[i].alloc_inst[j].free_cnt == 0 && // neither freed ...
+// alloc_tab[i].alloc_inst[j].force_free_cnt == 0 && // nor force-freed and
+// alloc_tab[i].alloc_cnt == j && // needs to be the last usage
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i) >-1) // needs to be preallocated in one of ports
+// begin
+// $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | pre-alloc-ed page %2d",
+// i, j,
+// alloc_tab[i].alloc_inst[j].is_allocated,
+// alloc_tab[i].alloc_inst[j].usecnt,
+// alloc_tab[i].alloc_inst[j].free_cnt,
+// alloc_tab[i].alloc_inst[j].force_free_cnt,
+// alloc_tab[i].alloc_inst[j].alloc_port_vec,
+// alloc_tab[i].alloc_inst[j].free_port_vec,
+// alloc_tab[i].alloc_inst[j].f_free_port_vec,
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i));
+// per_alloc_cnt++;
+// end
+ else if(alloc_tab[i].alloc_inst[j].force_free_cnt)
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | Force Free",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec);
+ else
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | check this one",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec);
+ end //for
+ i++;
+ end //while
+ $display("--------------------------------- --------------- -------------------------------------");
+ $display("pre-alloc pages: %3d",per_alloc_cnt);
+ for(i=0;i<`g_num_ports;i++) begin
+ if(pre_s_alloc_tab[i] != 1 || pre_i_alloc_tab[i] != 1)
+ $display("something wrong....: port %2d pre-allocation skrewed: start cnt=%2d | inter cnt = %2d",i, pre_s_alloc_tab[i], pre_i_alloc_tab[i]);
+ end
+
+endfunction
+
+
+
diff --git a/testbench/scb_top_8p/main.sv b/testbench/scb_top_8p/main.sv
new file mode 100644
index 00000000..96dcb627
--- /dev/null
+++ b/testbench/scb_top_8p/main.sv
@@ -0,0 +1,856 @@
+`timescale 1ns/1ps
+
+`include "tbi_utils.sv"
+`include "simdrv_wrsw_nic.svh"
+`include "simdrv_rtu.sv"
+`include "simdrv_txtsu.svh"
+`include "simdrv_hwdu.svh"
+`include "simdrv_wdog.svh"
+`include "endpoint_regs.v"
+`include "endpoint_mdio.v"
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+`include "wb_packet_source.svh"
+`include "wb_packet_sink.svh"
+`include "scb_top_sim_svwrap.svh"
+`include "pfilter.svh"
+`include "alloc.svh"
+
+module main;
+
+ reg clk_ref=0;
+ reg clk_sys=0;
+ reg clk_swc_mpm_core=0;
+ reg rst_n=0;
+ parameter g_max_ports = 8;
+ parameter g_num_ports = 8;
+ parameter g_mvlan = 9; //max simulation vlans
+
+ typedef struct {
+ integer tx;
+ integer rx;
+ integer op;
+ } t_trans_path;
+
+ typedef struct{
+ rtu_vlan_entry_t vlan_entry;
+ integer vlan_id;
+ bit valid;
+ } t_sim_vlan_entry;
+
+ typedef struct {
+ CSimDrv_WR_Endpoint ep;
+ EthPacketSource send;
+ EthPacketSink recv;
+ } port_t;
+
+ typedef struct{
+ int qmode;
+ int fix_prio;
+ int prio_val;
+ int pvid;
+ } t_vlan_port_config;
+
+ int mmu_alloc_cnt[g_num_ports+1];
+ int mmu_usecnt_cnt[g_num_ports+1];
+ int mmu_free_cnt[g_num_ports+1];
+ int mmu_f_free_cnt[g_num_ports+1];
+ int tx_done = 0;
+ int rx_done = 0;
+ reg [g_num_ports-1:0] txrx_done = 0;
+ int tb_wrd_cnt = 0;
+ int tb_forced = 0;
+ int tb_got_cyc = 0;
+ int tb_rtu_cnt = 0;
+ int tb_rtu_fsm = 0;
+
+ port_t ports[$];
+ CSimDrv_NIC nic;
+ CRTUSimDriver rtu;
+ CSimDrv_TXTSU txtsu;
+ CSimDrv_HWDU hwdu;
+ CSimDrv_WDOG wdog;
+
+ reg [g_num_ports-1:0] ep_ctrl;
+ reg [15:0] ep_failure_type = 'h00;
+
+ /** *************************** basic conf ************************************* **/
+ integer g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ integer g_min_pck_gap = 300; // cycles
+ integer g_max_pck_gap = 300; // cycles
+ integer g_force_payload_size = 0; // if 0, then opt is used
+ integer g_payload_range_min = 63;
+ integer g_payload_range_max = 257;
+ integer g_active_port = 0;
+ integer g_backup_port = 1;
+ integer g_is_qvlan = 1; // has vlan header
+ integer g_pfilter_enabled = 0;
+ integer g_limit_config_to_port_num = g_num_ports;
+
+ t_trans_path trans_paths[g_max_ports] ='{'{0 ,7 , 0 }, // port 0:
+ '{1 ,6 , 0 }, // port 1
+ '{2 ,5 , 0 }, // port 2
+ '{3 ,4 , 0 }, // port 3
+ '{4 ,3 , 0 }, // port 4
+ '{5 ,2 , 0 }, // port 5
+ '{6 ,1 , 0 }, // port 6
+ '{7 ,0 , 0 }}; // port 7
+ //index: 1,2,3,4,5,6,7,8,9, ....
+ integer start_send_init_delay[g_max_ports] = '{0,0,0,0,0,0,0,0};
+ //mask with ports we want to use, port number: 18 ...............0
+ reg [g_max_ports-1:0] portUnderTest = 8'b11111111; //
+ reg [g_max_ports-1:0] portRtuEnabled = 8'b11111111; //
+ integer repeat_number = 20;
+ integer tries_number = 3;
+ integer vid_init_for_inc = 0; // with opt 666 and 668
+// reg [31:0] vlan_port_mask = 32'hFFFFFFFF;
+ reg [31:0] mirror_src_mask = 'h00000002;
+ reg [31:0] mirror_dst_mask = 'h00000080;
+ reg [7 :0] hp_prio_mask ='b10000001;
+ bit mr_rx = 1;
+ bit mr_tx = 1;
+ bit mr = 0;
+ bit mac_ptp = 0;
+ bit mac_ll = 0;
+ bit mac_single = 0;
+ bit mac_range = 0;
+ bit mac_br = 0;
+ bit hp_fw_cpu = 0;
+ bit rx_forward_on_fmatch_full = 0;
+ bit unrec_fw_cpu = 0;
+ bit rtu_dbg_f_fast_match = 0;
+ bit rtu_dbg_f_full_match = 0;
+ bit g_ignore_rx_test_check = 0;
+
+ // vlans
+ int prio_map[8] = '{0, // Class of Service masked into prioTag 0
+ 1, // Class of Service masked into prioTag 1
+ 2, // Class of Service masked into prioTag 2
+ 3, // Class of Service masked into prioTag 3
+ 4, // Class of Service masked into prioTag 4
+ 5, // Class of Service masked into prioTag 5
+ 6, // Class of Service masked into prioTag 6
+ 7};// Class of Service masked into prioTag 7
+ int qmode = 2; //VLAN tagging/untagging disabled- pass as is
+ //0: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN
+ //1: TRUNK port - passes only tagged VLAN packets. Drops all untagged packets.
+ //3: unqualified port - passes all traffic regardless of VLAN configuration
+
+ int fix_prio = 0;
+ int prio_val = 0;
+ int pvid = 0;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ t_sim_vlan_entry sim_vlan_tab[g_mvlan] = '{'{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b0 }};
+ PFilterMicrocode mc = new;
+
+
+ //qmode, fix_prio, prio_val, pvid
+ t_vlan_port_config ep_vlan_conf[] ='{'{ 0, 0, 0, 1 }, //port = 0
+ '{ 0, 0, 0, 1 }, //port = 1
+ '{ 0, 0, 0, 2 }, //port = 2
+ '{ 0, 0, 0, 2 }, //port = 3
+ '{ 0, 0, 0, 3 }, //port = 4
+ '{ 0, 0, 0, 3 }, //port = 5
+ '{ 0, 0, 0, 4 }, //port = 6
+ '{ 0, 0, 0, 4 }, //port = 7
+ '{ 0, 0, 0, 5 }, //port = 8
+ '{ 0, 0, 0, 5 }, //port = 9
+ '{ 0, 0, 0, 6 }, //port = 10
+ '{ 0, 0, 0, 6 }, //port = 11
+ '{ 0, 0, 0, 7 }, //port = 12
+ '{ 0, 0, 0, 7 }, //port = 13
+ '{ 0, 0, 0, 8 }, //port = 14
+ '{ 0, 0, 0, 8 }, //port = 15
+ '{ 0, 0, 0, 9 }, //port = 16
+ '{ 0, 0, 0, 9 }};//port = 17
+
+ integer g_do_vlan_config = 1;
+
+ integer g_set_untagging = 0;
+ int lacp_df_hp_id = 0;
+ int lacp_df_br_id = 2;
+ int lacp_df_un_id = 1;
+ int g_simple_allocator_unicast_check = 0;
+
+ /** *************************** test scenario 62 ************************************* **/
+ /*
+ * test 100% (high) load for 2 streams of small frames
+ **/
+ //GD
+
+ initial begin
+ portUnderTest = 8'b00000001;
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 0; //10;
+ g_max_pck_gap = 0; //10;
+ repeat_number = 20; //1000; //3000; //500000;
+ tries_number = 1;
+ g_force_payload_size = 1517; //696; //1517; //682; //46;
+
+ g_is_qvlan = 0;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,7 ,1};
+ trans_paths[7] = '{7 ,0 ,1};
+
+ trans_paths[1] = '{1 ,6 ,1};
+ trans_paths[6] = '{6 ,1 ,1};
+
+ trans_paths[2] = '{2 ,5 ,1};
+ trans_paths[5] = '{5 ,2 ,1};
+
+ trans_paths[3] = '{3 ,4 ,1};
+ trans_paths[4] = '{4 ,3 ,1};
+
+ end
+
+ /* check state machines of the swcore */
+ //always @(posedge clk_sys) begin
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.trans_FSM == 4'h9)
+ // $warning("ll_FSM 0");
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[1].INPUT_BLOCK.trans_FSM == 4'h9)
+ // $warning("ll_FSM 1");
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[6].INPUT_BLOCK.trans_FSM == 4'h9)
+ // $warning("ll_FSM 6");
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[7].INPUT_BLOCK.trans_FSM == 4'h9)
+ // $warning("ll_FSM 7");
+ //end
+
+ //always @(negedge clk_sys) begin
+ // if (tb_forced==1) begin
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_stb_int = 0;
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_cyc_int = 0;
+ // //force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_cyc_d0 = 1;
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.in_pck_err = 0;
+ // //tb_forced = 2;
+ // end
+ // //else if (tb_forced==2) begin
+ // // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_cyc_d0 = 0;
+ // //end
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.endpoint_src_out[0].cyc == 0 && tb_forced>0) begin
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_stb_int;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_cyc_int;
+ // //release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_cyc_d0;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_ack_int;
+ // tb_forced = 0;
+ // end
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_cyc_int == 1'h0 && tb_wrd_cnt==3) begin
+ // tb_wrd_cnt = 0;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.in_pck_err;
+ // end
+ // else begin
+ // //we are inside the frame
+ // if(tb_wrd_cnt<3 && DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.page_word_cnt == 64)
+ // tb_wrd_cnt = tb_wrd_cnt + 1;
+ // if(tb_wrd_cnt == 3 && DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.page_word_cnt == 63) begin
+ // //if(tb_wrd_cnt == 3 && DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.page_word_cnt == 53) begin
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.in_pck_err = 1;
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.snk_ack_int= 1;
+ // tb_forced = 1;
+ // end
+ // end
+ //end
+
+ /////////////////////////////////////////////////////////////////////////
+
+ //always @(negedge clk_sys) begin
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.endpoint_src_out[0].cyc == 1 && tb_got_cyc == 0) begin
+ // tb_got_cyc = 1;
+ // tb_wrd_cnt = 0;
+ // end
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.endpoint_src_out[0].cyc == 0 && tb_got_cyc==1) begin
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X.U_Wrapped_Endpoint.src_in.stall = 1;
+ // tb_wrd_cnt = tb_wrd_cnt + 1;
+ // if(tb_wrd_cnt == 365) begin
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X.U_Wrapped_Endpoint.src_in.stall = 0;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X.U_Wrapped_Endpoint.src_in.stall;
+ // tb_got_cyc = 2;
+ // end
+ // end
+
+
+ // if (tb_rtu_fsm == 3)
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rtu_rsp_valid_i = 0;
+ // if (tb_rtu_fsm == 2) begin
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rtu_rsp_valid_i = 1;
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rtu_rsp_ack_o == 1)
+ // tb_rtu_fsm = 3;
+ // end
+ // else if (tb_rtu_cnt > 1) begin
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rtu_dst_port_mask_i = 0;
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rtu_rsp_valid_i = 0;
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rcv_p_FSM == 1)
+ // tb_rtu_fsm = 1;
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rcv_p_FSM == 3)
+ // tb_rtu_fsm = 2;
+ // end
+
+ // if (DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.rtu_rsp_ack)
+ // tb_rtu_cnt = tb_rtu_cnt + 1;
+ //end
+
+ //initial begin
+ // //#67608ns
+ // //#66616ns
+ // #66632ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.mmu_page_alloc_done_i = 0;
+ // #944ns
+ // //#1000ns --> check this as well !!
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.mmu_page_alloc_done_i = 1;
+ // #16ns
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.gen_blocks[0].INPUT_BLOCK.mmu_page_alloc_done_i;
+ //end
+
+ //addition
+ //initial begin
+ // #125us;
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.PCK_PAGES_FREEEING_MODULE.lpd_gen[0].LPD.dbg_sv_force = 1;
+ // #335us;
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.PCK_PAGES_FREEEING_MODULE.lpd_gen[0].LPD.dbg_sv_force = 0;
+ //end
+
+ /////////////////////////////////////////////////////////////////////////
+
+ // Trying to reproduce RTU hanging bug
+ //initial begin
+ // #1ns //shift because SV code is executed before VHDL so I need to make sure that whatever I force here
+ // //will be visible for VHDL on next clk cycle.
+ // #51832ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 0;
+ // //RTU req
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rq_i.valid = 1;
+ // #16ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rq_i.valid = 0;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rq_i.valid;
+ // #240ns
+ // //#208ns
+ // //RTU req
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rq_i.valid = 1;
+ // #16ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rq_i.valid = 0;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rq_i.valid;
+ // //66072
+ // //finally let's ack
+ // #13968ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 1;
+ // #16ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 0;
+
+ // //ack
+ // #64ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 1;
+ // #16ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 0;
+
+ // //ack
+ // #64ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 1;
+ // #16ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i = 0;
+
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gen_network_stuff.U_RTU.ports[0].U_PortX.rtu_rsp_ack_i;
+ //end
+
+ /////////////////////////////////////////////////////////////////////////
+
+ // Trying with the watchdog reset
+ //initial begin
+ // //#203247ns
+ // //force DUT.WRS_Top.U_Wrapped_SCBCore.reset_mode = 1;
+ // //force DUT.WRS_Top.U_Wrapped_SCBCore.reset_mode2 = 1;
+ // //#100ns
+ // //force DUT.WRS_Top.U_Wrapped_SCBCore.reset_mode = 0;
+ // //#40us
+ // //force DUT.WRS_Top.U_Wrapped_SCBCore.reset_mode2 = 0;
+ // //release DUT.WRS_Top.U_Wrapped_SCBCore.reset_mode;
+ // //release DUT.WRS_Top.U_Wrapped_SCBCore.reset_mode2;
+
+ // #203247ns
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gpio_out_1 = 1;
+ // #40us
+ // force DUT.WRS_Top.U_Wrapped_SCBCore.gpio_out_1 = 0;
+ // release DUT.WRS_Top.U_Wrapped_SCBCore.gpio_out_1;
+ //end
+
+ initial begin
+ #104us;
+ //$display("---------------------------");
+ //wdog.print_fsms(0);
+ //$display("---------------------------");
+ //wdog.print_fsms(0);
+ //#10us;
+ //$display("---------------------------");
+ //wdog.print_fsms(0);
+ #19us;
+ wdog.force_reset();
+ end
+
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+
+ always #2.66ns clk_swc_mpm_core <=~clk_swc_mpm_core;
+// always #3.11ns clk_swc_mpm_core <=~clk_swc_mpm_core;
+// always #4.2ns clk_swc_mpm_core <=~clk_swc_mpm_core;
+ always #8ns clk_sys <= ~clk_sys;
+ always #8ns clk_ref <= ~clk_ref;
+
+ initial begin
+ repeat(100) @(posedge clk_sys);
+ rst_n <= 1;
+ end
+/*
+ * wait ncycles
+ */
+ task automatic wait_cycles;
+ input [31:0] ncycles;
+ begin : wait_body
+ integer i;
+
+ for(i=0;i<ncycles;i=i+1) @(posedge clk_sys);
+
+ end
+ endtask // wait_cycles
+
+ task automatic tx_test(ref int seed, input int n_tries, input int is_q,input int unvid, ref EthPacketSource src, ref EthPacketSink sink, input int srcPort, input int dstPort, input int opt=0);
+ EthPacketGenerator gen = new;
+ EthPacket pkt, tmpl, pkt2;
+ EthPacket arr[];
+ integer pck_gap = 0;
+ integer dmac_dist = 0;
+
+ if(g_enable_pck_gaps == 1)
+ if(g_min_pck_gap == g_max_pck_gap)
+ pck_gap = g_min_pck_gap;
+ else
+ pck_gap = $dist_uniform(seed,g_min_pck_gap,g_max_pck_gap);
+
+ arr = new[n_tries](arr);
+ if(opt !=3 && opt != 4)
+ gen.set_seed(seed);
+
+ tmpl = new;
+
+ if(opt == 0 || opt == 200 || opt == 201 || opt == 666 || opt == 667 || opt == 1000 || opt == 2000)
+ tmpl.src = '{srcPort, 2,3,4,5,6};
+ else if(opt == 101 | opt == 102)
+ tmpl.src = '{0,0,0,0,0,0};
+ else if(opt > 2 )
+ tmpl.src = '{0,2,3,4,5,6};
+ else
+ tmpl.src = '{srcPort, 2,3,4,5,6};
+
+ if(opt==0 || opt == 200 || opt == 202 || opt == 1000 || opt == 2000)
+ tmpl.dst = '{dstPort, 'h50, 'hca, 'hfe, 'hba, 'hbe};
+ else if(opt==1)
+ tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF};
+ else
+ tmpl.dst = '{'h00, 'h00, 'h00, 'h00, 'h00, 'h00}; // link-limited
+
+
+ tmpl.has_smac = 1;
+ tmpl.pcp = 0; //priority
+ tmpl.is_q = is_q;
+ tmpl.vid = 0;
+ tmpl.ethertype = 'h88f7;
+
+ gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::SEQ_ID);
+ gen.set_template(tmpl);
+ if(g_force_payload_size >= 1520) // more than max
+ gen.set_size(64, 1500);
+ else if(g_force_payload_size < 42)
+ gen.set_size(g_payload_range_min, g_payload_range_max);
+ else
+ gen.set_size(g_force_payload_size, g_force_payload_size+1); // setting the precise size below
+
+ fork
+ begin // fork 1
+ integer vid_cnt=0;
+ for(int i=0;i<n_tries;i++) begin
+ pkt = gen.gen();
+
+ if(g_force_payload_size >= 1520) // more than max
+ $faltal("wrong g_force_payload_size with wrong opt param");
+ else if(g_force_payload_size >= 42) // min size of frame is 64,
+ pkt.set_size(g_force_payload_size);
+
+ pkt.oob = TX_FID;
+ $display("|=> TX: port = %2d, pck_i = %4d (opt=%1d, pck_gap=%3d, size=%2d, n=%d)" , srcPort, i,opt,pck_gap, pkt.payload.size, i);
+ src.send(pkt);
+ arr[i] = pkt;
+ //if(pck_gap)
+ // wait_cycles(pck_gap);
+ end
+ tx_done = 1;
+ end // fork 1
+
+ begin // fork 2
+ if(g_ignore_rx_test_check == 0) begin
+ //for(int j=0;j<n_tries;j++)
+ while(1) begin
+ sink.recv(pkt2);
+ $display("|<= RX: port = %2d (size=%2d)" , dstPort, pkt2.payload.size);
+ //$display("|<= RX: port = %2d, pck_i = %4d (size=%2d)" , dstPort, j, pkt2.payload.size);
+ //if(unvid)
+ // arr[j].is_q = 0;
+ //if((arr[j].payload.size != pkt2.payload.size) || !arr[j].equal(pkt2)) begin
+ // $display("Fault at %d", j);
+ // $display("Should be: ");
+ // arr[j].dump();
+ // $display("Is: ");
+ // pkt2.dump();
+ //end
+ end // for (i=0;i<n_tries;i++)
+ rx_done = 1;
+ end
+ end // fork 2
+ join
+ seed = gen.get_seed();
+
+ endtask // tx_test
+
+
+ ///////////////////////////////////////////////////////
+ ////////////////// DUT ///////////////////////////////
+ ///////////////////////////////////////////////////////
+ scb_top_sim_svwrap #(
+ .g_num_ports (g_num_ports),
+ .g_with_TRU (0),
+ .g_with_TATSU (0))
+ DUT (
+ .clk_sys_i(clk_sys),
+ .clk_ref_i(clk_ref),
+ .rst_n_i(rst_n),
+ .cpu_irq(cpu_irq),
+ .clk_swc_mpm_core_i(clk_swc_mpm_core),
+ .ep_ctrl_i(ep_ctrl),
+ .ep_failure_type(ep_failure_type)
+ );
+ ///////////////////////////////////////////////////////
+ ///////////////////////////////////////////////////////
+ ///////////////////////////////////////////////////////
+
+
+
+ task automatic init_ports(ref port_t p[$], ref CWishboneAccessor wb);
+ int i,j;
+
+ for(i=0;i<g_num_ports;i++)
+ begin
+ port_t tmp;
+ CSimDrv_WR_Endpoint ep;
+ ep = new(wb, 'h30000 + i * 'h400);
+ ep.init(i);
+ if(g_do_vlan_config == 2 & i < g_limit_config_to_port_num )
+ ep.vlan_config(ep_vlan_conf[i].qmode, ep_vlan_conf[i].fix_prio, ep_vlan_conf[i].prio_val, ep_vlan_conf[i].pvid, prio_map);
+ else if(g_do_vlan_config == 1 & i < g_limit_config_to_port_num )
+ ep.vlan_config(qmode, fix_prio, prio_val, pvid, prio_map);
+ else
+ ep.vlan_config(2, 0, 0, 0, '{0,1,2,3,4,5,6,7});//default
+
+ if(g_pfilter_enabled == 1 & i < g_limit_config_to_port_num )
+ begin
+ ep.pfilter_load_microcode(mc.assemble());
+ ep.pfilter_enable(1);
+ end
+
+ if(g_set_untagging == 1)
+ begin
+ for(j=0;j<g_limit_config_to_port_num; j++)
+ ep.vlan_egress_untag(j /*vlan*/ ,1);
+ end
+ else if(g_set_untagging == 2)
+ begin
+ for(j=0;j<g_limit_config_to_port_num; j++)
+ ep.vlan_egress_untag(ep_vlan_conf[j].pvid /*vlan*/ ,1);
+ end
+ else if(g_set_untagging == 3)
+ begin
+ ep.vlan_egress_untag_direct('hFFFF /*vlan*/ ,0);
+ ep.vlan_egress_untag_direct('hFFFF /*vlan*/ ,1);
+ end
+ tmp.ep = ep;
+ tmp.send = EthPacketSource'(DUT.to_port[i]);
+ tmp.recv = EthPacketSink'(DUT.from_port[i]);
+ p.push_back(tmp);
+ end
+ endtask // init_endpoints
+
+ task automatic init_nic(ref port_t p[$],ref CWishboneAccessor wb);
+ NICPacketSource nic_src;
+ NICPacketSink nic_snk;
+ port_t tmp;
+
+ nic = new(wb, 'h20000);
+ $display("NICInit");
+ nic.init();
+ $display("Done");
+
+ nic_src = new (nic);
+ nic_snk = new (nic);
+ $display("Src: %x\n",nic_src);
+
+ tmp.send = EthPacketSource'(nic_src);
+ tmp.recv = EthPacketSink'(nic_snk);
+ p.push_back(tmp);
+
+ endtask // init_nic
+
+
+ initial begin
+ uint64_t msr;
+ int seed;
+ rtu_vlan_entry_t def_vlan;
+ int q;
+ int z;
+
+ CWishboneAccessor cpu_acc = DUT.cpu.get_accessor();
+
+ for(int gg=0;gg<g_num_ports;gg++)
+ begin
+ ep_ctrl[gg] = 'b1;
+ end
+ repeat(200) @(posedge clk_sys);
+
+ $display("Startup!");
+ cpu_acc.set_mode(PIPELINED);
+ cpu_acc.write('h10304, (1<<3));
+
+ init_ports(ports, cpu_acc);
+
+ $display("InitNIC");
+ init_nic(ports, cpu_acc);
+
+ $display("InitTXTS");
+ txtsu = new (cpu_acc, 'h51000);
+ txtsu.init();
+
+ $display("Initialization done");
+
+ rtu = new;
+ rtu.set_bus(cpu_acc, 'h60000);
+ for (int dd=0;dd<g_num_ports;dd++)
+ begin
+ rtu.set_port_config(dd /*port ID*/, portRtuEnabled[dd] /*pass_all*/, 0 /*pass_bpdu*/, 1 /*learn_en*/);
+ end
+
+ rtu.set_port_config(g_num_ports, 1, 0, 0); // for NIC
+
+ rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h00}, (1<<18));
+ rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h01}, (1<<18));
+ rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h02}, (1<<18));
+
+ rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 0 /*FID*/);
+
+ //GD if(portUnderTest[0]) rtu.add_static_rule('{7, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<7));
+ //GD if(portUnderTest[1]) rtu.add_static_rule('{6, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<6));
+ if(portUnderTest[2]) rtu.add_static_rule('{5, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<5));
+ if(portUnderTest[3]) rtu.add_static_rule('{4, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<4));
+ if(portUnderTest[4]) rtu.add_static_rule('{3, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<3));
+ if(portUnderTest[5]) rtu.add_static_rule('{2, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<2));
+ //GD if(portUnderTest[6]) rtu.add_static_rule('{1, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<1));
+ //GD if(portUnderTest[7]) rtu.add_static_rule('{10, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<10));
+ //if(portUnderTest[8]) rtu.add_static_rule('{ 9, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<9 ));
+ //if(portUnderTest[9]) rtu.add_static_rule('{ 8, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<8 ));
+ //if(portUnderTest[10]) rtu.add_static_rule('{ 7, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<7 ));
+ //if(portUnderTest[11]) rtu.add_static_rule('{ 6, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<6 ));
+ //if(portUnderTest[12]) rtu.add_static_rule('{ 5, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<5 ));
+ //if(portUnderTest[13]) rtu.add_static_rule('{ 4, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<4 ));
+ //if(portUnderTest[14]) rtu.add_static_rule('{ 3, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<3 ));
+ //if(portUnderTest[15]) rtu.add_static_rule('{ 2, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<2 ));
+ //if(portUnderTest[16]) rtu.add_static_rule('{ 1, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<1 ));
+ //GD if(portUnderTest[17]) rtu.add_static_rule('{ 0, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<0 ));
+
+ $display(">>>>>>>>>>>>>>>>>>> RTU initialization <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ for(int dd=0;dd<g_mvlan;dd++)
+ begin
+ def_vlan.port_mask = sim_vlan_tab[dd].vlan_entry.port_mask;
+ def_vlan.fid = sim_vlan_tab[dd].vlan_entry.fid;
+ def_vlan.drop = sim_vlan_tab[dd].vlan_entry.drop;
+ def_vlan.prio = sim_vlan_tab[dd].vlan_entry.prio;
+ def_vlan.has_prio = sim_vlan_tab[dd].vlan_entry.has_prio;
+ def_vlan.prio_override = sim_vlan_tab[dd].vlan_entry.prio_override;
+ if(sim_vlan_tab[dd].valid == 1)
+ rtu.add_vlan_entry(sim_vlan_tab[dd].vlan_id, def_vlan);
+ end
+
+ /////////////////////////// RTU extension settings: ////////////////////////////////
+
+ rtu.rx_add_ff_mac_single(0/*ID*/,1/*valid*/,'h1150cafebabe /*MAC*/);
+ rtu.rx_add_ff_mac_single(1/*ID*/,1/*valid*/,'h111111111111 /*MAC*/);
+ rtu.rx_add_ff_mac_single(2/*ID*/,1/*valid*/,'h0150cafebabe /*MAC*/);
+ rtu.rx_add_ff_mac_single(3/*ID*/,1/*valid*/,'h0050cafebabe /*MAC*/);
+ rtu.rx_add_ff_mac_range (0/*ID*/,1/*valid*/,'h0050cafebabe /*MAC_lower*/,'h0850cafebabe/*MAC_upper*/);
+ rtu.rx_set_port_mirror (mirror_src_mask, mirror_dst_mask,mr_rx, mr_tx);
+ rtu.rx_set_hp_prio_mask (hp_prio_mask /*hp prio mask*/);
+ rtu.rx_read_cpu_port();
+ if(rx_forward_on_fmatch_full)
+ rtu.rx_forward_on_fmatch_full();
+ else
+ rtu.rx_drop_on_fmatch_full();
+ rtu.rx_feature_ctrl(mr, mac_ptp , mac_ll, mac_single, mac_range, mac_br);
+ rtu.rx_fw_to_CPU(hp_fw_cpu,unrec_fw_cpu);
+ rtu.rx_feature_dbg(rtu_dbg_f_fast_match, rtu_dbg_f_full_match);
+
+ ////////////////////////////////////////////////////////////////////////////////////////
+
+ rtu.enable();
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+
+ hwdu=new(cpu_acc, 'h59000);
+ hwdu.dump_mpm_page_utilization(1);
+
+ wdog = new(cpu_acc, 'h5a000);
+
+ ////////////// sending packest on all the ports (16) according to the portUnderTest mask.///////
+ for(q=0; q<g_max_ports; q++)
+ fork
+ automatic int qq=q;
+ begin
+ if(portUnderTest[qq])
+ begin
+ wait_cycles(start_send_init_delay[qq]);
+ for(int g=0;g<tries_number;g++)
+ begin
+ //$display("Try port_%d:%d", qq, g);
+ tx_test(seed /* seed */,
+ repeat_number /* n_tries */,
+ g_is_qvlan /* is_q */,
+ 0 /* unvid */,
+ ports[trans_paths[qq].tx].send /* src */,
+ ports[trans_paths[qq].rx].recv /* sink */,
+ trans_paths[qq].tx /* srcPort */ ,
+ trans_paths[qq].rx /* dstPort */,
+ trans_paths[qq].op /*option=4 */);
+ end //for
+ txrx_done[qq]=1;
+ end //if
+
+ end //thread
+ join_none;//fork
+
+ fork
+ forever begin
+ nic.update(DUT.WRS_Top.U_Wrapped_SCBCore.vic_irqs[0]);
+ @(posedge clk_sys);
+ end
+ forever begin
+ txtsu.update(DUT.WRS_Top.U_Wrapped_SCBCore.vic_irqs[1]);
+ @(posedge clk_sys);
+ end
+ join_none
+
+ end
+
+ /* ***************************************************************************************
+ * Page allocator and resource manager debugging
+ * ***************************************************************************************
+ * this stuff is used to debug allocator and resource manager - it is very slow and has
+ * static tables which causes simulation to crash if we run it tooo long
+ * uncomment only if debugging allocator
+ * ***************************************************************************************
+
+ initial begin
+ int q =0;
+ while(!rst_n) @(posedge clk_sys);
+
+ if(g_simple_allocator_unicast_check)
+ forever begin
+ for(q=0;q<g_max_ports;q++) begin
+ if(portUnderTest[q]) begin
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.alloc_done_o[q])
+ mmu_alloc_cnt[q]++;
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.set_usecnt_done_o[q])
+ mmu_usecnt_cnt[q]++;
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.free_done_o[q])
+ mmu_free_cnt[q]++;
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.force_free_done_o[q])
+ mmu_f_free_cnt[q]++;
+ end //if
+ end // for
+ @(posedge clk_sys);
+ end //forever
+ end //initial begin
+
+
+ initial begin
+ int l = 0;
+ int pg_cnt =0;
+ while(!rst_n) @(posedge clk_sys);
+ while(txrx_done != portUnderTest || g_transition_scenario != 0) @(posedge clk_sys);
+ wait_cycles(100);
+ while(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages < 985) @(posedge clk_sys);
+ $display("free pages: %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages);
+ if(!g_simple_allocator_unicast_check)
+ begin
+ wait_cycles(2000);// wait so we can do other stuff (i.e. display the other alloc check
+ $stop; //$finish; // finish sim
+ end
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.g_with_RESOURCE_MGR) begin
+ $display("unknown: %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.dbg_o[9 : 0]);
+ $display("special: %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.dbg_o[19:10]);
+ $display("normal : %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.dbg_o[29:20]);
+ end
+ $display("------------------- this check works only for unicast traffic ------------------------");
+ for(l=0;l<g_max_ports+1;l++)
+ begin
+ pg_cnt = mmu_alloc_cnt[trans_paths[l].tx]-mmu_f_free_cnt[trans_paths[l].tx]-mmu_free_cnt[trans_paths[l].rx];
+ if(pg_cnt == 2) // very simple sanity check
+ $display("CNT: tx_port=%2d: alloc=%3d; usecnt=%3d; force free=%3d | rx_port=%2d: free=%3d [OK]",trans_paths[l].tx, mmu_alloc_cnt[trans_paths[l].tx], mmu_usecnt_cnt[trans_paths[l].tx],mmu_f_free_cnt[trans_paths[l].tx], trans_paths[l].rx, mmu_free_cnt[trans_paths[l].rx]);
+ else
+ $display("CNT: tx_port=%2d: alloc=%3d; usecnt=%3d; force free=%3d | rx_port=%2d: free=%3d [--]",trans_paths[l].tx, mmu_alloc_cnt[trans_paths[l].tx], mmu_usecnt_cnt[trans_paths[l].tx],mmu_f_free_cnt[trans_paths[l].tx], trans_paths[l].rx, mmu_free_cnt[trans_paths[l].rx]);
+ end//if
+ $display("------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ------------------------");
+ end //initla begin
+
+
+ initial begin
+ int l = 0;
+ int pg_cnt =0;
+ init_alloc_tab();
+ while(!rst_n) @(posedge clk_sys);
+ forever begin
+ alloc_check(
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_alloc_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_usecnt_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_free_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_force_free_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.usecnt_alloc,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.usecnt_set,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.pgaddr_free,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.pgaddr_usecnt,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.pgaddr_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.rsp_vec_o
+ );
+ @(posedge clk_sys);
+ end
+ end //initla begin
+
+ initial begin
+ int l = 0;
+ int pg_cnt =0;
+ init_alloc_tab();
+ while(!rst_n) @(posedge clk_sys);
+ while(txrx_done != portUnderTest || g_transition_scenario != 0) @(posedge clk_sys);
+ wait_cycles(1000);
+ while(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages < 985) @(posedge clk_sys);
+ wait_cycles(1000);
+ dump_results(
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.dbg_pckstart_pageaddr,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.dbg_pckinter_pageaddr);
+
+ $stop;
+ end //initla begin
+ */
+
+endmodule // main
+
diff --git a/testbench/scb_top_8p/run.do b/testbench/scb_top_8p/run.do
new file mode 100644
index 00000000..86fd7475
--- /dev/null
+++ b/testbench/scb_top_8p/run.do
@@ -0,0 +1,14 @@
+make -f Makefile
+#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
+vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+ do wave.do
+#do wave_new.do
+#do wave-master.do
+#do wave-allports.do
+radix -hexadecimal
+run 39000us
+#run 100us
+wave zoomfull
+radix -hexadecimal
diff --git a/testbench/scb_top_8p/scb_top_sim_svwrap.svh b/testbench/scb_top_8p/scb_top_sim_svwrap.svh
new file mode 100644
index 00000000..2c48a7ba
--- /dev/null
+++ b/testbench/scb_top_8p/scb_top_sim_svwrap.svh
@@ -0,0 +1,329 @@
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "simdrv_wr_endpoint.svh"
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+
+
+function automatic bit f_next_8b10b_disparity8(bit cur_disp, bit k, bit [7:0] data);
+ const bit[0:31] c_disPar_6b = 32'b11101000100000011000000110010111;
+ const bit [0:7] c_disPar_4b = 8'b10001001;
+ bit dp4bit, dp6bit, new_disp;
+
+ dp4bit = c_disPar_4b[data[7:5]];
+ dp6bit = c_disPar_6b[data[4:0]];
+ new_disp = cur_disp;
+
+
+ case (cur_disp)
+ 1'b0: if (k ^ dp6bit ^ dp4bit)
+ new_disp = 1;
+ 1'b1: if (k ^ dp6bit ^ dp4bit)
+ new_disp = 0;
+ endcase // case (cur_disp)
+
+ if ( data[1:0] != 2'b0 && k)
+ new_disp = cur_disp;
+
+ return new_disp;
+endfunction // f_next_8b10b_disparity8
+
+function automatic bit f_next_8b10b_disparity16(bit cur_disp,bit[1:0] k, bit[15:0] data);
+ bit tmp;
+ bit [7:0] msb;
+
+ msb = data[15:0];
+ tmp = f_next_8b10b_disparity8(cur_disp, k[1], msb);
+ tmp = f_next_8b10b_disparity8(tmp, k[0], data[7:0]);
+ return tmp;
+endfunction // f_next_8b10b_disparity16
+
+
+
+module scb_top_sim_svwrap
+(
+ clk_sys_i,
+ clk_ref_i,
+ rst_n_i,
+ cpu_irq,
+ clk_swc_mpm_core_i,
+ ep_ctrl_i,
+ ep_failure_type
+);
+
+ parameter g_num_ports = 8;
+ parameter g_with_TRU = 1;
+ parameter g_with_TATSU = 1;
+ parameter g_with_HWIU = 1;
+
+ input clk_sys_i, clk_ref_i,rst_n_i,clk_swc_mpm_core_i;
+ input bit[g_num_ports-1:0] ep_ctrl_i;
+ output cpu_irq;
+ input [15:0] ep_failure_type;
+
+ reg [15:0] tx_data_invalid[g_num_ports];
+ reg [ 1:0] tx_k_invalid[g_num_ports];
+ reg [g_num_ports-1:0] phys_rdy;
+
+ wire [g_num_ports-1:0] rbclk;
+ wire [18 * g_num_ports - 1:0] td, rd;
+
+ typedef struct {
+ logic rst;
+ logic loopen;
+ logic enable;
+ logic syncen;
+ logic [15:0] tx_data;
+ logic [1:0] tx_k;
+ } t_phyif_output;
+
+ typedef struct {
+ logic ref_clk;
+ logic tx_disparity;
+ logic tx_enc_err;
+ logic [15:0]rx_data;
+ logic rx_clk;
+ logic [1:0] rx_k;
+ logic rx_enc_err;
+ logic rx_bitslide;
+ } t_phyif_input;
+
+ t_phyif_output phys_out[g_num_ports];
+ t_phyif_input phys_in[g_num_ports];
+
+ WBPacketSource to_port[g_num_ports];
+ WBPacketSink from_port[g_num_ports];
+
+ IWishboneMaster #(32, 32) cpu(clk_sys_i, rst_n_i);
+
+ initial begin
+ cpu.settings.cyc_on_stall = 1;
+ cpu.settings.addr_gran = BYTE;
+ end
+
+ reg [g_num_ports-1:0] clk_ref_phys = 0;
+ time periods[g_num_ports];
+
+
+ generate
+ genvar i;
+
+ for(i=0; i<g_num_ports; i++) begin
+ initial forever #(periods[i]) clk_ref_phys[i] <= ~clk_ref_phys[i];
+ initial periods[i] = 8ns;
+
+ IWishboneMaster U_ep_wb (clk_sys_i, rst_n_i) ;
+ IWishboneMaster #(2,16) U_ep_src (clk_sys_i, rst_n_i) ;
+ IWishboneSlave #(2,16) U_ep_snk (clk_sys_i, rst_n_i) ;
+
+ wr_endpoint #(
+ .g_simulation (1),
+ .g_pcs_16bit (1),
+ .g_rx_buffer_size (1024),
+ .g_with_rx_buffer (0),
+ .g_with_timestamper (1),
+ .g_with_dpi_classifier (1),
+ .g_with_vlans (1),
+ .g_with_rtu (0))
+ DUT (
+ .clk_ref_i (clk_ref_phys[i]),
+ .clk_sys_i (clk_sys_i),
+ .clk_dmtd_i (clk_ref_i),
+ .rst_n_i (rst_n_i),
+ .pps_csync_p1_i (1'b0),
+
+ .phy_rst_o (phys_out[i].rst),
+ .phy_loopen_o (),
+ .phy_enable_o (),
+ .phy_syncen_o (),
+ .phy_rdy_i (phys_rdy[i]),
+
+ .phy_ref_clk_i (phys_in[i].ref_clk),
+ .phy_tx_data_o (phys_out[i].tx_data),
+ .phy_tx_k_o (phys_out[i].tx_k),
+ .phy_tx_disparity_i (phys_in[i].tx_disparity),
+ .phy_tx_enc_err_i (phys_in[i].tx_enc_err),
+
+ .phy_rx_data_i (phys_in[i].rx_data),
+ .phy_rx_clk_i (phys_in[i].rx_clk),
+ .phy_rx_k_i (phys_in[i].rx_k),
+ .phy_rx_enc_err_i (phys_in[i].rx_enc_err),
+ .phy_rx_bitslide_i (5'b0),
+
+ .src_dat_o (U_ep_snk.slave.dat_i),
+ .src_adr_o (U_ep_snk.slave.adr),
+ .src_sel_o (U_ep_snk.slave.sel),
+ .src_cyc_o (U_ep_snk.slave.cyc),
+ .src_stb_o (U_ep_snk.slave.stb),
+ .src_we_o (U_ep_snk.slave.we),
+ .src_stall_i (U_ep_snk.slave.stall),
+ .src_ack_i (U_ep_snk.slave.ack),
+ .src_err_i(1'b0),
+
+ .snk_dat_i (U_ep_src.master.dat_o[15:0]),
+ .snk_adr_i (U_ep_src.master.adr[1:0]),
+ .snk_sel_i (U_ep_src.master.sel[1:0]),
+ .snk_cyc_i (U_ep_src.master.cyc),
+ .snk_stb_i (U_ep_src.master.stb),
+ .snk_we_i (U_ep_src.master.we),
+ .snk_stall_o (U_ep_src.master.stall),
+ .snk_ack_o (U_ep_src.master.ack),
+ .snk_err_o (U_ep_src.master.err),
+ .snk_rty_o (U_ep_src.master.rty),
+
+ .txtsu_ack_i (1'b1),
+ .rtu_full_i (1'b0),
+
+ .wb_cyc_i(U_ep_wb.master.cyc),
+ .wb_stb_i(U_ep_wb.master.stb),
+ .wb_we_i (U_ep_wb.master.we),
+ .wb_sel_i(U_ep_wb.master.sel),
+ .wb_adr_i(U_ep_wb.master.adr[7:0]),
+ .wb_dat_i(U_ep_wb.master.dat_o),
+ .wb_dat_o(U_ep_wb.master.dat_i),
+ .wb_ack_o (U_ep_wb.master.ack),
+
+ // new stuff
+ .pfilter_pclass_o (),
+ .pfilter_drop_o (),
+ .pfilter_done_o (),
+ .fc_tx_pause_req_i (1'b0),
+ .fc_tx_pause_delay_i (16'b0),
+ .fc_tx_pause_ready_o (),
+ .inject_req_i (1'b0),
+ .inject_ready_o (),
+ .inject_packet_sel_i (3'b0),
+ .inject_user_value_i (16'b0),
+ .led_link_o (),
+ .led_act_o (),
+ .link_kill_i ((~ep_ctrl_i[i])),
+ .link_up_o ()
+ );
+
+ initial begin
+ CWishboneAccessor ep_acc;
+ CSimDrv_WR_Endpoint ep_drv;
+
+ U_ep_src.settings.gen_random_throttling = 0;
+ U_ep_snk.settings.gen_random_stalls = 0;
+
+ @(posedge rst_n_i);
+ repeat(100) @(posedge clk_sys_i);
+
+ ep_acc = U_ep_wb.get_accessor();
+ ep_drv = new (ep_acc, 0);
+ ep_drv.init(0);
+
+ from_port[i] = new (U_ep_snk.get_accessor());
+ to_port[i] = new (U_ep_src.get_accessor());
+ end
+ end // for (i=0; i<g_num_ports; i++)
+ endgenerate
+
+ generate
+ genvar j;
+
+ for(j=0;j<g_num_ports;j++) begin
+ assign rbclk[j] = clk_ref_phys[j];
+
+ ///////////////// nasty hack by Maciej /////////////////
+ // causing sync error in the Switch
+// assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : 'h00BC;
+// assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : 2'b01;
+ assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : tx_data_invalid[j];
+ assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : tx_k_invalid[j];
+
+ // causing transmission error in the driving simulation
+ assign phys_in[j].tx_enc_err = ~ep_ctrl_i[j];
+ ///////////////////////////////////////////////////////
+
+ assign phys_in[j].ref_clk = clk_ref_phys[j];
+ assign phys_in[j].rx_data = rd[18 * j + 15 : 18 * j];
+ assign phys_in[j].rx_k = rd[18 * j + 17 : 18 * j + 16];
+ assign phys_in[j].rx_clk = clk_ref_i;
+// assign phys_in[j].tx_enc_err = 0;
+ assign phys_in[j].rx_enc_err = 0;
+
+ always@(posedge clk_ref_i) begin : gen_disparity
+ if(phys_out[j].rst)
+ phys_in[j].tx_disparity = 0;
+ else
+ phys_in[j].tx_disparity = f_next_8b10b_disparity16 (
+ phys_in[j].tx_disparity,
+ phys_out[j].tx_k,
+ phys_out[j].tx_data);
+ end
+
+ always@(posedge clk_sys_i) begin
+ integer jj;
+ if(ep_ctrl_i[j] == 1) begin
+ tx_data_invalid[j] = 'h00BC;
+ tx_k_invalid[j] = 2'b01 ;
+ jj = 0;
+ end
+ else begin
+ if(ep_failure_type == 1) begin
+ $display("Link failure type: 1 [generate some random noise, starting with data='h00BC, k = 'b01]");
+ while(jj++<100) begin
+ tx_data_invalid[j] = 'h00BC + jj;
+ tx_k_invalid[j] = 2'b01 & jj;
+ @(posedge clk_sys_i);
+ end
+ tx_data_invalid[j] = 'h00BC;
+ tx_k_invalid[j] = 2'b01 ;
+ end
+ else begin //including 0
+ $display("Link failure type: 0 [simply off the link: data='h00BC, k = 'b01]");
+ tx_data_invalid[j] = 'h00BC;
+ tx_k_invalid[j] = 2'b01 ;
+ end
+ end;
+ end;
+
+ end //for loop
+
+ endgenerate
+
+ // generate phys_rdy (fifo reset signal)
+ initial begin
+ phys_rdy = 8'hff;
+ @(posedge rst_n_i);
+ repeat(20) @(posedge clk_sys_i);
+ phys_rdy = 8'h00;
+ repeat(20) @(posedge clk_sys_i);
+ phys_rdy = 8'hff;
+ end
+
+ scb_top_sim #(
+ .g_num_ports (g_num_ports),
+ .g_with_TRU (g_with_TRU),
+ .g_with_TATSU (g_with_TATSU),
+ .g_with_HWIU (g_with_HWIU))
+ WRS_Top (
+ .sys_rst_n_i (rst_n_i),
+ .clk_startup_i (clk_sys_i),
+ .clk_ref_i (clk_ref_i),
+ .clk_dmtd_i (clk_ref_i),
+// .clk_sys_i (clk_sys_i),
+ .clk_aux_i (clk_swc_mpm_core_i),
+ .wb_adr_i (cpu.master.adr),
+ .wb_dat_i (cpu.master.dat_o),
+ .wb_dat_o (cpu.master.dat_i),
+ .wb_cyc_i (cpu.master.cyc),
+ .wb_sel_i (cpu.master.sel),
+ .wb_stb_i (cpu.master.stb),
+ .wb_we_i (cpu.master.we),
+ .wb_ack_o (cpu.master.ack),
+ .wb_stall_o (cpu.master.stall),
+ .wb_irq_o (cpu_irq ),
+ .pps_i (1'b0 ),
+ .td_o (rd),
+ .rd_i (td),
+ .rbclk_i (rbclk),
+ .phys_rdy_i (phys_rdy)
+ );
+
+
+endmodule // scb_top_sim_svwrap
+
diff --git a/testbench/scb_top_8p/simdrv_wr_endpoint.svh b/testbench/scb_top_8p/simdrv_wr_endpoint.svh
new file mode 100644
index 00000000..f1ef42eb
--- /dev/null
+++ b/testbench/scb_top_8p/simdrv_wr_endpoint.svh
@@ -0,0 +1,250 @@
+`ifndef __SIMDRV_WR_ENDPOINT_SVH
+`define __SIMDRV_WR_ENDPOINT_SVH 1
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "endpoint_regs.v"
+
+class CSimDrv_WR_Endpoint;
+
+ protected CBusAccessor m_acc;
+ protected uint64_t m_base;
+ protected uint16_t untag_tab[256];
+
+ function new(CBusAccessor acc, uint64_t base);
+ int i;
+ m_acc = acc;
+ m_base = base;
+// for(i=0;i<10;i++)
+// untag_tab[i]=0;
+ endfunction // new
+
+ task vlan_egress_untag(int vid, int untag);
+ uint64_t wval=0;
+ if(untag>0)
+ untag_tab[(vid>>4)] = untag_tab[(vid>>4)] | (1<<('h000F & vid));
+ else
+ untag_tab[(vid>>4)] = untag_tab[(vid>>4)] & ! (1<<('h000F & vid));
+
+ wval = (untag_tab[(vid>>4)] << 10) | ('h000003FF & (vid>>4));
+
+ $display("[vlan_egress_untag], write offset: %d, data: 0x%x (val=0x%x)",
+ (vid>>4),untag_tab[(vid>>4)], wval);
+ m_acc.write(m_base + `ADDR_EP_VCR1, wval);
+
+ // m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
+ endtask // vlan_egress_untag
+
+ task vlan_egress_untag_direct(uint16_t mask, uint16_t addr);
+ uint64_t wval=0;
+ wval = (mask << 10) | ('h000003FF & addr);
+ $display("[vlan_egress_untag], write offset: %d, data: 0x%x ", addr,wval);
+ m_acc.write(m_base + `ADDR_EP_VCR1, wval);
+ endtask // vlan_egress_untag
+
+ task vcr1_buffer_write(int is_vlan, int addr, uint64_t data);
+// $display("addr=0x%x , data=0x%x",addr,data);
+ m_acc.write(m_base + `ADDR_EP_VCR1,
+ (((is_vlan ? 0 : 'h200) + addr) << `EP_VCR1_OFFSET_OFFSET)
+ | (data << `EP_VCR1_DATA_OFFSET));
+ endtask // vlan_buffer_write
+
+ task write_template(int slot, byte data[], int user_offset=-1);
+ int i;
+
+ if(data.size() & 1)
+ $fatal("CSimDrv_WR_Endpoint::write_template(): data size must be even");
+
+ if(user_offset >= data.size()-2)
+ $fatal("CSimDrv_WR_Endpoint::write_template(): user_offset cannot be set to the last word of the template");
+
+ if(user_offset & 1)
+ $fatal("CSimDrv_WR_Endpoint::write_template(): user_offset must be even");
+
+
+ $display("write_template: size %d", data.size());
+
+ for(i=0;i<data.size();i+=2)
+ begin
+ uint64_t v = 0;
+
+ v = ((data[i] << 8) | data[i+1]) & 64'h0000FFFF;
+ if(i == 0)
+ v |= (1<<16); // start of template
+ if(i == data.size() - 2)
+ v |= (1<<16); // end of template
+
+ if(i == user_offset)
+ v |= (1<<17);
+
+ vcr1_buffer_write(0, slot * 64 + i/2, v);
+ end
+ endtask // write_template
+
+ task write_inj_gen_frame(byte header[], int frame_size);
+ int i;
+ int slot = 0;
+
+ if(header.size() & 1)
+ $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): header size must be even");
+ if(frame_size < 64)
+ $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): frame size needs to be greater than 64");
+ if(frame_size > 1024)
+ $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): frame size needs to be less than 1024 (to be modified)");
+
+ $display("write_template: size %d",frame_size);
+
+ frame_size = frame_size -4;//CRC which is automaticly suffixed
+ for(i=0;i<frame_size;i+=2)
+ begin
+ uint64_t v = 0;
+ if(i < header.size())
+ v = ((header[i] << 8) | header[i+1]) & 64'h0000FFFF;
+ else
+ v = 0;
+
+ if(i == 0)
+ v |= (1<<16); // start of template
+
+ if((frame_size & 1) && (i == (frame_size - 1))) // end of template with odd size
+ v |= (1<<16) | (1<<17);
+ else if(i == (frame_size - 2)) // end of template with even size
+ v |= (1<<16);
+
+ if(i == header.size())
+ v |= (1<<17); // place for frame ID
+
+ vcr1_buffer_write(0, slot * 64 + i/2, v);
+ end
+ endtask // write_template
+
+ task pfilter_load_microcode(uint64_t mcode[]);
+ int i;
+
+ for(i=0;i<mcode.size();i++)
+ begin
+ m_acc.write(m_base + `ADDR_EP_PFCR1, (mcode[i] & 'hfff) << `EP_PFCR1_MM_DATA_LSB_OFFSET);
+
+ m_acc.write(m_base + `ADDR_EP_PFCR0,
+ (i << `EP_PFCR0_MM_ADDR_OFFSET) |
+ (((mcode[i] >> 12) & 'hffffff) << `EP_PFCR0_MM_DATA_MSB_OFFSET) |
+ `EP_PFCR0_MM_WRITE);
+
+ $display("code_pos=%2d : PFCR0=0x%4x PFCR1=0x%4x ",i,
+ ((i << `EP_PFCR0_MM_ADDR_OFFSET) |
+ (((mcode[i] >> 12) & 'hffffff) << `EP_PFCR0_MM_DATA_MSB_OFFSET) |
+ `EP_PFCR0_MM_WRITE ),
+ ((mcode[i] & 'hfff) << `EP_PFCR1_MM_DATA_LSB_OFFSET));
+ end
+ $display("pfilter: loaded code [size=%d] ",mcode.size());
+ endtask // pfilter_load_microcde
+
+ task pfilter_enable(int enable);
+ m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0);
+ endtask // pfilter_enable
+
+`define EP_QMODE_VLAN_DISABLED 2
+
+ task init(int port_id);
+ m_acc.write(m_base + `ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN | (port_id << `EP_ECR_PORTID_OFFSET)) ;
+ m_acc.write(m_base + `ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
+ m_acc.write(m_base + `ADDR_EP_VCR0, `EP_QMODE_VLAN_DISABLED << `EP_VCR0_QMODE_OFFSET);
+ m_acc.write(m_base + `ADDR_EP_TSCR, `EP_TSCR_EN_RXTS | `EP_TSCR_EN_TXTS);
+ endtask // init
+
+ task automatic mdio_read(int addr, output int val);
+ uint64_t rval;
+
+ m_acc.write(m_base + `ADDR_EP_MDIO_CR, (addr>>2) << 16, 4);
+ while(1)begin
+ m_acc.read(m_base + `ADDR_EP_MDIO_ASR, rval, 4);
+ if(rval & 'h80000000) begin
+ val = rval & 'hffff;
+ return;
+ end
+
+ end
+ endtask // mdio_read
+
+ task automatic mdio_write(int addr,int val);
+ uint64_t rval;
+
+ m_acc.write(m_base+`ADDR_EP_MDIO_CR, ((addr>>2) << 16) | `EP_MDIO_CR_RW | val);
+ while(1)begin
+ #8ns;
+ m_acc.read(m_base+`ADDR_EP_MDIO_ASR, rval);
+ if(rval & 'h80000000)
+ return;
+ end
+ endtask // automatic
+
+ task automatic check_link(ref int up);
+ reg[31:0] rval;
+ mdio_read(m_base + `ADDR_MDIO_MSR, rval);
+ up= (rval & `MDIO_MSR_LSTATUS) ? 1 : 0;
+ endtask // check_link
+
+ task automatic vlan_config(int qmode,int fix_prio, int prio_val, int pvid, int prio_map[]);
+ uint64_t wval;
+ int i;
+ wval = (qmode << `EP_VCR0_QMODE_OFFSET ) & `EP_VCR0_QMODE |
+ (fix_prio << `EP_VCR0_FIX_PRIO_OFFSET ) & `EP_VCR0_FIX_PRIO |
+ (prio_val << `EP_VCR0_PRIO_VAL_OFFSET ) & `EP_VCR0_PRIO_VAL |
+ (pvid << `EP_VCR0_PVID_OFFSET ) & `EP_VCR0_PVID;
+
+ m_acc.write(m_base + `ADDR_EP_VCR0, wval);
+ wval = 0;
+ for(i=0;i<8;i++)
+ wval = ('h7 & prio_map[i]) << (i*3) | wval;
+
+ m_acc.write(m_base + `ADDR_EP_TCAR, `EP_TCAR_PCP_MAP & (wval << `EP_TCAR_PCP_MAP_OFFSET));
+
+ $display("VLAN cofig: qmode=%1d, fix_prio=%1d, prio_val=%1d, pvid=%1d, prio_map=%1d-%1d-%1d-%1d-%1d-%1d-%1d-%1d",
+ qmode,fix_prio, prio_val, pvid, prio_map[7],prio_map[6],prio_map[5],prio_map[4],
+ prio_map[3],prio_map[2],prio_map[1],prio_map[0]);
+ endtask // automatic
+
+ task automatic pause_config(int txpause_802_3,int rxpause_802_3, int txpause_802_1q, int rxpause_802_1q);
+ uint64_t wval;
+ wval = (txpause_802_1q << `EP_FCR_TXPAUSE_802_1Q_OFFSET) & `EP_FCR_TXPAUSE_802_1Q | // Tx
+ (rxpause_802_1q << `EP_FCR_RXPAUSE_802_1Q_OFFSET) & `EP_FCR_RXPAUSE_802_1Q | // Rx
+ (txpause_802_3 << `EP_FCR_TXPAUSE_OFFSET ) & `EP_FCR_TXPAUSE | // Tx
+ (rxpause_802_3 << `EP_FCR_RXPAUSE_OFFSET ) & `EP_FCR_RXPAUSE; // Rx
+ m_acc.write(m_base + `ADDR_EP_FCR, wval);
+ $display("PAUSE cofig: tx_802.3 en=%1d, rx_802.3 en=%1d, tx_801.2Q (prio-based)=%1d, rx_802.1Q (prio-based)=%1d",
+ txpause_802_3, rxpause_802_3, txpause_802_1q, rxpause_802_1q);
+ endtask // automatic
+
+ task automatic inject_gen_ctrl_config(int interframe_gap, int sel_id, int mode);
+ uint64_t wval = 0;
+ wval = (interframe_gap << `EP_INJ_CTRL_PIC_CONF_IFG_OFFSET) & `EP_INJ_CTRL_PIC_CONF_IFG |
+ (sel_id << `EP_INJ_CTRL_PIC_CONF_SEL_OFFSET) & `EP_INJ_CTRL_PIC_CONF_SEL |
+ (mode << `EP_INJ_CTRL_PIC_MODE_ID_OFFSET ) & `EP_INJ_CTRL_PIC_MODE_ID_OFFSET |
+ `EP_INJ_CTRL_PIC_CONF_VALID | `EP_INJ_CTRL_PIC_MODE_VALID;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: interframe gap=%1d, pattern sel id=%1d, mode = %1d",interframe_gap,sel_id, mode);
+ endtask // automatic
+ task automatic inject_gen_ctrl_enable();
+ uint64_t wval = 0;
+ wval = `EP_INJ_CTRL_PIC_ENA;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: enabled");
+ endtask // automatic
+ task automatic inject_gen_ctrl_disable();
+ uint64_t wval = 0;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: disabled");
+ endtask // automatic
+
+ task automatic inject_gen_ctrl_mode(int mode );
+ uint64_t wval = 0;
+ wval = (mode << `EP_INJ_CTRL_PIC_MODE_ID_OFFSET ) & `EP_INJ_CTRL_PIC_MODE_ID |
+ `EP_INJ_CTRL_PIC_MODE_VALID | `EP_INJ_CTRL_PIC_ENA;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: mode = %1d",mode);
+ endtask // automatic
+
+
+endclass // CSimDrv_WR_Endpoint
+
+`endif // `ifndef __SIMDRV_WR_ENDPOINT_SVH
diff --git a/testbench/scb_top_8p/wave.do b/testbench/scb_top_8p/wave.do
new file mode 100644
index 00000000..95d7edd9
--- /dev/null
+++ b/testbench/scb_top_8p/wave.do
@@ -0,0 +1,216 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/phys_rdy
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_dat_i}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_adr_i}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_sel_i}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_cyc_i}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_stb_i}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_we_i}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_stall_o}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_ack_o}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_err_o}
+add wave -noupdate -group TB_EP -expand -group EP0 {/main/DUT/genblk1[0]/DUT/snk_rty_o}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_dat_i}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_adr_i}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_sel_i}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_cyc_i}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_stb_i}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_we_i}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_stall_o}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_ack_o}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_err_o}
+add wave -noupdate -group TB_EP -expand -group EP1 {/main/DUT/genblk1[1]/DUT/snk_rty_o}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_dat_i}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_adr_i}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_sel_i}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_cyc_i}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_stb_i}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_we_i}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_stall_o}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_ack_o}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_err_o}
+add wave -noupdate -group TB_EP -expand -group EP6 {/main/DUT/genblk1[6]/DUT/snk_rty_o}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_dat_i}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_adr_i}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_sel_i}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_cyc_i}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_stb_i}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_we_i}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_stall_o}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_ack_o}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_err_o}
+add wave -noupdate -group TB_EP -expand -group EP7 {/main/DUT/genblk1[7]/DUT/snk_rty_o}
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/dbg_rtu_bug(0)
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/rtu_req(0).valid
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/rtu_rsp_ack(0)
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rxbuf_full
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe
+add wave -noupdate -expand -group EP0 -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/state
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/sof_reg
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/snk_fab_i.sof
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RX_Wishbone_Master/snk_dreq_o
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_in.stall
+add wave -noupdate -expand -group EP0 -expand /main/DUT/WRS_Top/U_Wrapped_SCBCore/endpoint_src_out(0)
+add wave -noupdate -expand -group EP0 -expand /main/DUT/WRS_Top/U_Wrapped_SCBCore/endpoint_src_in(0)
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/endpoint_snk_in(0)
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/endpoint_snk_out(0)
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_full_i
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_almost_full_i
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_strobe_p1_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_abort_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_smac_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_dmac_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_vid_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_has_vid_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_prio_o
+add wave -noupdate -expand -group EP0 -expand -group rtu_req(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/rtu_rq_has_prio_o
+add wave -noupdate -expand -group EP0 -expand /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp(0)
+add wave -noupdate -expand -group EP0 /main/clk_sys
+add wave -noupdate -expand -group EP0 -group RTU_port -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_state
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_str_config_i.dop_on_fmatch_full
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/drop
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/dbg_fwd_mask
+add wave -noupdate -expand -group EP0 -group RTU_port -expand /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/nice_dbg_o
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_aboard
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_aboard_d
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_valid_reg
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_valid_reg
+add wave -noupdate -expand -group EP0 -group RTU_port -group FULL_MATCH /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_write_o
+add wave -noupdate -expand -group EP0 -group RTU_port -group FULL_MATCH -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/mstate
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_in.valid
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_rsp_cnt
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_req_in_progress
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -expand -group EP0 -group RTU_port -expand /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_o
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match
+add wave -noupdate -expand -group EP0 -group RTU_port /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/nomem_cnt
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/nomem_trig
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/reset_mode
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/rst_cnt
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/rst_trig
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/rst_trig_d0
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/swcrst_n_o
+add wave -noupdate -expand -group EP0 -expand -group Watchdog /main/DUT/WRS_Top/U_Wrapped_SCBCore/GEN_SWC_RST/WDOG/wb_regs_out.cr_port_load_o
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/nomem_o
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/res_full_o
+add wave -noupdate -expand -group EP0 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/res_almost_full_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/dbg_rtu_cnt(0)
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/swc_dbg.ib(0).sof_cnt
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -radix unsigned /main/DUT/WRS_Top/U_Wrapped_SCBCore/dbg_cnt_eq(0)
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -radix unsigned /main/DUT/WRS_Top/U_Wrapped_SCBCore/dbg_cnt_dif(0)
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/dbg_rtu_bug(0)
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/hwiu_dbg1
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/hwiu_dbg2
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/hwiu_val1
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/hwiu_val2
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_o.stall
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_ff_done_reg
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ffree_mask
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ffree_pre_mask
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rcv_pckstart_new
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pcknew_reg
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/new_pck_first_page_ack
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/new_pck_first_page_p1
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_ll_stored
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/dbg_last_ffreed_pg
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -childformat {{/main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry.size -radix unsigned}} -expand -subitemconfig {/main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry.size {-radix unsigned}} /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input -radix unsigned /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_reg
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_reg_ack
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/nice_dbg_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -expand -group EP0 -expand -group SWC_Input /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_nomem
+add wave -noupdate /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_i
+add wave -noupdate /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_done_o
+add wave -noupdate /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ports(0)
+add wave -noupdate /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/clk_i
+add wave -noupdate /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/grant_ib_d0
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/initializing
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_o
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_write_p1
+add wave -noupdate -group PAGE_ALLOC -radix unsigned /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_pages
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_i
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_req_d0.alloc
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_alloc_done
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_read_p0
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/out_nomem
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/out_nomem_d0
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/out_nomem_d1
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/pg_adv_valid
+add wave -noupdate -group PAGE_ALLOC /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rd_ptr_p0
+add wave -noupdate -expand -group FREE(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_i
+add wave -noupdate -expand -group FREE(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_done_o
+add wave -noupdate -expand -group FREE(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_pgaddr_i
+add wave -noupdate -expand -group FREE(0) -height 16 /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/state
+add wave -noupdate -expand -group FREE(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_full
+add wave -noupdate -expand -group FREE(0) /main/DUT/WRS_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_clean
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {104100070290 fs} 1} {{Cursor 2} {115415611850 fs} 1}
+configure wave -namecolwidth 264
+configure wave -valuecolwidth 40
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 fs} {166723200 ps}
--
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