diff --git a/Manifest.py b/Manifest.py
index 10f16a3a0969ac09a13bf6070d8b75de3ad898c9..534dd435a368164d3b53133f6c86602da6fae2f2 100644
--- a/Manifest.py
+++ b/Manifest.py
@@ -4,6 +4,10 @@ modules = { "local" : [
"modules/wrsw_txtsu",
"modules/wrsw_swcore",
"modules/wrsw_rtu",
+ "modules/wrsw_tru",
+ "modules/wrsw_tatsu",
+ "modules/wrsw_pstats",
+ "modules/wrsw_hwdu",
"modules/wrsw_hwiu",
"platform/virtex6/chipscope",
"platform/xilinx"],
diff --git a/ip_cores/general-cores b/ip_cores/general-cores
index 4beed175b6d89016320eda0881f6dc6f18fafbca..7e96fdf781836afc781c1346ed6705026b76d018 160000
--- a/ip_cores/general-cores
+++ b/ip_cores/general-cores
@@ -1 +1 @@
-Subproject commit 4beed175b6d89016320eda0881f6dc6f18fafbca
+Subproject commit 7e96fdf781836afc781c1346ed6705026b76d018
diff --git a/ip_cores/wr-cores b/ip_cores/wr-cores
index 0aafd085c14f0629a9ae4dce6e3efaacb48d8f43..6294a6abe1545b0c8813f253ab15c0c87062dc7c 160000
--- a/ip_cores/wr-cores
+++ b/ip_cores/wr-cores
@@ -1 +1 @@
-Subproject commit 0aafd085c14f0629a9ae4dce6e3efaacb48d8f43
+Subproject commit 6294a6abe1545b0c8813f253ab15c0c87062dc7c
diff --git a/modules/wrsw_hwdu/Manifest.py b/modules/wrsw_hwdu/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..6d820d21e948614094c718705a14e5a44e0c2e9e
--- /dev/null
+++ b/modules/wrsw_hwdu/Manifest.py
@@ -0,0 +1 @@
+files = ["wrsw_hwdu.vhd", "hwdu_wishbone_slave.vhd", "hwdu_wbgen2_pkg.vhd", "xwrsw_hwdu.vhd"]
diff --git a/modules/wrsw_hwdu/build_wb.sh b/modules/wrsw_hwdu/build_wb.sh
new file mode 100755
index 0000000000000000000000000000000000000000..bde48abfca3dae5eabfb804986fc58b8a445dcfb
--- /dev/null
+++ b/modules/wrsw_hwdu/build_wb.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+
+mkdir -p doc
+wbgen2 -D ./doc/wrsw_hwdu.html -C hwdu_regs.h -V hwdu_wishbone_slave.vhd --cstyle struct --lang vhdl -K ../../sim/regs/hwdu_regs.vh -p hwdu_wbgen2_pkg.vhd --hstyle record wrsw_hwdu.wb
diff --git a/modules/wrsw_hwdu/doc/wrsw_hwdu.html b/modules/wrsw_hwdu/doc/wrsw_hwdu.html
new file mode 100644
index 0000000000000000000000000000000000000000..6592c719b994d780cee37a16f6038cd14cbc7348
--- /dev/null
+++ b/modules/wrsw_hwdu/doc/wrsw_hwdu.html
@@ -0,0 +1,816 @@
+<HTML>
+<HEAD>
+<TITLE>hwdu_wishbone_slave</TITLE>
+<STYLE TYPE="text/css" MEDIA="all">
+
+ <!--
+ BODY { background: white; color: black;
+ font-family: Arial,Helvetica; font-size:12; }
+ h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
+ h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
+ h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
+ .td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
+ .td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
+ .td_code { font-family:Courier New,Courier; padding: 3px; }
+ .td_desc { padding: 3px; }
+ .td_sym_center { background: #e0e0f0; padding: 3px; }
+ .td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
+ .td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
+ .td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
+ .td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
+ .td_field { background: #e0e0f0; padding: 3px; text-align:center; }
+ .td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
+ th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
+ .tr_even { background: #f0eff0; }
+ .tr_odd { background: #e0e0f0; }
+ -->
+</STYLE>
+</HEAD>
+<BODY>
+<h1 class="heading">hwdu_wishbone_slave</h1>
+<h3>WR Switch Hardware Debugging Unit</h3>
+<p>The module is used for reading the value of registers from inside of WR Switch. Usefull for debugging during development.</p>
+<h3>Contents:</h3>
+<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
+<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
+<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
+<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Control Register</a></span><br/>
+<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Value of the requested register</a></span><br/>
+<h3><a name="sect_1_0">1. Memory map summary</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<th >
+H/W Address
+</th>
+<th >
+Type
+</th>
+<th >
+Name
+</th>
+<th >
+VHDL/Verilog prefix
+</th>
+<th >
+C prefix
+</th>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x0
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#CR">Control Register</a>
+</td>
+<td class="td_code">
+hwdu_cr
+</td>
+<td class="td_code">
+CR
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x1
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#REG_VAL">Value of the requested register</a>
+</td>
+<td class="td_code">
+hwdu_reg_val
+</td>
+<td class="td_code">
+REG_VAL
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_2_0">2. HDL symbol</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+rst_n_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Control Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+clk_sys_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+hwdu_cr_adr_o[15:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_adr_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+hwdu_cr_rd_err_i
+</td>
+<td class="td_arrow_right">
+←
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇒
+</td>
+<td class="td_pblock_left">
+wb_dat_i[31:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+hwdu_cr_rd_en_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇐
+</td>
+<td class="td_pblock_left">
+wb_dat_o[31:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+hwdu_cr_rd_en_i
+</td>
+<td class="td_arrow_right">
+←
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_cyc_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+hwdu_cr_rd_en_load_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇒
+</td>
+<td class="td_pblock_left">
+wb_sel_i[3:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_stb_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Value of the requested register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_we_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+hwdu_reg_val_i[31:0]
+</td>
+<td class="td_arrow_right">
+⇐
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+←
+</td>
+<td class="td_pblock_left">
+wb_ack_o
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+←
+</td>
+<td class="td_pblock_left">
+wb_stall_o
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_3_0">3. Register description</a></h3>
+<a name="CR"></a>
+<h3><a name="sect_3_1">3.1. Control Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+hwdu_cr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x0
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+CR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x0
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+RD_EN
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+RD_ERR
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+ADR[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+ADR[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+ADR
+</b>[<i>read/write</i>]: Address of the register
+<br>Which register (among those connected to HWDU) will be read
+<li><b>
+RD_ERR
+</b>[<i>read-only</i>]: Read error
+<br>read 1: read error, provided address is out of range <br> read 0: read done successfully
+<li><b>
+RD_EN
+</b>[<i>read/write</i>]: Read register value
+<br>write 1: read the content <br> write 0: no effect <br> read 1: reading in progress <br> read 0: reading done, register value available
+</ul>
+<a name="REG_VAL"></a>
+<h3><a name="sect_3_2">3.2. Value of the requested register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+hwdu_reg_val
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x1
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+REG_VAL
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x4
+</td>
+</tr>
+</table>
+<p>
+The value of the register under ADR from the Control Register
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+REG_VAL[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+REG_VAL[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+REG_VAL[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+REG_VAL[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+REG_VAL
+</b>[<i>read-only</i>]: register value
+</ul>
+
+
+
+</BODY>
+</HTML>
diff --git a/modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd b/modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5c55edffdb99d859a80593c86a784d019ee1d0e5
--- /dev/null
+++ b/modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd
@@ -0,0 +1,83 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR Switch Hardware Debugging Unit
+---------------------------------------------------------------------------------------
+-- File : hwdu_wbgen2_pkg.vhd
+-- Author : auto-generated by wbgen2 from wrsw_hwdu.wb
+-- Created : Mon Nov 11 09:11:51 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwdu.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package hwdu_wbgen2_pkg is
+
+
+ -- Input registers (user design -> WB slave)
+
+ type t_hwdu_in_registers is record
+ cr_rd_err_i : std_logic;
+ cr_rd_en_i : std_logic;
+ reg_val_i : std_logic_vector(31 downto 0);
+ end record;
+
+ constant c_hwdu_in_registers_init_value: t_hwdu_in_registers := (
+ cr_rd_err_i => '0',
+ cr_rd_en_i => '0',
+ reg_val_i => (others => '0')
+ );
+
+ -- Output registers (WB slave -> user design)
+
+ type t_hwdu_out_registers is record
+ cr_adr_o : std_logic_vector(15 downto 0);
+ cr_rd_en_o : std_logic;
+ cr_rd_en_load_o : std_logic;
+ chps_id_o : std_logic_vector(7 downto 0);
+ end record;
+
+ constant c_hwdu_out_registers_init_value: t_hwdu_out_registers := (
+ cr_adr_o => (others => '0'),
+ cr_rd_en_o => '0',
+ cr_rd_en_load_o => '0',
+ chps_id_o => (others => '0')
+ );
+ function "or" (left, right: t_hwdu_in_registers) return t_hwdu_in_registers;
+ function f_x_to_zero (x:std_logic) return std_logic;
+ function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body hwdu_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if;
+end loop;
+return tmp;
+end function;
+function "or" (left, right: t_hwdu_in_registers) return t_hwdu_in_registers is
+variable tmp: t_hwdu_in_registers;
+begin
+tmp.cr_rd_err_i := f_x_to_zero(left.cr_rd_err_i) or f_x_to_zero(right.cr_rd_err_i);
+tmp.cr_rd_en_i := f_x_to_zero(left.cr_rd_en_i) or f_x_to_zero(right.cr_rd_en_i);
+tmp.reg_val_i := f_x_to_zero(left.reg_val_i) or f_x_to_zero(right.reg_val_i);
+return tmp;
+end function;
+end package body;
diff --git a/modules/wrsw_hwdu/hwdu_wishbone_slave.vhd b/modules/wrsw_hwdu/hwdu_wishbone_slave.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1a1b9789c8b83934a84fb1378924e78546802829
--- /dev/null
+++ b/modules/wrsw_hwdu/hwdu_wishbone_slave.vhd
@@ -0,0 +1,172 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR Switch Hardware Debugging Unit
+---------------------------------------------------------------------------------------
+-- File : hwdu_wishbone_slave.vhd
+-- Author : auto-generated by wbgen2 from wrsw_hwdu.wb
+-- Created : Mon Nov 11 09:11:51 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwdu.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.hwdu_wbgen2_pkg.all;
+
+
+entity hwdu_wishbone_slave is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(1 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ regs_i : in t_hwdu_in_registers;
+ regs_o : out t_hwdu_out_registers
+ );
+end hwdu_wishbone_slave;
+
+architecture syn of hwdu_wishbone_slave is
+
+signal hwdu_cr_adr_int : std_logic_vector(15 downto 0);
+signal hwdu_chps_id_int : std_logic_vector(7 downto 0);
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(1 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_dat_i;
+ bwsel_reg <= wb_sel_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ hwdu_cr_adr_int <= "0000000000000000";
+ regs_o.cr_rd_en_load_o <= '0';
+ hwdu_chps_id_int <= "00000000";
+ elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ regs_o.cr_rd_en_load_o <= '0';
+ ack_in_progress <= '0';
+ else
+ regs_o.cr_rd_en_load_o <= '0';
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(1 downto 0) is
+ when "00" =>
+ if (wb_we_i = '1') then
+ hwdu_cr_adr_int <= wrdata_reg(15 downto 0);
+ regs_o.cr_rd_en_load_o <= '1';
+ end if;
+ rddata_reg(15 downto 0) <= hwdu_cr_adr_int;
+ rddata_reg(30) <= regs_i.cr_rd_err_i;
+ rddata_reg(31) <= regs_i.cr_rd_en_i;
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.reg_val_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "10" =>
+ if (wb_we_i = '1') then
+ hwdu_chps_id_int <= wrdata_reg(7 downto 0);
+ end if;
+ rddata_reg(7 downto 0) <= hwdu_chps_id_int;
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Drive the data output bus
+ wb_dat_o <= rddata_reg;
+-- Address of the register
+ regs_o.cr_adr_o <= hwdu_cr_adr_int;
+-- Read error
+-- Read register value
+ regs_o.cr_rd_en_o <= wrdata_reg(31);
+-- register value
+-- MUX ID
+ regs_o.chps_id_o <= hwdu_chps_id_int;
+ rwaddr_reg <= wb_adr_i;
+ wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/modules/wrsw_hwdu/wrsw_hwdu.vhd b/modules/wrsw_hwdu/wrsw_hwdu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..60a83156c29db5a553e6312b169f660a0776b7d2
--- /dev/null
+++ b/modules/wrsw_hwdu/wrsw_hwdu.vhd
@@ -0,0 +1,144 @@
+-------------------------------------------------------------------------------
+-- Title : Hardware Debugging Unit
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : wrsw_hwdu.vhd
+-- Author : Grzegorz Daniluk
+-- Company : CERN BE-CO-HT
+-- Created : 2013-03-26
+-- Last update: 2013-03-26
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Debugging module, allows reading the content of selected registers inside
+-- WR Switch GW through Wishbone interface.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2013-03-26 0.1 greg.d Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.hwdu_wbgen2_pkg.all;
+
+entity wrsw_hwdu is
+ generic (
+ g_nregs : integer := 1;
+ g_rwidth : integer := 32);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+ dbg_chps_id_o : out std_logic_vector(7 downto 0);
+
+ wb_adr_i : in std_logic_vector(1 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic);
+end wrsw_hwdu;
+
+architecture behav of wrsw_hwdu is
+
+ component hwdu_wishbone_slave
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(1 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ regs_i : in t_hwdu_in_registers;
+ regs_o : out t_hwdu_out_registers
+ );
+ end component;
+
+ signal wb_regs_in : t_hwdu_in_registers;
+ signal wb_regs_out : t_hwdu_out_registers;
+
+ type t_rd_st is (IDLE, READ);
+ signal rd_state : t_rd_st;
+
+ signal rd_val : std_logic_vector(g_rwidth-1 downto 0);
+ signal rd_err, rd_en : std_logic;
+
+begin
+
+ U_WB_Slave : hwdu_wishbone_slave
+ port map(
+ rst_n_i => rst_n_i,
+ clk_sys_i => clk_i,
+ wb_adr_i => wb_adr_i,
+ wb_dat_i => wb_dat_i,
+ wb_dat_o => wb_dat_o,
+ wb_cyc_i => wb_cyc_i,
+ wb_sel_i => wb_sel_i,
+ wb_stb_i => wb_stb_i,
+ wb_we_i => wb_we_i,
+ wb_ack_o => wb_ack_o,
+ wb_stall_o => wb_stall_o,
+ regs_i => wb_regs_in,
+ regs_o => wb_regs_out
+ );
+ wb_int_o <= '0';
+
+ wb_regs_in.reg_val_i(g_rwidth-1 downto 0) <= rd_val;
+ GEN_regval : if g_rwidth < 32 generate
+ wb_regs_in.reg_val_i(31 downto g_rwidth) <= (others => '0');
+ end generate;
+
+ wb_regs_in.cr_rd_err_i <= rd_err;
+ wb_regs_in.cr_rd_en_i <= rd_en;
+
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ rd_state <= IDLE;
+ rd_en <= '0';
+ rd_err <= '0';
+ else
+ case(rd_state) is
+ when IDLE =>
+ if(wb_regs_out.cr_rd_en_o = '1' and wb_regs_out.cr_rd_en_load_o = '1') then
+ rd_en <= '1';
+ rd_state <= READ;
+ end if;
+ when READ =>
+ rd_en <= '0';
+ rd_state <= IDLE;
+ if(to_integer(unsigned(wb_regs_out.cr_adr_o)) > g_nregs-1) then
+ rd_err <= '1';
+ else
+ rd_err <= '0';
+ --get part of dbg_regs input vector
+ rd_val <= dbg_regs_i((to_integer(unsigned(wb_regs_out.cr_adr_o))+1)*g_rwidth-1 downto
+ to_integer(unsigned(wb_regs_out.cr_adr_o))*g_rwidth);
+ end if;
+
+ when others =>
+ rd_state <= IDLE;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ dbg_chps_id_o <= wb_regs_out.chps_id_o;
+
+end behav;
diff --git a/modules/wrsw_hwdu/wrsw_hwdu.wb b/modules/wrsw_hwdu/wrsw_hwdu.wb
new file mode 100644
index 0000000000000000000000000000000000000000..26d399585c2910f08a1c006182260c1b34c55849
--- /dev/null
+++ b/modules/wrsw_hwdu/wrsw_hwdu.wb
@@ -0,0 +1,86 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+-- White-Rabbit Hardware Debugging Unit
+-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+--
+-- Use wbgen2 to generate code, documentation and more.
+-- wbgen2 is available at:
+-- http://www.ohwr.org/projects/wishbone-gen
+--
+
+peripheral {
+
+ name = "WR Switch Hardware Debugging Unit";
+ description = "The module is used for reading the value of registers from inside of WR Switch. Usefull for debugging during development.";
+ hdl_entity = "hwdu_wishbone_slave";
+ prefix = "hwdu";
+
+
+ reg {
+ name = "Control Register";
+ prefix = "CR";
+
+ field {
+ name = "Address of the register";
+ description = "Which register (among those connected to HWDU) will be read";
+ prefix = "ADR";
+ size = 16;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Read error";
+ description = "read 1: read error, provided address is out of range \
+ read 0: read done successfully";
+ prefix = "RD_ERR";
+ type = BIT;
+ align = 30;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+ field {
+ name = "Read register value";
+ description = "write 1: read the content \
+ write 0: no effect \
+ read 1: reading in progress \
+ read 0: reading done, register value available";
+ prefix = "RD_EN";
+
+ type = BIT;
+ align = 31;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+ };
+
+ reg {
+ name = "Value of the requested register";
+ description = "The value of the register under ADR from the Control Register";
+ prefix = "REG_VAL";
+
+ field {
+ name = "register value";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+ reg {
+ name = "Choose Chipscope input";
+ description = "Single chipscope module is connected to a MUX, this register is used to contol the MUX";
+ prefix = "CHPS_ID";
+
+ field {
+ name = "MUX ID";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+};
diff --git a/modules/wrsw_hwdu/xwrsw_hwdu.vhd b/modules/wrsw_hwdu/xwrsw_hwdu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..edc2dc0decefc2cb3027b609cce0ee3c999073ec
--- /dev/null
+++ b/modules/wrsw_hwdu/xwrsw_hwdu.vhd
@@ -0,0 +1,114 @@
+-------------------------------------------------------------------------------
+-- Title : Hardware Debugging Unit wrapper
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : xwrsw_hwdu.vhd
+-- Author : Grzegorz Daniluk
+-- Company : CERN BE-CO-HT
+-- Created : 2013-03-26
+-- Last update: 2013-03-26
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Record-based wrapper for wrsw_hwdu module.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2013-03-26 0.1 greg.d Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+entity xwrsw_hwdu is
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nregs : integer := 1;
+ g_rwidth : integer := 32);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+ dbg_chps_id_o : out std_logic_vector(7 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+end xwrsw_hwdu;
+
+architecture behav of xwrsw_hwdu is
+
+ component wrsw_hwdu
+ generic (
+ g_nregs : integer := 1;
+ g_rwidth : integer := 32);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+ dbg_chps_id_o : out std_logic_vector(7 downto 0);
+
+ wb_adr_i : in std_logic_vector(1 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic);
+ end component;
+
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+
+begin
+
+ U_Adapter : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => true,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_i,
+ rst_n_i => rst_n_i,
+ slave_i => wb_i,
+ slave_o => wb_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ wb_out.err <= '0';
+ wb_out.rty <= '0';
+
+ U_Wrapped_HWDU : wrsw_hwdu
+ generic map(
+ g_nregs => g_nregs,
+ g_rwidth => g_rwidth)
+ port map(
+ rst_n_i => rst_n_i,
+ clk_i => clk_i,
+ dbg_regs_i => dbg_regs_i,
+ dbg_chps_id_o => dbg_chps_id_o,
+ wb_adr_i => wb_in.adr(1 downto 0),
+ wb_dat_i => wb_in.dat,
+ wb_dat_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
+ wb_stall_o => wb_out.stall,
+ wb_int_o => wb_out.int
+ );
+
+end behav;
diff --git a/modules/wrsw_nic/nic_buffer.vhd b/modules/wrsw_nic/nic_buffer.vhd
index e949a7d1e60a1c3aa415783f4047868a2eb955ba..0a897bd29e8d140f2674a7955f9635ad63224b21 100644
--- a/modules/wrsw_nic/nic_buffer.vhd
+++ b/modules/wrsw_nic/nic_buffer.vhd
@@ -76,9 +76,10 @@ begin -- syn
RAM : generic_dpram
generic map (
- g_data_width => 32,
- g_size => 2**g_memsize_log2,
- g_dual_clock => false)
+ g_data_width => 32,
+ g_size => 2**g_memsize_log2,
+ g_dual_clock => false,
+ g_with_byte_enable => false)
port map (
-- host port
rst_n_i => rst_n_i,
diff --git a/modules/wrsw_nic/nic_descriptor_manager.vhd b/modules/wrsw_nic/nic_descriptor_manager.vhd
index ce5db2468553ede0d9308917fdbf4006b1762345..720b0941a37101a65ba3f8d8157783688aadcdab 100644
--- a/modules/wrsw_nic/nic_descriptor_manager.vhd
+++ b/modules/wrsw_nic/nic_descriptor_manager.vhd
@@ -28,13 +28,12 @@ library work;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
-
-
entity nic_descriptor_manager is
generic (
g_desc_mode : string := "tx";
g_num_descriptors : integer;
- g_num_descriptors_log2 : integer);
+ g_num_descriptors_log2 : integer;
+ g_port_mask_bits : integer := 32); --worth using only in TX mode
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -77,7 +76,7 @@ end nic_descriptor_manager;
architecture behavioral of nic_descriptor_manager is
- type t_desc_arb_state is (ARB_DISABLED, ARB_START_SCAN, ARB_CHECK_EMPTY, ARB_FETCH, ARB_GRANT, ARB_UPDATE, ARB_WRITE_DESC);
+ type t_desc_arb_state is (ARB_START_SCAN, ARB_CHECK_EMPTY, ARB_FETCH, ARB_GRANT, ARB_UPDATE, ARB_WRITE_DESC);
signal state : t_desc_arb_state;
@@ -85,15 +84,8 @@ architecture behavioral of nic_descriptor_manager is
signal granted_desc_tx : t_tx_descriptor;
signal granted_desc_rx : t_rx_descriptor;
- signal granted_desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
- signal desc_idx_d0 : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_subreg : unsigned(1 downto 0);
- signal cntr : unsigned(1 downto 0);
-
- signal check_count : unsigned(g_num_descriptors_log2 downto 0);
- signal stupid_hack : std_logic;
-
impure function f_write_marshalling(index : integer)
return std_logic_vector is
@@ -112,6 +104,15 @@ begin -- behavioral
cur_desc_idx_o <= std_logic_vector(desc_idx);
+ --GD can do that, those outputs are validated by desc_grant_o
+ --and nic_rx_fsm stores it in internal register too
+ GEN_TXDESC_CUR: if g_desc_mode = "tx" generate
+ txdesc_current_o <= granted_desc_tx;
+ end generate;
+ GEN_RXDESC_CUR: if g_desc_mode = "rx" generate
+ rxdesc_current_o <= granted_desc_rx;
+ end generate;
+
p_rxdesc_arbiter : process(clk_sys_i, rst_n_i)
variable tmp_desc_rx : t_rx_descriptor;
variable tmp_desc_tx : t_tx_descriptor;
@@ -121,7 +122,7 @@ begin -- behavioral
if(rst_n_i = '0') then
desc_write_done_o <= '0';
desc_grant_o <= '0';
- state <= ARB_DISABLED;
+ state <= ARB_START_SCAN;
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
dtbl_wr_o <= '0';
@@ -130,36 +131,24 @@ begin -- behavioral
else
case state is
- when ARB_DISABLED =>
- desc_idx <= (others => '0');
- desc_subreg <= (others => '0');
-
- if(enable_i = '1') then
--- dtbl_rd_o <= '1';
- state <= ARB_START_SCAN;
- desc_idx <= (others => '0');
- check_count <= (others => '0');
- end if;
-
when ARB_START_SCAN =>
-
- if(enable_i = '0') then
- state <= ARB_DISABLED;
+ desc_subreg <= (others => '0');
+ dtbl_wr_o <= '0';
+ if(enable_i = '1') then
+ state <= ARB_CHECK_EMPTY;
else
- -- wait until the current descriptor is read from the memorry
- state <= ARB_CHECK_EMPTY;
--- dtbl_rd_o <='1';
- dtbl_wr_o <= '0';
+ desc_idx <= (others => '0');
end if;
when ARB_CHECK_EMPTY =>
- p_unmarshall_rx_descriptor(dtbl_data_i, 1, tmp_desc_rx);
- p_unmarshall_tx_descriptor(dtbl_data_i, 1, tmp_desc_tx);
+ dtbl_wr_o <= '0';
+ tmp_desc_rx := f_unmarshall_rx_descriptor(dtbl_data_i, 1);
+ tmp_desc_tx := f_unmarshall_tx_descriptor(dtbl_data_i, 1);
+ granted_desc_tx <= tmp_desc_tx;
+ granted_desc_rx <= tmp_desc_rx;
if((tmp_desc_rx.empty = '1' and g_desc_mode = "rx") or (tmp_desc_tx.ready = '1' and g_desc_mode = "tx")) then
- granted_desc_tx <= tmp_desc_tx;
- granted_desc_rx <= tmp_desc_rx;
desc_subreg <= "01";
state <= ARB_FETCH;
bna_o <= '0';
@@ -168,21 +157,22 @@ begin -- behavioral
end if;
when ARB_FETCH =>
+ dtbl_wr_o <= '0';
case desc_subreg is
when "10" => -- ignore the timestamps for RX
-- descriptors (they're
-- write-only by the NIC)
- p_unmarshall_tx_descriptor(dtbl_data_i, 2, tmp_desc_tx);
+ tmp_desc_tx := f_unmarshall_tx_descriptor(dtbl_data_i, 2);
granted_desc_tx.len <= tmp_desc_tx.len;
granted_desc_tx.offset <= tmp_desc_tx.offset;
when "11" =>
- p_unmarshall_tx_descriptor(dtbl_data_i, 3, tmp_desc_tx); -- TX
- granted_desc_tx.dpm <= tmp_desc_tx.dpm;
+ tmp_desc_tx := f_unmarshall_tx_descriptor(dtbl_data_i, 3); -- TX
+ granted_desc_tx.dpm(g_port_mask_bits-1 downto 0) <= tmp_desc_tx.dpm(g_port_mask_bits-1 downto 0);
- p_unmarshall_rx_descriptor(dtbl_data_i, 3, tmp_desc_rx); -- RX
+ tmp_desc_rx := f_unmarshall_rx_descriptor(dtbl_data_i, 3); -- RX
granted_desc_rx.len <= tmp_desc_rx.len;
granted_desc_rx.offset <= tmp_desc_rx.offset;
@@ -193,67 +183,46 @@ begin -- behavioral
desc_subreg <= desc_subreg + 1;
when ARB_GRANT =>
+ dtbl_wr_o <= '0';
+ desc_subreg <= "11";
if(desc_request_next_i = '1') then
desc_grant_o <= '1';
- if(g_desc_mode = "tx") then
- txdesc_current_o <= granted_desc_tx;
- elsif (g_desc_mode = "rx") then
- rxdesc_current_o <= granted_desc_rx;
- end if;
-
state <= ARB_UPDATE;
end if;
desc_write_done_o <= '0';
when ARB_UPDATE =>
+ dtbl_wr_o <= '0';
desc_grant_o <= '0';
+ desc_subreg <= "11";
if(desc_write_i = '1') then
-
if(g_desc_mode = "rx") then
granted_desc_rx <= rxdesc_new_i;
elsif(g_desc_mode = "tx") then
granted_desc_tx <= txdesc_new_i;
end if;
- desc_subreg <= (others => '0');
--- dtbl_rd_o <= '0';
state <= ARB_WRITE_DESC;
- cntr <= "00";
end if;
when ARB_WRITE_DESC =>
- cntr <= cntr + 1;
- -- fprint(output,l, "WriteDesc %b %b\n",fo(cntr),fo(f_write_marshalling(1)));
- case cntr is
- when "00" =>
- desc_subreg <= "00";
- dtbl_data_o <= f_write_marshalling(1);
- dtbl_wr_o <= '1';
- when "01" =>
- desc_subreg <= "01";
- dtbl_data_o <= f_write_marshalling(2);
- dtbl_wr_o <= '1';
- when "10" =>
- desc_subreg <= "10";
- dtbl_data_o <= f_write_marshalling(3);
- dtbl_wr_o <= '1';
- when "11" =>
- dtbl_wr_o <= '0';
- desc_subreg <= (others => '0');
-
- state <= ARB_START_SCAN;
-
- if(desc_reload_current_i = '0') then
- desc_idx <= desc_idx + 1;
- end if;
-
- desc_write_done_o <= '1';
- when others => null;
- end case;
+ dtbl_data_o <= f_write_marshalling(to_integer(desc_subreg));
+ if(desc_subreg = "10") then
+ dtbl_wr_o <= '0';
+ desc_subreg <= "00";
+ state <= ARB_START_SCAN;
+ if(desc_reload_current_i = '0') then
+ desc_idx <= desc_idx + 1;
+ end if;
+ desc_write_done_o <= '1';
+ else
+ dtbl_wr_o <= '1';
+ desc_subreg <= desc_subreg + 1;
+ end if;
when others => null;
end case;
diff --git a/modules/wrsw_nic/nic_descriptors_pkg.vhd b/modules/wrsw_nic/nic_descriptors_pkg.vhd
index a318d34b9635fd1b5b107aa1e343f3d747f6b56c..39290119e4058a77410716fc676258a8c73e75c5 100644
--- a/modules/wrsw_nic/nic_descriptors_pkg.vhd
+++ b/modules/wrsw_nic/nic_descriptors_pkg.vhd
@@ -65,13 +65,11 @@ package nic_descriptors_pkg is
function f_marshall_rx_descriptor(desc : t_rx_descriptor;
regnum : integer) return std_logic_vector;
- procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
- regnum : in integer;
- desc : inout t_tx_descriptor);
+ function f_unmarshall_tx_descriptor(mem_input : std_logic_vector(31 downto 0);
+ regnum : integer) return t_tx_descriptor;
- procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
- regnum : in integer;
- desc : inout t_rx_descriptor);
+ function f_unmarshall_rx_descriptor(mem_input : std_logic_vector(31 downto 0);
+ regnum : integer) return t_rx_descriptor;
function f_resize_slv(x : std_logic_vector;
newsize : integer) return std_logic_vector;
@@ -95,9 +93,9 @@ package body NIC_descriptors_pkg is
begin
case regnum is
- when 1 => tmp := desc.ts_id & x"000" & desc.pad_e & desc.ts_e & desc.error & desc.ready;
- when 2 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
- when 3 => tmp := desc.dpm;
+ when 3 => tmp := desc.ts_id & x"000" & desc.pad_e & desc.ts_e & desc.error & desc.ready;
+ when 0 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
+ when 1 => tmp := desc.dpm;
when others => null;
end case;
@@ -108,9 +106,9 @@ package body NIC_descriptors_pkg is
variable tmp : std_logic_vector(31 downto 0);
begin
case regnum is
- when 1 => tmp := "0000000000000000" & desc.ts_incorrect & desc.got_ts & desc.port_id & "000000" & desc.error & desc.empty;
- when 2 => tmp := desc.ts_f & desc.ts_r;
- when 3 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
+ when 3 => tmp := "0000000000000000" & desc.ts_incorrect & desc.got_ts & desc.port_id & "000000" & desc.error & desc.empty;
+ when 0 => tmp := desc.ts_f & desc.ts_r;
+ when 1 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when others => null;
end case;
@@ -119,11 +117,10 @@ package body NIC_descriptors_pkg is
end f_marshall_rx_descriptor;
- procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
- regnum : in integer;
- desc : inout t_tx_descriptor) is
+ function f_unmarshall_tx_descriptor(mem_input : std_logic_vector(31 downto 0); regnum : integer)
+ return t_tx_descriptor is
+ variable desc : t_tx_descriptor;
begin
-
case regnum is
when 1 =>
desc.ts_id := mem_input(31 downto 16);
@@ -138,13 +135,13 @@ package body NIC_descriptors_pkg is
desc.dpm := mem_input;
when others => null;
end case;
- end p_unmarshall_tx_descriptor;
+ return desc;
+ end f_unmarshall_tx_descriptor;
- procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
- regnum : in integer;
- desc : inout t_rx_descriptor) is
+ function f_unmarshall_rx_descriptor(mem_input : std_logic_vector(31 downto 0); regnum : integer)
+ return t_rx_descriptor is
+ variable desc : t_rx_descriptor;
begin
-
case regnum is
when 1 =>
desc.empty := mem_input(0);
@@ -162,7 +159,8 @@ package body NIC_descriptors_pkg is
desc.offset := mem_input(c_nic_buf_size_log2-1 downto 0);
when others => null;
end case;
- end p_unmarshall_rx_descriptor;
+ return desc;
+ end f_unmarshall_rx_descriptor;
end package body;
diff --git a/modules/wrsw_nic/nic_elastic_buffer.vhd b/modules/wrsw_nic/nic_elastic_buffer.vhd
index 24bfcb59724a190c8ccaef12d8c67f2f76d674aa..b2157ee2f278c15c3a6232d1ea602628e0f490b1 100644
--- a/modules/wrsw_nic/nic_elastic_buffer.vhd
+++ b/modules/wrsw_nic/nic_elastic_buffer.vhd
@@ -48,7 +48,8 @@ architecture rtl of nic_elastic_buffer is
signal fifo_out_ser : std_logic_vector(c_fifo_width-1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
- signal fifo_usedw : std_logic_vector(log2(g_depth)-1 downto 0);
+ signal fifo_almost_empty : std_logic;
+ signal fifo_almost_full : std_logic;
signal output_valid : std_logic;
signal got_empty : std_logic;
@@ -105,14 +106,10 @@ begin -- rtl
p_gen_stall : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
+ if rst_n_i = '0' or fifo_almost_empty = '1' then
stall_int <= '0';
- else
- if (unsigned(fifo_usedw) < g_depth/2) then
- stall_int <= '0';
- elsif (unsigned(fifo_usedw) > g_depth-5) then
- stall_int <= '1';
- end if;
+ elsif fifo_almost_full = '1' then
+ stall_int <= '1';
end if;
end if;
end process;
@@ -135,7 +132,11 @@ begin -- rtl
generic map (
g_data_width => c_fifo_width,
g_size => g_depth,
- g_with_count => true)
+ g_with_almost_empty => true,
+ g_with_almost_full => true,
+ g_almost_empty_threshold => g_depth/2,
+ g_almost_full_threshold => g_depth-5,
+ g_with_count => false)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
@@ -145,7 +146,8 @@ begin -- rtl
q_o => fifo_out_ser,
empty_o => fifo_empty,
full_o => fifo_full,
- count_o => fifo_usedw
+ almost_empty_o => fifo_almost_empty,
+ almost_full_o => fifo_almost_full
);
fab_o.data <= fifo_out_ser(15 downto 0);
diff --git a/modules/wrsw_nic/nic_rx_fsm.vhd b/modules/wrsw_nic/nic_rx_fsm.vhd
index 2c3549e84c55901033039f958310c6a67c5144c9..c0f506bb7b84ca69a1a49bf7be42e4441f4777d5 100644
--- a/modules/wrsw_nic/nic_rx_fsm.vhd
+++ b/modules/wrsw_nic/nic_rx_fsm.vhd
@@ -109,7 +109,6 @@ architecture behavioral of NIC_RX_FSM is
signal cur_rx_desc : t_rx_descriptor;
signal state : t_rx_fsm_state;
- signal rx_avail : unsigned(c_nic_buf_size_log2-1 downto 0);
signal rx_length : unsigned(c_nic_buf_size_log2-1 downto 0);
signal rx_dreq_mask : std_logic;
signal rx_rdreg_toggle : std_logic;
@@ -206,7 +205,6 @@ begin
rx_newpacket <= '0';
rx_dreq_mask <= '0';
rx_buf_addr <= (others => '0');
- rx_avail <= (others => '0');
buf_wr_o <= '0';
increase_addr <= '0';
@@ -262,10 +260,9 @@ begin
-- rx_buf_addr is in 32-bit word, but the offsets and lengths in
-- the descriptors are in bytes to make driver developer's life
- -- easier.
+ -- easier.
rx_buf_addr <= unsigned(cur_rx_desc.offset(c_nic_buf_size_log2-1 downto 2));
- rx_avail <= unsigned(cur_rx_desc.len);
rx_length <= (others => '0');
oob_sreg <= "001";
@@ -283,6 +280,7 @@ begin
when RX_DATA =>
+ buf_wr_o <= '0';
-- increase the address 1 cycle after committing the data to the memory
if(increase_addr = '1') then
rx_buf_addr <= rx_buf_addr + 1;
@@ -290,116 +288,113 @@ begin
end if;
-- check if we still have enough space in the buffer
- if(fab_in.dvalid = '1' and rx_avail(rx_avail'length-1 downto 1) = to_unsigned(0, rx_avail'length-1)) then
+ if(fab_in.dvalid = '1' and rx_length(rx_length'length-1 downto 1) = unsigned(cur_rx_desc.len(rx_length'length-1 downto 1))) then
-- no space? drop an error
cur_rx_desc.error <= '1';
- buf_wr_o <= '0';
state <= RX_UPDATE_DESC;
- end if;
-
- -- got an abort/error/end-of-frame?
- if(wrf_terminate = '1') then
-
- -- check if the ends with an error and eventually indicate it.
- -- For the NIC, there's no difference between an abort and an RX
- -- error.
- cur_rx_desc.error <= fab_in.error;
-
- -- make sure the remaining packet data is written into the buffer
- state <= RX_MEM_FLUSH;
-
- -- disable the WRF sink data flow, so we won't get another
- -- packet before we are done with the memory flush and RX descriptor update
- rx_dreq_mask <= '0';
- end if;
-
- -- got a valid payload word?
- if(fab_in.dvalid = '1' and wrf_is_payload = '1') then
- -- check if it's a byte or a word transfer and update the length
- -- and buffer space counters accordingly
- if(fab_in.bytesel = '1') then
- rx_avail <= rx_avail - 1;
- rx_length <= rx_length + 1;
- else
- rx_avail <= rx_avail - 2;
- rx_length <= rx_length + 2;
- end if;
-
- -- pack two 16-bit words received from the fabric I/F into one
- -- 32-bit buffer word
-
- if(c_nic_buf_little_endian = false) then
- -- CPU is big-endian
- if(rx_rdreg_toggle = '0') then
- -- 1st word
- rx_buf_data(31 downto 16) <= fab_in.data;
- else
- -- 2nd word
- rx_buf_data(15 downto 0) <= fab_in.data;
- end if;
- else
- -- CPU is little endian
-
- if(rx_rdreg_toggle = '0') then
- -- 1st word
- rx_buf_data(15 downto 8) <= fab_in.data(7 downto 0);
- rx_buf_data(7 downto 0) <= fab_in.data(15 downto 8);
- else
- -- 2nd word
- rx_buf_data(31 downto 24) <= fab_in.data(7 downto 0);
- rx_buf_data(23 downto 16) <= fab_in.data(15 downto 8);
- end if;
- end if;
-
- -- toggle the current word
- rx_rdreg_toggle <= not rx_rdreg_toggle;
- end if;
-
-
- -- got a valid OOB word?
- if(fab_in.dvalid = '1' and wrf_is_oob = '1') then
-
- -- oob_sreg is a shift register, where each bit represents one of
- -- 3 RX OOB words
- oob_sreg <= oob_sreg(oob_sreg'length-2 downto 0) & '0';
-
-
- -- check which word we've just received and put its contents into
- -- the descriptor
-
- if(oob_sreg (0) = '1') then -- 1st OOB word
- cur_rx_desc.port_id <= '0' & fab_in.data(4 downto 0);
- cur_rx_desc.ts_incorrect <= fab_in.data(11);
- end if;
-
- if(oob_sreg (1) = '1') then -- 2nd OOB word
- cur_rx_desc.ts_f <= fab_in.data(15 downto 12);
- cur_rx_desc.ts_r (27 downto 16) <= fab_in.data(11 downto 0);
- end if;
-
- if(oob_sreg (2) = '1') then -- 3rd OOB word
- cur_rx_desc.ts_r(15 downto 0) <= fab_in.data;
- cur_rx_desc.got_ts <= '1';
- end if;
- end if;
-
-
- -- we've got 2 valid word of the payload in rx_buf_data, write them to the
- -- memory
- if(rx_rdreg_toggle = '1' and fab_in.dvalid = '1' and (wrf_is_oob = '1' or wrf_is_payload = '1') and wrf_terminate = '0') then
- increase_addr <= '1';
- buf_wr_o <= '1';
-
- -- check if we are synchronized with the memory write arbiter,
- -- which grants us the memory acces every 2 clock cycles.
- -- If we're out of the "beat" (for example when the RX traffic
- -- was throttled by the WRF source), we need to resynchronize ourselves.
- if(buf_grant_i = '1') then
- state <= RX_MEM_RESYNC;
- end if;
- else
- -- nothing to write
- buf_wr_o <= '0';
+ else
+
+ -- got an abort/error/end-of-frame?
+ if(wrf_terminate = '1') then
+ -- check if the ends with an error and eventually indicate it.
+ -- For the NIC, there's no difference between an abort and an RX
+ -- error.
+ cur_rx_desc.error <= fab_in.error;
+
+ -- make sure the remaining packet data is written into the buffer
+ state <= RX_MEM_FLUSH;
+
+ -- disable the WRF sink data flow, so we won't get another
+ -- packet before we are done with the memory flush and RX descriptor update
+ rx_dreq_mask <= '0';
+ end if;
+ ---------------------------------------
+
+ -- got a valid payload word?
+ if(fab_in.dvalid = '1' and wrf_is_payload = '1') then
+ -- check if it's a byte or a word transfer and update the length
+ -- and buffer space counters accordingly
+ if(fab_in.bytesel = '1') then
+ rx_length <= rx_length + 1;
+ else
+ rx_length <= rx_length + 2;
+ end if;
+
+ -- pack two 16-bit words received from the fabric I/F into one
+ -- 32-bit buffer word
+
+ if(c_nic_buf_little_endian = false) then
+ -- CPU is big-endian
+ if(rx_rdreg_toggle = '0') then
+ -- 1st word
+ rx_buf_data(31 downto 16) <= fab_in.data;
+ else
+ -- 2nd word
+ rx_buf_data(15 downto 0) <= fab_in.data;
+ end if;
+ else
+ -- CPU is little endian
+ if(rx_rdreg_toggle = '0') then
+ -- 1st word
+ rx_buf_data(15 downto 8) <= fab_in.data(7 downto 0);
+ rx_buf_data(7 downto 0) <= fab_in.data(15 downto 8);
+ else
+ -- 2nd word
+ rx_buf_data(31 downto 24) <= fab_in.data(7 downto 0);
+ rx_buf_data(23 downto 16) <= fab_in.data(15 downto 8);
+ end if;
+ end if;
+
+ -- toggle the current word
+ rx_rdreg_toggle <= not rx_rdreg_toggle;
+ end if;
+ ---------------------------------------
+
+ -- got a valid OOB word?
+ if(fab_in.dvalid = '1' and wrf_is_oob = '1') then
+
+ -- oob_sreg is a shift register, where each bit represents one of
+ -- 3 RX OOB words
+ oob_sreg <= oob_sreg(oob_sreg'length-2 downto 0) & '0';
+
+
+ -- check which word we've just received and put its contents into
+ -- the descriptor
+
+ if(oob_sreg (0) = '1') then -- 1st OOB word
+ cur_rx_desc.port_id <= '0' & fab_in.data(4 downto 0);
+ cur_rx_desc.ts_incorrect <= fab_in.data(11);
+ end if;
+
+ if(oob_sreg (1) = '1') then -- 2nd OOB word
+ cur_rx_desc.ts_f <= fab_in.data(15 downto 12);
+ cur_rx_desc.ts_r (27 downto 16) <= fab_in.data(11 downto 0);
+ end if;
+
+ if(oob_sreg (2) = '1') then -- 3rd OOB word
+ cur_rx_desc.ts_r(15 downto 0) <= fab_in.data;
+ cur_rx_desc.got_ts <= '1';
+ end if;
+ end if;
+ ---------------------------------------
+
+ -- we've got 2 valid word of the payload in rx_buf_data, write them to the
+ -- memory
+ if(rx_rdreg_toggle = '1' and fab_in.dvalid = '1' and (wrf_is_oob = '1' or wrf_is_payload = '1') and wrf_terminate = '0') then
+ increase_addr <= '1';
+ buf_wr_o <= '1';
+
+ -- check if we are synchronized with the memory write arbiter,
+ -- which grants us the memory acces every 2 clock cycles.
+ -- If we're out of the "beat" (for example when the RX traffic
+ -- was throttled by the WRF source), we need to resynchronize ourselves.
+ if(buf_grant_i = '1') then
+ state <= RX_MEM_RESYNC;
+ end if;
+ --else
+ -- nothing to write
+ --buf_wr_o <= '0';
+ end if;
end if;
@@ -469,7 +464,7 @@ begin
-------------------------------------------------------------------------------
-- helper process for producing the RX fabric data request signal (combinatorial)
-------------------------------------------------------------------------------
- gen_rx_dreq : process(rx_dreq_mask, buf_grant_i, rx_rdreg_toggle, fab_in, regs_i)
+ gen_rx_dreq : process(rx_dreq_mask, buf_grant_i, rx_rdreg_toggle, fab_in, regs_i, state)
begin
-- make sure we don't have any incoming data when the reception is masked (e.g.
-- the NIC is updating the descriptors of finishing the memory write.
diff --git a/modules/wrsw_nic/nic_tx_fsm.vhd b/modules/wrsw_nic/nic_tx_fsm.vhd
index 721d14ec238ff94d390d30164cac0bd1a9b6261a..59827cb021e6b74fa1a0322ec3ae409ea178e3c3 100644
--- a/modules/wrsw_nic/nic_tx_fsm.vhd
+++ b/modules/wrsw_nic/nic_tx_fsm.vhd
@@ -27,82 +27,80 @@ use IEEE.NUMERIC_STD.all;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
use work.wr_fabric_pkg.all;
-use work.endpoint_private_pkg.all; -- dirty hack
use work.nic_wbgen2_pkg.all;
entity nic_tx_fsm is
generic(
- g_cyc_on_stall : boolean := false);
-
- port (clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
+ g_port_mask_bits : integer := 32;
+ g_cyc_on_stall : boolean := false);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- WRF source
-------------------------------------------------------------------------------
- src_o : out t_wrf_source_out;
- src_i : in t_wrf_source_in;
+ src_o : out t_wrf_source_out;
+ src_i : in t_wrf_source_in;
-------------------------------------------------------------------------------
-- "Fake" RTU interface
-------------------------------------------------------------------------------
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
- rtu_prio_o : out std_logic_vector(2 downto 0);
- rtu_drop_o : out std_logic;
- rtu_rsp_valid_o : out std_logic;
- rtu_rsp_ack_i : in std_logic;
-
-
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
+ rtu_prio_o : out std_logic_vector(2 downto 0);
+ rtu_drop_o : out std_logic;
+ rtu_rsp_valid_o : out std_logic;
+ rtu_rsp_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone regs & IRQs
-------------------------------------------------------------------------------
- regs_i : in t_nic_out_registers;
- regs_o : out t_nic_in_registers;
+ regs_i : in t_nic_out_registers;
+ regs_o : out t_nic_in_registers;
- irq_tcomp_o : out std_logic;
- irq_tcomp_ack_i : in std_logic;
- irq_tcomp_mask_i : in std_logic;
+ irq_tcomp_o : out std_logic;
+ irq_tcomp_ack_i : in std_logic;
+ irq_tcomp_mask_i : in std_logic;
- irq_txerr_o : out std_logic;
- irq_txerr_ack_i : in std_logic;
- irq_txerr_mask_i : in std_logic;
+ irq_txerr_o : out std_logic;
+ irq_txerr_ack_i : in std_logic;
+ irq_txerr_mask_i : in std_logic;
-------------------------------------------------------------------------------
-- TX Descriptor Manager I/F
-------------------------------------------------------------------------------
- txdesc_reload_current_o : out std_logic;
- -- 1 requests next available (empty) TX descriptor
- txdesc_request_next_o : out std_logic;
- -- 1 indicates that an empty descriptor has been granted and it's available
- -- on rxdesc_current_i
- txdesc_grant_i : in std_logic;
- -- currently granted TX descriptor
- txdesc_current_i : in t_tx_descriptor;
- -- updated RX descriptor (with new length, error flags, timestamp, etc.)
- txdesc_new_o : out t_tx_descriptor;
- -- 1 requests an update of the current TX descriptor with the values
- -- given on rxdesc_new_o output
- txdesc_write_o : out std_logic;
- -- 1 indicates that the TX descriptor update is done
- txdesc_write_done_i : in std_logic;
-
- bna_i : in std_logic;
+ txdesc_reload_current_o : out std_logic;
+ -- 1 requests next available (empty) TX descriptor
+ txdesc_request_next_o : out std_logic;
+ -- 1 indicates that an empty descriptor has been granted and it's available
+ -- on rxdesc_current_i
+ txdesc_grant_i : in std_logic;
+ -- currently granted TX descriptor
+ txdesc_current_i : in t_tx_descriptor;
+ -- updated RX descriptor (with new length, error flags, timestamp, etc.)
+ txdesc_new_o : out t_tx_descriptor;
+ -- 1 requests an update of the current TX descriptor with the values
+ -- given on rxdesc_new_o output
+ txdesc_write_o : out std_logic;
+ -- 1 indicates that the TX descriptor update is done
+ txdesc_write_done_i : in std_logic;
+
+ bna_i : in std_logic;
-------------------------------------------------------------------------------
-- Packet buffer RAM
-------------------------------------------------------------------------------
- -- 1 indicates that we'll have the memory access in the following clock
- -- cycle
- buf_grant_i : in std_logic;
- -- buffer address, data and write enable lines.
- buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
- buf_data_i : in std_logic_vector(31 downto 0)
- );
+ -- 1 indicates that we'll have the memory access in the following clock
+ -- cycle
+ buf_grant_i : in std_logic;
+ -- buffer address, data and write enable lines.
+ buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
+ buf_data_i : in std_logic_vector(31 downto 0)
+ );
end nic_tx_fsm;
@@ -112,19 +110,6 @@ architecture behavioral of nic_tx_fsm is
signal cur_tx_desc : t_tx_descriptor;
- component ep_rx_wb_master
- generic (
- g_ignore_ack : boolean;
- g_cyc_on_stall : boolean);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_wb_i : in t_wrf_source_in;
- src_wb_o : out t_wrf_source_out);
- end component;
-
function f_buf_swap_endian_32
(
data : std_logic_vector(31 downto 0)
@@ -142,24 +127,23 @@ architecture behavioral of nic_tx_fsm is
signal odd_length : std_logic;
signal tx_buf_addr : unsigned(c_nic_buf_size_log2-3 downto 0);
- signal tx_start_delayed : std_logic;
signal tx_data_reg : std_logic_vector(31 downto 0);
signal tx_done : std_logic;
signal ignore_first_hword : std_logic;
signal tx_cntr_expired : std_logic;
- signal is_runt_frame : std_logic;
signal needs_padding : std_logic;
- signal padding_size : unsigned(7 downto 0);
+ signal padding_size : unsigned(4 downto 0);
signal rtu_valid_int : std_logic;
signal rtu_valid_int_d0 : std_logic;
- signal fab_dreq : std_logic;
- signal fab_out : t_ep_internal_fabric;
-
signal tx_err : std_logic;
signal default_status_reg : t_wrf_status_reg;
+
+ signal ack_count : unsigned(3 downto 0);
+ signal src_stb_int : std_logic;
+
begin -- behavioral
@@ -172,24 +156,29 @@ begin -- behavioral
buf_addr_o <= std_logic_vector(tx_buf_addr);
- is_runt_frame <= '1' when (to_integer(unsigned(cur_tx_desc.len)) < 60) else '0';
- tx_cntr_expired <= '1' when (tx_remaining = 0) else '0';
+ needs_padding <= '1' when (to_integer(unsigned(cur_tx_desc.len)) < 60 and cur_tx_desc.pad_e='1') else '0';
+ odd_length <= (not needs_padding) and cur_tx_desc.len(0);
+ tx_cntr_expired <= '1' when (tx_remaining = 0) else '0';
txdesc_new_o <= cur_tx_desc;
+ src_o.stb <= src_stb_int;
+ --because it's validated with rtu_rsp_valid_o and sw_core stores it to internal register on rtu_rsp_valid strobe
+ rtu_dst_port_mask_o <= cur_tx_desc.dpm(g_port_mask_bits-1 downto 0);
+ rtu_prio_o <= (others => '0');
+ rtu_drop_o <= '0';
-
- U_WB_Master : ep_rx_wb_master
- generic map(
- g_ignore_ack => true,
- g_cyc_on_stall => g_cyc_on_stall)
- port map (
- clk_sys_i => clk_sys_i,
- rst_n_i => rst_n_i,
- snk_fab_i => fab_out,
- snk_dreq_o => fab_dreq,
- src_wb_i => src_i,
- src_wb_o => src_o);
-
+ count_acks: process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if(rst_n_i='0') then
+ ack_count <= (others=>'0');
+ elsif(src_stb_int = '1' and src_i.stall = '0' and src_i.ack = '0') then
+ ack_count <= ack_count + 1;
+ elsif(src_i.ack = '1' and not(src_stb_int = '1' and src_i.stall = '0')) then
+ ack_count <= ack_count - 1;
+ end if;
+ end if;
+ end process;
p_gen_tcomp_irq : process(clk_sys_i, rst_n_i)
begin
@@ -235,22 +224,18 @@ begin -- behavioral
txdesc_write_o <= '0';
txdesc_reload_current_o <= '0';
- fab_out.sof <= '0';
- fab_out.eof <= '0';
- fab_out.dvalid <= '0';
- fab_out.bytesel <= '0';
- fab_out.data <= (others => '0');
- fab_out.addr <= (others => '0');
- fab_out.error <= '0';
+ src_o.cyc <= '0';
+ src_stb_int <= '0';
+ src_o.we <= '1';
+ src_o.adr <= (others => '0');
+ src_o.dat <= (others => '0');
+ src_o.sel <= (others => '0');
tx_done <= '0';
rtu_valid_int <= '0';
irq_txerr_o <= '0';
regs_o.sr_tx_error_i <= '0';
- rtu_dst_port_mask_o <= (others => '0');
- rtu_drop_o <= '0';
-
else
case state is
when TX_DISABLED =>
@@ -268,8 +253,6 @@ begin -- behavioral
if(txdesc_grant_i = '1') then
cur_tx_desc <= txdesc_current_i;
- txdesc_request_next_o <= '0';
- state <= TX_START_PACKET;
tx_buf_addr <= resize(unsigned(txdesc_current_i.offset(tx_buf_addr'length+1 downto 2)), tx_buf_addr'length);
tx_remaining <= unsigned(txdesc_current_i.len(tx_remaining'length downto 1));
state <= TX_MEM_FETCH;
@@ -279,6 +262,7 @@ begin -- behavioral
-- 1 wait cycle to make sure the 1st TX word has been successfully
-- read from the buffer
when TX_MEM_FETCH =>
+ txdesc_request_next_o <= '0';
if(txdesc_current_i.len(0) = '1') then
tx_remaining <= tx_remaining + 1;
end if;
@@ -288,45 +272,34 @@ begin -- behavioral
when TX_START_PACKET =>
regs_o.sr_tx_error_i <= '0';
- rtu_prio_o <= (others => '0');
- rtu_dst_port_mask_o <= cur_tx_desc.dpm;
- rtu_drop_o <= '0';
rtu_valid_int <= '1';
+ ignore_first_hword <= '1';
+ if(cur_tx_desc.len(0) = '1') then
+ padding_size <= 29 - unsigned(cur_tx_desc.len(padding_size'length downto 1));
+ else
+ padding_size <= 30 - unsigned(cur_tx_desc.len(padding_size'length downto 1));
+ end if;
-- check if the memory is ready, read the 1st word of the payload
- if(fab_dreq = '1' and buf_grant_i = '0') then
- tx_data_reg <= buf_data_i;
- fab_out.sof <= '1';
+ if( ( (src_i.stall = '0' and g_cyc_on_stall = false) or g_cyc_on_stall = true)
+ and buf_grant_i = '0') then
+ src_o.cyc <= '1';
tx_buf_addr <= tx_buf_addr + 1;
- ignore_first_hword <= '1';
state <= TX_STATUS;
- if(is_runt_frame = '1' and cur_tx_desc.pad_e = '1') then
- odd_length <= '0';
- needs_padding <= '1';
- if(cur_tx_desc.len(0) = '1') then
- padding_size <= 29 - unsigned(cur_tx_desc.len(padding_size'length downto 1));
- else
- padding_size <= 30 - unsigned(cur_tx_desc.len(padding_size'length downto 1));
- end if;
- else
- odd_length <= cur_tx_desc.len(0);
- needs_padding <= '0';
- end if;
-
tx_data_reg <= f_buf_swap_endian_32(buf_data_i);
end if;
when TX_STATUS =>
- fab_out.sof <= '0';
+ src_o.adr <= c_WRF_STATUS;
+ src_o.sel <= "11";
+ src_o.dat <= f_marshall_wrf_status(default_status_reg);
- if(fab_dreq = '1' and buf_grant_i = '0') then
- fab_out.dvalid <= '1';
- fab_out.addr <= c_WRF_STATUS;
- fab_out.data <= f_marshall_wrf_status(default_status_reg);
- state <= TX_HWORD;
- else
- fab_out.dvalid <= '0';
+ if( src_i.stall = '0' and buf_grant_i = '0') then
+ src_stb_int <= '1';
+ state <= TX_HWORD;
+ else
+ src_stb_int <= '0';
end if;
when TX_HWORD =>
@@ -334,87 +307,75 @@ begin -- behavioral
-- generate the control value depending on the packet type, OOB and the current
-- transmission offset.
- fab_out.addr <= c_WRF_DATA;
- fab_out.data <= tx_data_reg(31 downto 16);
if(tx_err = '1') then
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
- elsif(fab_dreq = '1') then
+ elsif( src_i.stall = '0' ) then
+ src_o.adr <= c_WRF_DATA;
+ src_o.dat <= tx_data_reg(31 downto 16);
+ ignore_first_hword <= '0';
+ src_stb_int <= not ignore_first_hword;
+
if(tx_cntr_expired = '1') then
- fab_out.bytesel <= odd_length and (not needs_padding);
+ -- we are at the end of transmitted frame
+ src_o.sel(1) <= '1';
+ src_o.sel(0) <= (not odd_length) or needs_padding;
- if(needs_padding = '1' and padding_size /= 0) then
+ if(needs_padding = '1') then
state <= TX_PAD;
elsif(cur_tx_desc.ts_e = '1') then
state <= TX_OOB1;
else
state <= TX_END_PACKET;
end if;
- fab_out.dvalid <= '1';
else
-
- if(ignore_first_hword = '1') then
- ignore_first_hword <= '0';
- fab_out.dvalid <= '0';
- tx_remaining <= tx_remaining - 1;
- else
- fab_out.dvalid <= '1';
- tx_remaining <= tx_remaining - 1;
- end if;
-
+ src_o.sel <= "11";
+ tx_remaining <= tx_remaining - 1;
state <= TX_LWORD;
end if;
-
- else
- fab_out.dvalid <= '0';
end if;
- fab_out.sof <= '0';
-
--- check for errors
-
-
when TX_LWORD =>
- fab_out.addr <= c_WRF_DATA;
- fab_out.data <= tx_data_reg (15 downto 0);
-
-- the TX fabric is ready, the memory is ready and we haven't reached the end
-- of the packet yet:
if(tx_err = '1') then
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
- elsif(fab_dreq = '1' and buf_grant_i = '0') then
- if(tx_cntr_expired = '0') then
- fab_out.dvalid <= '1';
-
- tx_data_reg <= f_buf_swap_endian_32(buf_data_i);
+ elsif( src_i.stall='0' and buf_grant_i = '0') then
+ src_o.adr <= c_WRF_DATA;
+ src_o.dat <= tx_data_reg(15 downto 0);
+ src_stb_int <= '1';
+ if(tx_cntr_expired = '0') then
+ src_o.sel <= "11";
tx_remaining <= tx_remaining - 1;
- tx_buf_addr <= tx_buf_addr + 1;
state <= TX_HWORD;
+ -- but we also fetch next word from the buffer
+ tx_data_reg <= f_buf_swap_endian_32(buf_data_i);
+ tx_buf_addr <= tx_buf_addr + 1;
+
-- We're at the end of the packet. Generate an end-of-packet condition on the
-- fabric I/F
else
-
- fab_out.bytesel <= odd_length and (not needs_padding);
- fab_out.dvalid <= '1';
- if(needs_padding = '1' and padding_size /= 0) then
+ -- (tx_cntr_expired=1) we are at the end of transmitted frame
+ src_o.sel(1) <= '1';
+ src_o.sel(0) <= (not odd_length) or needs_padding;
+ if(needs_padding = '1') then
state <= TX_PAD;
-
elsif(cur_tx_desc.ts_e = '1') then
state <= TX_OOB1;
else
- state <= TX_END_PACKET;
- fab_out.eof <= '0';
+ state <= TX_END_PACKET;
end if;
end if;
- else
--- the fabric is not ready, don't send anything
- fab_out.dvalid <= '0';
+
+ elsif( src_i.stall='0' and buf_grant_i = '1') then
+ --if we wait for buffer then drop stb so that we don't retransmit last data word
+ src_stb_int <= '0';
end if;
when TX_PAD =>
@@ -422,60 +383,55 @@ begin -- behavioral
if(tx_err = '1') then
state <= TX_UPDATE_DESCRIPTOR;
cur_tx_desc.error <= '1';
- elsif(fab_dreq = '1') then
- fab_out.data <= x"0000";
- fab_out.addr <= c_WRF_DATA;
- fab_out.dvalid <= '1';
+ elsif( src_i.stall='0' ) then
+ src_o.dat <= x"0000";
+ src_o.adr <= c_WRF_DATA;
+ src_o.sel <= "11";
+ src_stb_int <= '1';
padding_size <= padding_size - 1;
if(padding_size = 0) then
- fab_out.dvalid <= '0';
- if(cur_tx_desc.ts_e = '1')then
+ src_stb_int <= '0';
+ if(cur_tx_desc.ts_e = '1') then
state <= TX_OOB1;
else
- fab_out.eof <= '0';
- state <= TX_END_PACKET;
+ state <= TX_END_PACKET;
end if;
end if;
- else
- fab_out.dvalid <= '0';
end if;
when TX_OOB1 =>
- fab_out.bytesel <= '0';
-
- if(fab_dreq = '1') then
- fab_out.data <= c_WRF_OOB_TYPE_TX & x"000";
- fab_out.addr <= c_WRF_OOB;
- fab_out.dvalid <= '1';
- fab_out.eof <= '0';
- state <= TX_OOB2;
+ src_o.sel <= "11";
+
+ if( src_i.stall='0' ) then
+ src_o.dat <= c_WRF_OOB_TYPE_TX & x"000";
+ src_o.adr <= c_WRF_OOB;
+ src_stb_int <= '1';
+ state <= TX_OOB2;
end if;
when TX_OOB2 =>
- fab_out.bytesel <= '0';
-
- if(fab_dreq = '1') then
- fab_out.data <= cur_tx_desc.ts_id;
- fab_out.addr <= c_WRF_OOB;
- fab_out.dvalid <= '1';
- fab_out.eof <= '0';
- state <= TX_END_PACKET;
+ src_o.sel <= "11";
+
+ if( src_i.stall='0' ) then
+ src_o.dat <= cur_tx_desc.ts_id;
+ src_o.adr <= c_WRF_OOB;
+ src_stb_int <= '1';
+ state <= TX_END_PACKET;
end if;
when TX_END_PACKET =>
- fab_out.dvalid <= '0';
- fab_out.bytesel <= '0';
+ src_stb_int <= '0';
+ src_o.sel <= "11";
- if(fab_dreq = '1') then
- fab_out.eof <= '1';
- state <= TX_UPDATE_DESCRIPTOR;
+ if( src_i.stall='0' and ack_count = 0) then
+ state <= TX_UPDATE_DESCRIPTOR;
end if;
when TX_UPDATE_DESCRIPTOR =>
- fab_out.eof <= '0';
+ src_o.cyc <= '0';
txdesc_write_o <= '1';
txdesc_reload_current_o <= cur_tx_desc.error;
cur_tx_desc.ready <= '0';
@@ -494,7 +450,6 @@ begin -- behavioral
if(irq_txerr_mask_i = '1') then -- clear the error status in
-- interrupt-driver mode
-
irq_txerr_o <= '1';
if(irq_txerr_ack_i = '1') then
irq_txerr_o <= '0';
@@ -503,7 +458,6 @@ begin -- behavioral
end if;
regs_o.sr_tx_error_i <= '1';
-
if(regs_i.sr_tx_error_o = '1' and regs_i.sr_tx_error_load_o = '1') then --
-- or in status register mode
irq_txerr_o <= '0';
diff --git a/modules/wrsw_nic/nic_wbgen2_pkg.vhd b/modules/wrsw_nic/nic_wbgen2_pkg.vhd
index 8818ef7150167989987aed3abf13016014b1a062..87a78aef56ec120d011573b8347abc415af3a01e 100644
--- a/modules/wrsw_nic/nic_wbgen2_pkg.vhd
+++ b/modules/wrsw_nic/nic_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
--- Created : Fri Jul 5 14:53:50 2013
+-- Created : Thu Mar 28 09:24:42 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
@@ -43,27 +43,25 @@ package nic_wbgen2_pkg is
type t_nic_out_registers is record
cr_rx_en_o : std_logic;
cr_tx_en_o : std_logic;
+ cr_sw_rst_o : std_logic;
sr_rec_o : std_logic;
sr_rec_load_o : std_logic;
sr_tx_done_o : std_logic;
sr_tx_done_load_o : std_logic;
sr_tx_error_o : std_logic;
sr_tx_error_load_o : std_logic;
- reset_o : std_logic_vector(31 downto 0);
- reset_wr_o : std_logic;
end record;
constant c_nic_out_registers_init_value: t_nic_out_registers := (
cr_rx_en_o => '0',
cr_tx_en_o => '0',
+ cr_sw_rst_o => '0',
sr_rec_o => '0',
sr_rec_load_o => '0',
sr_tx_done_o => '0',
sr_tx_done_load_o => '0',
sr_tx_error_o => '0',
- sr_tx_error_load_o => '0',
- reset_o => (others => '0'),
- reset_wr_o => '0'
+ sr_tx_error_load_o => '0'
);
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
diff --git a/modules/wrsw_nic/nic_wishbone_slave.vhd b/modules/wrsw_nic/nic_wishbone_slave.vhd
index 12cecb8bc219447ae6cd65943132ca85dd27fa6e..825f605add84ceeee81706b151038e6ece671237 100644
--- a/modules/wrsw_nic/nic_wishbone_slave.vhd
+++ b/modules/wrsw_nic/nic_wishbone_slave.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
--- Created : Fri Jul 5 14:53:50 2013
+-- Created : Thu Mar 28 09:24:42 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
@@ -69,6 +69,8 @@ architecture syn of nic_wishbone_slave is
signal nic_cr_rx_en_int : std_logic ;
signal nic_cr_tx_en_int : std_logic ;
+signal nic_cr_sw_rst_dly0 : std_logic ;
+signal nic_cr_sw_rst_int : std_logic ;
signal nic_dtx_rddata_int : std_logic_vector(31 downto 0);
signal nic_dtx_rd_int : std_logic ;
signal nic_dtx_wr_int : std_logic ;
@@ -114,10 +116,10 @@ begin
rddata_reg <= "00000000000000000000000000000000";
nic_cr_rx_en_int <= '0';
nic_cr_tx_en_int <= '0';
+ nic_cr_sw_rst_int <= '0';
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
- regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
@@ -127,10 +129,10 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
+ nic_cr_sw_rst_int <= '0';
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
- regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
@@ -139,7 +141,6 @@ begin
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
- regs_o.reset_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
@@ -150,9 +151,11 @@ begin
if (wb_we_i = '1') then
nic_cr_rx_en_int <= wrdata_reg(0);
nic_cr_tx_en_int <= wrdata_reg(1);
+ nic_cr_sw_rst_int <= wrdata_reg(31);
end if;
rddata_reg(0) <= nic_cr_rx_en_int;
rddata_reg(1) <= nic_cr_tx_en_int;
+ rddata_reg(31) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
@@ -182,8 +185,7 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- ack_sreg(0) <= '1';
+ ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
@@ -221,44 +223,6 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "0010" =>
- if (wb_we_i = '1') then
- regs_o.reset_wr_o <= '1';
- end if;
- rddata_reg(0) <= 'X';
- rddata_reg(1) <= 'X';
- rddata_reg(2) <= 'X';
- rddata_reg(3) <= 'X';
- rddata_reg(4) <= 'X';
- rddata_reg(5) <= 'X';
- rddata_reg(6) <= 'X';
- rddata_reg(7) <= 'X';
- rddata_reg(8) <= 'X';
- rddata_reg(9) <= 'X';
- rddata_reg(10) <= 'X';
- rddata_reg(11) <= 'X';
- rddata_reg(12) <= 'X';
- rddata_reg(13) <= 'X';
- rddata_reg(14) <= 'X';
- rddata_reg(15) <= 'X';
- rddata_reg(16) <= 'X';
- rddata_reg(17) <= 'X';
- rddata_reg(18) <= 'X';
- rddata_reg(19) <= 'X';
- rddata_reg(20) <= 'X';
- rddata_reg(21) <= 'X';
- rddata_reg(22) <= 'X';
- rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
- rddata_reg(28) <= 'X';
- rddata_reg(29) <= 'X';
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
@@ -474,6 +438,19 @@ begin
regs_o.cr_rx_en_o <= nic_cr_rx_en_int;
-- Transmit enable
regs_o.cr_tx_en_o <= nic_cr_tx_en_int;
+-- Software Reset
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ nic_cr_sw_rst_dly0 <= '0';
+ regs_o.cr_sw_rst_o <= '0';
+ elsif rising_edge(clk_sys_i) then
+ nic_cr_sw_rst_dly0 <= nic_cr_sw_rst_int;
+ regs_o.cr_sw_rst_o <= nic_cr_sw_rst_int and (not nic_cr_sw_rst_dly0);
+ end if;
+ end process;
+
+
-- Buffer Not Available
-- Frame Received
regs_o.sr_rec_o <= wrdata_reg(1);
@@ -483,9 +460,6 @@ begin
regs_o.sr_tx_error_o <= wrdata_reg(3);
-- Current TX descriptor
-- Current RX descriptor
--- Software reset
--- pass-through field: Software reset in register: SW_Reset
- regs_o.reset_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst : wbgen2_dpssram
diff --git a/modules/wrsw_nic/wr_nic.wb b/modules/wrsw_nic/wr_nic.wb
index 1bcd215f9865cbff2702d8b7643abcfe5fdb0dfe..6c63d87441fc4df4dec063cee53032c028d80e86 100644
--- a/modules/wrsw_nic/wr_nic.wb
+++ b/modules/wrsw_nic/wr_nic.wb
@@ -36,9 +36,6 @@ top = peripheral {
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
- Todo \
- ~~~~ \
- * Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
@@ -66,6 +63,16 @@ top = peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
+
+ field {
+ name = "Software Reset";
+ description = "write 1: reset the NIC, zero all registers and reset the state of the module \
+ write 0: no effect";
+ prefix = "sw_rst";
+ size = 1;
+ align = 31;
+ type = MONOSTABLE;
+ };
};
reg {
@@ -145,18 +152,6 @@ top = peripheral {
};
};
-
- reg {
- name = "SW_Reset";
- description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
- prefix = "reset";
- field {
- name = "Software reset";
- type = PASS_THROUGH;
- size = 32;
- };
- };
-
irq {
name = "Receive Complete";
prefix = "rcomp";
diff --git a/modules/wrsw_nic/wrsw_nic.vhd b/modules/wrsw_nic/wrsw_nic.vhd
index 63655342182d0abf055305dfd285294067847c7b..dd336e23906851e8afef121f61485f0195a538f1 100644
--- a/modules/wrsw_nic/wrsw_nic.vhd
+++ b/modules/wrsw_nic/wrsw_nic.vhd
@@ -11,8 +11,8 @@ entity wrsw_nic is
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
- g_src_cyc_on_stall : boolean := false
- );
+ g_src_cyc_on_stall : boolean := false;
+ g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -47,7 +47,7 @@ entity wrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
@@ -66,7 +66,7 @@ entity wrsw_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
- wb_irq_o : out std_logic
+ wb_int_o : out std_logic
);
@@ -78,7 +78,8 @@ architecture rtl of wrsw_nic is
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
- g_src_cyc_on_stall : boolean);
+ g_src_cyc_on_stall : boolean := false;
+ g_port_mask_bits : integer := 32);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -86,7 +87,7 @@ architecture rtl of wrsw_nic is
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
@@ -111,7 +112,8 @@ begin
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
- g_src_cyc_on_stall => g_src_cyc_on_stall)
+ g_src_cyc_on_stall => g_src_cyc_on_stall,
+ g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
@@ -158,6 +160,6 @@ begin
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
- wb_irq_o <= wb_out.int;
+ wb_int_o <= wb_out.int;
end rtl;
diff --git a/modules/wrsw_nic/xwrsw_nic.vhd b/modules/wrsw_nic/xwrsw_nic.vhd
index 44b6fc30b2405daf0171b71a20af1db39c0767dd..433304b307b75cd84ab2e81b72a31ad0577cd802 100644
--- a/modules/wrsw_nic/xwrsw_nic.vhd
+++ b/modules/wrsw_nic/xwrsw_nic.vhd
@@ -17,8 +17,8 @@ entity xwrsw_nic is
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
- g_src_cyc_on_stall : boolean := false
- );
+ g_src_cyc_on_stall : boolean := false;
+ g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -37,7 +37,7 @@ entity xwrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
@@ -59,7 +59,8 @@ architecture rtl of xwrsw_nic is
generic (
g_desc_mode : string;
g_num_descriptors : integer;
- g_num_descriptors_log2 : integer);
+ g_num_descriptors_log2 : integer;
+ g_port_mask_bits : integer := 32);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -129,9 +130,9 @@ architecture rtl of xwrsw_nic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
- wb_adr_i : in std_logic_vector(6 downto 0);
- wb_dat_i : in std_logic_vector(31 downto 0);
- wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_adr_i : in std_logic_vector(6 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
@@ -162,14 +163,15 @@ architecture rtl of xwrsw_nic is
end component;
component nic_tx_fsm
- generic (
- g_cyc_on_stall : boolean);
+ generic(
+ g_port_mask_bits : integer := 32;
+ g_cyc_on_stall : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
@@ -287,7 +289,7 @@ begin -- rtl
wb_out.err <= '0';
wb_out.rty <= '0';
- nic_reset_n <= rst_n_i and (not regs_fromwb.reset_wr_o);
+ nic_reset_n <= rst_n_i and (not regs_fromwb.cr_sw_rst_o);
regs_towb <= regs_towb_tx or regs_towb_rx or regs_towb_main;
@@ -295,15 +297,15 @@ begin -- rtl
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
- wb_adr_i => wb_in.adr(6 downto 0),
- wb_dat_i => wb_in.dat,
- wb_dat_o => wb_rdata_slave,
+ wb_adr_i => wb_in.adr(6 downto 0),
+ wb_dat_i => wb_in.dat,
+ wb_dat_o => wb_rdata_slave,
wb_cyc_i => wb_cyc_slave,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_ack_slave,
- wb_stall_o => wb_out.stall,
+ wb_stall_o=> wb_out.stall,
wb_int_o => wb_out.int,
@@ -399,8 +401,8 @@ begin -- rtl
generic map (
g_desc_mode => "rx",
g_num_descriptors => c_nic_num_rx_descriptors,
- g_num_descriptors_log2 => c_nic_num_rx_descriptors_log2)
-
+ g_num_descriptors_log2 => c_nic_num_rx_descriptors_log2,
+ g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
@@ -465,7 +467,8 @@ begin -- rtl
generic map (
g_desc_mode => "tx",
g_num_descriptors => c_nic_num_tx_descriptors,
- g_num_descriptors_log2 => c_nic_num_tx_descriptors_log2)
+ g_num_descriptors_log2 => c_nic_num_tx_descriptors_log2,
+ g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
@@ -494,7 +497,8 @@ begin -- rtl
U_TX_FSM : nic_tx_fsm
generic map(
- g_cyc_on_stall => g_src_cyc_on_stall)
+ g_cyc_on_stall => g_src_cyc_on_stall,
+ g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
diff --git a/modules/wrsw_pstats/Manifest.py b/modules/wrsw_pstats/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..69e02715ed92b905bc491463cd44c8a286b92b23
--- /dev/null
+++ b/modules/wrsw_pstats/Manifest.py
@@ -0,0 +1,2 @@
+files = ["wrsw_pstats.vhd", "port_cntr.vhd", "irq_ram.vhd", "pstats_wishbone_slave.vhd", "pstats_wbgen2_pkg.vhd",
+ "xwrsw_pstats.vhd", "wrsw_dummy"]
diff --git a/modules/wrsw_pstats/irq_ram.vhd b/modules/wrsw_pstats/irq_ram.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4793df712e8b781bb568dad463d2273f5376b559
--- /dev/null
+++ b/modules/wrsw_pstats/irq_ram.vhd
@@ -0,0 +1,220 @@
+-------------------------------------------------------------------------------
+-- Title : IRQ RAM for Per-port statistics counters
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : irq_ram.vhd
+-- Author : Grzegorz Daniluk
+-- Company : CERN BE-CO-HT
+-- Created : 2013-02-27
+-- Last update: 2013-07-24
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Module stores irq flags from each counter of each port of WR Switch. Its
+-- structure is simplified design of port_cntr module. IRQ flags are stored in
+-- Block-RAM. Each 32-bit memory word can store up to 32 irq flags. IRQ events
+-- comming from each port are first aligned so that each port's flags start
+-- from a new word in memory to simplify reading FSM in top module.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2013-02-27 0.1 greg.d Created
+-- 2013-07-24 0.2 greg.d Optimized to save FPGA resources
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.gencores_pkg.all;
+
+entity irq_ram is
+ generic(
+ g_nports : integer := 8;
+ g_cnt_pp : integer := 64; --number of counters per port
+ g_cnt_pw : integer := 32); --number of counters per word
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ irq_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ --memory interface
+ ext_cyc_i : in std_logic := '0';
+ ext_adr_i : in std_logic_vector(f_log2_size(g_nports*((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw))-1 downto 0) := (others => '0');
+ ext_we_i : in std_logic := '0';
+ ext_dat_i : in std_logic_vector(31 downto 0) := (others => '0');
+ ext_dat_o : out std_logic_vector(31 downto 0)
+
+ --debug
+ --dbg_evt_ov_o : out std_logic;
+ --clr_flags_i : in std_logic := '0'
+ );
+end irq_ram;
+
+architecture behav of irq_ram is
+
+ constant c_rr_range : integer := g_nports*((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw);
+ constant c_evt_range : integer := c_rr_range*g_cnt_pw;
+ constant c_mem_adr_sz : integer := f_log2_size(c_rr_range);
+ constant c_evt_align_sz : integer := ((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw)*g_cnt_pw;
+
+ type t_cnt_st is (SEL, WRITE);
+ signal cnt_state : t_cnt_st;
+
+ signal mem_dat_in : std_logic_vector(31 downto 0);
+ signal mem_dat_out : std_logic_vector(31 downto 0);
+ signal mem_adr : integer range 0 to c_rr_range-1;
+ signal mem_adr_d1 : integer range 0 to c_rr_range-1;
+ signal mem_adr_lv : std_logic_vector(c_mem_adr_sz-1 downto 0);
+ signal mem_wr : std_logic;
+
+ signal events_reg : std_logic_vector(c_evt_range-1 downto 0);
+ signal events_aligned : std_logic_vector(c_evt_range-1 downto 0);
+ signal events_clr : std_logic_vector(c_evt_range-1 downto 0);
+ signal events_sub : std_logic_vector(g_cnt_pw-1 downto 0);
+ signal events_ored : std_logic_vector(c_rr_range-1 downto 0);
+ signal events_preg : std_logic_vector(c_rr_range-1 downto 0);
+ signal events_grant : std_logic_vector(c_rr_range-1 downto 0);
+ signal events_presub : std_logic_vector(g_cnt_pw-1 downto 0);
+
+ signal wr_conflict : std_logic;
+
+ function f_onehot_decode
+ (x : std_logic_vector) return integer is
+ begin
+ for i in 0 to x'length-1 loop
+ if(x(i) = '1') then
+ return i;
+ end if;
+ end loop;
+ return 0;
+ end f_onehot_decode;
+
+begin
+
+ RAM_A1 : generic_dpram
+ generic map(
+ g_data_width => 32,
+ g_size => c_rr_range,
+ g_with_byte_enable => false,
+ g_addr_conflict_resolution => "read_first",
+ g_dual_clock => false)
+ port map(
+ rst_n_i => rst_n_i,
+
+ clka_i => clk_i,
+ bwea_i => (others => '1'),
+ wea_i => ext_we_i,
+ aa_i => ext_adr_i,
+ da_i => ext_dat_i,
+ qa_o => ext_dat_o,
+
+ clkb_i => clk_i,
+ bweb_i => (others => '1'),
+ web_i => mem_wr,
+ ab_i => mem_adr_lv,
+ db_i => mem_dat_in,
+ qb_o => mem_dat_out);
+
+ mem_adr_lv <= std_logic_vector(to_unsigned(mem_adr, c_mem_adr_sz));
+
+
+ --align events to 32-bit words
+ GEN_ALIGN : for i in 0 to g_nports-1 generate
+ events_aligned(i*c_evt_align_sz+g_cnt_pp-1 downto i*c_evt_align_sz) <=
+ irq_i((i+1)*g_cnt_pp-1 downto i*g_cnt_pp);
+ --zero padding for word aligning
+ events_aligned((i+1)*c_evt_align_sz-1 downto i*c_evt_align_sz+g_cnt_pp) <= (others => '0');
+ end generate;
+
+ --store events into temp register, and clear those already counted
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ events_reg <= (others => '0');
+ --dbg_evt_ov_o <= '0';
+ else
+ --clear counted events and store new events to be counted
+ events_reg <= (events_reg xor events_clr) or events_aligned;
+
+ --if(to_integer(unsigned((events_reg(g_cnt_pp-1 downto 0) xor events_clr(g_cnt_pp-1 downto 0))
+ -- and events_aligned(g_cnt_pp-1 downto 0))) /= 0) then
+ -- dbg_evt_ov_o <= '1';
+ --end if;
+
+ --if(clr_flags_i = '1') then
+ -- dbg_evt_ov_o <= '0';
+ --end if;
+ end if;
+ end if;
+ end process;
+
+
+ GEN_EVT_ORED : for i in 0 to c_rr_range-1 generate
+ events_ored(i) <= or_reduce(events_reg((i+1)*g_cnt_pw-1 downto i*g_cnt_pw));
+ end generate;
+
+ events_presub <= events_reg((f_onehot_decode(events_grant)+1)*g_cnt_pw-1 downto f_onehot_decode(events_grant)*g_cnt_pw);
+
+ GEN_EVT_CLR: for i in 0 to c_rr_range-1 generate
+ events_clr((i+1)*g_cnt_pw-1 downto i*g_cnt_pw) <= events_presub when(cnt_state=WRITE and events_grant(i)='1') else
+ (others=>'0');
+ end generate;
+
+ mem_adr <= f_onehot_decode(events_grant);
+
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ cnt_state <= SEL;
+ mem_wr <= '0';
+ events_sub <= (others => '0');
+ events_preg <= (others => '0');
+ wr_conflict <= '0';
+ else
+
+ case(cnt_state) is
+ when SEL =>
+ --check each segment of events_i starting from the one pointed by round robin
+ mem_wr <= '0';
+ wr_conflict <= '0';
+
+ f_rr_arbitrate(events_ored, events_preg, events_grant);
+ if(or_reduce(events_ored) = '1') then
+ events_preg <= events_grant;
+
+ if(f_onehot_decode(events_grant) = to_integer(unsigned(ext_adr_i)) and ext_cyc_i = '1' and ext_we_i = '0') then
+ wr_conflict <= '1';
+ end if;
+ cnt_state <= WRITE;
+ end if;
+
+ when WRITE =>
+ events_sub <= events_presub;
+ if(std_logic_vector(to_unsigned(mem_adr, c_mem_adr_sz)) = ext_adr_i and ext_cyc_i = '1' and ext_we_i = '0') then
+ mem_wr <= '0';
+ cnt_state <= WRITE;
+ wr_conflict <= '1';
+ else
+ mem_wr <= '1';
+ cnt_state <= SEL;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ mem_dat_in <= mem_dat_out or events_sub;
+
+
+end behav;
diff --git a/modules/wrsw_pstats/port_cntr.vhd b/modules/wrsw_pstats/port_cntr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d38051d13651b7ddc09c879b5063a80bff9fb1e5
--- /dev/null
+++ b/modules/wrsw_pstats/port_cntr.vhd
@@ -0,0 +1,253 @@
+-------------------------------------------------------------------------------
+-- Title : One port statistics counter
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : port_cntr.vhd
+-- Author : Grzegorz Daniluk
+-- Company : CERN BE-CO-HT
+-- Created : 2012-12-20
+-- Last update: 2013-07-24
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Set of counters for a single Ethernet port of WR Switch. Inputs a vector of
+-- events and increments counters stored in Block-RAM. Each word of RAM stores
+-- g_cnt_pw counters so that they can be incremented all at once.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012, 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-12-20 0.1 greg.d Created
+-- 2013-07-24 0.2 greg.d Optimized to save FPGA resources
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+use work.wishbone_pkg.all;
+use work.gencores_pkg.all;
+
+entity port_cntr is
+ generic(
+ g_cnt_pp : integer := 64; --number of counters per port
+ g_cnt_pw : integer := 8; --number of counters per word
+ g_keep_ov : integer := 1);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ events_i : in std_logic_vector(g_cnt_pp-1 downto 0);
+
+ --memory interface, only for reading
+ ext_adr_i : in std_logic_vector(f_log2_size((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw)-1 downto 0) := (others => '0');
+ ext_dat_o : out std_logic_vector(31 downto 0);
+
+ --overflow events for 2nd layer
+ ov_cnt_o : out std_logic_vector(((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw)*g_cnt_pw-1 downto 0) --c_evt_range
+
+ --debug
+ --dbg_evt_ov_o : out std_logic;
+ --clr_flags_i : in std_logic := '0'
+ );
+end port_cntr;
+
+architecture behav of port_cntr is
+
+ constant c_rr_range : integer := (g_cnt_pp+g_cnt_pw-1)/g_cnt_pw;
+ constant c_evt_range : integer := c_rr_range*g_cnt_pw;
+ constant c_cnt_width : integer := c_wishbone_data_width/g_cnt_pw;
+ constant c_mem_adr_sz : integer := f_log2_size(c_rr_range);
+
+ type t_cnt_st is (SEL, WRITE);
+ signal cnt_state : t_cnt_st;
+
+ signal mem_dat_in : std_logic_vector(31 downto 0);
+ signal mem_dat_out : std_logic_vector(31 downto 0);
+ signal mem_adr : integer range 0 to c_rr_range-1;
+ signal mem_adr_d1 : integer range 0 to c_rr_range-1;
+ signal mem_adr_lv : std_logic_vector(c_mem_adr_sz-1 downto 0);
+ signal mem_wr : std_logic;
+
+ signal events_reg : std_logic_vector(c_evt_range-1 downto 0);
+ signal events_clr : std_logic_vector(c_evt_range-1 downto 0);
+ signal events_sub : std_logic_vector(g_cnt_pw-1 downto 0);
+ signal events_ored : std_logic_vector(c_rr_range-1 downto 0);
+ signal events_preg : std_logic_vector(c_rr_range-1 downto 0);
+ signal events_grant : std_logic_vector(c_rr_range-1 downto 0);
+ signal events_presub : std_logic_vector(g_cnt_pw-1 downto 0);
+
+ signal cnt_ov : std_logic_vector(g_cnt_pw-1 downto 0);
+
+ function f_onehot_decode
+ (x : std_logic_vector) return integer is
+ begin
+ for i in 0 to x'length-1 loop
+ if(x(i) = '1') then
+ return i;
+ end if;
+ end loop;
+ return 0;
+ end f_onehot_decode;
+
+begin
+
+ RAM_A1 : generic_dpram
+ generic map(
+ g_data_width => 32,
+ g_size => c_rr_range,
+ g_with_byte_enable => false,
+ g_addr_conflict_resolution => "read_first",
+ g_dual_clock => false)
+ port map(
+ rst_n_i => rst_n_i,
+
+ clka_i => clk_i,
+ bwea_i => (others => '1'),
+ wea_i => '0',
+ aa_i => ext_adr_i,
+ da_i => (others => '0'),
+ qa_o => ext_dat_o,
+
+ clkb_i => clk_i,
+ bweb_i => (others => '1'),
+ web_i => mem_wr,
+ ab_i => mem_adr_lv,
+ db_i => mem_dat_in,
+ qb_o => mem_dat_out);
+
+ mem_adr_lv <= std_logic_vector(to_unsigned(mem_adr, c_mem_adr_sz));
+
+ --store events into temp register, and clear those already counted
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ events_reg <= (others => '0');
+ -- dbg_evt_ov_o <= '0';
+ else
+ --clear counted events and store new events to be counted
+ events_reg(g_cnt_pp-1 downto 0) <= (events_reg(g_cnt_pp-1 downto 0) xor
+ events_clr(g_cnt_pp-1 downto 0)) or events_i(g_cnt_pp-1 downto 0);
+
+ -- if(to_integer(unsigned((events_reg(g_cnt_pp-1 downto 0) xor events_clr(g_cnt_pp-1 downto 0))
+ -- and events_i(g_cnt_pp-1 downto 0))) /= 0) then
+ -- dbg_evt_ov_o <= '1';
+ -- end if;
+
+ -- if(clr_flags_i = '1') then
+ -- dbg_evt_ov_o <= '0';
+ -- end if;
+ end if;
+ end if;
+ end process;
+
+
+ GEN_EVT_ORED : for i in 0 to c_rr_range-1 generate
+ events_ored(i) <= or_reduce(events_reg((i+1)*g_cnt_pw-1 downto i*g_cnt_pw));
+ end generate;
+
+ events_presub <= events_reg((f_onehot_decode(events_grant)+1)*g_cnt_pw-1 downto f_onehot_decode(events_grant)*g_cnt_pw);
+
+ GEN_EVT_CLR: for i in 0 to c_rr_range-1 generate
+ events_clr((i+1)*g_cnt_pw-1 downto i*g_cnt_pw) <= events_presub when(cnt_state=WRITE and events_grant(i)='1') else
+ (others=>'0');
+ end generate;
+
+ mem_adr <= f_onehot_decode(events_grant);
+
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ cnt_state <= SEL;
+ mem_wr <= '0';
+ events_sub <= (others => '0');
+ events_preg <= (others => '0');
+ else
+
+
+ case(cnt_state) is
+ when SEL =>
+ --check each segment of events_i starting from the one pointed by round robin
+ mem_wr <= '0';
+
+ f_rr_arbitrate(events_ored, events_preg, events_grant);
+ if(or_reduce(events_ored) = '1') then
+ events_preg <= events_grant;
+
+ cnt_state <= WRITE;
+ end if;
+
+ when WRITE =>
+ events_sub <= events_presub;
+ mem_wr <= '1';
+ cnt_state <= SEL;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ GEN_INCR : for i in 0 to g_cnt_pw-1 generate
+
+ KEEP_OV : if g_keep_ov = 1 generate
+ mem_dat_in((i+1)*c_cnt_width-1 downto i*c_cnt_width) <=
+ --counter overflow, don't increment
+ mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width) when (unsigned(mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width))+1 = 0) else
+ --otherwise, normal situation, just increment
+ std_logic_vector(unsigned(mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width)) + 1) when (events_sub(i) = '1') else
+ --no change
+ mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width);
+ end generate;
+
+ NKEEP_OV : if g_keep_ov = 0 generate
+ mem_dat_in((i+1)*c_cnt_width-1 downto i*c_cnt_width) <=
+ --otherwise, normal situation, just increment
+ std_logic_vector(unsigned(mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width)) + 1) when (events_sub(i) = '1') else
+ --no change
+ mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width);
+ end generate;
+
+
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ cnt_ov(i) <= '0';
+ else
+ if((unsigned(mem_dat_out((i+1)*c_cnt_width-1 downto i*c_cnt_width))+1 = 0) and mem_wr = '1' and events_sub(i) = '1') then
+ cnt_ov(i) <= '1';
+ else
+ cnt_ov(i) <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ end generate;
+
+ -----------------------------------------------
+ --overflow events for 2nd layer counter
+ process(clk_i) --delay mem_adr by 1 cycle to match ov_cnt_o signal
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ mem_adr_d1 <= 0;
+ else
+ mem_adr_d1 <= mem_adr;
+ end if;
+ end if;
+ end process;
+
+ --multiplexer driven from mem_adr delayed by 1 cycle
+ GEN_CNT_OV: for I in 0 to c_rr_range-1 generate
+ ov_cnt_o((I+1)*g_cnt_pw-1 downto I*g_cnt_pw) <= cnt_ov when (mem_adr_d1 = I) else (others=>'0');
+ end generate;
+
+
+end behav;
diff --git a/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd b/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d0c8eed2d828511ab2a0d9694920c45a050a404a
--- /dev/null
+++ b/modules/wrsw_pstats/pstats_wbgen2_pkg.vhd
@@ -0,0 +1,91 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR Switch Per-Port Statistic Counters
+---------------------------------------------------------------------------------------
+-- File : pstats_wbgen2_pkg.vhd
+-- Author : auto-generated by wbgen2 from wrsw_pstats.wb
+-- Created : Tue Jul 23 13:48:48 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pstats.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package pstats_wbgen2_pkg is
+
+
+ -- Input registers (user design -> WB slave)
+
+ type t_pstats_in_registers is record
+ cr_rd_en_i : std_logic;
+ cr_rd_irq_i : std_logic;
+ l1_cnt_val_i : std_logic_vector(31 downto 0);
+ l2_cnt_val_i : std_logic_vector(31 downto 0);
+ end record;
+
+ constant c_pstats_in_registers_init_value: t_pstats_in_registers := (
+ cr_rd_en_i => '0',
+ cr_rd_irq_i => '0',
+ l1_cnt_val_i => (others => '0'),
+ l2_cnt_val_i => (others => '0')
+ );
+
+ -- Output registers (WB slave -> user design)
+
+ type t_pstats_out_registers is record
+ cr_rd_en_o : std_logic;
+ cr_rd_en_load_o : std_logic;
+ cr_rd_irq_o : std_logic;
+ cr_rd_irq_load_o : std_logic;
+ cr_port_o : std_logic_vector(4 downto 0);
+ cr_addr_o : std_logic_vector(4 downto 0);
+ end record;
+
+ constant c_pstats_out_registers_init_value: t_pstats_out_registers := (
+ cr_rd_en_o => '0',
+ cr_rd_en_load_o => '0',
+ cr_rd_irq_o => '0',
+ cr_rd_irq_load_o => '0',
+ cr_port_o => (others => '0'),
+ cr_addr_o => (others => '0')
+ );
+ function "or" (left, right: t_pstats_in_registers) return t_pstats_in_registers;
+ function f_x_to_zero (x:std_logic) return std_logic;
+ function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body pstats_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if;
+end loop;
+return tmp;
+end function;
+function "or" (left, right: t_pstats_in_registers) return t_pstats_in_registers is
+variable tmp: t_pstats_in_registers;
+begin
+tmp.cr_rd_en_i := f_x_to_zero(left.cr_rd_en_i) or f_x_to_zero(right.cr_rd_en_i);
+tmp.cr_rd_irq_i := f_x_to_zero(left.cr_rd_irq_i) or f_x_to_zero(right.cr_rd_irq_i);
+tmp.l1_cnt_val_i := f_x_to_zero(left.l1_cnt_val_i) or f_x_to_zero(right.l1_cnt_val_i);
+tmp.l2_cnt_val_i := f_x_to_zero(left.l2_cnt_val_i) or f_x_to_zero(right.l2_cnt_val_i);
+return tmp;
+end function;
+end package body;
diff --git a/modules/wrsw_pstats/pstats_wishbone_slave.vhd b/modules/wrsw_pstats/pstats_wishbone_slave.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed3da704fbdbfdcf0b2c10bb7827b2f8d5fa11cd
--- /dev/null
+++ b/modules/wrsw_pstats/pstats_wishbone_slave.vhd
@@ -0,0 +1,427 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR Switch Per-Port Statistic Counters
+---------------------------------------------------------------------------------------
+-- File : pstats_wishbone_slave.vhd
+-- Author : auto-generated by wbgen2 from wrsw_pstats.wb
+-- Created : Tue Jul 23 13:48:48 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pstats.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+use work.pstats_wbgen2_pkg.all;
+
+
+entity pstats_wishbone_slave is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic;
+ irq_port0_i : in std_logic;
+ irq_port0_ack_o : out std_logic;
+ irq_port1_i : in std_logic;
+ irq_port1_ack_o : out std_logic;
+ irq_port2_i : in std_logic;
+ irq_port2_ack_o : out std_logic;
+ irq_port3_i : in std_logic;
+ irq_port3_ack_o : out std_logic;
+ irq_port4_i : in std_logic;
+ irq_port4_ack_o : out std_logic;
+ irq_port5_i : in std_logic;
+ irq_port5_ack_o : out std_logic;
+ irq_port6_i : in std_logic;
+ irq_port6_ack_o : out std_logic;
+ irq_port7_i : in std_logic;
+ irq_port7_ack_o : out std_logic;
+ irq_port8_i : in std_logic;
+ irq_port8_ack_o : out std_logic;
+ irq_port9_i : in std_logic;
+ irq_port9_ack_o : out std_logic;
+ irq_port10_i : in std_logic;
+ irq_port10_ack_o : out std_logic;
+ irq_port11_i : in std_logic;
+ irq_port11_ack_o : out std_logic;
+ irq_port12_i : in std_logic;
+ irq_port12_ack_o : out std_logic;
+ irq_port13_i : in std_logic;
+ irq_port13_ack_o : out std_logic;
+ irq_port14_i : in std_logic;
+ irq_port14_ack_o : out std_logic;
+ irq_port15_i : in std_logic;
+ irq_port15_ack_o : out std_logic;
+ irq_port16_i : in std_logic;
+ irq_port16_ack_o : out std_logic;
+ irq_port17_i : in std_logic;
+ irq_port17_ack_o : out std_logic;
+ regs_i : in t_pstats_in_registers;
+ regs_o : out t_pstats_out_registers
+ );
+end pstats_wishbone_slave;
+
+architecture syn of pstats_wishbone_slave is
+
+signal pstats_cr_port_int : std_logic_vector(4 downto 0);
+signal pstats_cr_addr_int : std_logic_vector(4 downto 0);
+signal eic_idr_int : std_logic_vector(17 downto 0);
+signal eic_idr_write_int : std_logic ;
+signal eic_ier_int : std_logic_vector(17 downto 0);
+signal eic_ier_write_int : std_logic ;
+signal eic_imr_int : std_logic_vector(17 downto 0);
+signal eic_isr_clear_int : std_logic_vector(17 downto 0);
+signal eic_isr_status_int : std_logic_vector(17 downto 0);
+signal eic_irq_ack_int : std_logic_vector(17 downto 0);
+signal eic_isr_write_int : std_logic ;
+signal irq_inputs_vector_int : std_logic_vector(17 downto 0);
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(3 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_dat_i;
+ bwsel_reg <= wb_sel_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ regs_o.cr_rd_en_load_o <= '0';
+ regs_o.cr_rd_irq_load_o <= '0';
+ pstats_cr_port_int <= "00000";
+ pstats_cr_addr_int <= "00000";
+ eic_idr_write_int <= '0';
+ eic_ier_write_int <= '0';
+ eic_isr_write_int <= '0';
+ elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ regs_o.cr_rd_en_load_o <= '0';
+ regs_o.cr_rd_irq_load_o <= '0';
+ eic_idr_write_int <= '0';
+ eic_ier_write_int <= '0';
+ eic_isr_write_int <= '0';
+ ack_in_progress <= '0';
+ else
+ regs_o.cr_rd_en_load_o <= '0';
+ regs_o.cr_rd_irq_load_o <= '0';
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(3 downto 0) is
+ when "0000" =>
+ if (wb_we_i = '1') then
+ regs_o.cr_rd_en_load_o <= '1';
+ regs_o.cr_rd_irq_load_o <= '1';
+ pstats_cr_port_int <= wrdata_reg(12 downto 8);
+ pstats_cr_addr_int <= wrdata_reg(20 downto 16);
+ end if;
+ rddata_reg(0) <= regs_i.cr_rd_en_i;
+ rddata_reg(1) <= regs_i.cr_rd_irq_i;
+ rddata_reg(12 downto 8) <= pstats_cr_port_int;
+ rddata_reg(20 downto 16) <= pstats_cr_addr_int;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "0001" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.l1_cnt_val_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "0010" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.l2_cnt_val_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1000" =>
+ if (wb_we_i = '1') then
+ eic_idr_write_int <= '1';
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1001" =>
+ if (wb_we_i = '1') then
+ eic_ier_write_int <= '1';
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1010" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(17 downto 0) <= eic_imr_int(17 downto 0);
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1011" =>
+ if (wb_we_i = '1') then
+ eic_isr_write_int <= '1';
+ end if;
+ rddata_reg(17 downto 0) <= eic_isr_status_int(17 downto 0);
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Drive the data output bus
+ wb_dat_o <= rddata_reg;
+-- Enable transfer of counter content
+ regs_o.cr_rd_en_o <= wrdata_reg(0);
+-- Enable transfer of per-counter IRQ state
+ regs_o.cr_rd_irq_o <= wrdata_reg(1);
+-- Port number
+ regs_o.cr_port_o <= pstats_cr_port_int;
+-- Memory address
+ regs_o.cr_addr_o <= pstats_cr_addr_int;
+-- 4 counters' values
+-- 4 counters' values
+-- extra code for reg/fifo/mem: Interrupt disable register
+ eic_idr_int(17 downto 0) <= wrdata_reg(17 downto 0);
+-- extra code for reg/fifo/mem: Interrupt enable register
+ eic_ier_int(17 downto 0) <= wrdata_reg(17 downto 0);
+-- extra code for reg/fifo/mem: Interrupt status register
+ eic_isr_clear_int(17 downto 0) <= wrdata_reg(17 downto 0);
+-- extra code for reg/fifo/mem: IRQ_CONTROLLER
+ eic_irq_controller_inst : wbgen2_eic
+ generic map (
+ g_num_interrupts => 18,
+ g_irq00_mode => 3,
+ g_irq01_mode => 3,
+ g_irq02_mode => 3,
+ g_irq03_mode => 3,
+ g_irq04_mode => 3,
+ g_irq05_mode => 3,
+ g_irq06_mode => 3,
+ g_irq07_mode => 3,
+ g_irq08_mode => 3,
+ g_irq09_mode => 3,
+ g_irq0a_mode => 3,
+ g_irq0b_mode => 3,
+ g_irq0c_mode => 3,
+ g_irq0d_mode => 3,
+ g_irq0e_mode => 3,
+ g_irq0f_mode => 3,
+ g_irq10_mode => 3,
+ g_irq11_mode => 3,
+ g_irq12_mode => 0,
+ g_irq13_mode => 0,
+ g_irq14_mode => 0,
+ g_irq15_mode => 0,
+ g_irq16_mode => 0,
+ g_irq17_mode => 0,
+ g_irq18_mode => 0,
+ g_irq19_mode => 0,
+ g_irq1a_mode => 0,
+ g_irq1b_mode => 0,
+ g_irq1c_mode => 0,
+ g_irq1d_mode => 0,
+ g_irq1e_mode => 0,
+ g_irq1f_mode => 0
+ )
+ port map (
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ irq_i => irq_inputs_vector_int,
+ irq_ack_o => eic_irq_ack_int,
+ reg_imr_o => eic_imr_int,
+ reg_ier_i => eic_ier_int,
+ reg_ier_wr_stb_i => eic_ier_write_int,
+ reg_idr_i => eic_idr_int,
+ reg_idr_wr_stb_i => eic_idr_write_int,
+ reg_isr_o => eic_isr_status_int,
+ reg_isr_i => eic_isr_clear_int,
+ reg_isr_wr_stb_i => eic_isr_write_int,
+ wb_irq_o => wb_int_o
+ );
+
+ irq_inputs_vector_int(0) <= irq_port0_i;
+ irq_port0_ack_o <= eic_irq_ack_int(0);
+ irq_inputs_vector_int(1) <= irq_port1_i;
+ irq_port1_ack_o <= eic_irq_ack_int(1);
+ irq_inputs_vector_int(2) <= irq_port2_i;
+ irq_port2_ack_o <= eic_irq_ack_int(2);
+ irq_inputs_vector_int(3) <= irq_port3_i;
+ irq_port3_ack_o <= eic_irq_ack_int(3);
+ irq_inputs_vector_int(4) <= irq_port4_i;
+ irq_port4_ack_o <= eic_irq_ack_int(4);
+ irq_inputs_vector_int(5) <= irq_port5_i;
+ irq_port5_ack_o <= eic_irq_ack_int(5);
+ irq_inputs_vector_int(6) <= irq_port6_i;
+ irq_port6_ack_o <= eic_irq_ack_int(6);
+ irq_inputs_vector_int(7) <= irq_port7_i;
+ irq_port7_ack_o <= eic_irq_ack_int(7);
+ irq_inputs_vector_int(8) <= irq_port8_i;
+ irq_port8_ack_o <= eic_irq_ack_int(8);
+ irq_inputs_vector_int(9) <= irq_port9_i;
+ irq_port9_ack_o <= eic_irq_ack_int(9);
+ irq_inputs_vector_int(10) <= irq_port10_i;
+ irq_port10_ack_o <= eic_irq_ack_int(10);
+ irq_inputs_vector_int(11) <= irq_port11_i;
+ irq_port11_ack_o <= eic_irq_ack_int(11);
+ irq_inputs_vector_int(12) <= irq_port12_i;
+ irq_port12_ack_o <= eic_irq_ack_int(12);
+ irq_inputs_vector_int(13) <= irq_port13_i;
+ irq_port13_ack_o <= eic_irq_ack_int(13);
+ irq_inputs_vector_int(14) <= irq_port14_i;
+ irq_port14_ack_o <= eic_irq_ack_int(14);
+ irq_inputs_vector_int(15) <= irq_port15_i;
+ irq_port15_ack_o <= eic_irq_ack_int(15);
+ irq_inputs_vector_int(16) <= irq_port16_i;
+ irq_port16_ack_o <= eic_irq_ack_int(16);
+ irq_inputs_vector_int(17) <= irq_port17_i;
+ irq_port17_ack_o <= eic_irq_ack_int(17);
+ rwaddr_reg <= wb_adr_i;
+ wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/modules/wrsw_pstats/wrsw_dummy/Manifest.py b/modules/wrsw_pstats/wrsw_dummy/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..47918b5e1b11d740f9a0ff94d649550f9485caf2
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_dummy/Manifest.py
@@ -0,0 +1 @@
+files = ["dummy_rmon.vhd", "dummy_wbgen2_pkg.vhd", "dummy_wishbone_slave.vhd"]
diff --git a/modules/wrsw_pstats/wrsw_dummy/dummy_regs.h b/modules/wrsw_pstats/wrsw_dummy/dummy_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..9a8885359c7a07d4c4891a54b64d452ff3aeae00
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_regs.h
@@ -0,0 +1,108 @@
+/*
+ Register definitions for slave core: WR Switch dummy Statistic Counters
+
+ * File : dummy_regs.h
+ * Author : auto-generated by wbgen2 from wrsw_dummy.wb
+ * Created : Thu Feb 14 15:43:14 2013
+ * Standard : ANSI C
+
+ THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dummy.wb
+ DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WRSW_DUMMY_WB
+#define __WBGEN2_REGDEFS_WRSW_DUMMY_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: control reg */
+
+/* definitions for field: reset counters in reg: control reg */
+#define DUMMY_CR_RST WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: port 0 cnt */
+
+/* definitions for register: port 0 cnt */
+
+/* definitions for register: port 1 cnt */
+
+/* definitions for register: port 1 cnt */
+
+/* definitions for register: port 1 cnt */
+
+/* definitions for register: port 1 cnt */
+
+/* definitions for register: port 3 cnt */
+
+/* definitions for register: port 3 cnt */
+
+/* definitions for register: port 4 cnt */
+
+/* definitions for register: port 4 cnt */
+
+/* definitions for register: port 5 cnt */
+
+/* definitions for register: port 5 cnt */
+
+/* definitions for register: port 6 cnt */
+
+/* definitions for register: port 6 cnt */
+
+/* definitions for register: port 7 cnt */
+
+/* definitions for register: port 7 cnt */
+
+PACKED struct DUMMY_WB {
+ /* [0x0]: REG control reg */
+ uint32_t CR;
+ /* [0x4]: REG port 0 cnt */
+ uint32_t P0_TX;
+ /* [0x8]: REG port 0 cnt */
+ uint32_t P0_RX;
+ /* [0xc]: REG port 1 cnt */
+ uint32_t P1_TX;
+ /* [0x10]: REG port 1 cnt */
+ uint32_t P1_RX;
+ /* [0x14]: REG port 1 cnt */
+ uint32_t P2_TX;
+ /* [0x18]: REG port 1 cnt */
+ uint32_t P2_RX;
+ /* [0x1c]: REG port 3 cnt */
+ uint32_t P3_TX;
+ /* [0x20]: REG port 3 cnt */
+ uint32_t P3_RX;
+ /* [0x24]: REG port 4 cnt */
+ uint32_t P4_TX;
+ /* [0x28]: REG port 4 cnt */
+ uint32_t P4_RX;
+ /* [0x2c]: REG port 5 cnt */
+ uint32_t P5_TX;
+ /* [0x30]: REG port 5 cnt */
+ uint32_t P5_RX;
+ /* [0x34]: REG port 6 cnt */
+ uint32_t P6_TX;
+ /* [0x38]: REG port 6 cnt */
+ uint32_t P6_RX;
+ /* [0x3c]: REG port 7 cnt */
+ uint32_t P7_TX;
+ /* [0x40]: REG port 7 cnt */
+ uint32_t P7_RX;
+};
+
+#endif
diff --git a/modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd b/modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90229cfaae91e941f6075a992d8b4c597633b36b
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd
@@ -0,0 +1,116 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.dummy_wbgen2_pkg.all;
+use work.wishbone_pkg.all;
+
+entity dummy_rmon is
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nports : integer := 8;
+ g_cnt_pp : integer := 2);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+end dummy_rmon;
+
+architecture behav of dummy_rmon is
+
+ component dummy_wishbone_slave
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(4 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ regs_i : in t_dummy_in_registers;
+ regs_o : out t_dummy_out_registers
+ );
+ end component;
+
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+ signal wb_regs_in : t_dummy_in_registers;
+ signal wb_regs_out : t_dummy_out_registers;
+
+ type t_rmon_reg is array(natural range <>) of std_logic_vector(31 downto 0);
+ signal regs : t_rmon_reg(g_nports*g_cnt_pp-1 downto 0);
+
+
+begin
+
+ U_Adapter : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => true,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_i,
+ rst_n_i => rst_n_i,
+ slave_i => wb_i,
+ slave_o => wb_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ U_WB_if: dummy_wishbone_slave
+ port map(
+ rst_n_i => rst_n_i,
+ clk_sys_i => clk_i,
+ wb_adr_i => wb_in.adr(4 downto 0),
+ wb_dat_i => wb_in.dat,
+ wb_dat_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
+ wb_stall_o => wb_out.stall,
+ regs_i => wb_regs_in,
+ regs_o => wb_regs_out
+ );
+
+ wb_regs_in.p0_tx_i <= regs(0);
+ wb_regs_in.p0_rx_i <= regs(1);
+ wb_regs_in.p1_tx_i <= regs(2);
+ wb_regs_in.p1_rx_i <= regs(3);
+ wb_regs_in.p2_tx_i <= regs(4);
+ wb_regs_in.p2_rx_i <= regs(5);
+ wb_regs_in.p3_tx_i <= regs(6);
+ wb_regs_in.p3_rx_i <= regs(7);
+ wb_regs_in.p4_tx_i <= regs(8);
+ wb_regs_in.p4_rx_i <= regs(9);
+ wb_regs_in.p5_tx_i <= regs(10);
+ wb_regs_in.p5_rx_i <= regs(11);
+ wb_regs_in.p6_tx_i <= regs(12);
+ wb_regs_in.p6_rx_i <= regs(13);
+ wb_regs_in.p7_tx_i <= regs(14);
+ wb_regs_in.p7_rx_i <= regs(15);
+
+ GEN_REGS: for i in 0 to g_nports*g_cnt_pp-1 generate
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i='0' or wb_regs_out.cr_rst_o='1') then
+ regs(i) <= (others=>'0');
+ elsif(events_i(i) = '1') then
+ regs(i) <= std_logic_vector(unsigned(regs(i)) + 1);
+ end if;
+ end if;
+ end process;
+ end generate;
+end behav;
diff --git a/modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd b/modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..845b810e4ca60f00cbfc2bbed793e0ca3172ed26
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd
@@ -0,0 +1,116 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR Switch dummy Statistic Counters
+---------------------------------------------------------------------------------------
+-- File : dummy_wbgen2_pkg.vhd
+-- Author : auto-generated by wbgen2 from wrsw_dummy.wb
+-- Created : Thu Feb 14 15:43:14 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dummy.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package dummy_wbgen2_pkg is
+
+
+ -- Input registers (user design -> WB slave)
+
+ type t_dummy_in_registers is record
+ p0_tx_i : std_logic_vector(31 downto 0);
+ p0_rx_i : std_logic_vector(31 downto 0);
+ p1_tx_i : std_logic_vector(31 downto 0);
+ p1_rx_i : std_logic_vector(31 downto 0);
+ p2_tx_i : std_logic_vector(31 downto 0);
+ p2_rx_i : std_logic_vector(31 downto 0);
+ p3_tx_i : std_logic_vector(31 downto 0);
+ p3_rx_i : std_logic_vector(31 downto 0);
+ p4_tx_i : std_logic_vector(31 downto 0);
+ p4_rx_i : std_logic_vector(31 downto 0);
+ p5_tx_i : std_logic_vector(31 downto 0);
+ p5_rx_i : std_logic_vector(31 downto 0);
+ p6_tx_i : std_logic_vector(31 downto 0);
+ p6_rx_i : std_logic_vector(31 downto 0);
+ p7_tx_i : std_logic_vector(31 downto 0);
+ p7_rx_i : std_logic_vector(31 downto 0);
+ end record;
+
+ constant c_dummy_in_registers_init_value: t_dummy_in_registers := (
+ p0_tx_i => (others => '0'),
+ p0_rx_i => (others => '0'),
+ p1_tx_i => (others => '0'),
+ p1_rx_i => (others => '0'),
+ p2_tx_i => (others => '0'),
+ p2_rx_i => (others => '0'),
+ p3_tx_i => (others => '0'),
+ p3_rx_i => (others => '0'),
+ p4_tx_i => (others => '0'),
+ p4_rx_i => (others => '0'),
+ p5_tx_i => (others => '0'),
+ p5_rx_i => (others => '0'),
+ p6_tx_i => (others => '0'),
+ p6_rx_i => (others => '0'),
+ p7_tx_i => (others => '0'),
+ p7_rx_i => (others => '0')
+ );
+
+ -- Output registers (WB slave -> user design)
+
+ type t_dummy_out_registers is record
+ cr_rst_o : std_logic;
+ end record;
+
+ constant c_dummy_out_registers_init_value: t_dummy_out_registers := (
+ cr_rst_o => '0'
+ );
+ function "or" (left, right: t_dummy_in_registers) return t_dummy_in_registers;
+ function f_x_to_zero (x:std_logic) return std_logic;
+ function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body dummy_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if;
+end loop;
+return tmp;
+end function;
+function "or" (left, right: t_dummy_in_registers) return t_dummy_in_registers is
+variable tmp: t_dummy_in_registers;
+begin
+tmp.p0_tx_i := f_x_to_zero(left.p0_tx_i) or f_x_to_zero(right.p0_tx_i);
+tmp.p0_rx_i := f_x_to_zero(left.p0_rx_i) or f_x_to_zero(right.p0_rx_i);
+tmp.p1_tx_i := f_x_to_zero(left.p1_tx_i) or f_x_to_zero(right.p1_tx_i);
+tmp.p1_rx_i := f_x_to_zero(left.p1_rx_i) or f_x_to_zero(right.p1_rx_i);
+tmp.p2_tx_i := f_x_to_zero(left.p2_tx_i) or f_x_to_zero(right.p2_tx_i);
+tmp.p2_rx_i := f_x_to_zero(left.p2_rx_i) or f_x_to_zero(right.p2_rx_i);
+tmp.p3_tx_i := f_x_to_zero(left.p3_tx_i) or f_x_to_zero(right.p3_tx_i);
+tmp.p3_rx_i := f_x_to_zero(left.p3_rx_i) or f_x_to_zero(right.p3_rx_i);
+tmp.p4_tx_i := f_x_to_zero(left.p4_tx_i) or f_x_to_zero(right.p4_tx_i);
+tmp.p4_rx_i := f_x_to_zero(left.p4_rx_i) or f_x_to_zero(right.p4_rx_i);
+tmp.p5_tx_i := f_x_to_zero(left.p5_tx_i) or f_x_to_zero(right.p5_tx_i);
+tmp.p5_rx_i := f_x_to_zero(left.p5_rx_i) or f_x_to_zero(right.p5_rx_i);
+tmp.p6_tx_i := f_x_to_zero(left.p6_tx_i) or f_x_to_zero(right.p6_tx_i);
+tmp.p6_rx_i := f_x_to_zero(left.p6_rx_i) or f_x_to_zero(right.p6_rx_i);
+tmp.p7_tx_i := f_x_to_zero(left.p7_tx_i) or f_x_to_zero(right.p7_tx_i);
+tmp.p7_rx_i := f_x_to_zero(left.p7_rx_i) or f_x_to_zero(right.p7_rx_i);
+return tmp;
+end function;
+end package body;
diff --git a/modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd b/modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..20f7d939766f41ce7e2871159865100b6b4da823
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd
@@ -0,0 +1,264 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR Switch dummy Statistic Counters
+---------------------------------------------------------------------------------------
+-- File : dummy_wishbone_slave.vhd
+-- Author : auto-generated by wbgen2 from wrsw_dummy.wb
+-- Created : Thu Feb 14 15:43:14 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dummy.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.dummy_wbgen2_pkg.all;
+
+
+entity dummy_wishbone_slave is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(4 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ regs_i : in t_dummy_in_registers;
+ regs_o : out t_dummy_out_registers
+ );
+end dummy_wishbone_slave;
+
+architecture syn of dummy_wishbone_slave is
+
+signal dummy_cr_rst_dly0 : std_logic ;
+signal dummy_cr_rst_int : std_logic ;
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(4 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_dat_i;
+ bwsel_reg <= wb_sel_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ dummy_cr_rst_int <= '0';
+ elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ dummy_cr_rst_int <= '0';
+ ack_in_progress <= '0';
+ else
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(4 downto 0) is
+ when "00000" =>
+ if (wb_we_i = '1') then
+ dummy_cr_rst_int <= wrdata_reg(0);
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(2) <= '1';
+ ack_in_progress <= '1';
+ when "00001" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p0_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00010" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p0_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00011" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p1_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00100" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p1_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00101" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p2_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00110" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p2_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00111" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p3_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01000" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p3_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01001" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p4_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01010" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p4_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01011" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p5_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01100" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p5_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01101" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p6_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01110" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p6_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01111" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p7_tx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "10000" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.p7_rx_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Drive the data output bus
+ wb_dat_o <= rddata_reg;
+-- reset counters
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ dummy_cr_rst_dly0 <= '0';
+ regs_o.cr_rst_o <= '0';
+ elsif rising_edge(clk_sys_i) then
+ dummy_cr_rst_dly0 <= dummy_cr_rst_int;
+ regs_o.cr_rst_o <= dummy_cr_rst_int and (not dummy_cr_rst_dly0);
+ end if;
+ end process;
+
+
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+-- Enable transfer of counter content
+ rwaddr_reg <= wb_adr_i;
+ wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/modules/wrsw_pstats/wrsw_dummy/wrsw_dummy.wb b/modules/wrsw_pstats/wrsw_dummy/wrsw_dummy.wb
new file mode 100644
index 0000000000000000000000000000000000000000..5ac263742cd245cd162179eb5eac9cee9e67532c
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_dummy/wrsw_dummy.wb
@@ -0,0 +1,240 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+-- White-Rabbit Per-Port Statistic Couters
+-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+--
+-- Use wbgen2 to generate code, documentation and more.
+-- wbgen2 is available at:
+-- http://www.ohwr.org/projects/wishbone-gen
+--
+
+peripheral {
+
+ name = "WR Switch dummy Statistic Counters";
+ description = "The set of counters for counting traffic statistics on each Ethernet port of WR Switch";
+ hdl_entity = "dummy_wishbone_slave";
+ prefix = "dummy";
+
+ reg {
+ name = "control reg";
+ prefix = "CR";
+
+ field {
+ name = "reset counters";
+ prefix = "RST";
+ type = MONOSTABLE;
+ size = 1;
+ };
+ };
+
+ reg {
+ name = "port 0 cnt";
+ prefix = "P0_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 0 cnt";
+ prefix = "P0_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 1 cnt";
+ prefix = "P1_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 1 cnt";
+ prefix = "P1_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+
+ reg {
+ name = "port 1 cnt";
+ prefix = "P2_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 1 cnt";
+ prefix = "P2_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 3 cnt";
+ prefix = "P3_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 3 cnt";
+ prefix = "P3_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 4 cnt";
+ prefix = "P4_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 4 cnt";
+ prefix = "P4_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 5 cnt";
+ prefix = "P5_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 5 cnt";
+ prefix = "P5_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+
+ reg {
+ name = "port 6 cnt";
+ prefix = "P6_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 6 cnt";
+ prefix = "P6_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+
+ reg {
+ name = "port 7 cnt";
+ prefix = "P7_TX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "port 7 cnt";
+ prefix = "P7_RX";
+
+ field {
+ name = "Enable transfer of counter content";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+};
diff --git a/modules/wrsw_pstats/wrsw_pstats.vhd b/modules/wrsw_pstats/wrsw_pstats.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4a72f1152bc91c12a300822142ba8fb931f3b285
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_pstats.vhd
@@ -0,0 +1,451 @@
+-------------------------------------------------------------------------------
+-- Title : Per-port statistics counters
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : wrsw_pstats.vhd
+-- Author : Grzegorz Daniluk
+-- Company : CERN BE-CO-HT
+-- Created : 2013-01-11
+-- Last update: 2013-03-04
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Module implements the set of statistic counters for each port of WR Switch.
+-- It is fully generic so that the number of ports, number of counters per port
+-- and number of counters stored in a single 32-bit memory word can be
+-- configured. It consists of two layers of counters. L1 is made of g_nports
+-- instances of port_cntrs while L2 collects overlow events from all L1
+-- port_cntrs to one port_cntrs component. The module can also generate an
+-- interrupt when any of the counters (in any port) overflows. IRQ_RAM component
+-- provides the information to the software saying which counters have
+-- overflowed.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2013-01-11 0.1 greg.d Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+use work.pstats_wbgen2_pkg.all;
+
+entity wrsw_pstats is
+ generic(
+ g_nports : integer := 2;
+ g_cnt_pp : integer := 16;
+ g_cnt_pw : integer := 4;
+ --Layer 2
+ g_L2_cnt_pw : integer := 4;
+ g_keep_ov : integer := 1);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic);
+end wrsw_pstats;
+
+architecture behav of wrsw_pstats is
+
+ component pstats_wishbone_slave
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic;
+ irq_port0_i : in std_logic;
+ irq_port0_ack_o : out std_logic;
+ irq_port1_i : in std_logic;
+ irq_port1_ack_o : out std_logic;
+ irq_port2_i : in std_logic;
+ irq_port2_ack_o : out std_logic;
+ irq_port3_i : in std_logic;
+ irq_port3_ack_o : out std_logic;
+ irq_port4_i : in std_logic;
+ irq_port4_ack_o : out std_logic;
+ irq_port5_i : in std_logic;
+ irq_port5_ack_o : out std_logic;
+ irq_port6_i : in std_logic;
+ irq_port6_ack_o : out std_logic;
+ irq_port7_i : in std_logic;
+ irq_port7_ack_o : out std_logic;
+ irq_port8_i : in std_logic;
+ irq_port8_ack_o : out std_logic;
+ irq_port9_i : in std_logic;
+ irq_port9_ack_o : out std_logic;
+ irq_port10_i : in std_logic;
+ irq_port10_ack_o : out std_logic;
+ irq_port11_i : in std_logic;
+ irq_port11_ack_o : out std_logic;
+ irq_port12_i : in std_logic;
+ irq_port12_ack_o : out std_logic;
+ irq_port13_i : in std_logic;
+ irq_port13_ack_o : out std_logic;
+ irq_port14_i : in std_logic;
+ irq_port14_ack_o : out std_logic;
+ irq_port15_i : in std_logic;
+ irq_port15_ack_o : out std_logic;
+ irq_port16_i : in std_logic;
+ irq_port16_ack_o : out std_logic;
+ irq_port17_i : in std_logic;
+ irq_port17_ack_o : out std_logic;
+ regs_i : in t_pstats_in_registers;
+ regs_o : out t_pstats_out_registers);
+ end component;
+
+ component port_cntr
+ generic(
+ g_cnt_pp : integer;
+ g_cnt_pw : integer;
+ g_keep_ov : integer);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+ events_i : in std_logic_vector(g_cnt_pp-1 downto 0);
+ ext_adr_i : in std_logic_vector(f_log2_size((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw)-1 downto 0);
+ ext_dat_o : out std_logic_vector(31 downto 0);
+ ov_cnt_o : out
+ std_logic_vector(((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw)*g_cnt_pw-1 downto 0)); --c_evt_range
+ end component;
+
+ component irq_ram
+ generic(
+ g_nports : integer := 8;
+ g_cnt_pp : integer := 64;
+ g_cnt_pw : integer := 32);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+ irq_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+ ext_cyc_i : in std_logic := '0';
+ ext_adr_i : in std_logic_vector(f_log2_size(g_nports*((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw))-1 downto 0) := (others => '0');
+ ext_we_i : in std_logic := '0';
+ ext_dat_i : in std_logic_vector(31 downto 0) := (others => '0');
+ ext_dat_o : out std_logic_vector(31 downto 0));
+ end component;
+
+ ----------------------------------------------------------
+ ----------------------------------------------------------
+
+ constant c_adr_mem_sz : integer := f_log2_size((g_cnt_pp+g_cnt_pw-1)/g_cnt_pw);
+ constant c_adr_psel_sz : integer := f_log2_size(g_nports);
+ constant c_portirq_sz : integer := (g_cnt_pp+g_cnt_pw-1)/g_cnt_pw;
+ constant c_L2_event_sz : integer := c_portirq_sz*g_cnt_pw;
+ constant c_L2_adr_mem_sz : integer := f_log2_size((g_nports*g_cnt_pp+g_L2_cnt_pw-1)/g_L2_cnt_pw);
+ constant c_IRQ_pw : integer := 32;
+ constant c_IRQ_adr_mem_sz : integer := f_log2_size(g_nports*((g_cnt_pp+c_IRQ_pw-1)/c_IRQ_pw));
+
+ ----------------------------------------------------------
+
+ --for wishbone interface
+ signal wb_regs_in : t_pstats_in_registers;
+ signal wb_regs_out : t_pstats_out_registers;
+
+ --for wb_gen wishbone interface
+ signal rd_port : std_logic_vector(c_adr_psel_sz-1 downto 0);
+ signal rd_val : std_logic_vector(31 downto 0);
+ signal rd_en : std_logic;
+
+ --for ports' ext mem interfaces
+ type t_ext_dat_array is array(natural range <>) of std_logic_vector(31 downto 0);
+ signal p_dat_out : t_ext_dat_array(g_nports-1 downto 0);
+
+ type t_rd_st is (IDLE, READ_LS, READ_MS, WRITE_LS, WRITE_MS);
+ signal rd_state : t_rd_st;
+ signal rd_irq : std_logic;
+
+ signal irq : std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+ --signal evt_ov : std_logic_vector(g_nports-1 downto 0);
+
+ --Layer 2
+ signal L2_events : std_logic_vector(g_nports*c_L2_event_sz-1 downto 0);
+ signal L2_adr : std_logic_vector(c_L2_adr_mem_sz-1 downto 0);
+ signal L2_dat_out : std_logic_vector(31 downto 0);
+ signal L2_rd_val : std_logic_vector(31 downto 0);
+
+ --Layer 3 (a.k.a. IRQ)
+ signal L3_events : std_logic_vector(g_nports*c_L2_event_sz-1 downto 0);
+ signal IRQ_cyc : std_logic;
+ signal IRQ_port_adr : unsigned(c_IRQ_adr_mem_sz-1 downto 0);
+ signal IRQ_adr : std_logic_vector(c_IRQ_adr_mem_sz-1 downto 0);
+ signal IRQ_we : std_logic;
+ signal IRQ_dat_out : std_logic_vector(31 downto 0);
+
+ signal port_irq : std_logic_vector(17 downto 0);
+ signal port_irq_ack : std_logic_vector(17 downto 0);
+ signal port_irq_reg : std_logic_vector(17 downto 0);
+
+begin
+
+ U_WB_Slave : pstats_wishbone_slave
+ port map (
+ rst_n_i => rst_n_i,
+ clk_sys_i => clk_i,
+ wb_adr_i => wb_adr_i,
+ wb_dat_i => wb_dat_i,
+ wb_dat_o => wb_dat_o,
+ wb_cyc_i => wb_cyc_i,
+ wb_sel_i => wb_sel_i,
+ wb_stb_i => wb_stb_i,
+ wb_we_i => wb_we_i,
+ wb_ack_o => wb_ack_o,
+ wb_stall_o => wb_stall_o,
+ wb_int_o => wb_int_o,
+ irq_port0_i => port_irq_reg(0),
+ irq_port0_ack_o => port_irq_ack(0),
+ irq_port1_i => port_irq_reg(1),
+ irq_port1_ack_o => port_irq_ack(1),
+ irq_port2_i => port_irq_reg(2),
+ irq_port2_ack_o => port_irq_ack(2),
+ irq_port3_i => port_irq_reg(3),
+ irq_port3_ack_o => port_irq_ack(3),
+ irq_port4_i => port_irq_reg(4),
+ irq_port4_ack_o => port_irq_ack(4),
+ irq_port5_i => port_irq_reg(5),
+ irq_port5_ack_o => port_irq_ack(5),
+ irq_port6_i => port_irq_reg(6),
+ irq_port6_ack_o => port_irq_ack(6),
+ irq_port7_i => port_irq_reg(7),
+ irq_port7_ack_o => port_irq_ack(7),
+ irq_port8_i => port_irq_reg(8),
+ irq_port8_ack_o => port_irq_ack(8),
+ irq_port9_i => port_irq_reg(9),
+ irq_port9_ack_o => port_irq_ack(9),
+ irq_port10_i => port_irq_reg(10),
+ irq_port10_ack_o => port_irq_ack(10),
+ irq_port11_i => port_irq_reg(11),
+ irq_port11_ack_o => port_irq_ack(11),
+ irq_port12_i => port_irq_reg(12),
+ irq_port12_ack_o => port_irq_ack(12),
+ irq_port13_i => port_irq_reg(13),
+ irq_port13_ack_o => port_irq_ack(13),
+ irq_port14_i => port_irq_reg(14),
+ irq_port14_ack_o => port_irq_ack(14),
+ irq_port15_i => port_irq_reg(15),
+ irq_port15_ack_o => port_irq_ack(15),
+ irq_port16_i => port_irq_reg(16),
+ irq_port16_ack_o => port_irq_ack(16),
+ irq_port17_i => port_irq_reg(17),
+ irq_port17_ack_o => port_irq_ack(17),
+ regs_i => wb_regs_in,
+ regs_o => wb_regs_out
+ );
+
+ wb_regs_in.cr_rd_en_i <= rd_en;
+ wb_regs_in.l1_cnt_val_i <= rd_val;
+ wb_regs_in.l2_cnt_val_i <= L2_rd_val;
+ rd_port <= wb_regs_out.cr_port_o(c_adr_psel_sz-1 downto 0);
+
+
+ -------------------------------------------------------------
+ -------------------------------------------------------------
+ -- LAYER 1
+ -------------------------------------------------------------
+
+ --wb_regs_in.dbg_evt_ov_i(g_nports-1 downto 0) <= evt_ov(g_nports-1 downto 0);
+ --connect rest of the evt_ov_i to '0' if synthesized for less than 18 ports
+ --GEN_NUSED_EVTOV: if g_nports < 18 generate
+ -- wb_regs_in.dbg_evt_ov_i(17 downto g_nports) <= (others=>'0');
+ --end generate;
+
+ GEN_PCNT : for i in 0 to g_nports-1 generate
+
+ PER_PORT_CNT : port_cntr
+ generic map(
+ g_cnt_pp => g_cnt_pp,
+ g_cnt_pw => g_cnt_pw,
+ g_keep_ov => 0)
+ port map(
+ rst_n_i => rst_n_i,
+ clk_i => clk_i,
+
+ events_i => events_i((i+1)*g_cnt_pp-1 downto i*g_cnt_pp),
+
+ ext_adr_i => wb_regs_out.cr_addr_o(c_adr_mem_sz-1 downto 0),
+ ext_dat_o => p_dat_out(i),
+
+ ov_cnt_o => L2_events((i+1)*c_L2_event_sz-1 downto i*c_L2_event_sz));
+ --dbg_evt_ov_o => evt_ov(i),
+ --clr_flags_i => wb_regs_out.dbg_clr_o);
+
+ end generate;
+
+ -------------------------------------------------------------
+ -------------------------------------------------------------
+ -- LAYER 2
+ -------------------------------------------------------------
+
+ L2_CNT : port_cntr
+ generic map(
+ g_cnt_pp => g_nports*c_L2_event_sz,
+ g_cnt_pw => g_L2_cnt_pw,
+ g_keep_ov => 0)
+ port map(
+ rst_n_i => rst_n_i,
+ clk_i => clk_i,
+
+ events_i => L2_events,
+
+ ext_adr_i => L2_adr,
+ ext_dat_o => L2_dat_out,
+
+ ov_cnt_o => L3_events);
+ --dbg_evt_ov_o => wb_regs_in.dbg_l2_evt_ov_i,
+ --clr_flags_i => wb_regs_out.dbg_l2_clr_o);
+
+ L2_adr <= std_logic_vector(to_unsigned(to_integer(unsigned(rd_port))*c_portirq_sz +
+ to_integer(unsigned(wb_regs_out.cr_addr_o(c_adr_mem_sz-1 downto 0))),
+ c_L2_adr_mem_sz));
+
+ -------------------------------------------------------------
+ -------------------------------------------------------------
+ -- LAYER IRQ
+ -------------------------------------------------------------
+ --select only the events from active counters
+ GEN_IRQS : for i in 0 to g_nports-1 generate
+ irq((i+1)*g_cnt_pp-1 downto i*g_cnt_pp) <= L3_events(i*c_L2_event_sz+g_cnt_pp-1 downto i*c_L2_event_sz);
+ port_irq(i) <= or_reduce(L3_events(i*c_L2_event_sz+g_cnt_pp-1 downto i*c_L2_event_sz));
+ end generate;
+
+ GEN_NUSED_IRQS : if g_nports < 18 generate
+ port_irq(17 downto g_nports) <= (others => '0');
+ end generate;
+
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ port_irq_reg <= (others => '0');
+ else
+ port_irq_reg <= (port_irq_reg xor port_irq_ack) or port_irq;
+ end if;
+ end if;
+ end process;
+
+ CNTRS_IRQ : irq_ram
+ generic map(
+ g_nports => g_nports,
+ g_cnt_pp => g_cnt_pp,
+ g_cnt_pw => c_IRQ_pw)
+ port map(
+ rst_n_i => rst_n_i,
+ clk_i => clk_i,
+ irq_i => irq,
+
+ ext_cyc_i => IRQ_cyc,
+ ext_adr_i => IRQ_adr,
+ ext_we_i => IRQ_we,
+ ext_dat_i => (others => '0'),
+ ext_dat_o => IRQ_dat_out);
+
+ -------------------------------------------------------------
+ -------------------------------------------------------------
+ --rd_port translated into the address in IRQ mem, based on g_cnt_pp
+ IRQ_port_adr <= to_unsigned(to_integer(unsigned(rd_port))*((g_cnt_pp+c_IRQ_pw-1)/c_IRQ_pw), c_IRQ_adr_mem_sz);
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ rd_state <= IDLE;
+ rd_val <= (others => '0');
+ L2_rd_val <= (others => '0');
+ IRQ_cyc <= '0';
+ IRQ_we <= '0';
+ IRQ_adr <= std_logic_vector(IRQ_port_adr);
+ rd_irq <= '0';
+ rd_en <= '0';
+ else
+ case(rd_state) is
+ when IDLE =>
+ IRQ_cyc <= '0';
+ IRQ_we <= '0';
+ rd_irq <= '0';
+ IRQ_adr <= std_logic_vector(IRQ_port_adr);
+ if(wb_regs_out.cr_rd_en_load_o = '1' and wb_regs_out.cr_rd_en_o = '1') then
+ rd_en <= '1';
+ rd_state <= READ_LS;
+ elsif(wb_regs_out.cr_rd_irq_load_o = '1' and wb_regs_out.cr_rd_irq_o = '1') then
+ rd_irq <= '1';
+ rd_en <= '1';
+ rd_state <= READ_LS;
+ end if;
+
+ when READ_LS =>
+ rd_en <= '1';
+ IRQ_we <= '0';
+ IRQ_adr <= std_logic_vector(IRQ_port_adr);
+ if(rd_irq = '0') then
+ IRQ_cyc <= '0';
+ rd_state <= WRITE_LS;
+ elsif(rd_irq = '1' and g_cnt_pp > c_IRQ_pw) then
+ --for irq read second word or clear the one already read
+ IRQ_cyc <= '1';
+ rd_STATE <= READ_MS;
+ else
+ IRQ_cyc <= '1';
+ rd_state <= WRITE_LS;
+ end if;
+
+ when READ_MS =>
+ rd_en <= '1';
+ IRQ_we <= '0';
+ IRQ_cyc <= '1';
+ IRQ_adr <= std_logic_vector(IRQ_port_adr+1);
+ rd_val <= IRQ_dat_out;
+ rd_state <= WRITE_LS;
+
+ when WRITE_LS =>
+ rd_en <= '0';
+ IRQ_adr <= std_logic_vector(IRQ_port_adr);
+ if(rd_irq = '0') then
+ rd_val <= p_dat_out(to_integer(unsigned(rd_port)));
+ L2_rd_val <= L2_dat_out;
+ rd_state <= IDLE;
+ elsif(rd_irq = '1' and g_cnt_pp > c_IRQ_pw) then
+ L2_rd_val <= IRQ_dat_out;
+ IRQ_we <= '1';
+ rd_state <= WRITE_MS;
+ else
+ rd_val <= IRQ_dat_out;
+ L2_rd_val <= (others => '0');
+ IRQ_we <= '1';
+ rd_state <= IDLE;
+ end if;
+
+ when WRITE_MS =>
+ rd_en <= '0';
+ IRQ_adr <= std_logic_vector(IRQ_port_adr+1);
+ IRQ_we <= '1';
+ rd_state <= IDLE;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end behav;
diff --git a/modules/wrsw_pstats/wrsw_pstats.wb b/modules/wrsw_pstats/wrsw_pstats.wb
new file mode 100644
index 0000000000000000000000000000000000000000..6c892693ec381f8fac8498e7843beac5f76dbf99
--- /dev/null
+++ b/modules/wrsw_pstats/wrsw_pstats.wb
@@ -0,0 +1,306 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+-- White-Rabbit Per-Port Statistic Couters
+-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+--
+-- Use wbgen2 to generate code, documentation and more.
+-- wbgen2 is available at:
+-- http://www.ohwr.org/projects/wishbone-gen
+--
+
+peripheral {
+
+ name = "WR Switch Per-Port Statistic Counters";
+ description = "The set of counters for counting traffic statistics on each Ethernet port of WR Switch";
+ hdl_entity = "pstats_wishbone_slave";
+ prefix = "pstats";
+
+
+ reg {
+ name = "Control Register";
+ prefix = "CR";
+
+ field {
+ name = "Enable transfer of counter content";
+ description = "write 1: start reading content \
+ write 0: no effect \
+ read 1: reading in progress \
+ read 0: reading done, counter value available";
+ prefix = "RD_EN";
+
+ type = BIT;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+ field {
+ name = "Enable transfer of per-counter IRQ state";
+ description = "write 1: start reading content \
+ write 0: no effect \
+ read 1: reading in progress \
+ read 0: reading done, counter value available";
+ prefix = "RD_IRQ";
+
+ type = BIT;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+ field {
+ name = "Port number";
+ description = "Number of port (0-17) from which couter's value is read";
+ prefix = "PORT";
+ size = 5;
+ align = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Memory address";
+ description = "Address of the 32-bit word in selected port's memory that contains the counter to be read";
+ prefix = "ADDR";
+ size = 5;
+ align = 16;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+ reg {
+ name = "L1 Counter Value/First word of per-counter IRQ state";
+ description = "32-bit word read from given memory address of selected Ethernet port containing the value of 4 counters \
+ or lower half of per-counter IRQ state for port given in CR register";
+ prefix = "L1_CNT_VAL";
+
+ field {
+ name = "4 counters' values";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "L2 Counter Value";
+ description = "32-bit word read from given memory address of selected Ethernet port containing the value of 4 counters \
+ or higher half of per-counter IRQ state for port given in CR register";
+ prefix = "L2_CNT_VAL";
+
+ field {
+ name = "4 counters' values";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+
+ irq {
+ name = "Port0 IRQ";
+ prefix = "port0";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port1 IRQ";
+ prefix = "port1";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port2 IRQ";
+ prefix = "port2";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port3 IRQ";
+ prefix = "port3";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port4 IRQ";
+ prefix = "port4";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port5 IRQ";
+ prefix = "port5";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port6 IRQ";
+ prefix = "port6";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port7 IRQ";
+ prefix = "port7";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port8 IRQ";
+ prefix = "port8";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port9 IRQ";
+ prefix = "port9";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port10 IRQ";
+ prefix = "port10";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port11 IRQ";
+ prefix = "port11";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port12 IRQ";
+ prefix = "port12";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port13 IRQ";
+ prefix = "port13";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port14 IRQ";
+ prefix = "port14";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port15 IRQ";
+ prefix = "port15";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port16 IRQ";
+ prefix = "port16";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+ irq {
+ name = "Port17 IRQ";
+ prefix = "port17";
+ ack_line = true;
+ mask_line = false;
+ description = "At least one of the counters on Port0 has overflown";
+ trigger = LEVEL_1;
+ };
+
+-- reg {
+-- name = "Debug register";
+-- prefix = "DBG";
+--
+-- field{
+-- name = "Events overflow";
+-- prefix = "EVT_OV";
+-- size = 18;
+-- type = SLV;
+-- access_bus = READ_ONLY;
+-- access_dev = WRITE_ONLY;
+-- };
+--
+-- field{
+-- name = "L2 Events overflow";
+-- prefix = "L2_EVT_OV";
+-- size = 1;
+-- type = SLV;
+-- access_bus = READ_ONLY;
+-- access_dev = WRITE_ONLY;
+-- };
+--
+-- field{
+-- name = "L2 Clear flags";
+-- prefix = "L2_CLR";
+-- size = 1;
+-- align = 30;
+-- type = MONOSTABLE;
+-- };
+--
+-- field{
+-- name = "Clear flags";
+-- prefix = "CLR";
+-- size = 1;
+-- align = 31;
+-- type = MONOSTABLE;
+-- };
+--
+-- };
+
+};
diff --git a/modules/wrsw_pstats/xwrsw_pstats.vhd b/modules/wrsw_pstats/xwrsw_pstats.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5af8d980906619213d3405d1842aa9ae0ef34004
--- /dev/null
+++ b/modules/wrsw_pstats/xwrsw_pstats.vhd
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+-- Title : Per-port statistics counters wrapper
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : xwrsw_pstats.vhd
+-- Author : Grzegorz Daniluk
+-- Company : CERN BE-CO-HT
+-- Created : 2013-01-11
+-- Last update: 2013-03-04
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Record-based wrapper for wrsw_pstats module.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2013-01-11 0.1 greg.d Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity xwrsw_pstats is
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nports : integer := 2;
+ g_cnt_pp : integer := 16;
+ g_cnt_pw : integer := 4);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+end xwrsw_pstats;
+
+architecture wrapper of xwrsw_pstats is
+
+ component wrsw_pstats
+ generic(
+ g_nports : integer := 2;
+ g_cnt_pp : integer := 16;
+ g_cnt_pw : integer := 4);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic);
+ end component;
+
+
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+
+begin
+
+ U_Adapter : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => true,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_i,
+ rst_n_i => rst_n_i,
+ slave_i => wb_i,
+ slave_o => wb_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ wb_out.err <= '0';
+ wb_out.rty <= '0';
+
+ U_Wrapped_PSTATS : wrsw_pstats
+ generic map(
+ g_nports => g_nports,
+ g_cnt_pp => g_cnt_pp,
+ g_cnt_pw => g_cnt_pw)
+ port map(
+ rst_n_i => rst_n_i,
+ clk_i => clk_i,
+
+ events_i => events_i,
+
+ wb_adr_i => wb_in.adr(3 downto 0),
+ wb_dat_i => wb_in.dat,
+ wb_dat_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
+ wb_stall_o => wb_out.stall,
+ wb_int_o => wb_out.int);
+
+end wrapper;
diff --git a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
index 9c656979b2047e87442ff3f6598fd3cb273b204b..97ebcb52a59086f1ec2b7096e2b7633c9c2951df 100644
--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -61,6 +61,11 @@ entity wrsw_rt_subsystem is
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
+ -- WR timebase
+ tm_utc_o : out std_logic_vector(39 downto 0);
+ tm_cycles_o : out std_logic_vector(27 downto 0);
+ tm_time_valid_o : out std_logic;
+
-- AD9516 signals
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
@@ -79,15 +84,10 @@ architecture rtl of wrsw_rt_subsystem is
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
- g_with_period_detector : boolean;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
- g_with_undersampling : boolean;
- g_divide_input_by_2 : boolean;
+ g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean;
- g_bb_ref_divider : integer;
- g_bb_feedback_divider : integer;
- g_bb_log2_gating : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
@@ -144,7 +144,7 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
- constant c_NUM_GPIO_PINS : integer := 32;
+ constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 7;
constant c_SLAVE_DPRAM : integer := 0;
@@ -283,12 +283,7 @@ begin -- rtl
g_reverse_dmtds => true,
g_with_ext_clock_input => true,
g_divide_input_by_2 => false,
- g_with_period_detector => false,
- g_with_undersampling => false,
- g_with_debug_fifo => true,
- g_bb_ref_divider => 8,
- g_bb_feedback_divider => 25,
- g_bb_log2_gating => 13)
+ g_with_debug_fifo => true)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
@@ -327,10 +322,9 @@ begin -- rtl
pps_csync_o => pps_csync_o,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid_o,
- tm_utc_o => open,
- tm_cycles_o => open,
- tm_time_valid_o => open);
-
+ tm_utc_o => tm_utc_o,
+ tm_cycles_o => tm_cycles_o,
+ tm_time_valid_o => tm_time_valid_o);
cpu_irq_vec(0) <= cnx_master_in(2).int;
cpu_irq_vec(31 downto 1) <= (others => '0');
@@ -338,7 +332,10 @@ begin -- rtl
U_SPI_Master : xwb_spi
generic map (
g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
+ g_address_granularity => BYTE,
+ g_divider_len => 8,
+ g_max_char_len => 24,
+ g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
@@ -346,7 +343,6 @@ begin -- rtl
slave_o => cnx_master_in(c_SLAVE_SPI),
desc_o => open,
pad_cs_o(0) => pll_cs_n_o,
- pad_cs_o(7 downto 1) => dummy(7 downto 1),
pad_sclk_o => pll_sck_o,
pad_mosi_o => pll_mosi_o,
pad_miso_i => pll_miso_i);
@@ -355,7 +351,7 @@ begin -- rtl
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
- g_num_pins => 32,
+ g_num_pins => c_NUM_GPIO_PINS,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_i,
diff --git a/modules/wrsw_rtu/Manifest.py b/modules/wrsw_rtu/Manifest.py
index a53e35c66f0f051161453c518b087c5e8a0af730..b1479df86f0061f6585791c5c98f0738ca9e72eb 100644
--- a/modules/wrsw_rtu/Manifest.py
+++ b/modules/wrsw_rtu/Manifest.py
@@ -5,13 +5,18 @@ files = [
"rtu_rr_arbiter.vhd",
"rtu_crc_pkg.vhd",
"rtu_match.vhd",
+"rtu_fast_match.vhd",
"rtu_private_pkg.vhd",
"rtu_components_pkg.vhd",
"rtu_crc.vhd",
-"rtu_port.vhd",
-"wrsw_rtu.vhd",
-"xwrsw_rtu.vhd",
+#"rtu_port.vhd",
+"rtu_port_new.vhd",
+#"wrsw_rtu.vhd",
+#"xwrsw_rtu.vhd",
+"xwrsw_rtu_new.vhd",
"rtu_wishbone_slave.vhd",
"rtu_wbgen2_pkg.vhd",
+#"rtu_wishbone_slave_old.vhd",
+#"rtu_wbgen2_pkg_old.vhd",
"pack_unpack_pkg.vhd"
]
\ No newline at end of file
diff --git a/modules/wrsw_rtu/rtu_components_pkg.vhd b/modules/wrsw_rtu/rtu_components_pkg.vhd
index 46194c97763ff58acfd6ca40de6f85f496ae89cb..d4239740c7f9fe357cd8b2edf9c886add95df94c 100644
--- a/modules/wrsw_rtu/rtu_components_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_components_pkg.vhd
@@ -112,6 +112,25 @@ package wrsw_rtu_components_pkg is
rsp_ack_i : in std_logic_vector(c_rtu_num_ports -1 downto 0);
port_almost_full_o : out std_logic_vector(c_rtu_num_ports -1 downto 0);
port_full_o : out std_logic_vector(c_rtu_num_ports -1 downto 0);
+-------------------------------------------------------------------------------
+-- TRU stuff
+-------------------------------------------------------------------------------
+ tru_req_valid_o : out std_logic;
+ tru_req_smac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_fid_o : out std_logic_vector(c_wrsw_fid_width -1 downto 0);
+ tru_req_isHP_o : out std_logic; -- high priority packet flag
+ tru_req_isBR_o : out std_logic; -- broadcast packet flag
+ tru_req_reqMask_o : out std_logic_vector(c_rtu_num_ports-1 downto 0); -- mask indicating requesting port
+ tru_resp_valid_i : in std_logic;
+ tru_resp_port_mask_i : in std_logic_vector(c_rtu_num_ports-1 downto 0); -- mask with 1's at forward ports
+ tru_resp_drop_i : in std_logic;
+ tru_resp_respMask_i : in std_logic_vector(c_rtu_num_ports-1 downto 0); -- mask with 1 at requesting port
+ tru_if_pass_all_o : out std_logic_vector(c_rtu_num_ports-1 downto 0);
+ tru_if_forward_bpdu_only_o: out std_logic_vector(c_rtu_num_ports-1 downto 0);
+ tru_if_request_valid_o : out std_logic_vector(c_rtu_num_ports-1 downto 0);
+ tru_if_priorities_o : out std_logic_vector(c_rtu_num_ports*c_wrsw_prio_width-1 downto 0);
+----------------------------------------------------------------------------------
wb_addr_i : in std_logic_vector(13 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
diff --git a/modules/wrsw_rtu/rtu_fast_match.vhd b/modules/wrsw_rtu/rtu_fast_match.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2e421c67feb8aa3fdacae9814ae2be45ba50d44d
--- /dev/null
+++ b/modules/wrsw_rtu/rtu_fast_match.vhd
@@ -0,0 +1,492 @@
+-------------------------------------------------------------------------------
+-- Title : Routing Table Unit's Fast Matching Component (RTU_FAST_MATCH)
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : rtu_fast_match.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2012-10-30
+-- Last update: 2012-11-06
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- This module implements deterministic matching of requests from ports.
+-- It provides forwarding decision based on:
+-- * VLAN table (for broadcast and multicast)
+-- * TRU decision (topology resolution unit for RSTP/MSTP/LACP)
+-- * link-limited (non-forward) traffic (e.g. BPUD)
+-- * some predefined addresses
+--
+-- it is generally meant for traffic which is broadcasted (within VLAN and TRU
+-- restrictions) and has few purposes:
+-- * to recognize and forward fast "special traffic" which is expected to be broadcast/multicast
+-- * to provide TRU mask for the full match
+-- * to provide fast forwarding decision if full_match takes too match time
+--
+-- The rising edge of response VALID signal is expected max after N+5 cycles after
+-- the rising edge of request, where N is -- the number of ports (23 cycles for 18 ports)
+--
+-- It is expected that the input data (rtu_req) is valid throughout the request (except first
+-- cycle).
+--
+-- The request (valid up of the input rtu_req) shall be a strobe
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-10-30 1.0 lipinskimm Created
+-- 2012-08-20 1.1 lipinskimm added chipscope (commented)
+-------------------------------------------------------------------------------
+-- Stuff debugged / that seems to be working:
+-- * HP, FF detection
+-- * Priorities
+-- * broadcast detection
+-- * single/range MAC
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.genram_pkg.all;
+use work.gencores_pkg.all;
+use work.pack_unpack_pkg.all;
+use work.wrsw_shared_types_pkg.all;
+use work.rtu_private_pkg.all;
+
+entity rtu_fast_match is
+ generic (
+ g_num_ports : integer;
+ g_port_mask_bits : integer);
+ port(
+
+ -----------------------------------------------------------------
+ --| General IOs
+ -----------------------------------------------------------------
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ match_req_i : in std_logic_vector(g_num_ports-1 downto 0);
+ match_req_data_i : in t_rtu_request_array(g_num_ports-1 downto 0);
+
+ -- fast forward response
+ match_rsp_data_o : out t_match_response;
+ match_rsp_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
+
+ vtab_rd_addr_o : out std_logic_vector(c_wrsw_vid_width-1 downto 0);
+ vtab_rd_entry_i : in t_rtu_vlan_tab_entry;
+
+ tru_req_o : out t_tru_request;
+ tru_rsp_i : in t_tru_response;
+ tru_enabled_i : in std_logic;
+
+ rtu_str_config_i : in t_rtu_special_traffic_config;
+ rtu_pcr_pass_all_i : in std_logic_vector(c_rtu_max_ports -1 downto 0)
+ );
+
+end rtu_fast_match;
+
+architecture behavioral of rtu_fast_match is
+
+ constant pipeline_depth : integer := 4;
+ type t_std_vector_array is array(0 to pipeline_depth-1) of std_logic_vector(g_num_ports-1 downto 0);
+ type t_match_rsp_array is array(0 to 1) of t_match_response;
+ signal req_strobe : std_logic_vector(g_num_ports-1 downto 0);
+ signal req_masked, req, grant : std_logic_vector(g_num_ports-1 downto 0);
+ signal pipeline_grant : t_std_vector_array;
+ signal pipeline_valid : std_logic_vector(pipeline_depth-1 downto 0);
+ signal zeros : std_logic_vector(47 downto 0);
+ signal ones : std_logic_vector(47 downto 0);
+ signal pipeline_match_rsp : t_match_rsp_array;
+ signal rsp_fast_match : t_match_response;
+ signal rtu_req_stage_g : t_rtu_request;
+ signal rtu_req_stage_0 : t_rtu_request;
+ signal rtu_req_stage_1 : t_rtu_request;
+ signal rq_prio_mask : std_logic_vector(7 downto 0);
+ signal traffic_ptp : std_logic; -- ptp traffic
+ signal traffic_nf : std_logic; -- non-forward (link-limited) traffic
+ signal traffic_br : std_logic; -- broadcast traffic
+ signal traffic_ff : std_logic; -- fast forward (special) traffic
+ signal traffic_hp : std_logic; -- high priority
+ -- registered signals
+ signal traffic_nf_d : std_logic;
+ signal traffic_ff_d : std_logic;
+ signal traffic_br_d : std_logic;
+ signal traffic_hp_d : std_logic;
+
+ signal rtu_pcr_nonvlan_drop_at_ingress : std_logic_vector(c_rtu_max_ports -1 downto 0);
+
+ signal vtab_rd_addr : std_logic_vector(c_wrsw_vid_width-1 downto 0);
+
+ signal CONTROL0 : std_logic_vector(35 downto 0);
+ signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
+
+ constant match_rsp_zero : t_match_response := (
+ valid => '0',
+ port_mask => (others => '0'),
+ prio => (others => '0'),
+ drop => '0',
+ nf => '0',
+ ff => '0',
+ hp => '0');
+
+ component chipscope_icon
+ port (
+ CONTROL0 : inout std_logic_vector(35 downto 0));
+ end component;
+
+ component chipscope_ila
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(31 downto 0);
+ TRIG1 : in std_logic_vector(31 downto 0);
+ TRIG2 : in std_logic_vector(31 downto 0);
+ TRIG3 : in std_logic_vector(31 downto 0));
+ end component;
+
+begin
+
+ zeros <= (others => '0');
+ ones <= (others => '1');
+ rtu_pcr_nonvlan_drop_at_ingress <= (others =>'0'); -- make it configurable from WB
+
+ -- round robin arbitration stuff (stolen from Toms module)
+ gen_inputs : for i in 0 to g_num_ports-1 generate
+ req_strobe(i) <= match_req_i(i) and not req(i);
+ p_input_reg : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ req(i) <= '0';
+ else
+ if(grant(i) = '1') then
+ req(i) <= '0';
+ elsif(req_strobe(i) = '1') then
+ req(i) <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate gen_inputs;
+
+ req_masked <= req and not grant;
+
+ -- using the ipnut data from (rtu_req) in different stages
+ rtu_req_stage_g <= match_req_data_i(f_onehot_decode(grant));
+ rtu_req_stage_0 <= match_req_data_i(f_onehot_decode(pipeline_grant(0)));
+ rtu_req_stage_1 <= match_req_data_i(f_onehot_decode(pipeline_grant(1)));
+
+ ----------------------------- stage: 0 -------------------------------------------------
+ -- in this stage we have the following data registered:
+ -- * VTAB address to read
+ -- We decide many things and register it for next stage
+ -- * traffic kind, can we recognize the address ?
+ --------------------------------------------------------------------------------------------
+ rq_prio_mask <= f_set_bit(zeros(7 downto 0),'1',to_integer(unsigned(rtu_req_stage_0.prio)));
+ traffic_ptp <= '0' when (rtu_str_config_i.ff_mac_ptp_ena = '0') else -- stuff disabled
+ '1' when (rtu_req_stage_0.dmac = x"011b19000000") else -- the other is no-forward (link-limted)
+ '0';
+ traffic_nf <= '0' when (rtu_str_config_i.ff_mac_ll_ena = '0' and
+ rtu_str_config_i.ff_mac_ptp_ena = '0') else -- stuff disabled
+ traffic_ptp when (rtu_str_config_i.ff_mac_ll_ena = '0' and
+ rtu_str_config_i.ff_mac_ptp_ena = '1') else -- stuff disabled
+ f_mac_in_range(rtu_req_stage_0.dmac,c_bpd_range_lower,c_bpd_range_upper) or traffic_ptp;
+
+ traffic_br <= '0' when (rtu_str_config_i.ff_mac_br_ena ='0') else -- stuff disabled
+ '1' when (rtu_req_stage_0.dmac = x"FFFFFFFFFFFF") else
+ '0';
+
+ -- the fast_match_mac_lookup function includes disabled/enabled future check
+ traffic_ff <= traffic_br or f_fast_match_mac_lookup(rtu_str_config_i, rtu_req_stage_0.dmac);
+
+ traffic_hp <= '1' when (traffic_ff='1' and rtu_req_stage_0.has_prio = '1' and
+ (rtu_str_config_i.hp_prio and rq_prio_mask) /= zeros(7 downto 0) ) else
+ '1' when traffic_ff='1' and rtu_req_stage_0.has_prio = '0' and
+ (rtu_str_config_i.hp_prio = ones(7 downto 0)) else
+ '0';
+ -- something is wrong here... HP works only for un-taggged traffic and if we set hp_prio to =0x1...
+ -- for any other value does not work... shit
+ ----------------------------- stage: 1 -------------------------------------------------
+ -- reading VLAN, we have FID
+ -- * we request TRU decision if necessary (forward traffic)
+ -- * we use the VLAN tab data to prepare fast match decision
+ --------------------------------------------------------------------------------------------
+
+ rsp_fast_match <= f_fast_match_response(vtab_rd_entry_i,
+ rtu_req_stage_1.prio,
+ rtu_req_stage_1.has_prio,
+ pipeline_grant(1),
+ traffic_br_d,
+ rtu_pcr_pass_all_i,
+ rtu_pcr_nonvlan_drop_at_ingress,
+ g_num_ports);
+
+ --------------------------------------------------------------------------------------------
+ -- process controlling fast match:
+ -- * arbitration
+ -- * registering proper stuff in proper stage
+ -- *
+ --------------------------------------------------------------------------------------------
+ p_fast_match_ctr : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ grant <= (others => '0');
+ RES_LOOP: for i in pipeline_depth-1 downto 0 loop
+ pipeline_grant(i) <= (others => '0');
+ pipeline_valid(i) <= '0';
+ end loop RES_LOOP;
+ pipeline_match_rsp(0) <= match_rsp_zero;
+ pipeline_match_rsp(1) <= match_rsp_zero;
+ traffic_nf_d <= '0';
+ traffic_ff_d <= '0';
+ traffic_hp_d <= '0';
+ traffic_br_d <= '0';
+ vtab_rd_addr <= (others => '0');
+ else
+
+ -- round robin arbiter
+ f_rr_arbitrate(req_masked , grant, grant);
+
+ --------------------------------------------------------------------------------------
+ -- register for stage 0: VLAN table address out
+ --------------------------------------------------------------------------------------
+ if(unsigned(grant) /= 0) then
+ -- VLAN access
+ vtab_rd_addr <= rtu_req_stage_g.vid;
+ pipeline_grant(0) <= grant;
+ pipeline_valid(0) <= '1';
+ else
+ vtab_rd_addr <= (others => '0');
+ pipeline_grant(0) <= (others => '0');
+ pipeline_valid(0) <= '0';
+ end if;
+
+ --------------------------------------------------------------------------------------
+ -- register for stage 1: VLAN entry in
+ --------------------------------------------------------------------------------------
+ if(unsigned(pipeline_grant(0)) /= 0) then
+ traffic_nf_d <= traffic_nf;
+ traffic_ff_d <= traffic_ff ;
+ traffic_hp_d <= traffic_hp;
+ traffic_br_d <= traffic_br;
+ else
+ traffic_nf_d <= '0';
+ traffic_ff_d <= '0';
+ traffic_hp_d <= '0';
+ traffic_br_d <= '0';
+ end if;
+
+ --------------------------------------------------------------------------------------
+ -- register for stage 2: register fast forward decision
+ --------------------------------------------------------------------------------------
+ if(unsigned(pipeline_grant(1)) /= 0) then
+ --================== FAST MATCH =================================
+ pipeline_match_rsp(0).valid <= '1';
+ if(traffic_nf_d = '1' and traffic_ff_d = '1') then -- special markers
+ pipeline_match_rsp(0).port_mask<= rtu_str_config_i.cpu_forward_mask or
+ rsp_fast_match.port_mask; -- for sure zeros when drop
+ pipeline_match_rsp(0).drop <= '0';
+ elsif(traffic_nf_d = '1') then -- only non-forward traffic
+ pipeline_match_rsp(0).port_mask<= rtu_str_config_i.cpu_forward_mask;
+ pipeline_match_rsp(0).drop <= '0';
+ else
+ pipeline_match_rsp(0).port_mask<= rsp_fast_match.port_mask;
+ pipeline_match_rsp(0).drop <= rsp_fast_match.drop;
+ end if;
+ pipeline_match_rsp(0).prio <= rsp_fast_match.prio;
+
+ pipeline_match_rsp(0).nf <= traffic_nf_d;
+ pipeline_match_rsp(0).ff <= traffic_ff_d;
+ pipeline_match_rsp(0).hp <= traffic_hp_d;
+ ---================================================================
+ else
+ pipeline_match_rsp(0) <= match_rsp_zero;
+ end if;
+
+ -- shifting
+ PIPELINE_SHIFT: for i in pipeline_depth-1 downto 1 loop
+ pipeline_valid(i) <= pipeline_valid(i-1);
+ pipeline_grant(i) <= pipeline_grant(i-1);
+ end loop PIPELINE_SHIFT;
+ pipeline_match_rsp(1) <= pipeline_match_rsp(0);
+ end if;
+ end if;
+ end process;
+
+ -- TRU request
+-- tru_req_o.valid <= pipeline_valid(1) and (not traffic_nf_d) and tru_enabled_i;
+ tru_req_o.valid <= pipeline_valid(1) and tru_enabled_i;
+ tru_req_o.smac <= rtu_req_stage_1.smac;
+ tru_req_o.dmac <= rtu_req_stage_1.dmac;
+ tru_req_o.fid <= vtab_rd_entry_i.fid; -- directly from VLAN TABLE
+ tru_req_o.isHP <= traffic_hp_d;
+ tru_req_o.isBR <= traffic_br_d;
+ tru_req_o.reqMask(g_num_ports-1 downto 0) <= pipeline_grant(1);
+ tru_req_o.reqMask(c_rtu_max_ports-1 downto g_num_ports) <= (others => '0');
+ -- this is more for testing then to be used
+ tru_req_o.prio <= rtu_req_stage_1.prio when(rtu_req_stage_1.has_prio = '1') else (others=>'0');
+
+ -- fast match response
+ -- 1) if TRU is disabled, we don't take TRU's decision in consideration and we can respond
+ -- faster
+ -- 2) if TRU is enabled, we responde on cycle later and we need to take TRU's decision in consideration
+ match_rsp_data_o.valid <= pipeline_match_rsp(0).valid when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).valid;
+ match_rsp_data_o.port_mask <= pipeline_match_rsp(0).port_mask when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).port_mask(c_rtu_max_ports -1 downto g_num_ports) &
+ (pipeline_match_rsp(1).port_mask(g_num_ports-1 downto 0) and -- in order not to affect CPU foreard (BPUD)
+ tru_rsp_i.port_mask(g_num_ports-1 downto 0)) ; -- we don't AND more ports then we have
+ match_rsp_data_o.prio <= pipeline_match_rsp(0).prio when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).prio ;
+ match_rsp_data_o.drop <= pipeline_match_rsp(0).drop when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).drop when (pipeline_match_rsp(1).nf = '1') else -- if non-forward, dont drop even if TRU says so
+ pipeline_match_rsp(1).drop or tru_rsp_i.drop;
+ match_rsp_data_o.nf <= pipeline_match_rsp(0).nf when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).nf;
+ match_rsp_data_o.ff <= pipeline_match_rsp(0).ff when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).ff;
+ match_rsp_data_o.hp <= pipeline_match_rsp(0).hp when (tru_enabled_i = '0') else
+ pipeline_match_rsp(1).hp;
+ match_rsp_valid_o <= pipeline_grant(2) when (tru_enabled_i = '0') else
+ pipeline_grant(3);
+
+ vtab_rd_addr_o <= vtab_rd_addr;
+
+-- CS_ICON : chipscope_icon
+-- port map (
+-- CONTROL0 => CONTROL0);
+-- CS_ILA : chipscope_ila
+-- port map (
+-- CONTROL => CONTROL0,
+-- CLK => clk_i,
+-- TRIG0 => TRIG0,
+-- TRIG1 => TRIG1,
+-- TRIG2 => TRIG2,
+-- TRIG3 => TRIG3);
+
+
+------------------debug_oldFFv4 ----------------------
+-- TRIG0(7 downto 0) <= match_req_i;
+-- TRIG0(19 downto 8) <= rtu_req_stage_g.vid;
+-- TRIG0(31 downto 20) <= vtab_rd_addr;
+--
+-- TRIG1(7 downto 0) <= vtab_rd_entry_i.port_mask(7 downto 0);
+-- TRIG1(15 downto 8) <= rsp_fast_match.port_mask(7 downto 0);
+-- TRIG1(18 downto 16) <= rtu_req_stage_g.prio; --vtab_rd_entry_d.port_mask(15 downto 0);
+-- TRIG1(21 downto 19) <= rtu_req_stage_0.prio;
+-- TRIG1(24 downto 22) <= rtu_req_stage_1.prio;
+-- TRIG1( 25) <= rtu_req_stage_g.has_prio;
+-- TRIG1( 26) <= rtu_req_stage_0.has_prio;
+-- TRIG1( 27) <= rtu_req_stage_1.has_prio;
+-- -- TRIG1( 28) <= traffic_ptp;
+-- -- TRIG1( 29) <= traffic_br;
+-- TRIG1( 28) <= rtu_req_stage_g.valid;
+-- TRIG1( 29) <= rtu_req_stage_g.has_vid;
+-- TRIG1( 30) <= traffic_ff;
+-- TRIG1( 31) <= traffic_hp;
+--
+-- TRIG2(1*8-1 downto 0*8) <= pipeline_grant(0);
+-- TRIG2(2*8-1 downto 1*8) <= pipeline_grant(1);
+-- TRIG2(3*8-1 downto 2*8) <= pipeline_grant(2);
+-- TRIG2(4*8-1 downto 3*8) <= pipeline_grant(3);
+--
+-- TRIG3(7 downto 0) <= grant;
+-- TRIG3(15 downto 8) <= rq_prio_mask;
+-- TRIG3(18 downto 16) <= vtab_rd_entry_i.prio;
+-- TRIG3(21 downto 19) <= rsp_fast_match.prio;
+-- TRIG3( 22) <= vtab_rd_entry_i.drop;
+-- TRIG3( 23) <= rsp_fast_match.drop;
+-- TRIG3(31 downto 24) <= vtab_rd_entry_i.fid;
+
+----------------- debug_oldFFv2 -------------------------
+-- TRIG0(11 downto 0) <= vtab_rd_addr;
+-- TRIG0(14 downto 12) <= vtab_rd_entry_i.prio;
+-- TRIG0(17 downto 15) <= rsp_fast_match.prio;
+-- TRIG0( 22) <= vtab_rd_entry_i.drop;
+-- TRIG0( 23) <= rsp_fast_match.drop;
+-- TRIG0(31 downto 24) <= vtab_rd_entry_i.fid;
+-- TRIG1(15 downto 0) <= vtab_rd_entry_i.port_mask(15 downto 0);
+-- TRIG1(31 downto 16) <= rsp_fast_match.port_mask(15 downto 0);
+-- TRIG2(1*8-1 downto 0*8) <= pipeline_grant(0);
+-- TRIG2(2*8-1 downto 1*8) <= pipeline_grant(1);
+-- TRIG2(3*8-1 downto 2*8) <= pipeline_grant(2);
+-- TRIG2(4*8-1 downto 3*8) <= pipeline_grant(3);
+-- TRIG3(1*8-1 downto 0*8) <= rq_prio_mask;
+-- TRIG3(10 downto 8) <= rtu_req_stage_g.prio; --vtab_rd_entry_d.port_mask(15 downto 0);
+-- TRIG3(13 downto 11) <= rtu_req_stage_0.prio;
+-- TRIG3(16 downto 14) <= rtu_req_stage_1.prio;
+-- TRIG3( 17) <= rtu_req_stage_g.has_prio;
+-- TRIG3( 18) <= rtu_req_stage_0.has_prio;
+-- TRIG3( 19) <= rtu_req_stage_1.has_prio;
+-- TRIG3( 20) <= traffic_ptp;
+-- -- TRIG3( 21) <= traffic_nf;
+-- TRIG3( 21) <= traffic_br;
+-- TRIG3( 22) <= traffic_ff;
+-- TRIG3( 23) <= traffic_hp;
+-- TRIG3(31 downto 24) <= match_req_i;
+
+------------------debug_oldFFv5 ----------------------
+-- TRIG0(7 downto 0) <= match_req_i;
+-- TRIG0(19 downto 8) <= rtu_req_stage_g.vid;
+-- TRIG0(31 downto 20) <= vtab_rd_addr;
+--
+-- TRIG1(7 downto 0) <= vtab_rd_entry_i.port_mask(7 downto 0);
+-- TRIG1(15 downto 8) <= rsp_fast_match.port_mask(7 downto 0);
+-- TRIG1(18 downto 16) <= rtu_req_stage_g.prio; --vtab_rd_entry_d.port_mask(15 downto 0);
+-- TRIG1(21 downto 19) <= rtu_req_stage_0.prio;
+-- TRIG1(24 downto 22) <= rtu_req_stage_1.prio;
+-- TRIG1( 25) <= rtu_req_stage_g.has_prio;
+-- TRIG1( 26) <= rtu_req_stage_0.has_prio;
+-- TRIG1( 27) <= rtu_req_stage_1.has_prio;
+-- TRIG1( 28) <= rtu_req_stage_g.valid;
+-- TRIG1( 29) <= rtu_req_stage_g.has_vid;
+-- TRIG1( 30) <= traffic_ff;
+-- TRIG1( 31) <= traffic_hp;
+--
+-- TRIG2(11 downto 0) <= match_req_data_i(0).vid;
+-- TRIG2(14 downto 12) <= match_req_data_i(0).prio;
+-- TRIG2( 15) <= match_req_data_i(0).valid;
+-- TRIG2( 16) <= match_req_data_i(0).has_vid;
+-- TRIG2( 17) <= match_req_data_i(0).has_prio;
+-- TRIG2( 18) <= match_req_i(0);
+-- TRIG2(27 downto 19) <= match_req_data_i(0).smac(8 downto 0);
+--
+-- TRIG2( 28) <= pipeline_grant(0)(0);
+-- TRIG2( 29) <= pipeline_grant(1)(0);
+-- TRIG2( 30) <= pipeline_grant(2)(0);
+-- TRIG2( 31) <= pipeline_grant(3)(0);
+--
+-- TRIG3(7 downto 0) <= grant;
+-- TRIG3(15 downto 8) <= rq_prio_mask;
+-- TRIG3(18 downto 16) <= vtab_rd_entry_i.prio;
+-- TRIG3(21 downto 19) <= rsp_fast_match.prio;
+-- TRIG3( 22) <= vtab_rd_entry_i.drop;
+-- TRIG3( 23) <= rsp_fast_match.drop;
+-- TRIG3(31 downto 24) <= vtab_rd_entry_i.fid;
+
+
+end architecture;
+
diff --git a/modules/wrsw_rtu/rtu_lookup_engine.vhd b/modules/wrsw_rtu/rtu_lookup_engine.vhd
index e4f5c3c59b74a26c91c8cb08ef9b56888315bd77..60a4dc0227adb94f60cc4e75291abd9008ce2317 100644
--- a/modules/wrsw_rtu/rtu_lookup_engine.vhd
+++ b/modules/wrsw_rtu/rtu_lookup_engine.vhd
@@ -190,7 +190,7 @@ begin
end process;
- p_gen_mem_addr : process(bucket_entry, hash_i, lookup_state, start_i)
+ p_gen_mem_addr : process(bucket_entry, hash_i, lookup_state, start_i, hash_reg)
begin
if(start_i = '1' and lookup_state = IDLE) then
mem_addr <= hash_i & "00";
diff --git a/modules/wrsw_rtu/rtu_match.vhd b/modules/wrsw_rtu/rtu_match.vhd
index 3e39d18d48f7aab4cdebd54305d29843072a216b..f9060b69a7b5394a9b5f43d598f570ce5e594682 100644
--- a/modules/wrsw_rtu/rtu_match.vhd
+++ b/modules/wrsw_rtu/rtu_match.vhd
@@ -17,7 +17,7 @@
--
-------------------------------------------------------------------------------
--
--- Copyright (c) 2010 Maciej Lipinski / CERN
+-- Copyright (c) 2010z Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
@@ -178,6 +178,9 @@ entity rtu_match is
-- 1: packet is broadcast
rtu_pcr_b_unrec_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ --
+ rtu_b_unrec_fw_cpu_i : in std_logic;
+ rtu_cpu_mask_i : in std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
-------------------------------------------------------------------------------
-- HASH based on CRC
-------------------------------------------------------------------------------
@@ -221,7 +224,7 @@ architecture behavioral of rtu_match is
signal s_rsp_dst_port_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
signal s_rsp_drop : std_logic;
signal s_rsp_prio : std_logic_vector (c_wrsw_prio_width-1 downto 0);
-
+ signal s_rsp_bpdu : std_logic; -- ML (oct 2012)
--|manage input fifo
--ML: signal s_rd_input_req_fifo : std_logic;
--ML: signal s_input_fifo_full : std_logic;
@@ -337,17 +340,35 @@ architecture behavioral of rtu_match is
return rv;
end f_onehot_encode;
-
-
- signal requesting_port : std_logic_vector(g_num_ports-1 downto 0);
+ signal requesting_port : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_urec_broadcast_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
signal zeros : std_logic_vector(g_num_ports-1 downto 0);
-
- signal s_urec_broadcast_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);-- ML (11/04/2013)
-------------------------------------------------------------------------------------------------------------------------
--| Address outs and flag generation and
-------------------------------------------------------------------------------------------------------------------------
begin
+
+ -- mask used for broadcasting unrecognizd traffic. such a broadcast should avoid
+ -- sending frames to NIC (CPU) which is port number g_num_ports - this coused switch's CPU
+ -- to get almost stuck. however, normal broadcast has to be forwarded to NIC so that
+ -- ARP and other protocols could work on it
+ --
+-- UREC_MASK: for i in 0 to c_RTU_MAX_PORTS-1 generate
+-- s_urec_broadcast_mask(i) <= '1' when (i < g_num_ports) else '0';
+-- end generate;
+
+ -- if forward of unrecognized frames to CPU is disabled (LOW), then we use
+ -- the cpu_mask to forward everywhere but to CPU, otherwise we do on all ports
+-- s_urec_broadcast_mask <= (not rtu_cpu_mask_i) when (rtu_b_unrec_fw_cpu_i = '0') else
+-- (others =>'1');
+
+ -- ML (11/04/2013) : to prevent broadcasting of unrecognized frames to CPU
+ s_urec_broadcast_mask(g_num_ports-1 downto 0) <= (others =>'1');
+ s_urec_broadcast_mask(c_RTU_MAX_PORTS-1 downto g_num_ports) <= (others =>'1') when (rtu_b_unrec_fw_cpu_i = '1') else
+ (others =>'0');
+
zeros <= (others =>'0');
+
-----------------------------------------------------------------------------------------------------------------------
--| Hash calculation
-----------------------------------------------------------------------------------------------------------------------
@@ -356,10 +377,6 @@ begin
-- will start calculating hash (which takes time)
s_hash_input_fid <= vlan_tab_entry_i.fid;
- -- ML (11/04/2013) : to prevent broadcasting of unrecognized frames to CPU
- s_urec_broadcast_mask(g_num_ports-1 downto 0) <= (others =>'1');
- s_urec_broadcast_mask(c_RTU_MAX_PORTS-1 downto g_num_ports) <= (others =>'0');
-
--source hash calculate
U_rtu_match_hash_src : rtu_crc
port map(
@@ -404,6 +421,7 @@ begin
--do reset
s_rsp_dst_port_mask <= (others => '0');
s_rsp_drop <= '0';
+ s_rsp_bpdu <= '0';
s_rsp_prio <= (others => '0');
s_htab_rd_data_ack <= '0';
@@ -448,6 +466,7 @@ begin
s_rsp_dst_port_mask <= (others => '0');
s_rsp_drop <= '0';
+ s_rsp_bpdu <= '0';
s_rsp_prio <= (others => '0');
s_htab_rd_data_ack <= '0';
@@ -561,6 +580,7 @@ begin
s_port_id <= requesting_port;
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
s_rsp_dst_port_mask <= (others => '0');
s_rsp_prio <= (others => '0');
mstate <= OUTPUT_RESPONSE;
@@ -609,6 +629,7 @@ begin
-- RETURN
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
mstate <= OUTPUT_RESPONSE;
s_vlan_tab_rd <= '0';
@@ -680,10 +701,6 @@ begin
-------------------------------------------
if(htab_found_i = '1') then
- -- ML (24/03/2013): aging bugfix : update aging only for source found
- -- s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(s_aram_bitsel_msb & htab_entry_i.bucket_entry)), 32);
- -- s_aram_main_wr <= '1';
-
----------------------------------------------------------------------------
-- SOURCE MAC ENTRY SEARCH
----------------------------------------------------------------------------
@@ -692,7 +709,7 @@ begin
-- ML (24/03/2013): aging bugfix : update aging only for source found
-- update aging aram (in any case that entry was found,
-- even if dropped later, we update aging aram
- s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(s_aram_bitsel_msb & htab_entry_i.bucket_entry)), 32);
+ s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(std_logic_vector'(s_aram_bitsel_msb & htab_entry_i.bucket_entry))), 32);
s_aram_main_wr <= '1';
-------------------------------------------
@@ -703,6 +720,7 @@ begin
-- RETURN
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
s_rsp_dst_port_mask <= (others => '0');
s_rsp_prio <= (others => '0');
mstate <= OUTPUT_RESPONSE;
@@ -744,6 +762,7 @@ begin
-- RETURN
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
s_rsp_dst_port_mask <= (others => '0');
s_rsp_prio <= (others => '0');
mstate <= OUTPUT_RESPONSE;
@@ -803,7 +822,8 @@ begin
if(s_src_dst_sel = '0') then
- s_src_entry_port_mask_src <= (others => '1'); -- changed
+ s_src_entry_port_mask_src <= s_urec_broadcast_mask; --ML changed (mar2013) again, to avoid broadast to NIC, old:
+ --(others => '1'); -- changed
s_src_entry_drop_unmatched_src_ports <= '0';
----------------------------------------------------------------------------
@@ -842,6 +862,7 @@ begin
-- so we drop
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
s_rsp_dst_port_mask <= (others => '0');
s_rsp_prio <= (others => '0');
mstate <= OUTPUT_RESPONSE;
@@ -888,7 +909,7 @@ begin
----------------------------------------------------------------------------
if(s_src_dst_sel = '0') then
- s_src_entry_port_mask_src <= (others => '1');
+ s_src_entry_port_mask_src <= s_urec_broadcast_mask; --ML changed (mar2013) to avoid broadcast to NIC, old: (others => '1');
s_src_entry_drop_unmatched_src_ports <= '0';
----------------------------------------------------------------------------
-- DESTINATION MAC ENTRY SEARCH
@@ -916,6 +937,7 @@ begin
-- so we drop
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
s_rsp_dst_port_mask <= (others => '0');
s_rsp_prio <= (others => '0');
mstate <= OUTPUT_RESPONSE;
@@ -958,6 +980,7 @@ begin
-- RETURN
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
mstate <= OUTPUT_RESPONSE;
-------------------------------------------
@@ -977,7 +1000,7 @@ begin
----------------------------------------------------------------------------
if(s_src_dst_sel = '0') then
- s_src_entry_port_mask_src <= (others => '1');
+ s_src_entry_port_mask_src <= s_urec_broadcast_mask; --ML changed (mar2013) to avoid broadcast to NIC, old:(others => '1');
s_src_entry_drop_unmatched_src_ports <= '0';
----------------------------------------------------------------------------
-- DESTINATION MAC ENTRY SEARCH
@@ -987,8 +1010,7 @@ begin
s_dst_entry_is_bpdu <= '0';
-- s_dst_entry_port_mask_dst <= (others => '1');
s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; -- ML(11/04/2013)
-
-
+
end if;
@@ -1067,6 +1089,7 @@ begin
-- RETURN
s_rsp_drop <= '1';
+ s_rsp_bpdu <= '0';
s_rsp_dst_port_mask <= (others => '0');
s_rsp_prio <= (others => '0');
@@ -1088,7 +1111,7 @@ begin
--evaluate the final priority of the packet
s_rsp_drop <= '0';
-
+ s_rsp_bpdu <= s_dst_entry_is_bpdu; --- ML (oct2012 - new, to be verified)
-------------------------------------------
-- set response PRIORITY
-------------------------------------------
@@ -1193,7 +1216,7 @@ begin
rsp_fifo_write_o <= '1' when mstate = OUTPUT_RESPONSE else '0';
-- response strobe
- rsp_fifo_output_o <= s_rsp_dst_port_mask & s_rsp_drop & s_rsp_prio & s_port_id;
+ rsp_fifo_output_o <= s_rsp_bpdu & s_rsp_dst_port_mask & s_rsp_drop & s_rsp_prio & s_port_id;
htab_src_dst_o <= s_src_dst_sel; -- ML (24/03/2013): aging bugfix
htab_port_o <= s_port_id; -- ML (24/03/2013): aging bugfix
diff --git a/modules/wrsw_rtu/rtu_port_new.vhd b/modules/wrsw_rtu/rtu_port_new.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0a3f32db00d82bc1c2f45510c1801737bf8f30f9
--- /dev/null
+++ b/modules/wrsw_rtu/rtu_port_new.vhd
@@ -0,0 +1,773 @@
+-------------------------------------------------------------------------------
+-- Title : Routing Table Unit's Port Representation (RTU_PORT)
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : wrsw_rtu_port.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2010-05-08
+-- Last update: 2012-01-26
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- It represents each switch's port (endpoint), it
+-- - take requests from a give port
+-- - forwards the request to request FIFO (access governed by Round Robin Alg)
+-- - awaits the answer from RTU engine
+-- - outputs response to the port which requested it (endpoint)
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+--
+-------------------------------------------------------------------------------
+--TODO:
+--1) change drop/flood - drop by default
+--2) might need to change RR of full match (change to strobe)
+--3) fill in aboard from extrnal (SWcore) source
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-05-08 1.0 lipinskimm Created
+-- 2010-05-29 1.1 lipinskimm modified FSM, added rtu_gcr_g_ena_i
+-- 2010-12-05 1.2 twlostow added independent output FIFOs
+-- 2012-05-20 1.3 mlipinsk making this stuff deterministic !!!
+-- 2012-11-06 1.4 mlipinsk literally, re-writing: adding i/f with fast_match, mirroring...
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+use ieee.numeric_std.all;
+
+use work.rtu_private_pkg.all;
+use work.genram_pkg.all;
+use work.wrsw_shared_types_pkg.all;
+use work.pack_unpack_pkg.all;
+
+entity rtu_port_new is
+ generic(
+ g_num_ports : integer;
+ g_port_mask_bits : integer; -- usually: g_num_ports + 1 for CPU
+ g_match_req_fifo_size : integer;
+ g_port_index : integer
+ );
+ port(
+
+ -- clock (62.5 MHz refclk/2)
+ clk_i : in std_logic;
+ -- reset (synchronous, active low)
+ rst_n_i : in std_logic;
+
+ -------------------------------------------------------------------------------
+ -- N-port RTU input interface (from the endpoint)
+ -------------------------------------------------------------------------------
+ -- 1 indicates that coresponding RTU port is idle and ready to accept requests
+ rtu_idle_o : out std_logic;
+ rtu_rq_i : in t_rtu_request;
+ rtu_rq_abort_i : in std_logic;
+ rtu_rsp_abort_i : in std_logic; -- not used yet
+ rtu_rsp_o : out t_rtu_response;
+ rtu_rsp_ack_i : in std_logic;
+
+ -------------------------------------------------------------------------------
+ -- Full Match I/F
+ -------------------------------------------------------------------------------
+ -- request
+ full_match_wr_req_o : out std_logic; -- shall be high till done (supressed by done)
+ full_match_wr_data_o : out std_logic_vector(c_PACKED_REQUEST_WIDTH - 1 downto 0);
+ full_match_wr_done_i : in std_logic;
+ full_match_wr_full_i : in std_logic;
+ -- response
+ full_match_rd_data_i : in std_logic_vector(g_num_ports + c_PACKED_RESPONSE_WIDTH - 1 downto 0);
+ full_match_rd_valid_i : in std_logic;
+
+ -------------------------------------------------------------------------------
+ -- Fast Match
+ -------------------------------------------------------------------------------
+ -- request
+ fast_match_wr_req_o : out std_logic; -- shall be a strobe
+ fast_match_wr_data_o : out t_rtu_request;
+ -- response
+ fast_match_rd_valid_i : in std_logic;
+ fast_match_rd_data_i : in t_match_response;
+ -------------------------------------------------------------------------------
+ -- REQUEST COUNTER
+ -------------------------------------------------------------------------------
+ port_almost_full_o : out std_logic;
+ port_full_o : out std_logic;
+
+ -------------------------------------------------------------------------------
+ -- info to TRU
+ -------------------------------------------------------------------------------
+-- tru_o : out t_rtu2tru;
+ -------------------------------------------------------------------------------
+ -- control register
+ -------------------------------------------------------------------------------
+ rtu_str_config_i : in t_rtu_special_traffic_config;
+
+ rtu_gcr_g_ena_i : in std_logic;
+-- rtu_pcr_pass_bpdu_i : in std_logic_vector(c_rtu_max_ports -1 downto 0);
+-- rtu_pcr_pass_all_i : in std_logic_vector(c_rtu_max_ports -1 downto 0);
+ rtu_pcr_pass_bpdu_i : in std_logic;
+ rtu_pcr_pass_all_i : in std_logic;
+ rtu_pcr_fix_prio_i : in std_logic;
+ rtu_pcr_prio_val_i : in std_logic_vector(c_wrsw_prio_width - 1 downto 0)
+ );
+
+end rtu_port_new;
+
+architecture behavioral of rtu_port_new is
+
+ type t_rtu_port_rq_states is (S_IDLE,
+ S_FAST_MATCH,
+ S_FULL_MATCH,
+ S_FINAL_MASK,
+ S_RESPONSE);
+
+ signal port_pcr_pass_bpdu : std_logic;
+ signal port_pcr_pass_all : std_logic;
+ signal rq_fifo_d : std_logic_vector(c_PACKED_REQUEST_WIDTH - 1 downto 0);
+ signal src_port_mask : std_logic_vector(c_rtu_max_ports-1 downto 0); --helper
+ signal fast_and_full_mask : std_logic_vector(c_rtu_max_ports-1 downto 0); --helper
+ signal mirror_port_dst : std_logic;
+ signal mirror_port_src_rx : std_logic;
+ signal mirror_port_src_tx : std_logic;
+ signal match_required : std_logic;
+ signal port_nofw_only : std_logic;
+ signal full_match_in : t_match_response;
+ signal fast_match : t_match_response;
+ signal full_match : t_match_response;
+ signal fast_match_wr_req : std_logic;
+ signal full_match_wr_req : std_logic;
+ signal none_match_wr_req : std_logic;
+ signal full_match_valid : std_logic;
+ signal fast_match_rd_valid : std_logic;
+ signal rq_prio : std_logic_vector(2 downto 0);
+ signal rq_has_prio : std_logic;
+ signal rtu_req_d : t_rtu_request;
+ signal full_match_wr_req_d : std_logic;
+ signal fast_match_wr_req_d : std_logic;
+ signal delayed_full_match_wr_req : std_logic;
+ signal rq_rsp_cnt : unsigned(integer(CEIL(LOG2(real(g_match_req_fifo_size ))))-1 downto 0);
+ signal rsp : t_rtu_response;
+ signal rtu_idle : std_logic;
+ signal forwarding_mask : std_logic_vector(c_rtu_max_ports-1 downto 0); --helper
+ signal forwarding_mask_CPU_filtered: std_logic_vector(c_rtu_max_ports-1 downto 0); --helper
+ signal forwarding_and_mirror_mask : std_logic_vector(c_rtu_max_ports-1 downto 0); --helper
+ signal forwarding_without_mr_dst_mask : std_logic_vector(c_rtu_max_ports-1 downto 0); --helper
+ signal drop : std_logic;
+ signal prio : std_logic_vector(2 downto 0);
+ signal hp : std_logic;
+ signal nf : std_logic;
+ signal port_state : t_rtu_port_rq_states;
+ signal full_match_rsp_port : std_logic_vector(g_num_ports-1 downto 0);
+ signal full_match_rsp_prio : std_logic_vector(c_wrsw_prio_width-1 downto 0);
+ signal full_match_req_in_progress : std_logic;
+ signal full_match_aboard : std_logic;
+ signal full_match_aboard_d : std_logic;
+ signal aboard_possible : std_logic;
+ -- VHDL -- lovn' it
+ signal zeros : std_logic_vector(47 downto 0);
+ signal dbg_force_fast_match_only : std_logic;
+ signal dbg_force_full_match_only : std_logic;
+ signal new_req_at_full_match_rsp_d : std_logic;
+
+ constant c_match_zero: t_match_response := (
+ valid => '0',
+ port_mask => (others =>'0'),
+ prio => (others =>'0'),
+ drop => '0',
+ nf => '0',
+ ff => '0',
+ hp => '0');
+
+ constant c_rtu_rsp_zero : t_rtu_response := (
+ valid => '0',
+ port_mask => (others =>'0'),
+ prio => (others =>'0'),
+ drop => '0',
+ hp => '0');
+
+ constant c_rtu_rsp_drop : t_rtu_response := (
+ valid => '1',
+ port_mask => (others =>'0'),
+ prio => (others =>'0'),
+ drop => '1',
+ hp => '0');
+
+ constant c_match_override: t_match_response := (
+ valid => '1',
+ port_mask => (others =>'1'),
+ prio => (others =>'0'),
+ drop => '0',
+ nf => '0',
+ ff => '0',
+ hp => '0');
+
+
+begin
+
+ zeros <= (others => '0');
+ dbg_force_fast_match_only <= '1' when (rtu_str_config_i.dbg_force_fast_match_only = '1') else '0';
+ dbg_force_full_match_only <= '1' when (rtu_str_config_i.dbg_force_full_match_only = '1') else '0';
+
+-- port_pcr_pass_bpdu <= rtu_pcr_pass_bpdu_i(g_port_index);
+-- port_pcr_pass_all <= rtu_pcr_pass_all_i(g_port_index);
+
+ port_pcr_pass_bpdu <= rtu_pcr_pass_bpdu_i;
+ port_pcr_pass_all <= rtu_pcr_pass_all_i;
+
+ -- create request fifo input data (registered data)
+ rq_fifo_d <=
+ rtu_req_d.has_vid &
+ rtu_req_d.prio & -- modified by per-port config
+ rtu_req_d.has_prio & -- modified by per-port config
+ rtu_req_d.vid &
+ rtu_req_d.dmac &
+ rtu_req_d.smac;
+
+ -- turn port number into bit vector
+ src_port_mask <= f_set_bit(zeros(c_rtu_max_ports-1 downto 0),'1',g_port_index);
+
+ -- check whether this port is a port which mirrors other port(s). In such case any incoming
+ -- traffic is not allowed and forwarded is only mirror traffic
+ mirror_port_dst <= '0' when (rtu_str_config_i.mr_ena = '0') else -- disabled
+ '1' when ((src_port_mask and rtu_str_config_i.mirror_port_dst) /=
+ zeros(c_rtu_max_ports-1 downto 0)) else
+ '0';
+
+ -- ingress traffic to this port (rx) is forwarded to mirror port if such port exists
+ mirror_port_src_rx <= '0' when (rtu_str_config_i.mr_ena = '0') else -- disabled
+ '1' when ((src_port_mask and rtu_str_config_i.mirror_port_src_rx) /=
+ zeros(c_rtu_max_ports-1 downto 0) ) else
+ '0';
+
+ -- traffic from this port is forwarded (tx) to the port being mirrord , so we forward it
+ -- also to mirror port (mirror_port_dst)
+ -- REMARK: if we have broadcast, the forwarding decision will show that we want to transmit
+ -- (tx) frame to the reception port... we don't mirror this traffic, this is why we
+ -- apply below the f_set_bit() mask
+ mirror_port_src_tx <= '0' when (rtu_str_config_i.mr_ena = '0') else -- disabled
+ '1' when ((f_set_bit(forwarding_mask,'0',g_port_index) and --no to myself
+ rtu_str_config_i.mirror_port_src_tx) /=
+ zeros(c_rtu_max_ports-1 downto 0) ) else
+ '0';
+
+ -- port enabled for all traffic (forward-able and link-limited)
+ match_required <= '0' when (rtu_gcr_g_ena_i = '0' or -- drop ingress traffic if RTU disabled
+ mirror_port_dst = '1') else -- drop ingress traffic if this is mirror port
+ '1';
+
+ -- port enabled only for link-limited traffic
+-- port_nofw_only <= '1' when (rtu_gcr_g_ena_i = '1' and
+-- port_pcr_pass_all = '0' and
+-- port_pcr_pass_bpdu = '1' and
+-- mirror_port_dst = '0') else
+-- '0' ;
+
+ -- unpack data from match engine into nice record
+ f_unpack5(full_match_rd_data_i,
+ full_match_in.nf,
+ full_match_in.port_mask,
+ full_match_in.drop,
+ full_match_rsp_prio,
+ full_match_rsp_port);
+
+ -- some bit optimization :)
+ full_match_in.prio(c_wrsw_prio_width-1 downto 0) <= full_match_rsp_prio;
+
+ -- valid Match Engine response for this port
+ full_match_in.valid <= full_match_rd_valid_i and
+ full_match_rsp_port(g_port_index);
+ full_match_in.ff <= '0'; -- full mutch does not provide this info (reserved for fast match)
+ full_match_in.hp <= '0'; -- full mutch does not provide this info (reserved for fast match)
+
+ -- requrest fast match (almost always)
+ fast_match_wr_req <= match_required and rtu_rq_i.valid;
+
+ -- request full match (only if:
+ full_match_wr_req <= '0' when (dbg_force_fast_match_only = '1') else -- when debugging
+ '1' when (fast_match_wr_req = '1' and -- fast match is required and
+ full_match_wr_full_i = '0' and -- full mtach is not stuck
+ rq_rsp_cnt = 0) else -- we don't process already full mach for this port
+ '1' when (full_match_wr_req_d = '1') else -- registered request
+ '1' when (delayed_full_match_wr_req = '1') else -- full match was busy at the beginning, we requrestd when it freed (later the usual)
+ '0';
+
+ -- the request is on disabled RTU /mirrored port so we don't bother with any match (full/fast)
+ none_match_wr_req <= (not match_required) and rtu_rq_i.valid;
+
+ full_match_valid <= '1' when (full_match_in.valid = '1' and -- full mach resp valid
+ rq_rsp_cnt = 1 and
+ full_match_req_in_progress = '1') else-- it is the right resp
+ '0';
+
+ -- filter out responses for other ports
+ fast_match_rd_valid<= fast_match_rd_valid_i and fast_match_rd_data_i.valid;
+
+ -- aboard signal (internal/external) shall take effect only in FULL_MATCH state, in other states:
+ -- * IDLE/FINAL_MASK/RESPONSE - useless, we have nothing to aboard (in FINAL_MASK it can be
+ -- disallowed when waiting for SWcore to ack response)
+ -- * FAST_MATCH/FINAL_MASK (waiting for SWcore ack) - impossible
+ aboard_possible <= '1' when (port_state = S_FULL_MATCH) else '0';
+
+ -- request to aboard full match
+ full_match_aboard <= (not full_match_valid) and -- suppress when we have replay from full match
+ ((aboard_possible and fast_match_wr_req));-- or -- new request when full match busy
+-- (rtu_rsp_abort_i)); -- other externa, e.g. from swcore, **not implemented yet
+
+ --------------------------------------------------------------------------------------------
+ -- register input request to make it available for both matches (full/fast)
+ --------------------------------------------------------------------------------------------
+ -- this gets registered for furthe processing (full/fast match)
+-- rq_prio <= f_pick(rtu_pcr_fix_prio_i = '0', rtu_req_d.prio, rtu_pcr_prio_val_i);
+-- rq_has_prio <= (rtu_pcr_fix_prio_i or rtu_req_d.has_prio);
+ rq_prio <= f_pick(rtu_pcr_fix_prio_i = '1', rtu_pcr_prio_val_i, rtu_rq_i.prio);
+ rq_has_prio <= '1' when (rtu_pcr_fix_prio_i = '1' or rtu_rq_i.has_prio = '1') else '0';
+
+-- -- NOTE: inside {fast,full}_match we also take into account the priority assigned to VLAN,
+-- -- this value is not taken into account in TRU !!
+-- tru_o.pass_all <= rtu_pcr_pass_all_i and rtu_gcr_g_ena_i;
+-- tru_o.forward_bpdu_only <= rtu_pcr_pass_bpdu_i;
+-- tru_o.request_valid <= rtu_rq_i.valid;
+-- tru_o.priorities <= rq_prio when (rq_has_prio = '1') else (others =>'0');
+
+ p_register_req: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ rtu_req_d.valid <= '0';
+ rtu_req_d.smac <= (others =>'0');
+ rtu_req_d.dmac <= (others =>'0');
+ rtu_req_d.vid <= (others =>'0');
+ rtu_req_d.has_vid <= '0';
+ rtu_req_d.prio <= (others =>'0');
+ rtu_req_d.has_prio <= '0';
+ else
+-- if(fast_match_wr_req = '1') then
+
+ if(fast_match_wr_req = '1' and -- request -> in principal single-cycle strope but...
+ fast_match_wr_req_d = '0') then -- .. just in case we make sure we remember the stuff once
+ rtu_req_d.valid <= rtu_rq_i.valid;
+ rtu_req_d.smac <= rtu_rq_i.smac;
+ rtu_req_d.dmac <= rtu_rq_i.dmac;
+ rtu_req_d.vid <= rtu_rq_i.vid;
+ rtu_req_d.has_vid <= rtu_rq_i.has_vid;
+ rtu_req_d.prio <= rq_prio;
+ rtu_req_d.has_prio <= rq_has_prio;
+ end if;
+ end if;
+ end if;
+ end process p_register_req;
+
+ --------------------------------------------------------------------------------------------
+ -- The request to Fast Match is done directly from input rtu_req, her we just track
+ -- current request (register req signal till response available)
+ --------------------------------------------------------------------------------------------
+ p_ctr_fast_match: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0' or dbg_force_full_match_only = '1') then
+ fast_match_wr_req_d <= '0';
+ fast_match <= c_match_zero;
+ else
+ if(fast_match_wr_req = '1') then
+ fast_match_wr_req_d <= '1';
+ elsif(fast_match_wr_req_d = '1' and fast_match_rd_valid = '1') then
+ fast_match_wr_req_d <= '0';
+ fast_match <= fast_match_rd_data_i;
+ end if;
+
+
+
+ end if;
+ end if;
+ end process p_ctr_fast_match;
+
+ --------------------------------------------------------------------------------------------
+ -- Controlling full match, more tricky ...
+ -- * we need to have wr_req_o high till request is accepted (wr_done)
+ -- * tracking (registering) aboard signal
+ -- * tracking if the current full match is processed (or some old one)
+ -- * registering valid full_match response
+ --------------------------------------------------------------------------------------------
+ p_ctr_full_match: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ full_match_wr_req_d <= '0';
+ full_match_req_in_progress <= '0';
+ full_match <= c_match_zero;
+ full_match_aboard_d <= '0';
+ new_req_at_full_match_rsp_d <='0';
+
+ else
+ -- we consider a case when new request appears when the FULL Match response
+ -- is available (full_match_valid='1' or the states that we create/send the response)
+ if((full_match_valid = '1' or port_state = S_FINAL_MASK or port_state = S_RESPONSE ) and
+ fast_match_wr_req ='1' and fast_match_wr_req_d = '0') then
+ new_req_at_full_match_rsp_d <= '1';
+ elsif(port_state = S_FAST_MATCH) then
+ new_req_at_full_match_rsp_d <= '0';
+ end if;
+
+ if(full_match_aboard = '1') then
+ full_match_aboard_d <= '1';
+ elsif(rsp.valid = '1' and rtu_rsp_ack_i ='1') then
+ full_match_aboard_d <= '0';
+ end if;
+
+ -- request access to fifo
+ if(full_match_wr_req ='1' and full_match_wr_req_d = '0') then
+ full_match_wr_req_d <= '1';
+ elsif(full_match_wr_req_d = '1' and full_match_wr_done_i = '1') then
+ full_match_wr_req_d <= '0';
+ end if;
+
+ -- register response
+ if(full_match_wr_req ='1' and full_match_wr_req_d = '0') then
+ full_match_req_in_progress <= '1';
+ full_match <= c_match_zero;
+ elsif(full_match_valid = '1' ) then
+ full_match_req_in_progress <= '0';
+ full_match <= full_match_in;
+ elsif(port_state = S_FINAL_MASK) then
+ full_match_req_in_progress <= '0';
+ end if;
+ end if;
+ end if;
+ end process p_ctr_full_match;
+
+ --------------------------------------------------------------------------------------------
+ -- counting scheduled match requets and responses, this is for the case
+ -- that we got aboard from SWcore, so that we don't take bad resonse from the match engine
+ --------------------------------------------------------------------------------------------
+ p_rq_rsp_cnt: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ rq_rsp_cnt <= (others => '0');
+ else
+ if(full_match_wr_req = '1' and full_match_wr_req_d ='0' and full_match_in.valid = '0') then
+ rq_rsp_cnt <= rq_rsp_cnt + 1;
+ elsif(full_match_in.valid = '1' ) then
+ rq_rsp_cnt <= rq_rsp_cnt - 1;
+ end if;
+ end if;
+ end if;
+ end process p_rq_rsp_cnt;
+
+ -------------------------------------------------------------------------------------------------------------------------
+ --|
+ --| (state transitions)
+ -------------------------------------------------------------------------------------------------------------------------
+ port_fsm_state : process (clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ ------------------------------------------------------------------------------------------------------------
+ --| RESET
+ ------------------------------------------------------------------------------------------------------------
+ port_state <= S_IDLE;
+ rsp <= c_rtu_rsp_zero;
+ delayed_full_match_wr_req <= '0';
+ ------------------------------------------------------------------------------------------------------------
+ else
+ -- FSM
+ case port_state is
+ ------------------------------------------------------------------------------------------------------------
+ --| IDLE: waiting for the request from a port
+ ------------------------------------------------------------------------------------------------------------
+ when S_IDLE =>
+
+ if(fast_match_wr_req = '1' or
+ new_req_at_full_match_rsp_d = '1') then -- should not be used, but just in case
+ port_state <= S_FAST_MATCH;
+ elsif(none_match_wr_req = '1') then
+ rsp <= c_rtu_rsp_drop;
+ port_state <= S_RESPONSE;
+ end if;
+
+ ------------------------------------------------------------------------------------------------------------
+ --|
+ ------------------------------------------------------------------------------------------------------------
+ when S_FAST_MATCH =>
+
+ if(rtu_rq_abort_i = '1' or rtu_rsp_abort_i = '1') then
+ port_state <= S_IDLE;
+ elsif(dbg_force_full_match_only = '1') then
+ port_state <= S_FULL_MATCH;
+ if(full_match_req_in_progress = '0' and full_match_wr_full_i = '0' and rq_rsp_cnt = 0) then
+ -- if full_match was not requested at the very beginning (directly from input requests)
+ -- it means that at that time old full_request was handled, check whether we can do
+ -- full request now, if yes, go for it
+ delayed_full_match_wr_req <= '1';
+ end if;
+ elsif(fast_match_rd_valid = '1' and fast_match_wr_req_d = '1') then
+ -- response the current fast_match request, registered
+ -- fast_match <= fast_match_rd_data_i;
+ if(dbg_force_fast_match_only = '1') then
+ port_state <= S_FINAL_MASK;
+ elsif(fast_match_rd_data_i.nf = '1' or -- non-forward (link-limited) e.g.: BPDU
+ fast_match_rd_data_i.ff = '1' or -- fast forward recongized
+ fast_match_rd_data_i.drop = '1' or -- no point in further work (drop due to VLAN)
+ full_match_aboard = '1') then -- aboard because next frame received
+ -- if we recognizd special traffic or aboard request , we don't need full match
+ port_state <= S_FINAL_MASK;
+ else
+ -- go for full match (can be abanoned any time)
+ port_state <= S_FULL_MATCH;
+ if(full_match_req_in_progress = '0' and full_match_wr_full_i = '0' and rq_rsp_cnt = 0) then
+ -- if full_match was not requested at the very beginning (directly from input requests)
+ -- it means that at that time old full_request was handled, check whether we can do
+ -- full request now, if yes, go for it
+ delayed_full_match_wr_req <= '1';
+ end if;
+ end if;
+-- elsif(rtu_rsp_abort_i = '1' and fast_match.valid = '0') then
+-- -- TODO: this should not happen -> handle exeption
+-- port_state <= S_FINAL_MASK;
+-- rsp <= c_rtu_rsp_drop;
+-- delayed_full_match_wr_req <= '0';
+ end if;
+
+ ------------------------------------------------------------------------------------------------------------
+ --| Full match :
+ --| * if not requested yet, wait for it to be possible to request
+ --| * wait for answer from Full match engine
+ --| * be ready to aboard at any moment
+ ------------------------------------------------------------------------------------------------------------
+ when S_FULL_MATCH =>
+
+ if(rtu_rq_abort_i = '1' or rtu_rsp_abort_i = '1') then
+ port_state <= S_IDLE;
+ delayed_full_match_wr_req <= '0';
+ elsif(full_match_aboard = '0' and full_match_req_in_progress = '0' and full_match_wr_full_i = '0' and rq_rsp_cnt = 0) then
+ -- request full match access
+ delayed_full_match_wr_req <= '1';
+ else
+ delayed_full_match_wr_req <= '0';
+ end if;
+
+ if(full_match_valid = '1') then --
+ -- full match done (input data registered in separate process)
+ port_state <= S_FINAL_MASK;
+ elsif(full_match_aboard = '1' and fast_match.valid = '1') then
+ -- aboard waiting for full match
+ port_state <= S_FINAL_MASK;
+ elsif(full_match_aboard = '1' and fast_match.valid = '0') then
+ -- TODO: this should not happen -> handle exeption
+ port_state <= S_FAST_MATCH;
+ end if;
+
+ ------------------------------------------------------------------------------------------------------------
+ --| prepare final mask based on :
+ --| * fast
+ --| * (if available) full match
+ --| * (some config settings)
+ ------------------------------------------------------------------------------------------------------------
+ when S_FINAL_MASK =>
+
+ if(rtu_rq_abort_i = '1' or rtu_rsp_abort_i = '1') then
+ port_state <= S_IDLE;
+ delayed_full_match_wr_req <= '0';
+ elsif(rsp.valid = '0') then
+ rsp.valid <= '1';
+ rsp.prio <= prio;
+ rsp.hp <= hp;
+
+ if(mirror_port_src_rx = '1' or mirror_port_src_tx = '1') then
+ -- if mirroring is enabled, and this port is source of mirror traffic, we don't drop
+ -- the traffic,
+ if(drop = '1' and mirror_port_src_rx = '1') then
+ -- forward only to the mirror (dst) port
+ -- (eliminate self-forward)
+ rsp.port_mask <= f_set_bit(rtu_str_config_i.mirror_port_dst,'0',g_port_index) ;
+ rsp.drop <= '0';
+ else
+ -- forward to "normal forwarding ports" + mirror (dst) port
+ -- (eliminate self-forward)
+ rsp.drop <= drop;
+ if(drop = '1') then
+ rsp.port_mask <= (others=> '0');
+ else
+ rsp.port_mask <= f_set_bit(forwarding_and_mirror_mask,'0',g_port_index);
+ end if;
+ end if;
+
+ else
+ -- normal forwarding
+ -- (eliminate self-forward)
+
+ if(f_set_bit(forwarding_without_mr_dst_mask,'0',g_port_index) = zeros(c_RTU_MAX_PORTS-1 downto 0)) then
+ rsp.drop <= '1';
+ rsp.port_mask <= (others=> '0');
+ else
+ rsp.drop <= drop;
+ if(drop = '1') then
+ rsp.port_mask <= (others=> '0');
+ else
+ rsp.port_mask <= f_set_bit(forwarding_without_mr_dst_mask,'0',g_port_index) ;
+ end if;
+ end if;
+ end if;
+
+ port_state <= S_RESPONSE;
+ end if;
+ ------------------------------------------------------------------------------------------------------------
+ --| in this state the answer is made available on the output (rtu_rsp_o). it is available until
+ --| the reception is acked by SWcore. However, new request from Endpoint can be handled in this time.
+ --| So, S_RESPONSE state is single-cyccle onliy
+ ------------------------------------------------------------------------------------------------------------
+ when S_RESPONSE =>
+
+ if((full_match_aboard_d = '1' or new_req_at_full_match_rsp_d = '1' or fast_match_wr_req = '1') and match_required ='1') then
+ -- if we are in this state because we received abanddon request and match is
+ -- required (RTU enabled/no mirroring), we go straight to FAST_MATCH
+ port_state <= S_FAST_MATCH;
+ elsif(full_match_aboard_d = '1' and match_required ='0') then
+ -- aboard, but no match required, so drop
+ rsp <= c_rtu_rsp_drop;
+ port_state <= S_RESPONSE;
+ else
+ -- go and wait for new requests
+ port_state <= S_IDLE;
+ end if;
+ ------------------------------------------------------------------------------------------------------------
+ --| OTHER:
+ ------------------------------------------------------------------------------------------------------------
+ when others =>
+ port_state <= S_IDLE;
+ rsp <= c_rtu_rsp_zero;
+ delayed_full_match_wr_req <= '0';
+ ------------------------------------------------------------------------------------------------------------
+ end case;
+ if(rtu_rsp_ack_i = '1' and rsp.valid ='1') then
+ rsp.valid <= '0';
+ rsp.port_mask <= (others =>'0');
+ rsp.prio <= (others =>'0');
+ rsp.drop <= '0';
+ rsp.hp <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process port_fsm_state;
+
+ -- we concatenate separately Switch's ports (g_num_ports-1 downto 0) and the rest (NIC) so that
+ -- frames go to NIC based on any of the decisions (fast or full match)
+ fast_and_full_mask <= (fast_match.port_mask(c_RTU_MAX_PORTS-1 downto g_num_ports) or full_match.port_mask(c_RTU_MAX_PORTS-1 downto g_num_ports)) &
+ (fast_match.port_mask(g_num_ports-1 downto 0) and full_match.port_mask(g_num_ports-1 downto 0));
+
+ -- TODO: HACK: FUCK
+ -- stupid temporary hack, the problem is that FAST MATCH does not read (for some reason) masks of VIDs different then 0...
+ -- this is only for the latency tests, later needs to be changee
+-- fast_and_full_mask <= full_match.port_mask;
+
+ -- the above solution migh not be the best - eventually, we don't really want so much traffic
+ -- to go to NIC...(this is mainly to prevent the "unrecognized" traffic to be forwarded to NIC)
+ -- fast_and_full_mask <= fast_match.port_mask and full_match.port_mask;
+
+ -- forming final mask:
+ -- d) for debugging: forcing to have only fast match
+ forwarding_mask <= fast_match.port_mask when (dbg_force_fast_match_only = '1') else
+ -- d) for debugging: forcing to have only full match
+ full_match.port_mask when (dbg_force_full_match_only = '1') else
+ -- 1) full match available, full match says that we have non-forward traffic<
+ -- to such traffic we don't apply fast_match (TRU and stuff)
+ full_match.port_mask when (full_match.valid = '1' and full_match.nf ='1') else
+ -- 2) full match available and it's normal traffic, so we apply both asks
+ fast_and_full_mask when (full_match.valid = '1') else
+ -- 3) we received aboard request and the setting indicates to drop ingressf rame in such case
+ c_rtu_rsp_drop.port_mask when (full_match_aboard_d = '1' and rtu_str_config_i.dop_on_fmatch_full = '0' ) else
+ -- 4) fast match decision only
+ fast_match.port_mask;
+
+ -- forming final drop:
+ -- d) for debugging: forcing to have only fast match
+ drop <= fast_match.drop when (dbg_force_fast_match_only = '1') else
+ -- d) for debugging: forcing to have only full match
+ full_match.drop when (dbg_force_full_match_only = '1') else
+ -- 1) drop from one of two matches, don't drop if we have non-forward traffic
+ (full_match.drop or fast_match.drop) and (not full_match.nf) when (full_match.valid = '1') else
+ -- 2) when aboarding and set to drop,
+ '1' when (full_match_aboard_d = '1' and rtu_str_config_i.dop_on_fmatch_full = '0' ) else
+ -- 3) if only fast match available, is it
+ fast_match.drop;
+ -- forming final prio:
+ -- d) for debugging: forcing to have only fast match
+ prio <= fast_match.prio when (dbg_force_fast_match_only = '1') else
+ -- d) for debugging: forcing to have only full match
+ full_match.prio when (dbg_force_full_match_only = '1') else
+ -- 1) when full match available, use it
+ full_match.prio when (full_match.valid = '1') else
+ -- 2) if aboard and set to drop, set it to zero
+ c_rtu_rsp_drop.prio when (full_match_aboard_d = '1' and rtu_str_config_i.dop_on_fmatch_full = '0' ) else
+ fast_match.prio;
+ -- forming final hp: decided by fast match, only
+ hp <= fast_match.hp when (dbg_force_fast_match_only = '1') else
+ full_match.hp when (dbg_force_full_match_only = '1') else
+ fast_match.hp;
+
+ nf <= fast_match.nf when (dbg_force_fast_match_only = '1') else
+ full_match.nf when (dbg_force_full_match_only = '1') else
+ fast_match.nf;
+
+ -- to make sure that HP traffic is not disturbed due to the fact that it's fowarded to slow NIC... just not
+ -- foward it there... (NIC should have it's own mechanism to prevent such situation, but precautions are not bad).
+ -- In case that some diagnostics is required, we can enable forwarding of HP traffic to NIC.
+ forwarding_mask_CPU_filtered <= forwarding_mask or rtu_str_config_i.cpu_forward_mask
+ when (rtu_str_config_i.hp_fw_cpu_ena = '1' and hp = '1') else
+ forwarding_mask when (hp = '0') else
+ forwarding_mask when (nf = '1') else
+ forwarding_mask and (not rtu_str_config_i.cpu_forward_mask);-- this is HP, not link-limited (nf) and
+ -- forwarding of HP to NIC is disabled
+-- f_set_bit(forwarding_mask,'0',g_num_ports) ; -- this is HP, not link-limited (nf) and
+-- -- forwarding of HP to NIC is disabled
+
+ -- forwarding mask without mirror destination port
+ -- it prevents sending traffic to mirror port from ports which are not mirrored (e.g.: when
+ -- we handle braodcast). If mirroring is disabled but the mask is set, we don't apply the
+ -- filtering.
+ forwarding_without_mr_dst_mask <=forwarding_mask_CPU_filtered when (rtu_str_config_i.mr_ena = '0') else
+ forwarding_mask_CPU_filtered and (not rtu_str_config_i.mirror_port_dst);
+
+ -- adding mirror port (dst) port to the mask
+ forwarding_and_mirror_mask <= forwarding_mask_CPU_filtered or rtu_str_config_i.mirror_port_dst;
+
+ -- decideing whe RTU can accept new request (if RTU port is not idle, and Endpoint has new
+ -- requests, it ignores incoming frame)
+ rtu_idle <= '0' when (port_state = S_FAST_MATCH) else
+ '0' when (port_state = S_FINAL_MASK and rsp.valid = '1') else -- only if we run over previus response (not ack-ed yet)
+ '0' when (port_state = S_FULL_MATCH and full_match_aboard_d = '1') else
+ '1';
+
+ rtu_idle_o <= rtu_idle;
+ rtu_rsp_o <= rsp;
+ full_match_wr_req_o <= full_match_wr_req and not full_match_wr_done_i;
+ full_match_wr_data_o<= rq_fifo_d;
+ fast_match_wr_req_o <= '0' when (dbg_force_full_match_only = '1') else
+ fast_match_wr_req;
+ fast_match_wr_data_o<= rtu_req_d;
+
+end architecture; --wrsw_rtu_port
diff --git a/modules/wrsw_rtu/rtu_private_pkg.vhd b/modules/wrsw_rtu/rtu_private_pkg.vhd
index 421e18e4e3731ad39ed96df26dee4af9ed4ed44a..c19f12f3a1becba7250dc99935d5daa20b9f53db 100644
--- a/modules/wrsw_rtu/rtu_private_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_private_pkg.vhd
@@ -47,6 +47,7 @@ library work;
use work.wishbone_pkg.all; -- for test part (to be moved)
use work.wrsw_shared_types_pkg.all;
use work.rtu_wbgen2_pkg.all;
+-- use work.rtu_wbgen2_pkg_old.all;
package rtu_private_pkg is
@@ -77,8 +78,9 @@ package rtu_private_pkg is
+ 1; -- has_priority
constant c_PACKED_RESPONSE_WIDTH : integer :=
- c_rtu_max_ports -- DPM size
+ c_rtu_max_ports -- DPM size
+ 1 -- drop bit
+ + 1 -- bpdu bit
+ c_wrsw_prio_width; -- priority
@@ -118,6 +120,75 @@ package rtu_private_pkg is
port_mask : std_logic_vector(c_rtu_max_ports-1 downto 0);
end record;
+
+ constant c_ff_single_macs_number : integer := 4;
+ constant c_ff_range_macs_number : integer := 1; -- not implemented
+
+------------------ new stuff ------------------------
+ constant c_bpd_range_lower : std_logic_vector := x"0180C2000000";
+ constant c_bpd_range_upper : std_logic_vector := x"0180C200000F";
+
+ type t_mac_array is array(integer range <>) of std_logic_vector(47 downto 0);
+ type t_rtu_special_traffic_config is record
+ -- control
+ ff_mac_br_ena : std_logic;
+ ff_mac_range_ena : std_logic;
+ ff_mac_single_ena : std_logic;
+ ff_mac_ll_ena : std_logic;
+ ff_mac_ptp_ena : std_logic;
+ mr_ena : std_logic;
+ hp_prio : std_logic_vector(7 downto 0);
+ dop_on_fmatch_full : std_logic;
+ hp_fw_cpu_ena : std_logic;
+ unrec_fw_cpu_ena : std_logic;
+ -- config
+ single_macs : t_mac_array(c_ff_single_macs_number-1 downto 0);
+ single_macs_valid : std_logic_vector(c_ff_single_macs_number-1 downto 0);
+
+ macs_range_up : std_logic_vector(47 downto 0);
+ macs_range_down : std_logic_vector(47 downto 0);
+ macs_range_valid : std_logic;
+ cpu_forward_mask : std_logic_vector(c_rtu_max_ports-1 downto 0);
+ mirror_port_src_tx : std_logic_vector(c_rtu_max_ports-1 downto 0);
+ mirror_port_src_rx : std_logic_vector(c_rtu_max_ports-1 downto 0);
+ mirror_port_dst : std_logic_vector(c_rtu_max_ports-1 downto 0);
+ dbg_force_fast_match_only : std_logic;
+ dbg_force_full_match_only : std_logic;
+ end record;
+ type t_match_response is record
+ valid : std_logic; -- entry valid
+ port_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0); -- forwarding mask
+ prio : std_logic_vector(2 downto 0); -- priority
+ drop : std_logic; -- drop on ingress
+ nf : std_logic; -- non-forward (link-limited) traffic (table 7-10,p51, IEEE 802.1D)
+ ff : std_logic; -- fast forward traffic
+ hp : std_logic; -- high priority traffic
+ end record;
+
+ function f_mac_in_range(in_mac, in_mac_lower, in_mac_upper : std_logic_vector(47 downto 0)
+ ) return std_logic;
+ function f_fast_match_mac_lookup(match_config : t_rtu_special_traffic_config;
+ in_mac : std_logic_vector(47 downto 0)
+ ) return std_logic;
+ function f_pick (condition : boolean; w_true : std_logic_vector; w_false : std_logic_vector)
+ return std_logic_vector;
+ function f_fast_match_response(vlan_entry : t_rtu_vlan_tab_entry;
+ rq_prio : std_logic_vector;
+ rq_has_prio : std_logic;
+ rq_port_mask : std_logic_vector;
+ traffic_br : std_logic;
+ pcr_pass_all : std_logic_vector;
+ pcr_drop_nonvlan_at_ingress: std_logic_vector;
+ port_mask_width : integer)
+ return t_match_response;
+ function f_set_bit(data : std_logic_vector;
+ bit_val : std_logic;
+ bit_num : integer ) return std_logic_vector;
+ function f_onehot_decode
+ (x : std_logic_vector) return integer;
+ function f_unmarshall_htab_entry (w0, w1, w2, w3, w4 : std_logic_vector) return t_rtu_htab_entry;
+------------------------------------------------------
+
component wrsw_rtu
generic(
g_num_ports: integer);
@@ -140,6 +211,25 @@ package rtu_private_pkg is
rsp_ack_i : in std_logic_vector(g_num_ports -1 downto 0);
port_almost_full_o : out std_logic_vector(g_num_ports -1 downto 0);
port_full_o : out std_logic_vector(g_num_ports -1 downto 0);
+-------------------------------------------------------------------------------
+-- TRU stuff
+-------------------------------------------------------------------------------
+ tru_req_valid_o : out std_logic;
+ tru_req_smac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_fid_o : out std_logic_vector(c_wrsw_fid_width -1 downto 0);
+ tru_req_isHP_o : out std_logic; -- high priority packet flag
+ tru_req_isBR_o : out std_logic; -- broadcast packet flag
+ tru_req_reqMask_o : out std_logic_vector(g_num_ports-1 downto 0); -- mask indicating requesting port
+ tru_resp_valid_i : in std_logic;
+ tru_resp_port_mask_i : in std_logic_vector(g_num_ports-1 downto 0); -- mask with 1's at forward ports
+ tru_resp_drop_i : in std_logic;
+ tru_resp_respMask_i : in std_logic_vector(g_num_ports-1 downto 0); -- mask with 1 at requesting port
+ tru_if_pass_all_o : out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_forward_bpdu_only_o: out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_request_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_priorities_o : out std_logic_vector(g_num_ports*c_wrsw_prio_width-1 downto 0);
+----------------------------------------------------------------------------------
wb_addr_i : in std_logic_vector(13 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
@@ -191,6 +281,45 @@ package rtu_private_pkg is
rtu_pcr_prio_val_i : in std_logic_vector(c_wrsw_prio_width - 1 downto 0));
end component;
+ component rtu_port_new
+ generic(
+ g_num_ports : integer;
+ g_port_mask_bits : integer; -- usually: g_num_ports + 1 for CPU
+ g_match_req_fifo_size : integer;
+ g_port_index : integer
+ );
+ port(
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ rtu_idle_o : out std_logic;
+ rtu_rq_i : in t_rtu_request;
+ rtu_rq_abort_i : in std_logic;
+ rtu_rsp_abort_i : in std_logic;
+ rtu_rsp_o : out t_rtu_response;
+ rtu_rsp_ack_i : in std_logic;
+ full_match_wr_req_o : out std_logic;
+ full_match_wr_data_o : out std_logic_vector(c_PACKED_REQUEST_WIDTH - 1 downto 0);
+ full_match_wr_done_i : in std_logic;
+ full_match_wr_full_i : in std_logic;
+ full_match_rd_data_i : in std_logic_vector(g_num_ports + c_PACKED_RESPONSE_WIDTH - 1 downto 0);
+ full_match_rd_valid_i : in std_logic;
+ fast_match_wr_req_o : out std_logic;
+ fast_match_wr_data_o : out t_rtu_request;
+ fast_match_rd_valid_i : in std_logic;
+ fast_match_rd_data_i : in t_match_response;
+ port_almost_full_o : out std_logic;
+ port_full_o : out std_logic;
+-- tru_o : out t_rtu2tru;
+ rtu_str_config_i : in t_rtu_special_traffic_config;
+ rtu_gcr_g_ena_i : in std_logic;
+-- rtu_pcr_pass_bpdu_i : in std_logic_vector(c_rtu_max_ports -1 downto 0);
+-- rtu_pcr_pass_all_i : in std_logic_vector(c_rtu_max_ports -1 downto 0);
+ rtu_pcr_pass_bpdu_i : in std_logic;
+ rtu_pcr_pass_all_i : in std_logic;
+ rtu_pcr_fix_prio_i : in std_logic;
+ rtu_pcr_prio_val_i : in std_logic_vector(c_wrsw_prio_width - 1 downto 0)
+ );
+ end component;
----------------------------------------------------------------------------------------
--| Round Robin Arbiter
----------------------------------------------------------------------------------------
@@ -293,9 +422,12 @@ package rtu_private_pkg is
rtu_pcr_learn_en_i : in std_logic_vector(g_num_ports - 1 downto 0);
rtu_pcr_pass_bpdu_i : in std_logic_vector(g_num_ports - 1 downto 0);
rtu_pcr_b_unrec_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_b_unrec_fw_cpu_i : in std_logic;
+ rtu_cpu_mask_i : in std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
rtu_crc_poly_i : in std_logic_vector(c_wrsw_crc_width - 1 downto 0));
end component;
+
component rtu_wishbone_slave
port (
rst_n_i : in std_logic;
@@ -321,7 +453,51 @@ package rtu_private_pkg is
regs_o : out t_rtu_out_registers);
end component;
- function f_unmarshall_htab_entry (w0, w1, w2, w3, w4 : std_logic_vector) return t_rtu_htab_entry;
+ component rtu_wishbone_slave_old
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(8 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ wb_int_o : out std_logic;
+ clk_match_i : in std_logic;
+ irq_nempty_i : in std_logic;
+ rtu_aram_addr_i : in std_logic_vector(7 downto 0);
+ rtu_aram_data_o : out std_logic_vector(31 downto 0);
+ rtu_aram_rd_i : in std_logic;
+ rtu_aram_data_i : in std_logic_vector(31 downto 0);
+ rtu_aram_wr_i : in std_logic;
+ regs_i : in t_rtu_in_registers;
+ regs_o : out t_rtu_out_registers);
+ end component;
+
+ component rtu_fast_match is
+ generic (
+ g_num_ports : integer;
+ g_port_mask_bits : integer);
+ port(
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ match_req_i : in std_logic_vector(g_num_ports-1 downto 0);
+ match_req_data_i : in t_rtu_request_array(g_num_ports-1 downto 0);
+ match_rsp_data_o : out t_match_response;
+ match_rsp_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
+ vtab_rd_addr_o : out std_logic_vector(c_wrsw_vid_width-1 downto 0);
+ vtab_rd_entry_i : in t_rtu_vlan_tab_entry;
+ tru_req_o : out t_tru_request;
+ tru_rsp_i : in t_tru_response;
+ tru_enabled_i : in std_logic;
+ rtu_str_config_i : in t_rtu_special_traffic_config;
+ rtu_pcr_pass_all_i : in std_logic_vector(c_rtu_max_ports -1 downto 0)
+ );
+ end component;
end package rtu_private_pkg;
@@ -363,6 +539,204 @@ package body rtu_private_pkg is
return t;
end function f_unmarshall_htab_entry;
+------------------ new stuff ------------------------
+
+ function f_mac_in_range(in_mac, in_mac_lower, in_mac_upper : std_logic_vector(47 downto 0)
+ ) return std_logic is
+ variable ret : std_logic;
+ begin
+
+ ret := '0';
+ if((in_mac <= in_mac_upper) and (in_mac >= in_mac_lower)) then
+ ret :='1';
+ end if;
+
+ return ret;
+ end function f_mac_in_range;
+
+ function f_fast_match_mac_lookup(match_config : t_rtu_special_traffic_config;
+ in_mac : std_logic_vector(47 downto 0)
+ ) return std_logic is
+ variable ret : std_logic;
+ begin
+
+ ret := '0';
+
+ -- pre-configured destination MAC
+ if(match_config.ff_mac_single_ena = '1') then
+ for i in 0 to c_ff_single_macs_number-1 loop
+ if(match_config.single_macs_valid(i) = '1' and in_mac = match_config.single_macs(i)) then
+ ret := '1';
+ end if;
+ end loop;
+ end if;
+
+ -- pre-configured range of destination addresses
+ if(match_config.ff_mac_range_ena = '1') then
+ if(match_config.macs_range_valid = '1') then
+ if((in_mac <= match_config.macs_range_up) and (in_mac >= match_config.macs_range_down)) then
+ ret :='1';
+ end if;
+ end if;
+ end if;
+
+ return ret;
+ end function f_fast_match_mac_lookup;
+
+
+ function f_pick (
+ condition : boolean;
+ w_true : std_logic_vector;
+ w_false : std_logic_vector) return std_logic_vector is
+
+ begin
+ if(condition) then
+ return w_true;
+ else
+ return w_false;
+ end if;
+ end function f_pick;
+
+ function f_fast_match_response(vlan_entry : t_rtu_vlan_tab_entry;
+ rq_prio : std_logic_vector;
+ rq_has_prio : std_logic;
+ rq_port_mask : std_logic_vector;
+ traffic_br : std_logic;
+ pcr_pass_all : std_logic_vector;
+ pcr_drop_nonvlan_at_ingress: std_logic_vector;
+ port_mask_width : integer)
+ return t_match_response is
+ variable rsp : t_match_response;
+ variable egress_allowed_on_vlan : std_logic;
+ begin
+ ------- mask -----------
+ rsp.port_mask := (others =>'0');
+
+ ------- prio ----------
+ if(vlan_entry.has_prio = '1') then -- regardless of vlan_entry.prio_override value
+ rsp.prio := vlan_entry.prio;
+ elsif(rq_has_prio = '1') then
+ rsp.prio := rq_prio;
+ else
+ rsp.prio := (others =>'0');
+ end if;
+
+ ------ drop ----------
+ if(((rq_port_mask and pcr_drop_nonvlan_at_ingress(rq_port_mask'length-1 downto 0)) = rq_port_mask) and
+ ((rq_port_mask and vlan_entry.port_mask(rq_port_mask'length-1 downto 0)) /= rq_port_mask)) then
+ rsp.drop := '1';
+ rsp.port_mask := (others =>'0');
+ elsif(vlan_entry.drop = '1') then
+ rsp.drop := '1';
+ rsp.port_mask := (others =>'0');
+ elsif(traffic_br = '1') then
+ rsp.port_mask := vlan_entry.port_mask and pcr_pass_all; -- broadcast also to NIC !!!!!!
+ rsp.drop := '0';
+ else
+ rsp.drop := '0';
+ rsp.port_mask(port_mask_width-1 downto 0) := vlan_entry.port_mask(port_mask_width-1 downto 0) and
+ pcr_pass_all(port_mask_width-1 downto 0);
+ end if;
+
+ ------ filled in later -----------
+-- rsp.bpdu := '0';
+ rsp.ff := '0';
+ rsp.nf := '0';
+ rsp.hp := '0';
+ rsp.valid := '0';
+
+ return rsp;
+
+ end function f_fast_match_response;
+
+ function f_set_bit(data : std_logic_vector;
+ bit_val : std_logic;
+ bit_num : integer ) return std_logic_vector is
+ variable ret : std_logic_vector(data'length-1 downto 0);
+ begin
+ ret := data;
+ ret(bit_num) := bit_val;
+ return ret;
+ end function f_set_bit;
+ function f_onehot_decode
+ (x : std_logic_vector) return integer is
+ begin
+ for i in 0 to x'length-1 loop
+ if(x(i) = '1') then
+ return i;
+ end if;
+ end loop; -- i
+ return 0;
+ end f_onehot_decode;
+-- function doPortMask(
+-- s_fast_match : std_logic: -- info what kind of input we have
+-- s_rtu_pcr_pass_bpdu, s_rtu_pcr_pass_all : std_logic; -- general config
+-- s_dst_entry_is_bpdu : std_logic; -- info from full match
+-- s_vlan_prio_override, s_vlan_has_prio, s_rq_has_prio : std_logic; -- validity of different priorities
+-- s_rq_prio, s_vlan_prio : std_logic_vector; -- different priorities
+-- s_vlan_port_mask, s_full_match_mask, s_tru_mask : std_logic_vector; -- different masks
+-- s_vlan_drop, s_tru_drop : std_logic;
+-- ) return t_rtu_response is
+-- variable s_rsp_drop : t_rtu_response;
+--
+-- begin
+--
+-- rsp.valid := '1';
+-- rsp.port_mask := (others=>'0');
+-- rsp.prio := (others=>'0');
+-- rsp.drop :='0';
+--
+-- if(s_fast_match = '1') then -------------- we need to do some additional work (normally done in match)
+--
+-- if(s_rtu_pcr_pass_all = '0') then -- we assume here that the PBDU is forwarded to FULL Match
+-- rsp.port_mask := (others => '0');
+-- rsp.prio := (others => '0');
+-- rsp.drop := '1';
+-- rsp.valid := '1';
+--
+-- else
+--
+-- rsp.port_mask := s_vlan_port_mask;
+--
+-- if (s_vlan_prio_override = '1' and s_vlan_has_prio = '1') then
+-- -- take vlan priority
+-- rsp.prio := s_vlan_prio;
+-- else
+-- if (s_vlan_has_prio = '1') then
+-- -- take vlan priority
+-- rsp.prio := s_vlan_prio;
+-- elsif (s_port_has_prio = '1') then
+-- -- take port priority
+-- rsp.prio := s_port_prio;
+-- else
+-- -- nothning matching
+-- rsp.prio := (others => '0');
+-- end if; -- if (s_vlan_has_prio = '1') then
+-- end if; -- (s_vlan_prio_override = '1' and s_vlan_has_prio = '1')
+-- end if; -- (s_rtu_pcr_pass_all = '0')
+--
+-- rsp.port_mask := rsp.port_mask and s_tru_mask;
+-- rsp.drop := s_tru_drop or s_vlan_drop;
+-- ---
+-- --- POSSIBLE BUG
+-- --- what about if the source port is not in the VLAN ??
+-- ---
+--
+-- end if; -- if(s_fast_match = '1')
+--
+-- -- we had normal match and it was BPDU pck, so it should be sent to all
+-- -- ports, regardless of TRU decision
+-- if(s_dst_entry_is_bpdu = '1' and s_fast_match = '0') then
+-- rsp.port_mask := s_full_match_mask;
+-- elsif(s_dst_entry_is_bpdu = '0' and s_fast_match = '0') then
+-- rsp.port_mask := s_full_match_mask and s_tru_mask;
+-- else
+-- rsp.port_mask := rsp.port_mask and s_tru_mask
+-- end if;
+--
+--
+--
+-- end doPortMask;
end rtu_private_pkg;
diff --git a/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd b/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
index abeabd8b9f9d5274249cd6986e3f2d73ea0c6ead..dd07dad7a87bd3b0aec7f304e3aa11f3f424835d 100644
--- a/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Routing Table Unit (RTU)
---------------------------------------------------------------------------------------
-- File : rtu_wbgen2_pkg.vhd
--- Author : auto-generated by wbgen2 from rtu_wishbone_slave.wb
--- Created : Mon Jun 25 14:23:30 2012
+-- Author : auto-generated by wbgen2 from rtu_wishbone_slave_new.wb
+-- Created : Mon Aug 5 16:03:51 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
--- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave.wb
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave_new.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
@@ -22,6 +22,7 @@ package rtu_wbgen2_pkg is
type t_rtu_in_registers is record
gcr_mfifotrig_i : std_logic;
+ gcr_rtu_version_i : std_logic_vector(3 downto 0);
psr_n_ports_i : std_logic_vector(7 downto 0);
pcr_learn_en_i : std_logic;
pcr_pass_all_i : std_logic;
@@ -40,10 +41,15 @@ package rtu_wbgen2_pkg is
ufifo_has_vid_i : std_logic;
ufifo_has_prio_i : std_logic;
mfifo_rd_req_i : std_logic;
+ rx_ff_mac_r1_hi_id_i : std_logic_vector(15 downto 0);
+ rx_ff_mac_r1_id_i : std_logic_vector(7 downto 0);
+ cpu_port_mask_i : std_logic_vector(31 downto 0);
+ rx_mp_r1_mask_i : std_logic_vector(31 downto 0);
end record;
constant c_rtu_in_registers_init_value: t_rtu_in_registers := (
gcr_mfifotrig_i => '0',
+ gcr_rtu_version_i => (others => '0'),
psr_n_ports_i => (others => '0'),
pcr_learn_en_i => '0',
pcr_pass_all_i => '0',
@@ -61,7 +67,11 @@ package rtu_wbgen2_pkg is
ufifo_pid_i => (others => '0'),
ufifo_has_vid_i => '0',
ufifo_has_prio_i => '0',
- mfifo_rd_req_i => '0'
+ mfifo_rd_req_i => '0',
+ rx_ff_mac_r1_hi_id_i => (others => '0'),
+ rx_ff_mac_r1_id_i => (others => '0'),
+ cpu_port_mask_i => (others => '0'),
+ rx_mp_r1_mask_i => (others => '0')
);
-- Output registers (WB slave -> user design)
@@ -98,6 +108,31 @@ package rtu_wbgen2_pkg is
mfifo_rd_usedw_o : std_logic_vector(5 downto 0);
mfifo_ad_sel_o : std_logic;
mfifo_ad_val_o : std_logic_vector(31 downto 0);
+ rx_ctr_ff_mac_br_o : std_logic;
+ rx_ctr_ff_mac_range_o : std_logic;
+ rx_ctr_ff_mac_single_o : std_logic;
+ rx_ctr_ff_mac_ll_o : std_logic;
+ rx_ctr_ff_mac_ptp_o : std_logic;
+ rx_ctr_mr_ena_o : std_logic;
+ rx_ctr_at_fmatch_too_slow_o : std_logic;
+ rx_ctr_prio_mask_o : std_logic_vector(7 downto 0);
+ rx_ctr_hp_fw_cpu_ena_o : std_logic;
+ rx_ctr_urec_fw_cpu_ena_o : std_logic;
+ rx_ctr_learn_dst_ena_o : std_logic;
+ rx_ctr_force_fast_match_ena_o : std_logic;
+ rx_ctr_force_full_match_ena_o : std_logic;
+ rx_ff_mac_r0_lo_o : std_logic_vector(31 downto 0);
+ rx_ff_mac_r1_hi_id_o : std_logic_vector(15 downto 0);
+ rx_ff_mac_r1_hi_id_load_o : std_logic;
+ rx_ff_mac_r1_id_o : std_logic_vector(7 downto 0);
+ rx_ff_mac_r1_id_load_o : std_logic;
+ rx_ff_mac_r1_type_o : std_logic;
+ rx_ff_mac_r1_valid_o : std_logic;
+ rx_mp_r0_dst_src_o : std_logic;
+ rx_mp_r0_rx_tx_o : std_logic;
+ rx_mp_r0_mask_id_o : std_logic_vector(15 downto 0);
+ rx_mp_r1_mask_o : std_logic_vector(31 downto 0);
+ rx_mp_r1_mask_load_o : std_logic;
end record;
constant c_rtu_out_registers_init_value: t_rtu_out_registers := (
@@ -131,7 +166,32 @@ package rtu_wbgen2_pkg is
mfifo_rd_empty_o => '0',
mfifo_rd_usedw_o => (others => '0'),
mfifo_ad_sel_o => '0',
- mfifo_ad_val_o => (others => '0')
+ mfifo_ad_val_o => (others => '0'),
+ rx_ctr_ff_mac_br_o => '0',
+ rx_ctr_ff_mac_range_o => '0',
+ rx_ctr_ff_mac_single_o => '0',
+ rx_ctr_ff_mac_ll_o => '0',
+ rx_ctr_ff_mac_ptp_o => '0',
+ rx_ctr_mr_ena_o => '0',
+ rx_ctr_at_fmatch_too_slow_o => '0',
+ rx_ctr_prio_mask_o => (others => '0'),
+ rx_ctr_hp_fw_cpu_ena_o => '0',
+ rx_ctr_urec_fw_cpu_ena_o => '0',
+ rx_ctr_learn_dst_ena_o => '0',
+ rx_ctr_force_fast_match_ena_o => '0',
+ rx_ctr_force_full_match_ena_o => '0',
+ rx_ff_mac_r0_lo_o => (others => '0'),
+ rx_ff_mac_r1_hi_id_o => (others => '0'),
+ rx_ff_mac_r1_hi_id_load_o => '0',
+ rx_ff_mac_r1_id_o => (others => '0'),
+ rx_ff_mac_r1_id_load_o => '0',
+ rx_ff_mac_r1_type_o => '0',
+ rx_ff_mac_r1_valid_o => '0',
+ rx_mp_r0_dst_src_o => '0',
+ rx_mp_r0_rx_tx_o => '0',
+ rx_mp_r0_mask_id_o => (others => '0'),
+ rx_mp_r1_mask_o => (others => '0'),
+ rx_mp_r1_mask_load_o => '0'
);
function "or" (left, right: t_rtu_in_registers) return t_rtu_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
@@ -163,6 +223,7 @@ function "or" (left, right: t_rtu_in_registers) return t_rtu_in_registers is
variable tmp: t_rtu_in_registers;
begin
tmp.gcr_mfifotrig_i := f_x_to_zero(left.gcr_mfifotrig_i) or f_x_to_zero(right.gcr_mfifotrig_i);
+tmp.gcr_rtu_version_i := f_x_to_zero(left.gcr_rtu_version_i) or f_x_to_zero(right.gcr_rtu_version_i);
tmp.psr_n_ports_i := f_x_to_zero(left.psr_n_ports_i) or f_x_to_zero(right.psr_n_ports_i);
tmp.pcr_learn_en_i := f_x_to_zero(left.pcr_learn_en_i) or f_x_to_zero(right.pcr_learn_en_i);
tmp.pcr_pass_all_i := f_x_to_zero(left.pcr_pass_all_i) or f_x_to_zero(right.pcr_pass_all_i);
@@ -181,6 +242,10 @@ tmp.ufifo_pid_i := f_x_to_zero(left.ufifo_pid_i) or f_x_to_zero(right.ufifo_pid_
tmp.ufifo_has_vid_i := f_x_to_zero(left.ufifo_has_vid_i) or f_x_to_zero(right.ufifo_has_vid_i);
tmp.ufifo_has_prio_i := f_x_to_zero(left.ufifo_has_prio_i) or f_x_to_zero(right.ufifo_has_prio_i);
tmp.mfifo_rd_req_i := f_x_to_zero(left.mfifo_rd_req_i) or f_x_to_zero(right.mfifo_rd_req_i);
+tmp.rx_ff_mac_r1_hi_id_i := f_x_to_zero(left.rx_ff_mac_r1_hi_id_i) or f_x_to_zero(right.rx_ff_mac_r1_hi_id_i);
+tmp.rx_ff_mac_r1_id_i := f_x_to_zero(left.rx_ff_mac_r1_id_i) or f_x_to_zero(right.rx_ff_mac_r1_id_i);
+tmp.cpu_port_mask_i := f_x_to_zero(left.cpu_port_mask_i) or f_x_to_zero(right.cpu_port_mask_i);
+tmp.rx_mp_r1_mask_i := f_x_to_zero(left.rx_mp_r1_mask_i) or f_x_to_zero(right.rx_mp_r1_mask_i);
return tmp;
end function;
end package body;
diff --git a/modules/wrsw_rtu/rtu_wishbone_slave.vhd b/modules/wrsw_rtu/rtu_wishbone_slave.vhd
index 3bfa36c760dfaa2e46ffca0e4fdd693f5dab8f3a..f1b3dd1d57f19d91051257cf688bff5c602abc6e 100644
--- a/modules/wrsw_rtu/rtu_wishbone_slave.vhd
+++ b/modules/wrsw_rtu/rtu_wishbone_slave.vhd
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Routing Table Unit (RTU)
---------------------------------------------------------------------------------------
-- File : rtu_wishbone_slave.vhd
--- Author : auto-generated by wbgen2 from rtu_wishbone_slave.wb
--- Created : Mon Jun 25 14:23:30 2012
+-- Author : auto-generated by wbgen2 from rtu_wishbone_slave_new.wb
+-- Created : Mon Aug 5 16:03:51 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
--- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave.wb
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave_new.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
@@ -33,7 +33,6 @@ entity rtu_wishbone_slave is
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_match_i : in std_logic;
- irq_nempty_i : in std_logic;
-- Ports for RAM: Aging bitmap for main hashtable
rtu_aram_addr_i : in std_logic_vector(7 downto 0);
-- Read data output
@@ -44,6 +43,7 @@ entity rtu_wishbone_slave is
rtu_aram_data_i : in std_logic_vector(31 downto 0);
-- Write strobe (active high)
rtu_aram_wr_i : in std_logic;
+ irq_nempty_i : in std_logic;
regs_i : in t_rtu_in_registers;
regs_o : out t_rtu_out_registers
);
@@ -84,13 +84,32 @@ signal rtu_ufifo_in_int : std_logic_vector(120 downto 0)
signal rtu_ufifo_out_int : std_logic_vector(120 downto 0);
signal rtu_ufifo_rdreq_int : std_logic ;
signal rtu_ufifo_rdreq_int_d0 : std_logic ;
-signal rtu_aram_rddata_int : std_logic_vector(31 downto 0);
-signal rtu_aram_rd_int : std_logic ;
-signal rtu_aram_wr_int : std_logic ;
signal rtu_mfifo_rst_n : std_logic ;
signal rtu_mfifo_in_int : std_logic_vector(32 downto 0);
signal rtu_mfifo_out_int : std_logic_vector(32 downto 0);
signal rtu_mfifo_wrreq_int : std_logic ;
+signal rtu_rx_ctr_ff_mac_br_int : std_logic ;
+signal rtu_rx_ctr_ff_mac_range_int : std_logic ;
+signal rtu_rx_ctr_ff_mac_single_int : std_logic ;
+signal rtu_rx_ctr_ff_mac_ll_int : std_logic ;
+signal rtu_rx_ctr_ff_mac_ptp_int : std_logic ;
+signal rtu_rx_ctr_mr_ena_int : std_logic ;
+signal rtu_rx_ctr_at_fmatch_too_slow_int : std_logic ;
+signal rtu_rx_ctr_prio_mask_int : std_logic_vector(7 downto 0);
+signal rtu_rx_ctr_hp_fw_cpu_ena_int : std_logic ;
+signal rtu_rx_ctr_urec_fw_cpu_ena_int : std_logic ;
+signal rtu_rx_ctr_learn_dst_ena_int : std_logic ;
+signal rtu_rx_ctr_force_fast_match_ena_int : std_logic ;
+signal rtu_rx_ctr_force_full_match_ena_int : std_logic ;
+signal rtu_rx_ff_mac_r0_lo_int : std_logic_vector(31 downto 0);
+signal rtu_rx_ff_mac_r1_type_int : std_logic ;
+signal rtu_rx_ff_mac_r1_valid_int : std_logic ;
+signal rtu_rx_mp_r0_dst_src_int : std_logic ;
+signal rtu_rx_mp_r0_rx_tx_int : std_logic ;
+signal rtu_rx_mp_r0_mask_id_int : std_logic_vector(15 downto 0);
+signal rtu_aram_rddata_int : std_logic_vector(31 downto 0);
+signal rtu_aram_rd_int : std_logic ;
+signal rtu_aram_wr_int : std_logic ;
signal eic_idr_int : std_logic_vector(0 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(0 downto 0);
@@ -157,6 +176,28 @@ begin
rtu_vtr1_prio_int <= "000";
rtu_vtr1_update_int <= '0';
rtu_vtr2_port_mask_int <= "00000000000000000000000000000000";
+ rtu_rx_ctr_ff_mac_br_int <= '0';
+ rtu_rx_ctr_ff_mac_range_int <= '0';
+ rtu_rx_ctr_ff_mac_single_int <= '0';
+ rtu_rx_ctr_ff_mac_ll_int <= '0';
+ rtu_rx_ctr_ff_mac_ptp_int <= '0';
+ rtu_rx_ctr_mr_ena_int <= '0';
+ rtu_rx_ctr_at_fmatch_too_slow_int <= '0';
+ rtu_rx_ctr_prio_mask_int <= "00000000";
+ rtu_rx_ctr_hp_fw_cpu_ena_int <= '0';
+ rtu_rx_ctr_urec_fw_cpu_ena_int <= '0';
+ rtu_rx_ctr_learn_dst_ena_int <= '0';
+ rtu_rx_ctr_force_fast_match_ena_int <= '0';
+ rtu_rx_ctr_force_full_match_ena_int <= '0';
+ rtu_rx_ff_mac_r0_lo_int <= "00000000000000000000000000000000";
+ regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
+ regs_o.rx_ff_mac_r1_id_load_o <= '0';
+ rtu_rx_ff_mac_r1_type_int <= '0';
+ rtu_rx_ff_mac_r1_valid_int <= '0';
+ rtu_rx_mp_r0_dst_src_int <= '0';
+ rtu_rx_mp_r0_rx_tx_int <= '0';
+ rtu_rx_mp_r0_mask_id_int <= "0000000000000000";
+ regs_o.rx_mp_r1_mask_load_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
@@ -175,6 +216,9 @@ begin
regs_o.pcr_prio_val_load_o <= '0';
regs_o.pcr_b_unrec_load_o <= '0';
rtu_vtr1_update_int <= '0';
+ regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
+ regs_o.rx_ff_mac_r1_id_load_o <= '0';
+ regs_o.rx_mp_r1_mask_load_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
@@ -195,6 +239,9 @@ begin
regs_o.pcr_fix_prio_load_o <= '0';
regs_o.pcr_prio_val_load_o <= '0';
regs_o.pcr_b_unrec_load_o <= '0';
+ regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
+ regs_o.rx_ff_mac_r1_id_load_o <= '0';
+ regs_o.rx_mp_r1_mask_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
@@ -222,16 +269,13 @@ begin
rtu_gcr_mfifotrig_rwsel <= '0';
end if;
rddata_reg(23 downto 8) <= rtu_gcr_poly_val_int;
+ rddata_reg(27 downto 24) <= regs_i.gcr_rtu_version_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
@@ -334,7 +378,114 @@ begin
rddata_reg(31 downto 0) <= rtu_vtr2_port_mask_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
+ when "00101" =>
+ if (wb_we_i = '1') then
+ rtu_rx_ctr_ff_mac_br_int <= wrdata_reg(0);
+ rtu_rx_ctr_ff_mac_range_int <= wrdata_reg(1);
+ rtu_rx_ctr_ff_mac_single_int <= wrdata_reg(2);
+ rtu_rx_ctr_ff_mac_ll_int <= wrdata_reg(3);
+ rtu_rx_ctr_ff_mac_ptp_int <= wrdata_reg(4);
+ rtu_rx_ctr_mr_ena_int <= wrdata_reg(5);
+ rtu_rx_ctr_at_fmatch_too_slow_int <= wrdata_reg(6);
+ rtu_rx_ctr_prio_mask_int <= wrdata_reg(15 downto 8);
+ rtu_rx_ctr_hp_fw_cpu_ena_int <= wrdata_reg(16);
+ rtu_rx_ctr_urec_fw_cpu_ena_int <= wrdata_reg(17);
+ rtu_rx_ctr_learn_dst_ena_int <= wrdata_reg(18);
+ rtu_rx_ctr_force_fast_match_ena_int <= wrdata_reg(24);
+ rtu_rx_ctr_force_full_match_ena_int <= wrdata_reg(25);
+ end if;
+ rddata_reg(0) <= rtu_rx_ctr_ff_mac_br_int;
+ rddata_reg(1) <= rtu_rx_ctr_ff_mac_range_int;
+ rddata_reg(2) <= rtu_rx_ctr_ff_mac_single_int;
+ rddata_reg(3) <= rtu_rx_ctr_ff_mac_ll_int;
+ rddata_reg(4) <= rtu_rx_ctr_ff_mac_ptp_int;
+ rddata_reg(5) <= rtu_rx_ctr_mr_ena_int;
+ rddata_reg(6) <= rtu_rx_ctr_at_fmatch_too_slow_int;
+ rddata_reg(15 downto 8) <= rtu_rx_ctr_prio_mask_int;
+ rddata_reg(16) <= rtu_rx_ctr_hp_fw_cpu_ena_int;
+ rddata_reg(17) <= rtu_rx_ctr_urec_fw_cpu_ena_int;
+ rddata_reg(18) <= rtu_rx_ctr_learn_dst_ena_int;
+ rddata_reg(24) <= rtu_rx_ctr_force_fast_match_ena_int;
+ rddata_reg(25) <= rtu_rx_ctr_force_full_match_ena_int;
+ rddata_reg(7) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00110" =>
+ if (wb_we_i = '1') then
+ rtu_rx_ff_mac_r0_lo_int <= wrdata_reg(31 downto 0);
+ end if;
+ rddata_reg(31 downto 0) <= rtu_rx_ff_mac_r0_lo_int;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00111" =>
+ if (wb_we_i = '1') then
+ regs_o.rx_ff_mac_r1_hi_id_load_o <= '1';
+ regs_o.rx_ff_mac_r1_id_load_o <= '1';
+ rtu_rx_ff_mac_r1_type_int <= wrdata_reg(24);
+ rtu_rx_ff_mac_r1_valid_int <= wrdata_reg(25);
+ end if;
+ rddata_reg(15 downto 0) <= regs_i.rx_ff_mac_r1_hi_id_i;
+ rddata_reg(23 downto 16) <= regs_i.rx_ff_mac_r1_id_i;
+ rddata_reg(24) <= rtu_rx_ff_mac_r1_type_int;
+ rddata_reg(25) <= rtu_rx_ff_mac_r1_valid_int;
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
when "01000" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.cpu_port_mask_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01001" =>
+ if (wb_we_i = '1') then
+ rtu_rx_mp_r0_dst_src_int <= wrdata_reg(0);
+ rtu_rx_mp_r0_rx_tx_int <= wrdata_reg(1);
+ rtu_rx_mp_r0_mask_id_int <= wrdata_reg(31 downto 16);
+ end if;
+ rddata_reg(0) <= rtu_rx_mp_r0_dst_src_int;
+ rddata_reg(1) <= rtu_rx_mp_r0_rx_tx_int;
+ rddata_reg(31 downto 16) <= rtu_rx_mp_r0_mask_id_int;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01010" =>
+ if (wb_we_i = '1') then
+ regs_o.rx_mp_r1_mask_load_o <= '1';
+ end if;
+ rddata_reg(31 downto 0) <= regs_i.rx_mp_r1_mask_i;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "10000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
@@ -372,7 +523,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "01001" =>
+ when "10001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
@@ -410,7 +561,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "01010" =>
+ when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= eic_imr_int(0);
@@ -447,7 +598,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "01011" =>
+ when "10011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
@@ -485,7 +636,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "01100" =>
+ when "10100" =>
if (wb_we_i = '1') then
end if;
if (rtu_ufifo_rdreq_int_d0 = '0') then
@@ -495,7 +646,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
- when "01101" =>
+ when "10101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= rtu_ufifo_out_int(47 downto 32);
@@ -517,13 +668,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "01110" =>
+ when "10110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= rtu_ufifo_out_int(79 downto 48);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "01111" =>
+ when "10111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= rtu_ufifo_out_int(95 downto 80);
@@ -545,7 +696,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000" =>
+ when "11000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(11 downto 0) <= rtu_ufifo_out_int(107 downto 96);
@@ -562,7 +713,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001" =>
+ when "11001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(17) <= rtu_ufifo_empty_int;
@@ -593,7 +744,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010" =>
+ when "11010" =>
if (wb_we_i = '1') then
rtu_mfifo_in_int(0) <= wrdata_reg(0);
end if;
@@ -631,7 +782,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011" =>
+ when "11011" =>
if (wb_we_i = '1') then
rtu_mfifo_in_int(32 downto 1) <= wrdata_reg(31 downto 0);
rtu_mfifo_wrreq_int <= '1';
@@ -670,7 +821,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10100" =>
+ when "11100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= rtu_mfifo_full_int;
@@ -816,6 +967,7 @@ begin
end process;
+-- Version
-- Port Select
regs_o.psr_port_sel_o <= rtu_psr_port_sel_int;
-- Number of ports
@@ -888,6 +1040,76 @@ begin
rd_data_o => rtu_ufifo_out_int
);
+-- extra code for reg/fifo/mem: Main hashtable CPU access FIFO (MFIFO)
+ regs_o.mfifo_ad_sel_o <= rtu_mfifo_out_int(0);
+ regs_o.mfifo_ad_val_o <= rtu_mfifo_out_int(32 downto 1);
+ rtu_mfifo_rst_n <= rst_n_i;
+ rtu_mfifo_INST : wbgen2_fifo_async
+ generic map (
+ g_size => 64,
+ g_width => 33,
+ g_usedw_size => 6
+ )
+ port map (
+ rd_req_i => regs_i.mfifo_rd_req_i,
+ rd_empty_o => regs_o.mfifo_rd_empty_o,
+ rd_usedw_o => regs_o.mfifo_rd_usedw_o,
+ wr_full_o => rtu_mfifo_full_int,
+ wr_empty_o => rtu_mfifo_empty_int,
+ wr_usedw_o => rtu_mfifo_usedw_int,
+ wr_req_i => rtu_mfifo_wrreq_int,
+ rst_n_i => rtu_mfifo_rst_n,
+ rd_clk_i => clk_match_i,
+ wr_clk_i => clk_sys_i,
+ wr_data_i => rtu_mfifo_in_int,
+ rd_data_o => rtu_mfifo_out_int
+ );
+
+-- Fast Forward for Broadcast
+ regs_o.rx_ctr_ff_mac_br_o <= rtu_rx_ctr_ff_mac_br_int;
+-- Fast Forward for MAC Range
+ regs_o.rx_ctr_ff_mac_range_o <= rtu_rx_ctr_ff_mac_range_int;
+-- Fast Forward for MAC Single Entries
+ regs_o.rx_ctr_ff_mac_single_o <= rtu_rx_ctr_ff_mac_single_int;
+-- Fast Forward for Link-Limited (Reserved) MACs
+ regs_o.rx_ctr_ff_mac_ll_o <= rtu_rx_ctr_ff_mac_ll_int;
+-- Fast Forward for PTP frames (PTP over IEEE 802.3 /Ethernet)
+ regs_o.rx_ctr_ff_mac_ptp_o <= rtu_rx_ctr_ff_mac_ptp_int;
+-- Port Mirror Enable
+ regs_o.rx_ctr_mr_ena_o <= rtu_rx_ctr_mr_ena_int;
+-- Drop/Forward on FullMatch Full
+ regs_o.rx_ctr_at_fmatch_too_slow_o <= rtu_rx_ctr_at_fmatch_too_slow_int;
+-- HP Priorities Mask
+ regs_o.rx_ctr_prio_mask_o <= rtu_rx_ctr_prio_mask_int;
+-- HP forward to CPU
+ regs_o.rx_ctr_hp_fw_cpu_ena_o <= rtu_rx_ctr_hp_fw_cpu_ena_int;
+-- Urecognized forward to CPU
+ regs_o.rx_ctr_urec_fw_cpu_ena_o <= rtu_rx_ctr_urec_fw_cpu_ena_int;
+-- Learn Destination MAC enable
+ regs_o.rx_ctr_learn_dst_ena_o <= rtu_rx_ctr_learn_dst_ena_int;
+-- DBG: Force Fast Match only
+ regs_o.rx_ctr_force_fast_match_ena_o <= rtu_rx_ctr_force_fast_match_ena_int;
+-- DBG: Force Full Match only
+ regs_o.rx_ctr_force_full_match_ena_o <= rtu_rx_ctr_force_full_match_ena_int;
+-- Fast Forward MAC
+ regs_o.rx_ff_mac_r0_lo_o <= rtu_rx_ff_mac_r0_lo_int;
+-- Fast Forward MAC
+ regs_o.rx_ff_mac_r1_hi_id_o <= wrdata_reg(15 downto 0);
+-- Fast Forward entry index (single/range)
+ regs_o.rx_ff_mac_r1_id_o <= wrdata_reg(23 downto 16);
+-- Fast Forward MAC single/range entry
+ regs_o.rx_ff_mac_r1_type_o <= rtu_rx_ff_mac_r1_type_int;
+-- Fast Forward MAC valid
+ regs_o.rx_ff_mac_r1_valid_o <= rtu_rx_ff_mac_r1_valid_int;
+-- CPU/LL Mask
+-- DST/SRC Mirror port
+ regs_o.rx_mp_r0_dst_src_o <= rtu_rx_mp_r0_dst_src_int;
+-- RX/TX mirror port source
+ regs_o.rx_mp_r0_rx_tx_o <= rtu_rx_mp_r0_rx_tx_int;
+-- Mirrored Port MASK Index
+ regs_o.rx_mp_r0_mask_id_o <= rtu_rx_mp_r0_mask_id_int;
+-- Mirror Port MASK
+ regs_o.rx_mp_r1_mask_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: Aging bitmap for main hashtable
-- RAM block instantiation for memory: Aging bitmap for main hashtable
rtu_aram_raminst : wbgen2_dpssram
@@ -915,31 +1137,6 @@ begin
bwsel_a_i => allones(3 downto 0)
);
--- extra code for reg/fifo/mem: Main hashtable CPU access FIFO (MFIFO)
- regs_o.mfifo_ad_sel_o <= rtu_mfifo_out_int(0);
- regs_o.mfifo_ad_val_o <= rtu_mfifo_out_int(32 downto 1);
- rtu_mfifo_rst_n <= rst_n_i;
- rtu_mfifo_INST : wbgen2_fifo_async
- generic map (
- g_size => 64,
- g_width => 33,
- g_usedw_size => 6
- )
- port map (
- rd_req_i => regs_i.mfifo_rd_req_i,
- rd_empty_o => regs_o.mfifo_rd_empty_o,
- rd_usedw_o => regs_o.mfifo_rd_usedw_o,
- wr_full_o => rtu_mfifo_full_int,
- wr_empty_o => rtu_mfifo_empty_int,
- wr_usedw_o => rtu_mfifo_usedw_int,
- wr_req_i => rtu_mfifo_wrreq_int,
- rst_n_i => rtu_mfifo_rst_n,
- rd_clk_i => clk_match_i,
- wr_clk_i => clk_sys_i,
- wr_data_i => rtu_mfifo_in_int,
- rd_data_o => rtu_mfifo_out_int
- );
-
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
diff --git a/modules/wrsw_rtu/rtu_wishbone_slave_new.wb b/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
new file mode 100644
index 0000000000000000000000000000000000000000..3aa860b759f306f973e0a2f3720111ba31e9f311
--- /dev/null
+++ b/modules/wrsw_rtu/rtu_wishbone_slave_new.wb
@@ -0,0 +1,702 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+ name = "Routing Table Unit (RTU)";
+ prefix = "rtu";
+
+ hdl_entity="rtu_wishbone_slave";
+
+-- Port Configuration Register
+ reg {
+ name = "RTU Global Control Register";
+ description = "Control register containing global (port-independent) settings of the RTU.";
+ prefix = "GCR";
+
+ field {
+ name = "RTU Global Enable";
+ description = "Global RTU enable bit. Overrides all port settings.\
+ 0: RTU is disabled. All packets are dropped.\
+ 1: RTU is enabled.";
+
+ type = BIT;
+ prefix = "G_ENA";
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ clock = "clk_match_i";
+
+ };
+
+ field {
+ name = "MFIFO Trigger";
+ description = "write 1: triggers a flush of MFIFO into the hash table (blocks the RTU for a few cycles)\
+ write 0: no effect\
+ read 1: MFIFO is busy\
+ read 0: MFIFO is idle";
+
+ prefix = "MFIFOTRIG";
+
+ type = BIT;
+ load = LOAD_EXT;
+ access_bus = READ_WRITE;
+ access_dev = READ_WRITE;
+ clock = "clk_match_i";
+
+ };
+
+ field {
+ name = "Hash Poly";
+ description = "Determines the polynomial used for hash computation. Currently available: 0x1021, 0x8005, 0x0589 ";
+
+ type = SLV;
+ prefix = "POLY_VAL";
+ align = 8;
+ size = 16 ;
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ clock = "clk_match_i";
+
+ };
+
+ field {
+ name = "Version";
+ description = "Information about the version of RTU gateware";
+
+ type = SLV;
+ prefix = "RTU_VERSION";
+ align = 8;
+ size = 4 ;
+ access_dev = WRITE_ONLY;
+ access_bus = READ_ONLY;
+ };
+ };
+
+ reg {
+ name = "Port Select Register";
+ description = "Selects the port to control through the PCR register";
+ prefix = "PSR";
+
+ field {
+ name = "Port Select";
+ prefix = "PORT_SEL";
+ description = "Selected Port";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Number of ports";
+ prefix = "N_PORTS";
+ description = "Number of RTU ports compiled in.";
+ size = 8;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "Port Control Register";
+ description = "Register controlling the mode of the RTU port selected by PSELR register.";
+ prefix = "PCR";
+
+ field {
+ name = "Learning enable";
+ description = "1: enables learning process on this port. Unrecognized requests will be put into UFIFO\
+ 0: disables learning. Unrecognized requests will be either broadcast or dropped.";
+ prefix = "LEARN_EN";
+
+ type = BIT;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+ field {
+ name = "Pass all packets";
+ description = "1: all packets are passed (depending on the rules in RT table). \
+ 0: all packets are dropped on this port.";
+
+ prefix = "PASS_ALL";
+
+ type = BIT;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+ field {
+ name = "Pass BPDUs";
+ description = "1: BPDU packets (with dst MAC 01:80:c2:00:00:00) are passed according to RT rules. This setting overrides PASS_ALL.\
+ 0: BPDU packets are passed according to RTU rules only if PASS_ALL is set.[ML by modified]";
+
+ prefix = "PASS_BPDU";
+
+ type = BIT;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+
+ };
+
+ field {
+ name = "Fix priority";
+ description = "1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint\
+ 0: Use priority from the endpoint";
+
+ prefix = "FIX_PRIO";
+
+ type = BIT;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+
+ field {
+ name = "Priority value";
+ description = "Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1";
+
+ prefix = "PRIO_VAL";
+
+ type = SLV;
+ align = 4;
+ size =3 ;
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+
+ field {
+ name = "Unrecognized request behaviour";
+ description = "Sets the port behaviour for all unrecognized requests:\
+ 0: packet is dropped\
+ 1: packet is broadcast";
+ prefix = "B_UNREC";
+
+ type = BIT;
+
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+ load = LOAD_EXT;
+ };
+ };
+
+ reg {
+ name = "VLAN Table Register 1";
+ prefix = "VTR1";
+
+ field {
+ prefix = "VID";
+ name = "VLAN ID";
+ size = 12;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "FID";
+ name = "Filtering Database ID";
+ description = "Assigns the VID to a particular filtering database";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "DROP";
+ name = "Drop";
+ description = "1: drop all packets belonging to this VLAN";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "HAS_PRIO";
+ name = "Has user-defined priority";
+ description = "1: VLAN has user-defined priority";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "PRIO_OVERRIDE";
+ name = "Override endpoint-assigned priority";
+ description = "1: always take the priority from the PRIO field, regardless of the priority value assigned at the endpoint. ";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "PRIO";
+ name = "Priority value";
+ type = SLV;
+ size = 3;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "UPDATE";
+ name = "Force VLAN table entry update";
+ description = "write 1: flush VTR1 and VTR2 registers to VLAN table entry designated in VTR1.VID";
+ type = MONOSTABLE;
+ }
+ };
+
+ reg {
+ prefix = "VTR2";
+ name = "VLAN Table Register 2";
+
+ field {
+ name = "Port Mask";
+ prefix = "PORT_MASK";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+
+
+ fifo_reg {
+ name = "Unrecognized request FIFO (UFIFO)";
+ description = "FIFO containing all RTU requests for which matching entries haven't been found. CPU reads these requests,\
+ evaluates them and updates the RTU tables accordingly.";
+
+ prefix = "UFIFO";
+ direction = CORE_TO_BUS;
+ size = 128;
+
+ flags_dev = {FIFO_FULL, FIFO_EMPTY};
+ flags_bus = {FIFO_EMPTY, FIFO_COUNT};
+
+ --clock = "clk_match_i";
+ -- clock = ""; - make it asynchronous if you want
+
+ field {
+ name = "Destination MAC address least-significant part";
+ description = "Bits [31:0] of packet destination MAC address";
+ prefix = "DMAC_LO";
+
+ type = SLV;
+ size = 32;
+ };
+
+ field {
+ name = "Destination MAC address most-significant part";
+ description = "Bits [47:32] of packet destination MAC address";
+ prefix = "DMAC_HI";
+
+ type = SLV;
+ size = 16;
+ };
+
+ field {
+ name = "Source MAC address least-significant part";
+ description = "Bits [31:0] of packet source MAC address";
+ prefix = "SMAC_LO";
+
+ type = SLV;
+ size = 32;
+ };
+
+
+ field {
+ name = "Source MAC address most-significant part";
+ description = "Bits [47:32] of packet source MAC address";
+ prefix = "SMAC_HI";
+
+ type = SLV;
+ size = 16;
+ };
+
+ field {
+ name = "VLAN Identifier";
+ description = "VLAN ID of the packet (from the endpoint)";
+ prefix = "VID";
+ size = 12;
+ type = SLV;
+ align = 32;
+ };
+
+ field {
+ name = "Priority";
+ description = "Priority value (from the endpoint)";
+ prefix = "PRIO";
+ size = 3;
+ align = 4;
+ type = SLV;
+ };
+
+ field {
+ name = "Port ID";
+ description = "Identifier of RTU port to which came the request.";
+ prefix = "PID";
+ size = 8;
+ align = 8;
+ type = SLV;
+ };
+
+ field {
+ name = "VID valid";
+ description = "1: VID value is valid\
+ 0: packet had no VLAN ID";
+ prefix = "HAS_VID";
+
+ align = 4;
+ type = BIT;
+ };
+
+ field {
+ name = "PRIO valid";
+ description = "1: PRIO value is valid\
+ 0: packet had no priority assigned";
+ prefix = "HAS_PRIO";
+
+ type = BIT;
+ };
+ };
+
+
+
+
+ fifo_reg {
+ name = "Main hashtable CPU access FIFO (MFIFO)";
+ description = "FIFO for writing to main hashtable";
+ prefix = "MFIFO";
+ direction = BUS_TO_CORE;
+ size = 64;
+
+ flags_dev = {FIFO_EMPTY, FIFO_COUNT};
+ flags_bus = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT};
+
+
+ field {
+ name = "Address/data select";
+ description = "1: AD_VAL contains new memory address\
+ 0: AD_VAL contains data word to be written at current memory address. Then, the address is incremented";
+ prefix = "AD_SEL";
+ type = BIT;
+ };
+
+ field {
+ name = "Address/data value";
+ description = "Value of new memory address (when AD_SEL = 1) or data word to be written (when AD_SEL = 0)";
+ prefix = "AD_VAL";
+ type = SLV;
+ align =32;
+ size = 32;
+ };
+
+ clock = "clk_match_i";
+
+ };
+
+ reg {
+ prefix = "RX_CTR";
+ name = "RTU Extension: Control Register";
+ field {
+ name = "Fast Forward for Broadcast";
+ description = "The feature is:\
+ 0: Disabled,\
+ 1: Enabled.";
+ prefix = "FF_MAC_BR";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Fast Forward for MAC Range";
+ description = "The feature is:\
+ 0: Disabled,\
+ 1: Enabled.";
+ prefix = "FF_MAC_RANGE";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Fast Forward for MAC Single Entries";
+ description = "The feature is:\
+ 0: Disabled,\
+ 1: Enabled.";
+ prefix = "FF_MAC_SINGLE";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Fast Forward for Link-Limited (Reserved) MACs";
+ description = "The feature is:\
+ 0: Disabled,\
+ 1: Enabled.";
+ prefix = "FF_MAC_LL";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Fast Forward for PTP frames (PTP over IEEE 802.3 /Ethernet)";
+ description = "The feature is:\
+ 0: Disabled,\
+ 1: Enabled.";
+ prefix = "FF_MAC_PTP";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Port Mirror Enable";
+ description = "Enable port mirroring as defined by proper configurition\
+ 0: Disable,\
+ 1: Enable.";
+ prefix = "MR_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Drop/Forward on FullMatch Full";
+ description = "In case that a new Frame arrives on Ingress when the previous is still handed (FullMatch process, or SWcore):\
+ 0: Drop currently processed frame (default),\
+ 1: Broadcast currently processed frame.";
+ prefix = "AT_FMATCH_TOO_SLOW";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "HP Priorities Mask";
+ description="Mask which defines which priorities of the Fast Forward traffic are considered High Priority (used also by SWcore)";
+ prefix = "PRIO_MASK";
+ type = SLV;
+ size = 8;
+ align = 8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "HP forward to CPU";
+ description = "Enables/disables forwarding of recognized HP frames to CPU (Network InterFace) - disabling forwarding can prevent flooding of switch CPU with unnecessary traffic, allowing forwarding can be enabled to snoop on network traffic). It uses HW-set (generic) mask which indicates port number of CPU - can be verified by reading\
+ 0: Disabled [default] - does not forward HP frames to CPU,\
+ 1: Enabled - forwards HP frames to CPU.";
+ prefix = "HP_FW_CPU_ENA";
+ align = 8;
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Urecognized forward to CPU";
+ description = "Allows to enable/disable forwarding of unrecognized frames (with unrecognized dstMAC) which are broadcast (when b_unrec enabled) CPU (Network InterFace) - disabled to prevent flooding of switch CPU with unnecessary traffic.It uses Link-Limited Frames Fast Forward Mask to know to which port CPU is connected.\
+ 0: Disabled [default] - does not forward unrecognized braodcast (b_unrec) frames to CPU,\
+ 1: Enabled - forwards unrecognized braodcast (b_unrec) frames to CPU.";
+ prefix = "UREC_FW_CPU_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Learn Destination MAC enable";
+ description = "Allows to enable/disable learning based on Destination MAC address (works only if learning is enabled on a port, i.e. LEARN_EN=1) .\
+ 0: Disabled [default] - frames with unrecognizd destinatin MAC do not trigger writes to UFIFO, i.e. ureq in software (unrecognized request),\
+ 1: Enabled - frames with unrecognizd destinatin MAC trigger writes to UFIFO, i.e. ureq in software.";
+ prefix = "LEARN_DST_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "DBG: Force Fast Match only";
+ description = "Forces RTU to use only Fast Match for forwarding decisions (useful for debugging).\
+ 0: Disabled [default]\
+ 1: Enabled (use when you know what you are doing, not in normal operation)";
+ prefix = "FORCE_FAST_MATCH_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ align = 8;
+ };
+ field {
+ name = "DBG: Force Full Match only";
+ description = "Forces RTU to use only Full Match for forwarding decisions (useful for debugging).\
+ 0: Disabled [default]\
+ 1: Enabled (use when you know what you are doing, not in normal operation)";
+ prefix = "FORCE_FULL_MATCH_ENA";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ prefix = "RX_FF_MAC_R0";
+ name = "RTU Extension: Fast Forward MAC bits [31:0] (validated on write to RX_FF_MAC_R1).";
+
+ field {
+ name = "Fast Forward MAC";
+ prefix = "LO";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ prefix = "RX_FF_MAC_R1";
+ name = "RTU Extension: Fast Forward MAC and control";
+ description = "Double purpose on \
+ WRITE: low bigs: MAC bits [47:32]; high bits: MAC ID, single/range, valid,\
+ READ: low bits: max number of single entries (MAX ID), high bits: max number of range entries (MAX ID).";
+ field {
+ name = "Fast Forward MAC";
+ prefix = "HI_ID";
+ type = SLV;
+ size = 16;
+ access_bus = READ_WRITE;
+ access_dev = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+ field {
+ name ="Fast Forward entry index (single/range)";
+ description = "Depending on the Single/Range bit: \
+ 0: Index of the Fast Forward MAC for single Fast Forward MAC\
+ 1: Index of the Fast Forward MAC for the Fast Forward MAC range (low bit 0 indicates lower range, low bit 1 indicates upper range, inclusive) ";
+ prefix = "ID";
+ type = SLV;
+ size = 8;
+ align =8;
+ access_bus = READ_WRITE;
+ access_dev = READ_WRITE;
+ load = LOAD_EXT;
+ };
+
+ field {
+ name = "Fast Forward MAC single/range entry";
+ description = "Indicates what kind of entry is written \
+ 0: Single Fast Forward MAC,\
+ 1: Range Fast Forward MAC (low bit of MAC ID equal to 0 indicates lower range, low bit of MAX ID equal to 1 indicates upper range, inclusive) ";
+ prefix = "TYPE";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Fast Forward MAC valid";
+ description = "The value of the bit (only validated entries are used):\
+ 0: Invalidates the entry,\
+ 1: Validates the entry.";
+ prefix = "VALID";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ prefix = "CPU_PORT";
+ name = "RTU Extension: CPU port mask (Link-Limited Frames Fast Forward Mask)";
+ field {
+ name = " CPU/LL Mask";
+ description = " It is only for debugging purposes. The ID of the CPU port is set in HW using generic which produces the CPU/LL Mask.\
+ It is used for\
+ * forwarding of the Link-Limited traffic to CPU (if enabled by config) \
+ * enabling/disabling forwarding of HP traffic to CPU (HP_FW_CPU_ENA)\
+ * enabling/disabling forwarding of unrecognized broadcast to CPU (UREC_FW_CPU_ENA).";
+ prefix = "MASK";
+ type = SLV;
+ size = 32;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+ reg {
+ prefix = "RX_MP_R0";
+ name = "RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1";
+ field {
+ name = "DST/SRC Mirror port";
+ description = "Defines whether destination or source mask is written to RX_MP_R1:\
+ 0: Mirror port(s) - destination of the mirrored traffic,\
+ 1: Mirrored port(s) - source of the mirrored traffic";
+ prefix = "DST_SRC";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "RX/TX mirror port source";
+ description = "Defines whether transmission or reception source mask is written to RX_MP_R1 (used only when DST_SRC bit is 1):\
+ 0: Reception traffic mirror source,\
+ 1: Transmission traffic mirror source.";
+ prefix = "RX_TX";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Mirrored Port MASK Index";
+ description = "Index of the mirrored configuration (to be considered for implementation in future, curreantly only single config available)";
+ prefix = "MASK_ID";
+ type = SLV;
+ size = 16;
+ align = 16;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ };
+ reg {
+ prefix = "RX_MP_R1";
+ name = "RTU Extension: Mirroring Ports Control Register 1";
+ field {
+ name = "Mirror Port MASK";
+ description = "MASK to define mirroring, depending on two lowets bit of select reg:\
+ 00: port(s) which output mirrored traffic from the mirrored port(s)- destination of the mirrored traffic (egress only, disabled for ingress traffic and traffic other then from mirrored, source, port(s))\
+ 10: port(s) whose ingress traffic is mirrored (reception source) - all the traffic received on this port(s) is forwarded to the mirror port(s)\
+ 11: port(s) whose egress traffic is mirrored (transmision source) - all the traffic forwareded to this port(s) is also forwarded to the mirror port(s).";
+ prefix = "MASK";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_WRITE;
+ load = LOAD_EXT;
+ };
+ };
+ ram {
+ name = "Aging bitmap for main hashtable";
+ description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
+ 0: entry wasn't matched\
+ 1: entry was matched at least once.\
+ CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
+ prefix = "ARAM";
+
+ width = 32;
+ size = 8192 / 32; -- 8192 bits
+ access_dev = READ_WRITE;
+ access_bus = READ_WRITE;
+
+ --[changed 6/10/2010] clock = "clk_match_i";
+ --clock = "clk_match_i"; --async?
+
+ };
+
+irq {
+ name = "UFIFO Not Empty IRQ";
+ description = "Interrupt active when there are some requests in UFIFO.";
+ prefix = "nempty";
+ trigger = LEVEL_0;
+ };
+
+};
+
+
diff --git a/modules/wrsw_rtu/wrsw_rtu.vhd b/modules/wrsw_rtu/wrsw_rtu.vhd
index 46a3499dfee16b5adcc756c9f168e3e7e2714191..3fbb5d55174612336d469459a529034166d9c5d9 100644
--- a/modules/wrsw_rtu/wrsw_rtu.vhd
+++ b/modules/wrsw_rtu/wrsw_rtu.vhd
@@ -121,8 +121,11 @@ use work.wishbone_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.rtu_private_pkg.all;
use work.rtu_wbgen2_pkg.all;
+-- use work.rtu_wbgen2_pkg_old.all;
use work.pack_unpack_pkg.all;
+
+
entity wrsw_rtu is
generic (
g_num_ports : integer);
@@ -184,6 +187,27 @@ entity wrsw_rtu is
port_almost_full_o : out std_logic_vector(g_num_ports -1 downto 0);
port_full_o : out std_logic_vector(g_num_ports -1 downto 0);
+-------------------------------------------------------------------------------
+-- TRU stuff
+-------------------------------------------------------------------------------
+
+ tru_req_valid_o : out std_logic;
+ tru_req_smac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_fid_o : out std_logic_vector(c_wrsw_fid_width -1 downto 0);
+ tru_req_isHP_o : out std_logic; -- high priority packet flag
+ tru_req_isBR_o : out std_logic; -- broadcast packet flag
+ tru_req_reqMask_o : out std_logic_vector(g_num_ports-1 downto 0); -- mask indicating requesting port
+
+ tru_resp_valid_i : in std_logic;
+ tru_resp_port_mask_i : in std_logic_vector(g_num_ports-1 downto 0); -- mask with 1's at forward ports
+ tru_resp_drop_i : in std_logic;
+ tru_resp_respMask_i : in std_logic_vector(g_num_ports-1 downto 0); -- mask with 1 at requesting port
+
+ tru_if_pass_all_o : out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_forward_bpdu_only_o: out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_request_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_priorities_o : out std_logic_vector(g_num_ports*c_wrsw_prio_width-1 downto 0);
-------------------------------------------------------------------------------
-- Wishbone (synchronous to refclk2_i). See the wbgen2 file for register details
@@ -229,8 +253,6 @@ architecture behavioral of wrsw_rtu is
-- response data outputed from RTU to rsp_fifo
signal rsp_rtu_match_data : std_logic_vector(g_num_ports + c_PACKED_RESPONSE_WIDTH - 1 downto 0);
-
-
--| HASH TABLE lookup engine
signal htab_rr_sel_w : std_logic;
@@ -553,7 +575,7 @@ begin
--| WISHBONE I/F: interface with CPU and RAM/CAM
- U_WB_Slave : rtu_wishbone_slave
+ U_WB_Slave : rtu_wishbone_slave_old
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
diff --git a/modules/wrsw_rtu/xwrsw_rtu.vhd b/modules/wrsw_rtu/xwrsw_rtu.vhd
index 193c5053ba770a23f2e7c28aa95884d0bb9dc887..0f682a53743235f08e2e3b568bb992e80a8fc54d 100644
--- a/modules/wrsw_rtu/xwrsw_rtu.vhd
+++ b/modules/wrsw_rtu/xwrsw_rtu.vhd
@@ -67,6 +67,11 @@ entity xwrsw_rtu is
rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
+ tru_req_o : out t_tru_request;
+ tru_resp_i : in t_tru_response;
+ rtu2tru_o : out t_rtu2tru;
+ tru_enabled_i: in std_logic;
+
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
);
@@ -96,6 +101,24 @@ architecture wrapper of xwrsw_rtu is
rsp_ack_i : in std_logic_vector(g_num_ports -1 downto 0);
port_almost_full_o : out std_logic_vector(g_num_ports -1 downto 0);
port_full_o : out std_logic_vector(g_num_ports -1 downto 0);
+-------------------------------------------------------------------------------
+-- TRU stuff
+-------------------------------------------------------------------------------
+ tru_req_valid_o : out std_logic;
+ tru_req_smac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width-1 downto 0);
+ tru_req_fid_o : out std_logic_vector(c_wrsw_fid_width -1 downto 0);
+ tru_req_isHP_o : out std_logic; -- high priority packet flag
+ tru_req_isBR_o : out std_logic; -- broadcast packet flag
+ tru_req_reqMask_o : out std_logic_vector(g_num_ports-1 downto 0); -- mask indicating requesting port
+ tru_resp_valid_i : in std_logic;
+ tru_resp_port_mask_i : in std_logic_vector(g_num_ports-1 downto 0); -- mask with 1's at forward ports
+ tru_resp_drop_i : in std_logic;
+ tru_resp_respMask_i : in std_logic_vector(g_num_ports-1 downto 0); -- mask with 1 at requesting port
+ tru_if_pass_all_o : out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_forward_bpdu_only_o: out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_request_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
+ tru_if_priorities_o : out std_logic_vector(g_num_ports*c_wrsw_prio_width-1 downto 0);
wb_adr_i : in std_logic_vector(13 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
@@ -129,6 +152,9 @@ architecture wrapper of xwrsw_rtu is
signal port_full_hacked : std_logic_vector(g_num_ports -1 downto 0);
signal port_full : std_logic_vector(g_num_ports -1 downto 0);
signal port_idle : std_logic_vector(g_num_ports -1 downto 0);
+ ----------- TRU stuff ---------
+ signal priorities : std_logic_vector(g_num_ports*c_wrsw_prio_width-1 downto 0);
+ -------------------------------
begin -- wrapper
@@ -147,6 +173,9 @@ begin -- wrapper
rsp_ack(i) <= rsp_ack_i(i);
rsp_o(i).prio <= rsp_prio(c_wrsw_prio_width*i + c_prio_num_width-1 downto c_wrsw_prio_width*i);
req_full_o(i) <= port_full_hacked(i) or port_full(i) or (not port_idle(i));
+ --- TRU stuff -------
+-- rtu2tru_o.priorities(i)(c_wrsw_prio_width-1 downto 0) <= priorities((i+1)*c_wrsw_prio_width-1 downto i*c_wrsw_prio_width);
+ -----------------------
end generate gen_merge_signals;
-------------------------- TEMPORARY HACK -------------------------------------------------------
@@ -230,6 +259,23 @@ begin -- wrapper
rsp_ack_i => rsp_ack,
port_full_o => port_full,
wb_adr_i => wb_in.adr(13 downto 0),
+ ----------------------------------------------------------------------------
+ tru_req_valid_o => tru_req_o.valid ,
+ tru_req_smac_o => tru_req_o.smac,
+ tru_req_dmac_o => tru_req_o.dmac,
+ tru_req_fid_o => tru_req_o.fid,
+ tru_req_isHP_o => tru_req_o.isHP,
+ tru_req_isBR_o => tru_req_o.isBR,
+ tru_req_reqMask_o => tru_req_o.reqMask(g_num_ports-1 downto 0),
+ tru_resp_valid_i => tru_resp_i.valid,
+ tru_resp_port_mask_i => tru_resp_i.port_mask(g_num_ports-1 downto 0),
+ tru_resp_drop_i => tru_resp_i.drop,
+ tru_resp_respMask_i => tru_resp_i.respMask(g_num_ports-1 downto 0),
+ tru_if_pass_all_o => rtu2tru_o.pass_all(g_num_ports-1 downto 0),
+ tru_if_forward_bpdu_only_o => rtu2tru_o.forward_bpdu_only(g_num_ports-1 downto 0),
+ tru_if_request_valid_o => rtu2tru_o.request_valid(g_num_ports-1 downto 0),
+ tru_if_priorities_o => priorities,
+ ----------------------------------------------------------------------------
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_sel_i => wb_in.sel,
@@ -239,4 +285,14 @@ begin -- wrapper
wb_irq_o => wb_out.int,
wb_we_i => wb_in.we);
+-- dummy TRU signals assigment
+--
+-- tru_req_o.valid <= req_i(0).valid;
+-- tru_req_o.smac <= req_i(0).smac;
+-- tru_req_o.dmac <= req_i(0).dmac;
+-- tru_req_o.fid <= req_i(0).vid(c_wrsw_fid_width-1 downto 0);
+-- tru_req_o.isHP <= req_i(0).has_prio when (tru_resp_i.drop = '0') else '1';
+-- tru_req_o.isBR <= req_i(0).has_vid;
+-- tru_req_o.reqMask <= req_i(0).smac(c_RTU_MAX_PORTS-1 downto 0) when (tru_resp_i.valid='1') else (others=>'0');
+
end wrapper;
diff --git a/modules/wrsw_rtu/xwrsw_rtu_new.vhd b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1455233a1d4f07b95e3efd4770e07de031e6b522
--- /dev/null
+++ b/modules/wrsw_rtu/xwrsw_rtu_new.vhd
@@ -0,0 +1,916 @@
+-------------------------------------------------------------------------------
+-- Title : eXtended Routing Table Unit (RTU)
+-- Project : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File : xwrsw_rtu_new.vhd
+-- Authors : Tomasz Wlostowski, Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2012-01-10
+-- Last update: 2012-12-03
+-- Platform : FPGA-generic
+-- Standard : VHDL
+-------------------------------------------------------------------------------
+-- Description: Module takes packet source & destination MAC addresses, VLAN ID
+-- and priority priority and decides where and with what final priority (after
+-- evalating the per MAC-assigned priorities, per-VLAN priorities, per-port and
+-- per-packet), the packet shall be routed. The exact lookup algorithm is described in
+-- rtu_sim.c file.
+--
+-- RTU has c_rtu_num_ports independent request ports which take RTU requests
+-- from the endpoints, and c_rtu_num_ports response ports which deliver the routing
+-- decisions for requests coming to associated input ports.
+--
+-- You can assume that RTU requests won't come more often than every 40 refclk2
+-- cycles for each port.
+--
+-- Since the RTU engine is shared by all ports, the requests are:
+-- - scheduled by a round-robin arbiter, so each port gets the same priority
+-- - inserted into a common request FIFO
+-- - processed by the lookup engine
+-- - responses are outputted to response FIFO and delivered into appropriate
+-- destination ports.
+--
+-- RTU has 2 memory blocks:
+-- external ZBT memory to store the main MAC table
+-- small BRAM block (HCAM) for storage of entries which cause hash collisions in main
+--
+-- The main MAC table is organized as a
+-- bucketed hashtable (see rtu_sim.c for details). Each bucket contains 4 entries:
+--
+-- addr 0: bucket 0 [entry 1] [entry 2] [entry 3] [entry 4]
+-- addr 1: bucket 1 [entry 1] [entry 2] [entry 3] [entry 4]
+--
+-- If there are more than 4 MAC addresses with the same hash, the last entry in
+-- the bucket contains a pointer to CAM memory which stores the remaining MAC
+-- entries.
+--
+-- Both memories (ZBT and HCAM) are split into 2 banks. While one bank is
+-- being used by the lookup engine, the other can be accessed from the Wishbone.
+-- Bank switching is done by setting appropriate bit in WB control register.
+-- RTU has a separate FIFO for writing the memories by the CPU (MFIFO). Each MFIFO
+-- entry has 2 fields:
+-- - address/data field select bit (determines if A/D field is a new address or
+-- data value)
+-- - address/data value
+-- MFIFO has a separate timeslot for accessing the memory, which is scheduled
+-- in the same manner as the input ports.
+--
+-- For all unrecognized requests RTU should (depending on configuration bit,
+-- independently for each port) either drop or broadcast the packet. The
+-- request itself is put into a separate FIFO (along with requesting port
+-- number) and an interrupt is triggered. CPU parses the request using more sophisticated
+-- algorithm and eventually updates the MAC table.
+--
+-- Aging: There is a separate RAM block ARAM (8192 + some bits for CAM entries), accessible both
+-- from the CPU and the Wishbone. Every time matching entry is found, it's
+-- corresponding bit is set to 1. CPU reads this table every few seconds and
+-- updates the aging counters (aging is not implemented in hardware to make it
+-- simpler)
+--
+-- Additional port configuration bits (needed for RSTP/STP implementation)
+-- - LEARN_EN: enable learning on certain port (unrecognized requests go to
+-- FIFO) (port is in ENABLED or LEARNING mode)
+-- - DROP: drop all the packets regardless of the RTU decision (port is BLOCKING)
+-- - PASS_BPDU: enable passing of BPDU packets (port is BLOCKING). BPDUs go to
+-- the designated NIC port (ID/mask set in separate register)
+--
+-- Maciek: if you decide to use CRC-based hash, make the initial hash value & polynomial
+-- programmable from Wishbone.
+--
+-- RTUeX:
+-- - debugged new feature (Simulation and H/W on the switch):
+-- * singe MAC FastForward
+-- * range MAC FastForward
+-- * Broadcast FastForward
+-- * PTP FastForward
+-- * LinkLimited FastForward
+-- * Mirroring
+-- - not debbuged: HP packet recognision - I need VLANs
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Tomasz Wlostowski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-01-10 1.0 twlostow created
+-- 2010-11-29 1.1 mlipinsk connected prio, added temp_hack
+-- 2012-11-06 1.2 mlipinsk RTUeX - added fast match and config, integrated with RTU,
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wrsw_shared_types_pkg.all;
+use work.rtu_private_pkg.all;
+use work.pack_unpack_pkg.all;
+use work.genram_pkg.all;
+use work.rtu_wbgen2_pkg.all;
+use work.gencores_pkg.all;
+
+entity xwrsw_rtu_new is
+
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_handle_only_single_req_per_port : boolean := FALSE;
+ g_prio_num : integer;
+ g_num_ports : integer;
+ g_cpu_port_num : integer := -1; --TODO: get rid of this
+ g_match_req_fifo_size : integer := 32;
+ g_port_mask_bits : integer;
+ g_rmon_events_bits_pp : integer := 9); -- rmon events num ber per port
+
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ req_i : in t_rtu_request_array(g_num_ports-1 downto 0);
+ req_full_o : out std_logic_vector(g_num_ports-1 downto 0);
+
+ rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
+ rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rq_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rsp_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
+ tru_req_o : out t_tru_request;
+ tru_resp_i : in t_tru_response;
+ rtu2tru_o : out t_rtu2tru;
+ tru_enabled_i: in std_logic;
+ rmon_events_o : out std_logic_vector(g_num_ports*g_rmon_events_bits_pp-1 downto 0);
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+ );
+
+end xwrsw_rtu_new;
+architecture behavioral of xwrsw_rtu_new is
+
+ constant c_prio_num_width : integer := integer(CEIL(LOG2(real(g_prio_num ))));
+ constant c_g_num_ports_width : integer := integer(CEIL(LOG2(real(g_num_ports ))));
+ constant c_VLAN_TAB_ENTRY_WIDTH : integer := 46;
+ constant c_match_req_fifo_size : integer := g_match_req_fifo_size + g_num_ports;
+ constant c_match_req_fifo_size_width : integer := integer(CEIL(LOG2(real(c_match_req_fifo_size ))));
+
+ -- PORT_N -> MATCH_FIFO_ACCESS (round robin access to FIFO)
+ signal rq_fifo_wr_access : std_logic_vector(g_num_ports-1 downto 0);
+ signal rq_fifo_write_sng : std_logic;
+ signal gnt_fifo_access : std_logic_vector(g_num_ports-1 downto 0);
+ type t_rq_fifo_request_array is array (integer range <>) of std_logic_vector(c_PACKED_REQUEST_WIDTH-1 downto 0);
+ signal rq_fifo_d_requests : t_rq_fifo_request_array(0 to g_num_ports-1);
+ signal rq_fifo_d_muxed : std_logic_vector(g_num_ports+ c_PACKED_REQUEST_WIDTH -1 downto 0);
+
+ -- PORT_N -> Fast_Match
+ signal fast_match_req : std_logic_vector(g_num_ports-1 downto 0);
+ signal fast_match_req_data : t_rtu_request_array(g_num_ports-1 downto 0);
+ signal fast_match_rsp_data : t_match_response;
+ signal fast_match_rsp_valid : std_logic_vector(g_num_ports-1 downto 0);
+
+ -- MATCH_FIFO_ACCESS -> rtu_match
+ signal rq_fifo_read : std_logic;
+ signal rq_fifo_qvalid : std_logic;
+ signal rq_fifo_data : std_logic_vector(g_num_ports + c_PACKED_REQUEST_WIDTH - 1 downto 0);
+ signal rq_fifo_full : std_logic;
+ signal rq_fifo_almost_full : std_logic;
+ signal rq_fifo_full_for_ports : std_logic;
+ signal rq_fifo_empty : std_logic;
+
+ -- rtu_match -> PORTs
+ signal rsp_valid : std_logic;
+ signal rsp_data : std_logic_vector(g_num_ports + c_PACKED_RESPONSE_WIDTH - 1 downto 0);
+
+ -- rtu_match -> rtu_lookup_engine (HTAB interface)
+ signal htab_start : std_logic;
+ signal htab_ack : std_logic;
+ signal htab_hash : std_logic_vector(c_wrsw_hash_width-1 downto 0);
+ signal htab_mac : std_logic_vector(47 downto 0);
+ signal htab_fid : std_logic_vector(7 downto 0);
+ signal htab_found : std_logic;
+ signal htab_drdy : std_logic;
+ signal htab_valid : std_logic;
+ signal htab_entry : t_rtu_htab_entry;
+
+ -- U_WB_Slave <-> others
+ type t_pcr_prio_val_array is array(integer range <>) of std_logic_vector(c_wrsw_prio_width-1 downto 0);
+ signal pcr_learn_en : std_logic_vector(c_rtu_max_ports - 1 downto 0);
+ signal pcr_pass_all : std_logic_vector(c_rtu_max_ports - 1 downto 0);
+ signal pcr_pass_bpdu : std_logic_vector(c_rtu_max_ports - 1 downto 0);
+ signal pcr_fix_prio : std_logic_vector(c_rtu_max_ports - 1 downto 0);
+ signal pcr_prio_val : t_pcr_prio_val_array(c_rtu_max_ports-1 downto 0);
+ signal pcr_b_unrec : std_logic_vector(c_rtu_max_ports - 1 downto 0);
+ signal regs_towb : t_rtu_in_registers;
+ signal regs_fromwb : t_rtu_out_registers;
+ signal current_pcr : integer;
+ signal current_mac_ID : integer;
+ signal rtu_gcr_poly_used : std_logic_vector(15 downto 0);
+ signal mfifo_trigger : std_logic;
+ signal current_MAC_entry : std_logic_vector(47 downto 0);
+
+ --|HCAM - Hash collision memory
+ signal aram_main_addr : std_logic_vector(7 downto 0);
+ signal aram_main_data_i : std_logic_vector(31 downto 0);
+ signal aram_main_data_o : std_logic_vector(31 downto 0);
+ signal aram_main_rd : std_logic;
+ signal aram_main_wr : std_logic;
+
+ signal irq_nempty : std_logic;
+
+ -- U_Adapter <-> U_WB_Slave : wishbone adapter (pipeline2classic) to WBgen-erated wisbhone slave
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+
+ -- FULL_Match to VLAN Tab memory
+ signal vlan_tab_rd_vid : std_logic_vector(c_wrsw_vid_width-1 downto 0);
+ signal vlan_tab_rd_data4match : std_logic_vector(c_VLAN_TAB_ENTRY_WIDTH-1 downto 0); --packed
+ signal vlan_tab_rd_entry4match : t_rtu_vlan_tab_entry; -- unpacked
+
+ -- Fast_Match to VLAN Tab memroy
+ signal vlan_tab_rd_entry4fast_match : t_rtu_vlan_tab_entry;
+ signal fast_match_vtab_addr : std_logic_vector(c_wrsw_vid_width-1 downto 0);
+ signal fast_match_vtab_data : std_logic_vector(c_VLAN_TAB_ENTRY_WIDTH-1 downto 0);
+
+ -- WB slave to VLAN tab
+ signal vlan_tab_wr_data : std_logic_vector(c_VLAN_TAB_ENTRY_WIDTH-1 downto 0);
+
+ signal port_idle : std_logic_vector(g_num_ports-1 downto 0);
+ signal rtu_special_traffic_config : t_rtu_special_traffic_config;
+ signal zeros : std_logic_vector(c_rtu_max_ports-1 downto 0);
+
+ -- coutning fifo occupanccy (no usecnt provided) to indicate full to port when there
+ -- is still N (port number) free places in FIFO (this is in case all the ports make
+ -- request at the same time)
+ signal match_req_fifo_cnt : unsigned(c_match_req_fifo_size_width-1 downto 0);
+
+ -- aux
+ signal rsp_fifo_read_all_zeros : std_logic_vector(g_num_ports - 1 downto 0);
+ signal cpu_port_mask : std_logic_vector(c_rtu_max_ports - 1 downto 0);
+
+ signal rsp : t_rtu_response_array(g_num_ports-1 downto 0);
+ signal htab_port : std_logic_vector(g_num_ports - 1 downto 0);
+ signal htab_src_dst : std_logic;
+
+ signal dbg_forwarded_to_port : std_logic_vector(g_num_ports - 1 downto 0);
+
+ signal CONTROL0 : std_logic_vector(35 downto 0);
+ signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
+
+ component chipscope_icon
+ port (
+ CONTROL0 : inout std_logic_vector(35 downto 0));
+ end component;
+
+ component chipscope_ila
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(31 downto 0);
+ TRIG1 : in std_logic_vector(31 downto 0);
+ TRIG2 : in std_logic_vector(31 downto 0);
+ TRIG3 : in std_logic_vector(31 downto 0));
+ end component;
+
+
+begin
+
+ zeros <= (others => '0');
+ rsp_fifo_read_all_zeros <= (others => '0');
+ irq_nempty <= regs_fromwb.ufifo_wr_empty_o;
+ req_full_o <= not port_idle;
+
+ GEN_NO_CPU_MASK: if(g_cpu_port_num < 0) generate
+ cpu_port_mask <= zeros;
+ end generate GEN_NO_CPU_MASK;
+ GEN_CPU_MASK: if(g_cpu_port_num >= 0) generate
+ cpu_port_mask <= f_set_bit(zeros,'1',g_cpu_port_num);
+ end generate GEN_CPU_MASK;
+
+ -- ??? (legacy)
+-- gen_term_unused : for i in g_num_ports to g_num_ports-1 generate
+-- rq_strobe_p(i) <= '0';
+-- rsp_ack(i) <= '1';
+-- end generate gen_term_unused;
+
+ U_Adapter : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => true,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ slave_i => wb_i,
+ slave_o => wb_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ wb_out.err <= '0';
+ wb_out.rty <= '0';
+ --------------------------------------------------------------------------------------------
+ --| PORTS - g_num_ports number of I/O ports, a port:
+ --| - inputs request to REQUEST FIFO
+ --| - waits for the response,
+ --| - reads response from RESPONSE FIFO of full match and from fast match
+ --------------------------------------------------------------------------------------------
+ ports : for i in 0 to (g_num_ports - 1) generate
+
+ U_PortX : rtu_port_new
+ generic map (
+ g_num_ports => g_num_ports,
+ g_port_mask_bits => g_port_mask_bits,
+ g_match_req_fifo_size => g_match_req_fifo_size,
+ g_port_index => i)
+ port map(
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+
+ rtu_idle_o => port_idle(i), -- TODO: req_full_o ??/
+ rtu_rq_i => req_i(i),
+ rtu_rq_abort_i => rq_abort_i(i),
+ rtu_rsp_abort_i => rsp_abort_i(i),--'0', -- new stuff from SWcore
+ rtu_rsp_o => rsp(i),
+ rtu_rsp_ack_i => rsp_ack_i(i),
+
+ full_match_wr_req_o => rq_fifo_wr_access(i),
+ full_match_wr_data_o => rq_fifo_d_requests(i),
+ full_match_wr_done_i => gnt_fifo_access(i),
+ full_match_wr_full_i => rq_fifo_full_for_ports,
+ full_match_rd_data_i => rsp_data,
+ full_match_rd_valid_i => rsp_valid,
+
+ fast_match_wr_req_o => fast_match_req(i),
+ fast_match_wr_data_o => fast_match_req_data(i),
+ fast_match_rd_valid_i => fast_match_rsp_valid(i),
+ fast_match_rd_data_i => fast_match_rsp_data,
+
+ port_almost_full_o => open,
+ port_full_o => open,
+
+-- tru_o => rtu2tru_o,
+
+ rtu_str_config_i => rtu_special_traffic_config,
+
+ rtu_gcr_g_ena_i => regs_fromwb.gcr_g_ena_o,
+ rtu_pcr_pass_bpdu_i => pcr_pass_bpdu(i),
+ rtu_pcr_pass_all_i => pcr_pass_all(i),
+-- rtu_pcr_pass_bpdu_i => pcr_pass_bpdu,
+-- rtu_pcr_pass_all_i => pcr_pass_all,
+ rtu_pcr_fix_prio_i => pcr_fix_prio(i),
+ rtu_pcr_prio_val_i => pcr_prio_val(i)
+ );
+
+ -- NOTE: inside {fast,full}_match we also take into account the priority assigned to VLAN,
+ -- this value is not taken into account in TRU !!
+ rtu2tru_o.request_valid(i) <= req_i(i).valid;
+ rtu2tru_o.priorities(i) <= f_pick(pcr_fix_prio(i) = '1', pcr_prio_val(i), req_i(i).prio) when (pcr_fix_prio(i)='1' or req_i(i).has_prio='1') else
+ (others=>'0');
+
+-- rtu2tru_o.priorities(i) <= f_pick(pcr_fix_prio(i) = '0', req_i(i).prio, pcr_prio_val(i));
+ rtu2tru_o.has_prio(i) <= '1' ;--req_i(i).has_prio;
+
+ rsp_o(i) <= rsp(i); -- for RMONs
+ end generate; -- end ports
+
+ rtu2tru_o.pass_all <= pcr_pass_all;
+ rtu2tru_o.forward_bpdu_only <= pcr_pass_bpdu;
+ ------------------------------------------------------------------------
+ -- REQUEST FIFO BUS
+ -- Data from all ports into one match module
+ ------------------------------------------------------------------------
+ U_req_fifo_arbiter : rtu_rr_arbiter
+ generic map (
+ g_width => g_num_ports)
+ port map(
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ req_i => rq_fifo_wr_access,
+ gnt_o => gnt_fifo_access
+ );
+
+ p_mux_fifo_req : process(rq_fifo_d_requests, gnt_fifo_access)
+ variable do_wr : std_logic;
+ variable do_data : std_logic_vector(c_PACKED_REQUEST_WIDTH-1 downto 0);
+ begin
+
+ do_data := (others => 'X');
+ do_wr := '0';
+
+ if(gnt_fifo_access = rsp_fifo_read_all_zeros) then
+ do_wr := '0';
+ else
+ do_wr := '1';
+ end if;
+
+ for i in 0 to g_num_ports-1 loop
+ if(gnt_fifo_access(i) = '1') then
+ do_data := rq_fifo_d_requests(i);
+ end if;
+ end loop; -- i
+
+ rq_fifo_write_sng <= do_wr;
+ rq_fifo_d_muxed <= gnt_fifo_access & do_data;
+ end process;
+
+ -----------------------------------------------------------------------------
+ -- REQUEST FIFO: takes requests from ports and makes it available for RTU MATCH
+ -----------------------------------------------------------------------------
+ U_ReqFifo : generic_shiftreg_fifo
+ generic map (
+ g_data_width => g_num_ports + c_PACKED_REQUEST_WIDTH,
+ g_size => 32
+ )
+ port map
+ (
+ rst_n_i => rst_n_i,
+ d_i => rq_fifo_d_muxed,
+ clk_i => clk_sys_i,
+ rd_i => rq_fifo_read, --rtu_match
+ we_i => rq_fifo_write_sng,
+ q_o => rq_fifo_data,
+ q_valid_o => rq_fifo_qvalid,
+ full_o => rq_fifo_full
+ );
+
+ rq_fifo_empty <= not rq_fifo_qvalid;
+
+ p_reqFifo_cnt : process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if(rst_n_i = '0') then
+ match_req_fifo_cnt <= (others =>'0');
+ else
+ if(rq_fifo_write_sng = '1' and rq_fifo_read ='0') then
+ match_req_fifo_cnt <= match_req_fifo_cnt + 1;
+ elsif(rq_fifo_write_sng = '0' and rq_fifo_read ='1') then
+ match_req_fifo_cnt <= match_req_fifo_cnt - 1;
+ end if;
+ end if;
+ end if;
+ end process p_reqFifo_cnt;
+
+ -- coutning fifo occupanccy (no usecnt provided) to indicate full to port when there
+ -- is still N (port number) free places in FIFO (this is in case all the ports make
+ -- request at the same time)
+ rq_fifo_almost_full <= '1' when (match_req_fifo_cnt > to_unsigned(g_match_req_fifo_size,c_match_req_fifo_size_width)) else '0';
+ rq_fifo_empty <= not rq_fifo_qvalid;
+ rq_fifo_full_for_ports <= rq_fifo_full or rq_fifo_almost_full;
+
+ ------------------------------------------------------------------------
+ -- RTU FAST MATCH
+ -- provides match :
+ -- * for special traffic
+ -- * based on VLANs and TRU (topology resolution: RSTP/MSTP/LACP)
+ -- * deterministic (N+5 cycles)
+ -- * forwarding decision when Full Match abandond when it takes too much time
+ ------------------------------------------------------------------------
+
+ U_Fast_match: rtu_fast_match
+ generic map(
+ g_num_ports => g_num_ports,
+ g_port_mask_bits => g_port_mask_bits
+ )
+ port map(
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ match_req_i => fast_match_req,
+ match_req_data_i => fast_match_req_data,
+ match_rsp_data_o => fast_match_rsp_data,
+ match_rsp_valid_o => fast_match_rsp_valid,
+ vtab_rd_addr_o => fast_match_vtab_addr,
+ vtab_rd_entry_i => vlan_tab_rd_entry4fast_match,
+ tru_req_o => tru_req_o,
+ tru_rsp_i => tru_resp_i,
+ tru_enabled_i => tru_enabled_i,
+ rtu_str_config_i => rtu_special_traffic_config,
+ rtu_pcr_pass_all_i => pcr_pass_all
+ );
+
+ --------------------------------------------------------------------------------------------
+ --| RTU FULL MATCH: Routing Table Unit Engine
+ --------------------------------------------------------------------------------------------
+ U_Full_Match : rtu_match
+ generic map (
+ g_num_ports => g_num_ports)
+ port map(
+
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ rq_fifo_read_o => rq_fifo_read,
+ rq_fifo_empty_i => rq_fifo_empty,
+ rq_fifo_input_i => rq_fifo_data,
+
+ rsp_fifo_write_o => rsp_valid,
+ rsp_fifo_full_i => '0', --rsp_fifo_full,
+ rsp_fifo_output_o => rsp_data,
+
+ htab_start_o => htab_start,
+ htab_ack_o => htab_ack,
+ htab_found_i => htab_found,
+ htab_hash_o => htab_hash,
+ htab_mac_o => htab_mac,
+ htab_fid_o => htab_fid,
+ htab_drdy_i => htab_drdy,
+ htab_entry_i => htab_entry,
+ htab_port_o => htab_port, -- ML (24/03/2013): aging bugfix
+ htab_src_dst_o => htab_src_dst, -- ML (24/03/2013): aging bugfix
+
+ rtu_ufifo_wr_req_o => regs_towb.ufifo_wr_req_i,
+ rtu_ufifo_wr_full_i => regs_fromwb.ufifo_wr_full_o,
+ rtu_ufifo_wr_empty_i => regs_fromwb.ufifo_wr_empty_o,
+ rtu_ufifo_dmac_lo_o => regs_towb.ufifo_dmac_lo_i,
+ rtu_ufifo_dmac_hi_o => regs_towb.ufifo_dmac_hi_i,
+ rtu_ufifo_smac_lo_o => regs_towb.ufifo_smac_lo_i,
+ rtu_ufifo_smac_hi_o => regs_towb.ufifo_smac_hi_i,
+ rtu_ufifo_vid_o => regs_towb.ufifo_vid_i,
+ rtu_ufifo_prio_o => regs_towb.ufifo_prio_i,
+ rtu_ufifo_pid_o => regs_towb.ufifo_pid_i,
+ rtu_ufifo_has_vid_o => regs_towb.ufifo_has_vid_i,
+ rtu_ufifo_has_prio_o => regs_towb.ufifo_has_prio_i,
+
+ rtu_aram_main_addr_o => aram_main_addr,
+ rtu_aram_main_data_i => aram_main_data_i,
+ rtu_aram_main_rd_o => aram_main_rd,
+ rtu_aram_main_data_o => aram_main_data_o,
+ rtu_aram_main_wr_o => aram_main_wr,
+
+ vlan_tab_addr_o => vlan_tab_rd_vid,
+ vlan_tab_entry_i => vlan_tab_rd_entry4match,
+
+ rtu_gcr_g_ena_i => regs_fromwb.gcr_g_ena_o,
+ rtu_pcr_pass_all_i => pcr_pass_all(g_num_ports - 1 downto 0),
+ rtu_pcr_learn_en_i => pcr_learn_en(g_num_ports - 1 downto 0),
+ rtu_pcr_pass_bpdu_i => pcr_pass_bpdu(g_num_ports - 1 downto 0),
+ rtu_pcr_b_unrec_i => pcr_b_unrec(g_num_ports - 1 downto 0),
+ rtu_b_unrec_fw_cpu_i => regs_fromwb.rx_ctr_urec_fw_cpu_ena_o,
+ rtu_cpu_mask_i => cpu_port_mask,
+ rtu_crc_poly_i => rtu_gcr_poly_used --x"1021"-- x"0589" -- x"8005" --x"1021" --x"8005", --
+-- rtu_rw_bank_i => s_vlan_bsel
+ );
+
+ rtu_gcr_poly_used <= c_default_hash_poly when (regs_fromwb.gcr_poly_val_o = x"0000") else regs_fromwb.gcr_poly_val_o;
+
+ mfifo_trigger <= regs_fromwb.gcr_mfifotrig_o and regs_fromwb.gcr_mfifotrig_load_o;
+
+ U_Lookup : rtu_lookup_engine
+ generic map (
+ g_num_ports => g_num_ports)
+ port map (
+ clk_sys_i => clk_sys_i,
+ clk_match_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+
+ mfifo_rd_req_o => regs_towb.mfifo_rd_req_i,
+ mfifo_rd_empty_i => regs_fromwb.mfifo_rd_empty_o,
+ mfifo_ad_sel_i => regs_fromwb.mfifo_ad_sel_o,
+ mfifo_ad_val_i => regs_fromwb.mfifo_ad_val_o,
+ mfifo_trigger_i => mfifo_trigger,
+ mfifo_busy_o => regs_towb.gcr_mfifotrig_i,
+
+ start_i => htab_start,
+ ack_i => htab_ack,
+ found_o => htab_found,
+ hash_i => htab_hash,
+ mac_i => htab_mac,
+ fid_i => htab_fid,
+ drdy_o => htab_drdy,
+ port_i => htab_port, -- ML (24/03/2013): aging bugfix
+ src_dst_i => htab_src_dst, -- ML (24/03/2013): aging bugfix
+ entry_o => htab_entry
+ );
+
+ --------------------------------------------------------------------------------------------
+ --| WISHBONE I/F: interface with CPU and RAM/CAM
+ --------------------------------------------------------------------------------------------
+-- U_WB_Slave : rtu_wishbone_slave_old
+ U_WB_Slave : rtu_wishbone_slave
+ port map(
+ rst_n_i => rst_n_i,
+ clk_sys_i => clk_sys_i,
+
+ wb_adr_i => wb_in.adr(8 downto 0),
+ wb_dat_i => wb_in.dat,
+ wb_dat_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
+ wb_int_o => wb_out.int,
+ wb_stall_o => open,
+ clk_match_i => clk_sys_i,
+ regs_o => regs_fromwb,
+ regs_i => regs_towb,
+ irq_nempty_i => irq_nempty, --'1',
+ rtu_aram_addr_i => aram_main_addr,
+ rtu_aram_data_o => aram_main_data_i,
+ rtu_aram_rd_i => aram_main_rd,
+ rtu_aram_data_i => aram_main_data_o,
+ rtu_aram_wr_i => aram_main_wr
+ );
+
+
+ current_pcr <= to_integer(unsigned(regs_fromwb.psr_port_sel_o));
+ regs_towb.psr_n_ports_i <= std_logic_vector(to_unsigned(g_num_ports, 8));
+
+ --------------------------------------------------------------------------------------------
+ --/ Her we interpret confiration registers (from CPU) provided by WB I/F
+ --------------------------------------------------------------------------------------------
+
+ -- indirectly addressed PCR registers - this is to allow easy generic-based
+ -- scaling of the number of ports
+ p_pcr_registers : process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if(rst_n_i = '0') then
+
+ regs_towb.pcr_learn_en_i <= '0';
+ regs_towb.pcr_pass_all_i <= '0';
+ regs_towb.pcr_pass_bpdu_i <= '0';
+ regs_towb.pcr_fix_prio_i <= '0';
+ regs_towb.pcr_prio_val_i <= (others => '0');
+ regs_towb.pcr_b_unrec_i <= '0';
+ pcr_learn_en <= (others => '0');
+ pcr_pass_all <= (others => '0');
+ pcr_pass_bpdu <= (others => '0');
+ pcr_fix_prio <= (others => '0');
+ pcr_prio_val <= (others => (others => '0'));
+ pcr_b_unrec <= (others => '0');
+
+ else
+
+ regs_towb.pcr_learn_en_i <= pcr_learn_en(current_pcr);
+ regs_towb.pcr_pass_all_i <= pcr_pass_all(current_pcr);
+ regs_towb.pcr_pass_bpdu_i <= pcr_pass_bpdu(current_pcr);
+ regs_towb.pcr_fix_prio_i <= pcr_fix_prio(current_pcr);
+ regs_towb.pcr_prio_val_i <= pcr_prio_val(current_pcr);
+ regs_towb.pcr_b_unrec_i <= pcr_b_unrec(current_pcr);
+
+ if(regs_fromwb.pcr_learn_en_load_o = '1') then
+ pcr_learn_en(current_pcr) <= regs_fromwb.pcr_learn_en_o;
+ pcr_pass_all(current_pcr) <= regs_fromwb.pcr_pass_all_o;
+ pcr_pass_bpdu(current_pcr) <= regs_fromwb.pcr_pass_bpdu_o;
+ pcr_fix_prio(current_pcr) <= regs_fromwb.pcr_fix_prio_o;
+ pcr_prio_val(current_pcr) <= regs_fromwb.pcr_prio_val_o;
+ pcr_b_unrec(current_pcr) <= regs_fromwb.pcr_b_unrec_o;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ irq_nempty <= regs_fromwb.ufifo_wr_empty_o;
+
+ current_mac_ID <= to_integer(unsigned(regs_fromwb.rx_ff_mac_r1_id_o));
+ current_MAC_entry <= regs_fromwb.rx_ff_mac_r1_hi_id_o & regs_fromwb.rx_ff_mac_r0_lo_o;
+ regs_towb.rx_ff_mac_r1_id_i <= std_logic_vector(to_unsigned(c_ff_single_macs_number, 8));
+ regs_towb.rx_ff_mac_r1_hi_id_i <= std_logic_vector(to_unsigned(c_ff_range_macs_number, 16));
+
+ regs_towb.gcr_rtu_version_i <= x"8";
+
+ -- RTU Extension index-access configration regiters for Fast Forward MACs
+ p_rx_registers : process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if(rst_n_i = '0') then
+ rtu_special_traffic_config.single_macs <= (others => std_logic_vector(to_unsigned(0, 48)));
+ rtu_special_traffic_config.single_macs_valid <= (others => '0');
+ rtu_special_traffic_config.macs_range_valid <= '0';
+ rtu_special_traffic_config.macs_range_up <= (others => '0');
+ rtu_special_traffic_config.macs_range_down <= (others => '0');
+ rtu_special_traffic_config.mirror_port_dst <= (others => '0');
+ rtu_special_traffic_config.mirror_port_src_rx <= (others => '0');
+ rtu_special_traffic_config.mirror_port_src_tx <= (others => '0');
+ else
+ -- output selected mirror mask
+ if(regs_fromwb.rx_mp_r0_dst_src_o = '0') then -- mirror destination mask
+ regs_towb.rx_mp_r1_mask_i <= rtu_special_traffic_config.mirror_port_dst;
+ else -- mirror source mask
+ if(regs_fromwb.rx_mp_r0_rx_tx_o = '0') then -- * rx
+ regs_towb.rx_mp_r1_mask_i <= rtu_special_traffic_config.mirror_port_src_rx;
+ else -- * tx
+ regs_towb.rx_mp_r1_mask_i <= rtu_special_traffic_config.mirror_port_src_tx;
+ end if;
+ end if;
+ -- register selected mirror mask
+ if(regs_fromwb.rx_mp_r1_mask_load_o = '1') then
+ if(regs_fromwb.rx_mp_r0_dst_src_o = '0') then -- mirror destination mask
+ rtu_special_traffic_config.mirror_port_dst <= regs_fromwb.rx_mp_r1_mask_o;
+ else -- mirror source mask
+ if(regs_fromwb.rx_mp_r0_rx_tx_o = '0') then -- * rx
+ rtu_special_traffic_config.mirror_port_src_rx <= regs_fromwb.rx_mp_r1_mask_o;
+ else -- * tx
+ rtu_special_traffic_config.mirror_port_src_tx <= regs_fromwb.rx_mp_r1_mask_o;
+ end if; -- rx_mp_r0_rx_tx_o
+ end if; -- rx_mp_r0_dst_src_o
+ end if; -- rx_mp_r1_mask_load_o
+
+ -- register selected Fast Forward MAC
+ if(regs_fromwb.rx_ff_mac_r1_hi_id_load_o = '1') then
+ if(regs_fromwb.rx_ff_mac_r1_type_o = '0') then-- TYPE: single MAC
+ rtu_special_traffic_config.single_macs(current_mac_ID) <= current_MAC_entry;
+ rtu_special_traffic_config.single_macs_valid(current_mac_ID) <= regs_fromwb.rx_ff_mac_r1_valid_o;
+ else -- TYPE: range MAC
+ if(regs_fromwb.rx_ff_mac_r1_id_o(7) = '0') then --lower range
+ rtu_special_traffic_config.macs_range_down <= current_MAC_entry;
+ else -- upper range
+ rtu_special_traffic_config.macs_range_up <= current_MAC_entry;
+ end if;
+ rtu_special_traffic_config.macs_range_valid <= regs_fromwb. rx_ff_mac_r1_valid_o;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ rtu_special_traffic_config.hp_prio <= regs_fromwb.rx_ctr_prio_mask_o;
+ rtu_special_traffic_config.cpu_forward_mask <= cpu_port_mask; --regs_fromwb.rx_llf_ff_mask_o;
+ rtu_special_traffic_config.dop_on_fmatch_full <= regs_fromwb.rx_ctr_at_fmatch_too_slow_o;
+ rtu_special_traffic_config.ff_mac_br_ena <= regs_fromwb.rx_ctr_ff_mac_br_o;
+ rtu_special_traffic_config.ff_mac_range_ena <= regs_fromwb.rx_ctr_ff_mac_range_o;
+ rtu_special_traffic_config.ff_mac_single_ena <= regs_fromwb.rx_ctr_ff_mac_single_o;
+ rtu_special_traffic_config.ff_mac_ll_ena <= regs_fromwb.rx_ctr_ff_mac_ll_o;
+ rtu_special_traffic_config.ff_mac_ptp_ena <= regs_fromwb.rx_ctr_ff_mac_ptp_o;
+ rtu_special_traffic_config.mr_ena <= regs_fromwb.rx_ctr_mr_ena_o;
+ rtu_special_traffic_config.hp_fw_cpu_ena <= regs_fromwb.rx_ctr_hp_fw_cpu_ena_o;
+ rtu_special_traffic_config.unrec_fw_cpu_ena <= regs_fromwb.rx_ctr_urec_fw_cpu_ena_o;
+ regs_towb.cpu_port_mask_i <= cpu_port_mask;
+ rtu_special_traffic_config.dbg_force_fast_match_only <= regs_fromwb.rx_ctr_force_fast_match_ena_o;
+ rtu_special_traffic_config.dbg_force_full_match_only <= regs_fromwb.rx_ctr_force_full_match_ena_o;
+ --------------------------------------------------------------------------------------------
+ --| VLAN memories
+ --| * one used by Full Match
+ --| * one used by Fast Match
+ --------------------------------------------------------------------------------------------
+ U_VLAN_Table_for_full_match : generic_dpram
+ generic map (
+ g_data_width => c_VLAN_TAB_ENTRY_WIDTH,
+ g_size => 4096,
+ g_with_byte_enable => false,
+ g_dual_clock => false)
+ port map (
+ rst_n_i => rst_n_i,
+
+ clka_i => clk_sys_i,
+ bwea_i => (others => '1'),
+ wea_i => regs_fromwb.vtr1_update_o,
+ aa_i => regs_fromwb.vtr1_vid_o,
+ da_i => vlan_tab_wr_data,
+ qa_o => open,
+
+ clkb_i => clk_sys_i, --'0',
+ bweb_i => (others => '1'),
+ web_i => '0',
+ ab_i => vlan_tab_rd_vid,
+ db_i => (others => '0'),
+ qb_o => vlan_tab_rd_data4match);
+
+ U_VLAN_Table_for_fast_match : generic_dpram
+ generic map (
+ g_data_width => c_VLAN_TAB_ENTRY_WIDTH,
+ g_size => 4096,
+ g_with_byte_enable => false,
+ g_dual_clock => false)
+ port map (
+ rst_n_i => rst_n_i,
+
+ clka_i => clk_sys_i,
+ bwea_i => (others => '1'),
+ wea_i => regs_fromwb.vtr1_update_o,
+ aa_i => regs_fromwb.vtr1_vid_o,
+ da_i => vlan_tab_wr_data,
+ qa_o => open,
+
+ clkb_i => clk_sys_i, --'0',
+ bweb_i => (others => '1'),
+ ab_i => fast_match_vtab_addr, -- address
+ db_i => (others => '0'),
+ qb_o => fast_match_vtab_data); -- data
+
+ vlan_tab_wr_data <= regs_fromwb.vtr2_port_mask_o
+ & regs_fromwb.vtr1_fid_o
+ & regs_fromwb.vtr1_drop_o
+ & regs_fromwb.vtr1_prio_override_o
+ & regs_fromwb.vtr1_prio_o
+ & regs_fromwb.vtr1_has_prio_o;
+
+ f_unpack6(vlan_tab_rd_data4match,
+ vlan_tab_rd_entry4match.port_mask,
+ vlan_tab_rd_entry4match.fid,
+ vlan_tab_rd_entry4match.drop,
+ vlan_tab_rd_entry4match.prio_override,
+ vlan_tab_rd_entry4match.prio,
+ vlan_tab_rd_entry4match.has_prio);
+
+ f_unpack6(fast_match_vtab_data,
+ vlan_tab_rd_entry4fast_match.port_mask,
+ vlan_tab_rd_entry4fast_match.fid,
+ vlan_tab_rd_entry4fast_match.drop,
+ vlan_tab_rd_entry4fast_match.prio_override,
+ vlan_tab_rd_entry4fast_match.prio,
+ vlan_tab_rd_entry4fast_match.has_prio);
+
+ events_gen: if(g_rmon_events_bits_pp = 9 ) generate
+ rmon_events_gen: for i in 0 to (g_num_ports - 1) generate
+ rmon_events_o((i+1)*g_rmon_events_bits_pp-1 downto i*g_rmon_events_bits_pp) <=
+ dbg_forwarded_to_port(i) & -- 8: forwarded to port
+ std_logic(rsp_valid and rsp_data(i)) & -- 7: FullMatch: resp valid
+ fast_match_rsp_valid(i) & -- 6: FastMatch: resp valid
+ std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.nf) & -- 5: FastMatch: non-forward (as config)
+ std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.ff) & -- 4: FastMatch: fast forward (as config)
+ std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.hp) & -- 3: FastMatch: high priority frames
+ std_logic(rsp(i).valid and rsp_ack_i(i) and rsp(i).drop ) & -- 2: dropped
+ std_logic(rsp(i).valid and rsp_ack_i(i) ) & -- 1: valid respons
+ std_logic(req_i(i).valid ) ; -- 0: valid request
+ end generate rmon_events_gen;
+ end generate events_gen;
+ no_events_gen: if(g_rmon_events_bits_pp /= 9 ) generate
+ rmon_events_o <= (others=>'0');
+ assert true report "g_rmon_events_bits_pp not equal to the defined number of RMON event ";
+ end generate no_events_gen;
+
+ fw_gen : for i in 0 to (g_num_ports - 1) generate
+ egress_port_p: process(rsp, rsp_ack_i)
+ variable fw : std_logic;
+ begin
+ fw := '0';
+ L0: for j in 0 to (g_num_ports -1) loop
+ fw := fw or (rsp(j).valid and rsp(j).port_mask(i) and rsp_ack_i(j) and not rsp(j).drop);
+ end loop;
+ dbg_forwarded_to_port(i) <= fw;
+ end process;
+ end generate fw_gen;
+
+-- CS_ICON : chipscope_icon
+-- port map (
+-- CONTROL0 => CONTROL0);
+-- CS_ILA : chipscope_ila
+-- port map (
+-- CONTROL => CONTROL0,
+-- CLK => clk_sys_i,
+-- TRIG0 => TRIG0,
+-- TRIG1 => TRIG1,
+-- TRIG2 => TRIG2,
+-- TRIG3 => TRIG3);
+--
+-- RAM
+-- TRIG0(11 downto 0) <= regs_fromwb.vtr1_vid_o;
+-- TRIG0(23 downto 12) <= fast_match_vtab_addr;
+-- TRIG0( 24) <= regs_fromwb.vtr1_update_o;
+--
+-- TRIG1(31 downto 0) <= vlan_tab_wr_data(31 downto 0);
+-- TRIG2(13 downto 0) <= vlan_tab_wr_data(45 downto 32);
+-- TRIG2(27 downto 14) <= fast_match_vtab_data(45 downto 32);
+-- TRIG3(31 downto 0) <= fast_match_vtab_data(31 downto 0);
+
+----------------------- port ----------------------
+-- TRIG0(31 downto 0) <= fast_match_req_data(0).smac(31 downto 0);
+--
+-- TRIG1(11 downto 0) <= fast_match_req_data(0).vid;
+-- TRIG1(14 downto 12) <= fast_match_req_data(0).prio;
+-- TRIG1( 15) <= fast_match_req_data(0).valid;
+-- TRIG1( 16) <= fast_match_req_data(0).has_vid;
+-- TRIG1( 17) <= fast_match_req_data(0).has_prio;
+-- TRIG1( 18) <= fast_match_req(0);
+--
+-- TRIG1( 19) <= fast_match_rsp_valid(0);
+-- TRIG1( 20) <= fast_match_rsp_data(0).valid;
+-- TRIG1(23 downto 21) <= fast_match_rsp_data(0).prio;
+-- TRIG1(31 downto 24) <= fast_match_rsp_data(0).port_mask(7 downto 0);
+--
+-- TRIG2(31 downto 0) <= fast_match_req_data(2).smac(31 downto 0);
+--
+-- TRIG3(11 downto 0) <= fast_match_req_data(2).vid;
+-- TRIG3(14 downto 12) <= fast_match_req_data(2).prio;
+-- TRIG3( 15) <= fast_match_req_data(2).valid;
+-- TRIG3( 16) <= fast_match_req_data(2).has_vid;
+-- TRIG3( 17) <= fast_match_req_data(2).has_prio;
+-- TRIG3( 18) <= fast_match_req(2);
+--
+-- TRIG3( 19) <= fast_match_rsp_valid(2);
+-- TRIG3( 20) <= fast_match_rsp_data(2).valid;
+-- TRIG3(23 downto 21) <= fast_match_rsp_data(2).prio;
+-- TRIG3(31 downto 24) <= fast_match_rsp_data(2).port_mask(7 downto 0);
+
+
+end behavioral;
diff --git a/modules/wrsw_shared_types_pkg.vhd b/modules/wrsw_shared_types_pkg.vhd
index 9a2eece76888bb88d592f2938f753caeb77788ee..2f6bd530961428aec0e07f5dc6f5ebd43d4a25ca 100644
--- a/modules/wrsw_shared_types_pkg.vhd
+++ b/modules/wrsw_shared_types_pkg.vhd
@@ -4,6 +4,7 @@ use ieee.STD_LOGIC_1164.all;
package wrsw_shared_types_pkg is
constant c_RTU_MAX_PORTS : integer := 32;
+ constant c_SWC_MAX_PORTS : integer := c_RTU_MAX_PORTS+1;
type t_rtu_request is record
valid : std_logic;
@@ -20,9 +21,99 @@ package wrsw_shared_types_pkg is
port_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
prio : std_logic_vector(2 downto 0);
drop : std_logic;
+ hp : std_logic;
end record;
type t_rtu_request_array is array(integer range <>) of t_rtu_request;
type t_rtu_response_array is array(integer range <>) of t_rtu_response;
+ type t_tru_request is record
+ valid : std_logic;
+ smac : std_logic_vector(47 downto 0);
+ dmac : std_logic_vector(47 downto 0);
+ fid : std_logic_vector(7 downto 0);
+ isHP : std_logic; -- high priority packet flag
+ isBR : std_logic; -- broadcast packet flag
+ reqMask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0); -- mask indicating requesting port
+ prio : std_logic_vector(2 downto 0); -- more for testing then to be used
+ end record;
+
+ type t_tru_response is record
+ valid : std_logic;
+ port_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0); -- mask with 1's at forward ports
+ drop : std_logic;
+ respMask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0); -- mask with 1 at requesting port
+ end record;
+
+ constant c_tru_response_zero : t_tru_response := (
+ valid => '0',
+ port_mask => (others => '0'),
+ drop => '0',
+ respMask => (others => '0'));
+
+ type t_tru_request_array is array(integer range <>) of t_tru_request;
+ type t_tru_response_array is array(integer range <>) of t_tru_response;
+
+-- type t_tru2ep is record
+-- -- ctrlWr : std_logic;
+-- --frmae generation
+-- tx_pck : std_logic; -- to be changed
+-- tx_pck_class : std_logic_vector(7 downto 0); -- to be changed
+-- -- pause generation
+-- -- pauseSend : std_logic;
+-- -- pauseTime : std_logic_vector(15 downto 0);
+-- outQueueBlockMask : std_logic_vector(7 downto 0);
+-- -- new stuff
+-- link_kill : std_logic; --ok
+-- fc_pause_req : std_logic; --ok
+-- fc_pause_delay : std_logic_vector(15 downto 0); --ok
+-- inject_req : std_logic;
+-- inject_packet_sel : std_logic_vector(2 downto 0) ;
+-- inject_user_value : std_logic_vector(15 downto 0) ;
+-- end record;
+--
+-- type t_ep2tru is record
+-- status : std_logic;
+-- -- ctrlRd : std_logic;
+-- -- frame detectin
+-- rx_pck : std_logic; -- in Endpoint this is : pfilter_done_i
+-- rx_pck_class : std_logic_vector(7 downto 0); -- in Endpoint this is :pfilter_pclass_i
+-- -- new stuff
+-- fc_pause_ready : std_logic;
+-- inject_ready : std_logic;
+-- pfilter_pclass_o : std_logic_vector(7 downto 0);
+-- pfilter_drop_o : std_logic;
+-- pfilter_done_o : std_logic;
+-- end record;
+--
+-- type t_tru2ep_array is array(integer range <>) of t_tru2ep;
+-- type t_ep2tru_array is array(integer range <>) of t_ep2tru;
+
+ type t_rtu_prio_array is array(integer range <>) of std_logic_vector(2 downto 0);
+
+ type t_rtu2tru is record -- single port
+ pass_all : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ forward_bpdu_only: std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ request_valid : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+-- priorities : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ priorities : t_rtu_prio_array(c_RTU_MAX_PORTS-1 downto 0);
+ has_prio : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ end record;
+
+ type t_pause_request is record
+ req : std_logic;
+ quanta : std_logic_vector(15 downto 0);
+ classes : std_logic_vector(7 downto 0); -- '1' for the classes which shall be PAUSED
+ end record;
+
+ type t_global_pause_request is record
+ req : std_logic;
+ quanta : std_logic_vector(15 downto 0);
+ classes : std_logic_vector(7 downto 0); -- '1' for the classes which shall be PAUSED
+ ports : std_logic_vector(c_SWC_MAX_PORTS-1 downto 0);
+ end record;
+
+ type t_pause_request_array is array(integer range <>) of t_pause_request;
+ type t_global_pause_request_array is array(integer range <>) of t_global_pause_request;
+
end wrsw_shared_types_pkg;
diff --git a/modules/wrsw_swcore/Manifest.py b/modules/wrsw_swcore/Manifest.py
index 3ad1187b8029f4801aa7fc0a1f5831ae47a26a9a..a34e877c231aece2c86ffdfc9028b71a46b43fde 100644
--- a/modules/wrsw_swcore/Manifest.py
+++ b/modules/wrsw_swcore/Manifest.py
@@ -11,12 +11,20 @@ files = [
"swc_core.vhd",
"swc_multiport_linked_list.vhd",
+"optimized_new_allocator/swc_multiport_page_allocator.vhd",
+"optimized_new_allocator/swc_page_alloc_ram_bug.vhd",
+#"optimized_new_allocator/swc_page_alloc.vhd",
+
+# new by TOM
#"new_allocator/swc_multiport_page_allocator.vhd",
#"new_allocator/swc_page_alloc_ram_bug.vhd",
+#"new_allocator/swc_page_alloc.vhd",
+# working
+#"old_allocator/swc_multiport_page_allocator.vhd",
+#"old_allocator/swc_page_alloc_old.vhd",
-"old_allocator/swc_multiport_page_allocator.vhd",
-"old_allocator/swc_page_alloc_old.vhd",
+"swc_alloc_resource_manager.vhd",
#"swc_multiport_page_allocator.vhd",
#"swc_page_alloc_old.vhd",
@@ -33,14 +41,20 @@ files = [
"swc_pck_transfer_input.vhd",
"swc_pck_transfer_output.vhd",
"swc_prio_encoder.vhd",
+"swc_output_queue_scheduler.vhd",
"swc_rr_arbiter.vhd",
"xswc_core.vhd",
"xswc_output_block.vhd",
+"xswc_output_block_new.vhd",
"xswc_input_block.vhd",
"../wrsw_shared_types_pkg.vhd",
"swc_ll_read_data_validation.vhd",
"swc_swcore_pkg.vhd",
-"ram_bug/swc_rd_wr_ram.vhd"];
+"ram_bug/swc_rd_wr_ram.vhd",
+
+"swc_output_traffic_shaper.vhd"
+
+];
#"buggy_ram.vhd",
#"buggy_ram.ngc"]
diff --git a/modules/wrsw_swcore/mpm/mpm_read_path.vhd b/modules/wrsw_swcore/mpm/mpm_read_path.vhd
index 472b0eca80e3e502c0eae80e7aa5d03c358369b6..b2edc49f264d7dfe7a32c845c23231efca3c9e3a 100644
--- a/modules/wrsw_swcore/mpm/mpm_read_path.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_read_path.vhd
@@ -177,7 +177,7 @@ architecture rtl of mpm_read_path is
type t_rport_core_state_array is array(integer range <>) of t_rport_core_state;
type t_rport_io_state_array is array(integer range <>) of t_rport_io_state;
- signal mem_req, mem_grant : std_logic_vector(g_num_ports-1 downto 0);
+ signal mem_req, mem_grant, mem_grant_sreg : std_logic_vector(g_num_ports-1 downto 0);
signal ll_req, ll_grant : std_logic_vector(g_num_ports-1 downto 0);
signal io : t_rport_io_state_array(g_num_ports-1 downto 0);
@@ -191,9 +191,28 @@ architecture rtl of mpm_read_path is
signal fbm_data_reg : std_logic_vector(c_fbm_data_width-1 downto 0);
signal muxed : std_logic_vector(g_page_addr_width-1 downto 0);
-
+
+ -- ML: signals to implement hack-ish abort by reseting read_path
+ -- * shorter reset signal for FIFOS
+ -- * longer reset signal for logic (i.e. U_Core_Block)
+ -- * abort which is prolonged, used as reset and connected to flush in U_IO_Block
+ signal fifos_rst_n_core : std_logic_vector (g_num_ports-1 downto 0); -- ML-added
+ signal logic_rst_n_core : std_logic_vector (g_num_ports-1 downto 0); -- ML-added
+ signal rport_abort_d : std_logic_vector (g_num_ports-1 downto 0); -- ML-added
begin -- rtl
+ --ML: process to register abort (produce resets of differnt width)
+ p_abort_reset : process(clk_io_i)
+ begin
+ if rising_edge(clk_io_i) then
+ if(rst_n_io_i = '0') then
+ rport_abort_d <= (others =>'0');
+ else
+ rport_abort_d <= rport_abort_i;
+ end if;
+ end if;
+ end process;
+
-- I/O structure serialization/deserialization
gen_serialize_ios : for i in 0 to g_num_ports-1 generate
@@ -215,27 +234,43 @@ begin -- rtl
end generate gen_serialize_ios;
-
-- The actual round-robin arbiter for muxing memory accesses.
- --p_mem_arbiter : process(clk_core_i)
- --begin
- -- if rising_edge(clk_core_i) then
- -- if rst_n_core_i = '0' then
- -- mem_grant <= (others => '0');
- -- else
- -- f_rr_arbitrate(mem_req, mem_grant, mem_grant);
- -- end if;
- -- end if;
- --end process;
-
- U_Mem_Arbiter: gc_rr_arbiter
- generic map (
- g_size => g_num_ports)
- port map (
- clk_i => clk_core_i,
- rst_n_i => rst_n_core_i,
- req_i => mem_req,
- grant_o => mem_grant);
+-- p_mem_arbiter : process(clk_core_i)
+-- begin
+-- if rising_edge(clk_core_i) then
+-- if rst_n_core_i = '0' then
+-- mem_grant <= (others => '0');
+-- else
+-- f_rr_arbitrate(mem_req, mem_grant, mem_grant);
+-- end if;
+-- end if;
+-- end process;
+
+-- U_Mem_Arbiter: gc_rr_arbiter
+-- generic map (
+-- g_size => g_num_ports)
+-- port map (
+-- clk_i => clk_core_i,
+-- rst_n_i => rst_n_core_i,
+-- req_i => mem_req,
+-- grant_o => mem_grant);
+
+
+ p_mem_arbiter : process(clk_core_i)
+ begin
+ if rising_edge(clk_core_i) then
+ if rst_n_core_i = '0' then
+ mem_grant <= (others => '0');
+ mem_grant_sreg(g_num_ports-1 downto 1) <= (others => '0');
+ mem_grant_sreg(0) <= '1';
+ else
+ -- spartan arbieter
+ mem_grant_sreg <= mem_grant_sreg(g_num_ports-2 downto 0) & mem_grant_sreg(g_num_ports-1); -- shift
+ mem_grant <= mem_grant_sreg and mem_req;
+ end if;
+ end if;
+ end process;
+
gen_mux_inputs : for i in 0 to g_num_ports-1 generate
rd_mux_a_in(c_fbm_addr_width * (i + 1) - 1 downto c_fbm_addr_width * i) <= core(i).fbm_addr;
@@ -267,7 +302,7 @@ begin -- rtl
g_width => c_line_size_width + c_fbm_addr_width,
g_size => 8)
port map (
- rst_n_a_i => rst_n_core_i,
+ rst_n_a_i => fifos_rst_n_core(i), --ML: abort by reset --rst_n_core_i,
clk_wr_i => clk_io_i,
clk_rd_i => clk_core_i,
we_i => io(i).pf_we,
@@ -284,7 +319,7 @@ begin -- rtl
g_size => g_fifo_size,
g_sideband_width => 0)
port map (
- rst_n_a_i => rst_n_core_i,
+ rst_n_a_i => fifos_rst_n_core(i), -- ML: abort by reset
clk_wr_i => clk_core_i,
clk_rd_i => clk_io_i,
we_i => core(i).df_we,
@@ -296,20 +331,31 @@ begin -- rtl
full_o => core(i).df_full,
empty_o => io(i).df_empty);
+ -- ML: producing reset triggerd by abort
+ -- both rst_n signals are used in mpm_async*fifo, inside this modules resets are asynch
+ -- (this is why we can use io_reset and io_signal)
+ p_reg_anded_reset: process(clk_io_i)
+ begin
+ if rising_edge(clk_io_i) then
+ fifos_rst_n_core(i) <= rst_n_io_i and (not rport_abort_i(i));
+ logic_rst_n_core(i) <= rst_n_io_i and (not rport_abort_i(i)) and (not rport_abort_d(i));
+ end if;
+ end process;
+-- fifos_rst_n_core(i) <= rst_n_core_i and (not rport_abort_i(i));
+-- logic_rst_n_core(i) <= rst_n_core_i and (not rport_abort_i(i)) and (not rport_abort_d(i));
end generate gen_fifos;
-
--- The arbiter for accessing the linked list
- --p_ll_arbiter : process(clk_io_i)
- --begin
- -- if rising_edge(clk_io_i) then
- -- if rst_n_io_i = '0' then
- -- ll_grant <= (others => '0');
- -- else
- -- f_rr_arbitrate(ll_req, ll_grant, ll_grant);
- -- end if;
- -- end if;
- --end process;
+ --The arbiter for accessing the linked list
+-- p_ll_arbiter : process(clk_io_i)
+-- begin
+-- if rising_edge(clk_io_i) then
+-- if rst_n_io_i = '0' then
+-- ll_grant <= (others => '0');
+-- else
+-- f_rr_arbitrate(ll_req, ll_grant, ll_grant);
+-- end if;
+-- end if;
+-- end process;
gen_ll_access_arbiter : for i in 0 to g_num_ports-1 generate
ll_req(i) <= io(i).ll_req ; --and not io(i).ll_grant;
@@ -342,10 +388,8 @@ begin -- rtl
end if;
end process;
-
gen_io_core_blocks : for i in 0 to g_num_ports-1 generate
-
U_Core_Block: mpm_rpath_core_block
generic map (
g_num_pages => g_num_pages,
@@ -354,8 +398,8 @@ begin -- rtl
g_page_size => g_page_size,
g_ratio => g_ratio)
port map (
- clk_core_i => clk_core_i,
- rst_n_core_i => rst_n_core_i,
+ clk_core_i => clk_core_i,
+ rst_n_core_i => logic_rst_n_core(i), --ML: abort by reset --rst_n_core_i,
fbm_req_o => mem_req(i),
fbm_grant_i => mem_grant(i),
fbm_addr_o => core(i).fbm_addr,
@@ -407,5 +451,4 @@ begin -- rtl
core(i).pf_pg_lines <= core(i).pf_q(c_fbm_addr_width + c_line_size_width-1 downto c_fbm_addr_width);
end generate gen_io_core_blocks;
-
end rtl;
diff --git a/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd b/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
index f275d0e965142d1f9cefe19f5b039c31e18badf9..dc12148879e4eaaab1054603388d9255f5363cb6 100644
--- a/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
@@ -115,7 +115,7 @@ architecture behavioral of mpm_rpath_io_block is
-- Page fetcher signals
- type t_page_fetch_state is (FIRST_PAGE, NEXT_LINK, WAIT_LAST_ACK, WAIT_ACK);
+ type t_page_fetch_state is (FIRST_PAGE, NEXT_LINK, WAIT_LAST_ACK, WAIT_ACK, NASTY_WAIT);
signal page_state : t_page_fetch_state;
signal cur_page : std_logic_vector(g_page_addr_width-1 downto 0);
signal cur_ll : t_ll_entry;
@@ -144,15 +144,14 @@ architecture behavioral of mpm_rpath_io_block is
-- next packet.
signal fetch_abort : std_logic;
-
-
--- Datapath signals
+ -- Datapath signals
signal df_we_d0 : std_logic;
signal last_page : std_logic;
signal words_total : unsigned(c_word_count_width-1 downto 0);
+ signal dsel_words_total : unsigned(c_word_count_width-1 downto 0);
signal words_xmitted : unsigned(c_word_count_width-1 downto 0);
- signal last_int, d_valid_int, df_rd_int : std_logic;
+ signal last_int, d_valid_int, df_rd_int : std_logic; --dsel--
signal pf_we_int : std_logic;
signal ll_req_int, ll_grant_d0, ll_grant_d1 : std_logic;
@@ -166,17 +165,54 @@ architecture behavioral of mpm_rpath_io_block is
signal min_pck_size_reached : std_logic;
signal d_counter_equal : std_logic;
+ signal pre_fetch : std_logic;
+ signal supress_pre_fetch : std_logic;
+
+ -- indicates the count (word number) from which the last page starts,
+ -- this is to activate output req_page signal only on last page
+ signal last_pg_start_ptr : unsigned(c_word_count_width-1 downto 0);
+ signal allow_rport_pg_req : std_logic;
+
+ -- signals to make the abort
+ signal abort_wait_cnt : unsigned(4 downto 0);
+ signal rport_abort_d : std_logic;
+ signal long_rst_at_abort : std_logic;
+
+ constant wait_at_abort : integer := 3; -- keeps the long_rst_at_abort HIGH for
+ -- (2 + wait_at_abort) cycles
+ -- the number (2) was derived experimentally (lowest
+ -- working)
begin -- behavioral
-
-
-
- fetch_abort <= '0'; -- FIXME: add support for ABORT
+ -- process to generate long abort signal. it is needed to make sure
+ -- that all the other parts of MPM's read_path reset and clear properly
+ --
+ p_gen_abort_d : process(clk_io_i)
+ begin
+ if rising_edge(clk_io_i) then
+ if rst_n_io_i = '0' then
+ rport_abort_d <= '0';
+ abort_wait_cnt<= (others =>'0');
+ else
+ if(rport_abort_i = '1') then
+ rport_abort_d <= '1';
+ abort_wait_cnt <= to_unsigned(wait_at_abort, abort_wait_cnt'length);
+ elsif(abort_wait_cnt = to_unsigned(0, abort_wait_cnt'length)) then
+ rport_abort_d <= '0';
+ else
+ abort_wait_cnt <= abort_wait_cnt - 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- this signal resets all the process (async) on abort
+ long_rst_at_abort <= '1' when (rport_abort_i = '1' or rport_abort_d ='1') else '0';
p_gen_page_ack : process(clk_io_i)
begin
if rising_edge(clk_io_i) then
- if rst_n_io_i = '0' then
+ if rst_n_io_i = '0' or long_rst_at_abort = '1' then
fetch_ack <= '0';
else
fetch_ack <= pf_we_int;
@@ -193,43 +229,49 @@ begin -- behavioral
-- when dvalid=LOW and not yet the last word)
--counters_equal <= '1' when (words_total = words_xmitted) else '0';
counters_equal <= '1' when (words_total = words_xmitted and rport_dreq_i = '1') else '0';
- -- ML
wait_next_valid_ll_read <= '1' when ((words_total < words_xmitted+2) and
last_int = '0' and
page_state /= FIRST_PAGE and
+ pre_fetch = '0' and
fetch_first = '0' ) else '0';
min_pck_size_reached <= '0' when (start_cnt < to_unsigned(g_min_packet_size, start_cnt'length ) ) else '1';
-
p_count_words : process(clk_io_i)
begin
if rising_edge(clk_io_i) then
- if rst_n_io_i = '0' or (last_int = '1' and d_valid_int = '1') then
- words_total <= (others => '0');
+ if rst_n_io_i = '0' or (last_int = '1' and d_valid_int = '1')
+ or long_rst_at_abort = '1' then -- ML: abort by reset
+ -- ML : pre-fetching
+ if(pre_fetch = '1') then
+ words_total <= resize(fetch_pg_words, words_total'length);
+ else
+ words_total <= (others => '0');
+ end if;
+ -----
words_xmitted <= to_unsigned(1, words_xmitted'length);
-- ML
-- last_int <= '0';
d_counter_equal <= '0';
else
-
if(df_rd_int = '1') then
words_xmitted <= words_xmitted + 1;
end if;
- if(fetch_ack = '1') then
- -- if(fetch_first = '1') then
- -- words_total <= resize(fetch_pg_words, words_total'length);
- -- else
+ if(fetch_ack = '1' and pre_fetch = '0') then
+ --if(fetch_valid = '1') then
+ --if(fetch_first = '1') then -- ML : prefetching
+ if(fetch_first = '1' ) then
+ words_total <= resize(fetch_pg_words, words_total'length);
+ else
words_total <= words_total + fetch_pg_words;
- -- end if;
+ end if;
end if;
-- ML:
-- last_int <= counters_equal;
d_counter_equal <= counters_equal;
- ---------
-
+ ---------
end if;
end if;
end process;
@@ -245,7 +287,7 @@ begin -- behavioral
p_gen_d_valid : process(clk_io_i)
begin
if rising_edge(clk_io_i) then
- if rst_n_io_i = '0' then
+ if rst_n_io_i = '0' or long_rst_at_abort = '1' then -- ML: abort by reset
d_valid_int <= '0';
else
@@ -255,13 +297,37 @@ begin -- behavioral
end if;
end process;
- df_flush_o <= last_int;-- counters_equal;
+ p_gen_pre_fetch : process(clk_io_i)
+ begin
+ if rising_edge(clk_io_i) then
+ if rst_n_io_i = '0' or long_rst_at_abort = '1' then -- ML: abort by reset
+ pre_fetch <= '0';
+ supress_pre_fetch <= '0';
+ else
+
+ if(fetch_last = '1' and rport_pg_valid_i = '1' and last_int = '0' and supress_pre_fetch = '0') then
+ pre_fetch <= '1';
+ elsif(pre_fetch='1' and last_int = '1') then
+ pre_fetch <= '0';
+ end if;
+
+ if(page_state = FIRST_PAGE and last_int = '1' and pre_fetch = '0' and rport_pg_valid_i = '0') then
+ supress_pre_fetch <= '1';
+ elsif(rport_pg_valid_i = '1') then
+ supress_pre_fetch <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+ df_flush_o <= last_int or long_rst_at_abort;-- counters_equal;
rport_dvalid_o <= d_valid_int;
rport_dlast_o <= last_int;
rport_d_o <= df_d_i;
- rport_dsel_o <= (others => '1');
+ rport_dsel_o <= (others =>'1'); --dsel--
rport_pg_req_o <= rport_pg_req;
-------------------------------------------------------------------------------
-- Page fetcher logic
@@ -275,13 +341,13 @@ begin -- behavioral
cur_ll.valid <= ll_data_i(g_ll_data_width-1);
-- 1: number of the words in page (1 = 1 word .. g_page_size-1 = full page)
cur_ll.size <= ll_data_i(c_page_size_width-1 downto 0);
-
+
fetch_valid <= fvalid_int and not fetch_ack;
p_count_down_start : process(clk_io_i)
begin
if rising_edge(clk_io_i) then
- if rst_n_io_i = '0' or rport_pg_req = '1' then
+ if rst_n_io_i = '0' or rport_pg_req = '1' or long_rst_at_abort = '1' then -- ML: abort by reset
start_cnt <= to_unsigned(0, start_cnt'length);
else
if(fetch_first = '1' ) then
@@ -290,11 +356,27 @@ begin -- behavioral
end if;
end if;
end process;
+
+-- p_delay_pg_req : process(clk_io_i)
+-- begin
+-- if rising_edge(clk_io_i) then
+-- if rst_n_io_i = '0' then
+-- allow_rport_pg_req <= '0';
+-- else
+-- if(words_xmitted >= last_pg_start_ptr ) then
+-- allow_rport_pg_req <='1';
+-- elsif(page_state = NEXT_LINK ) then
+-- allow_rport_pg_req <='0';
+-- end if;
+--
+-- end if;
+-- end if;
+-- end process;
p_page_fsm : process(clk_io_i)
begin
if rising_edge(clk_io_i) then
- if rst_n_io_i = '0' then
+ if rst_n_io_i = '0' or long_rst_at_abort = '1' then -- ML: abort by reset
page_state <= FIRST_PAGE;
fvalid_int <= '0';
@@ -304,6 +386,8 @@ begin -- behavioral
ll_grant_d1 <= '0';
wait_first_fetched <='1';
fetch_first <= '0';
+ last_pg_start_ptr <= (others => '0');
+ fetch_last <= '0';
else
ll_grant_d0 <= ll_grant_i;
@@ -311,7 +395,7 @@ begin -- behavioral
if((cur_ll.valid = '1' or min_pck_size_reached = '1' or page_state = WAIT_ACK or page_state = WAIT_LAST_ACK) and fetch_first = '1') then
wait_first_fetched <='0';
- elsif(fetch_first = '1' and (df_empty_i = '0' or min_pck_size_reached = '0')) then
+ elsif(fetch_first = '1' and (df_empty_i = '0' or min_pck_size_reached = '0') and pre_fetch = '0') then
wait_first_fetched <='1';
end if;
@@ -327,7 +411,10 @@ begin -- behavioral
ll_addr_o <= rport_pg_addr_i;
page_state <= NEXT_LINK;
fetch_first <= '1';
- else
+-- ML: start pre-fetching well in advance even if the payload is more-or-less equal to
+-- page-size-multiple (always starts in the middle of pre-last page)
+ elsif(words_xmitted + to_unsigned(g_page_size/2, words_total'length) >= last_pg_start_ptr and
+ pre_fetch = '0' ) then --ML not to start prefatching next page one already done so
rport_pg_req <= '1';
end if;
@@ -335,10 +422,7 @@ begin -- behavioral
-- current page
when NEXT_LINK =>
- if(fetch_abort = '1') then
- page_state <= FIRST_PAGE;
- ll_req_int <= '0';
- elsif(ll_grant_d1 = '1' and cur_ll.valid = '1') then
+ if(ll_grant_d1 = '1' and cur_ll.valid = '1') then
cur_page <= cur_ll.next_page;
ll_addr_o <= cur_ll.next_page;
@@ -349,7 +433,18 @@ begin -- behavioral
fetch_pg_addr <= cur_page;
fvalid_int <= '1';
fetch_last <= '1';
+
+ -- remember the total up to before the last page starts
+ if(fetch_first = '1') then -- this is first and last page
+ last_pg_start_ptr <= resize(unsigned(cur_ll.size), words_total'length );
+ else
+ last_pg_start_ptr <= words_total;
+ end if;
+
else
+
+ last_pg_start_ptr <= (others =>'0');
+
page_state <= WAIT_ACK;
fetch_pg_words <= to_unsigned(g_page_size, fetch_pg_words'length);
@@ -357,7 +452,11 @@ begin -- behavioral
fetch_pg_addr <= cur_page;
fetch_pg_addr <= cur_page;
fvalid_int <= '1';
- fetch_last <= '0';
+ if(fetch_first = '1') then -- prefetching conditin
+ fetch_last <= '1';
+ else -- normal condition
+ fetch_last <= '0';
+ end if;
end if;
ll_req_int <= '0';
else
@@ -365,24 +464,35 @@ begin -- behavioral
end if;
when WAIT_ACK =>
- if(fetch_abort = '1') then
- page_state <= FIRST_PAGE;
- elsif(fetch_ack = '1') then
- ll_req_int <= '1';
+ if(fetch_ack = '1') then
+ --ll_req_int <= '1';
fetch_first <= '0';
fvalid_int <= '0';
-
-
- page_state <= NEXT_LINK;
+ if(pre_fetch = '1' and last_int = '0') then
+ ll_req_int <= '0';
+ page_state <= NASTY_WAIT;
+ else
+ ll_req_int <= '1';
+ page_state <= NEXT_LINK;
+ end if;
end if;
when WAIT_LAST_ACK =>
if(fetch_ack = '1') then
- rport_pg_req <= '1';
+-- if(words_xmitted >= last_pg_start_ptr) then -- ML: to delay req -- only during last page
+-- rport_pg_req <= '1';
+-- else
+-- rport_pg_req <= '0';
+-- end if;
+
fetch_first <= '0';
fvalid_int <= '0';
page_state <= FIRST_PAGE;
end if;
+ when NASTY_WAIT =>
+ if(last_int = '1') then
+ page_state <= NEXT_LINK;
+ end if;
end case;
end if;
@@ -390,6 +500,5 @@ begin -- behavioral
end process;
ll_req_o <= ll_req_int and not (ll_grant_i or ll_grant_d0 or ll_grant_d1);
-
end behavioral;
diff --git a/modules/wrsw_swcore/mpm/mpm_top.vhd b/modules/wrsw_swcore/mpm/mpm_top.vhd
index 9336b200e589e4da252392f50704c9b8febbdf5d..82f0c528e7f804e7e601813d91d96d23fae39b37 100644
--- a/modules/wrsw_swcore/mpm/mpm_top.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_top.vhd
@@ -131,11 +131,19 @@ begin -- rtl
port map (
clk_i => clk_core_i,
rst_n_i => '1',
+-- data_i => rst_n_io, --rst_n_i,
data_i => rst_n_i,
synced_o => rst_n_core);
rst_n_io <= rst_n_i;
+-- p_sync_res: process(clk_io_i)
+-- begin
+-- if rising_edge(clk_io_i) then
+-- rst_n_io <= rst_n_i;
+-- end if;
+-- end process;
+
U_Write_Path : mpm_write_path
generic map (
g_data_width => g_data_width,
diff --git a/modules/wrsw_swcore/mpm/mpm_write_path.vhd b/modules/wrsw_swcore/mpm/mpm_write_path.vhd
index d1e2b87a9378ef3a1625b1a16714513e4f9c4cf2..7642d1cbe2ece62819546c88bb46ec6f6e4a27da 100644
--- a/modules/wrsw_swcore/mpm/mpm_write_path.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_write_path.vhd
@@ -135,7 +135,7 @@ architecture rtl of mpm_write_path is
signal wport : t_mpm_write_port_array(g_num_ports-1 downto 0);
- signal arb_req, arb_grant : std_logic_vector(g_num_ports-1 downto 0);
+ signal arb_req, arb_grant, arb_grant_sreg : std_logic_vector(g_num_ports-1 downto 0);
signal wr_mux_a_in : std_logic_vector(g_num_ports * c_fbm_addr_width -1 downto 0);
signal wr_mux_d_in : std_logic_vector(g_num_ports * c_fbm_data_width -1 downto 0);
@@ -188,27 +188,43 @@ begin -- rtl
end generate gen_input_arbiter_ios;
- U_RR_Arbiter: gc_rr_arbiter
- generic map (
- g_size => g_num_ports)
- port map (
- clk_i => clk_core_i,
- rst_n_i => rst_n_core_i,
- req_i => arb_req,
- grant_o => arb_grant);
+-- U_RR_Arbiter: gc_rr_arbiter
+-- generic map (
+-- g_size => g_num_ports)
+-- port map (
+-- clk_i => clk_core_i,
+-- rst_n_i => rst_n_core_i,
+-- req_i => arb_req,
+-- grant_o => arb_grant);
+--
+ -- The actual round-robin arbiter.
+-- p_input_arbiter : process(clk_core_i)
+-- begin
+-- if rising_edge(clk_core_i) then
+-- if rst_n_core_i = '0' then
+-- arb_grant <= (others => '0');
+-- else
+-- f_rr_arbitrate(arb_req, arb_grant, arb_grant);
+-- end if;
+-- end if;
+-- end process;
+
+
+ p_input_arbiter : process(clk_core_i)
+ begin
+ if rising_edge(clk_core_i) then
+ if rst_n_core_i = '0' then
+ arb_grant <= (others => '0');
+ arb_grant_sreg(g_num_ports-1 downto 1) <= (others => '0');
+ arb_grant_sreg(0) <= '1';
+ else
+ -- spartan arbieter
+ arb_grant_sreg <= arb_grant_sreg(g_num_ports-2 downto 0) & arb_grant_sreg(g_num_ports-1); -- shift
+ arb_grant <= arb_grant_sreg and arb_req;
+ end if;
+ end if;
+ end process;
- -- -- The actual round-robin arbiter.
- --p_input_arbiter : process(clk_core_i)
- --begin
- -- if rising_edge(clk_core_i) then
- -- if rst_n_core_i = '0' then
- -- arb_grant <= (others => '0');
- -- else
- -- f_rr_arbitrate(arb_req, arb_grant, arb_grant);
- -- end if;
- -- end if;
- --end process;
-
-- write side address counter. Calculates the address of the entry in the F.B. Memory
diff --git a/modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd b/modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
index 4c8aa0ed357a2bc22052b3f0a83f233f2c01dbba..7cc0e87acd70c08c1bd295622dd3dcdbe1edc927 100644
--- a/modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
+++ b/modules/wrsw_swcore/new_allocator/swc_multiport_page_allocator.vhd
@@ -55,7 +55,14 @@ entity swc_multiport_page_allocator is
g_page_addr_width : integer := 10; --:= c_swc_page_addr_width;
g_num_ports : integer := 7; --:= c_swc_num_ports
g_page_num : integer := 1024; --:= c_swc_packet_mem_num_pages
- g_usecount_width : integer := 3 --:= c_swc_usecount_width
+ g_usecount_width : integer := 3; --:= c_swc_usecount_width
+ --- resource manager
+ g_max_pck_size : integer ;
+ g_page_size : integer ;
+ g_special_res_num_pages : integer ;
+ g_resource_num : integer ; -- this include 1 for unknown
+ g_resource_num_width : integer ;
+ g_num_dbg_vector_width : integer
);
port (
rst_n_i : in std_logic;
@@ -83,7 +90,32 @@ entity swc_multiport_page_allocator is
nomem_o : out std_logic;
- tap_out_o : out std_logic_vector(62 + 49 downto 0)
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ resource_i : in std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+
+ -- outputed when freeing
+ resource_o : out std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+
+ -- used only when freeing page,
+ -- if HIGH then the input resource_i value will be used
+ -- if LOW then the value read from memory will be used (stored along with usecnt)
+ free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ force_free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+
+ -- number of pages added to the resurce
+ rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+
+ -- indicates whether the resources where re-located to the proper resource, if not, then the
+ -- whole usecnt operation is abandoned
+ set_usecnt_succeeded_o : out std_logic_vector(g_num_ports -1 downto 0);
+ res_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
+
+-- tap_out_o : out std_logic_vector(62 + 49 downto 0)
);
end swc_multiport_page_allocator;
@@ -349,32 +381,47 @@ begin -- syn
end if;
end process;
- tap_out_o <= f_slv_resize
- (
- dbg_q_write &
- dbg_q_read &
- dbg_initializing &
- alloc_i &
- free_i &
- force_free_i &
- set_usecnt_i &
-
- alloc_done&
- free_done &
- force_free_done& -- 56
- set_usecnt_done & -- 48
- pg_alloc & -- 47
- pg_free & -- 46
- pg_free_last_usecnt & -- 45
- pg_force_free & -- 44
- pg_set_usecnt & -- 43
- pg_usecnt & -- 40
- pg_addr & -- 30
- pg_addr_alloc & -- 20
- pg_done & -- 19
- pg_nomem & -- 18
- dbg_double_free & -- 17
- dbg_double_force_free , -- 16
- 50 + 62);
+
+ --------------------------------------------------------------------------------------------------
+ -- Resource Manager logic and instantiation
+ --------------------------------------------------------------------------------------------------
+ -- dummy
+ set_usecnt_succeeded_o <= (others => '1');
+ res_full_o <= (others => '0');
+ res_almost_full_o <= (others => '0');
+ resource_o <= (others => '0');
+
+
+
+
+ --------------------------------------------------------------------------------------------------
+
+-- tap_out_o <= f_slv_resize
+-- (
+-- dbg_q_write &
+-- dbg_q_read &
+-- dbg_initializing &
+-- alloc_i &
+-- free_i &
+-- force_free_i &
+-- set_usecnt_i &
+--
+-- alloc_done&
+-- free_done &
+-- force_free_done& -- 56
+-- set_usecnt_done & -- 48
+-- pg_alloc & -- 47
+-- pg_free & -- 46
+-- pg_free_last_usecnt & -- 45
+-- pg_force_free & -- 44
+-- pg_set_usecnt & -- 43
+-- pg_usecnt & -- 40
+-- pg_addr & -- 30
+-- pg_addr_alloc & -- 20
+-- pg_done & -- 19
+-- pg_nomem & -- 18
+-- dbg_double_free & -- 17
+-- dbg_double_force_free , -- 16
+-- 50 + 62);
end syn;
diff --git a/modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd b/modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
index 5a258296b5df2928be01ea1212aabab679a51fca..74559b5baeb09e75d454993ab2b17e0366ad5e08 100644
--- a/modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
+++ b/modules/wrsw_swcore/new_allocator/swc_page_alloc_ram_bug.vhd
@@ -22,6 +22,12 @@
-- - Set use count (set_usecnt_i = 1): sets the use count value for the given page.
-- Used to define the reference count for pages pre-allocated in advance by
-- the input blocks.
+--
+-- It is implemented as a queue:
+-- * queue head is the rd_ptr - it indicates the address in the memory of the next empty page
+-- * queue tail is the wr_ptr - it indicates the address in the memory where the freed page can be
+-- stored
+--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski, Maciej Lipinski / CERN
@@ -134,8 +140,14 @@ architecture syn of swc_page_allocator_new is
signal real_nomem, out_nomem : std_logic;
- signal rd_ptr, wr_ptr : unsigned(g_page_addr_width-1 downto 0);
- signal free_pages : unsigned(g_page_addr_width downto 0);
+ -- queue head
+ signal rd_ptr : unsigned(g_page_addr_width-1 downto 0);
+
+ -- queue tail
+ signal wr_ptr : unsigned(g_page_addr_width-1 downto 0);
+
+ -- diff between head and tail
+ signal free_pages : unsigned(g_page_addr_width downto 0);
signal q_write , q_read : std_logic;
signal pending_free : std_logic;
@@ -164,7 +176,9 @@ architecture syn of swc_page_allocator_new is
begin -- syn
ram_ones <= (others => '1');
-
+ -- memeory in which list of addresses of available pages is stored
+ -- rd_ptr points to the address of next available page_addr
+ -- wr_ptr points to the address where a freed page can be written
U_Queue_RAM : swc_rd_wr_ram
generic map (
g_data_width => g_page_addr_width,
@@ -208,7 +222,7 @@ begin -- syn
-- db_i => std_logic_vector(rd_ptr),
-- qb_o => q_output_addr);
-
+ -- stores usecnts of pages, the addres is the page_addr (not ptr)
U_UseCnt_RAM : swc_rd_wr_ram
generic map (
g_data_width => g_usecount_width,
@@ -269,6 +283,10 @@ begin -- syn
-- ab_i => std_logic_vector(rd_ptr),
-- db_i => f_gen_dummy_vec('0', g_usecount_width));
+
+ -- keeps track of write and read pointers (wr_ptr and rd_ptr) and the number of available
+ -- free pages (free_pages).
+ -- indicates when we run out of pages
p_pointers : process(clk_i)
begin
if rising_edge(clk_i) then
@@ -312,6 +330,7 @@ begin -- syn
end if;
end process;
+ -- registers control signals (alloc/free/force_free)-- creates strobes
p_delay_alloc : process(clk_i)
begin
if rising_edge(clk_i) then
@@ -329,6 +348,7 @@ begin -- syn
pgaddr_o <= q_output_addr;
+ -- generates done signal
p_gen_done : process(clk_i)
begin
if rising_edge(clk_i) then
@@ -347,7 +367,7 @@ begin -- syn
done_o <= done_int; -- and not(free_d0 or alloc_d0);
-- q_write <= (not initializing) when (free_d0 = '1' and unsigned(usecnt_rddata) = 1) or (force_free_i = '1' and done_int = '0') else '0';
-
+ -- generate non_memory output
p_gen_nomem_output : process(clk_i)
begin
if rising_edge(clk_i) then
diff --git a/modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd b/modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
index 2d8c10d5dae6d053ad7198f923e62a11d098704c..6d554220928ea3a4b82825526a8414f5bd2e2051 100644
--- a/modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
+++ b/modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
@@ -55,33 +55,68 @@ entity swc_multiport_page_allocator is
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_num_ports : integer ;--:= c_swc_num_ports
g_page_num : integer ;--:= c_swc_packet_mem_num_pages
- g_usecount_width : integer --:= c_swc_usecount_width
+ g_usecount_width : integer ; --:= c_swc_usecount_width
+ --- resource manager
+ g_max_pck_size : integer ;
+ g_page_size : integer ;
+ g_special_res_num_pages : integer ;
+ g_resource_num : integer ; -- this include 1 for unknown
+ g_resource_num_width : integer ;
+ g_num_dbg_vector_width : integer ;
+ g_with_RESOURCE_MGR : boolean := false
);
port (
- rst_n_i : in std_logic;
- clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
- alloc_i : in std_logic_vector(g_num_ports - 1 downto 0);
- free_i : in std_logic_vector(g_num_ports - 1 downto 0);
- force_free_i : in std_logic_vector(g_num_ports - 1 downto 0);
- set_usecnt_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ alloc_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ free_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ set_usecnt_i : in std_logic_vector(g_num_ports - 1 downto 0);
- alloc_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
- free_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
- force_free_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
- set_usecnt_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ alloc_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ free_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ set_usecnt_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
pgaddr_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
pgaddr_force_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
pgaddr_usecnt_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
- usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
- pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
+-- usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+ usecnt_set_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+ usecnt_alloc_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+ pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
- free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
- nomem_o : out std_logic
+ nomem_o : out std_logic;
+
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ resource_i : in std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+
+ -- outputed when freeing
+ resource_o : out std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+
+ -- used only when freeing page,
+ -- if HIGH then the input resource_i value will be used
+ -- if LOW then the value read from memory will be used (stored along with usecnt)
+ free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ force_free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+
+ -- number of pages added to the resurce
+ rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+
+ -- indicates whether the resources where re-located to the proper resource, if not, then the
+ -- whole usecnt operation is abandoned
+ set_usecnt_succeeded_o : out std_logic_vector(g_num_ports -1 downto 0);
+ res_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
);
end swc_multiport_page_allocator;
@@ -161,38 +196,78 @@ architecture syn of swc_multiport_page_allocator is
signal force_free_done : std_logic_vector(g_num_ports-1 downto 0);
- signal set_usecnt_done_feedback : std_logic_vector(g_num_ports-1 downto 0);
+ signal set_usecnt_req_succeeded_feedback : std_logic_vector(g_num_ports-1 downto 0);
+ signal set_usecnt_req_finished_feedback : std_logic_vector(g_num_ports-1 downto 0);
-- signal set_usecnt_done : std_logic_vector(g_num_ports-1 downto 0);
signal pg_free_last_usecnt : std_logic;
-begin -- syn
-
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ signal pg_resource_in : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_alloc_usecnt_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_force_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_resource_out : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_free_resource_valid : std_logic;
+ signal pg_rescnt_page_num : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal pg_res_full : std_logic_vector(g_resource_num -1 downto 0);
+ signal pg_res_almost_full : std_logic_vector(g_resource_num -1 downto 0);
+
+ type t_port_resource_out is record
+ resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ full : std_logic_vector(g_resource_num-1 downto 0);
+ almost_full : std_logic_vector(g_resource_num-1 downto 0);
+ end record;
+
+ type t_port_resource_out_array is array(integer range <>) of t_port_resource_out;
+
+ signal resources_feedback : t_port_resource_out_array(g_num_ports-1 downto 0);
+ signal resources_out : t_port_resource_out_array(g_num_ports-1 downto 0);
+ signal pg_set_usecnt_succeeded : std_logic;
+ signal set_usecnt_succeeded : std_logic_vector(g_num_ports -1 downto 0);
+begin -- syn
-- one allocator/deallocator for all ports
--ALLOC_CORE : swc_page_allocator_new -- tom's new allocator, not debugged, looses pages :(
ALLOC_CORE : swc_page_allocator
generic map (
- g_num_pages => g_page_num,
- g_page_addr_width=> g_page_addr_width,
- g_num_ports => g_num_ports,
- g_usecount_width => g_usecount_width)
+ g_num_pages => g_page_num,
+ g_page_addr_width => g_page_addr_width,
+ g_num_ports => g_num_ports,
+ g_usecount_width => g_usecount_width,
+ --- management
+ g_page_size => g_page_size,
+ g_max_pck_size => g_max_pck_size,
+ g_special_res_num_pages => g_special_res_num_pages,
+ g_resource_num => g_resource_num,
+ g_resource_num_width => g_resource_num_width,
+ g_num_dbg_vector_width => g_num_dbg_vector_width
+)
port map (
- clk_i => clk_i,
- rst_n_i => rst_n_i,
- alloc_i => pg_alloc,
- free_i => pg_free,
- free_last_usecnt_o => pg_free_last_usecnt,
- force_free_i => pg_force_free,
- set_usecnt_i => pg_set_usecnt,
- usecnt_i => pg_usecnt,
- pgaddr_i => pg_addr,--pg_addr_free,
- pgaddr_o => pg_addr_alloc,
--- pgaddr_valid_o => pg_addr_valid,
--- idle_o => open, --pg_idle,
- done_o => pg_done,
- nomem_o => pg_nomem);
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ alloc_i => pg_alloc,
+ free_i => pg_free,
+ free_last_usecnt_o => pg_free_last_usecnt,
+ force_free_i => pg_force_free,
+ set_usecnt_i => pg_set_usecnt,
+ usecnt_i => pg_usecnt,
+ pgaddr_i => pg_addr,
+ pgaddr_o => pg_addr_alloc,
+ done_o => pg_done,
+ nomem_o => pg_nomem,
+ -------- resource management --------
+ set_usecnt_succeeded_o => pg_set_usecnt_succeeded,
+ resource_i => pg_resource_in,
+ resource_o => pg_resource_out,
+ free_resource_valid_i => pg_free_resource_valid,
+ rescnt_page_num_i => pg_rescnt_page_num,
+ res_full_o => pg_res_full,
+ res_almost_full_o => pg_res_almost_full,
+ dbg_o => dbg_o
+ );
-- creating request vector with 'alloc' requests at even addresses
@@ -201,7 +276,7 @@ begin -- syn
gen_request_vec : for i in 0 to g_num_ports - 1 generate
request_vec(4 * i + 0) <= alloc_i(i) and (not (alloc_done_feedback(i) or alloc_done(i))) and (not pg_nomem);
request_vec(4 * i + 1) <= free_i(i) and (not (free_done_feedback(i) or free_done(i)));
- request_vec(4 * i + 2) <= set_usecnt_i(i) and (not (set_usecnt_done_feedback(i)));-- or set_usecnt_done(i)));
+ request_vec(4 * i + 2) <= set_usecnt_i(i) and (not (set_usecnt_req_finished_feedback(i)));-- or set_usecnt_done(i)));
request_vec(4 * i + 3) <= force_free_i(i) and (not (force_free_done_feedback(i) or force_free_done(i)));
end generate gen_request_vec;
@@ -255,16 +330,23 @@ begin -- syn
-- getting the ouser count which should be assigned to freshly allocated page
pg_usecnt <= usecnt_i(in_sel * g_usecount_width + g_usecount_width - 1 downto in_sel * g_usecount_width);
- process(clk_i, rst_n_i)
+ MUX1: process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
- alloc_done_feedback <= (others => '0');
- free_done_feedback <= (others => '0');
- set_usecnt_done_feedback <= (others => '0');
- force_free_done_feedback <= (others => '0');
+
+ alloc_done <= (others => '0');
+ free_done <= (others => '0');
+ free_last_usecnt <= (others => '0');
+ force_free_done <= (others => '0');
+ set_usecnt_succeeded <= (others => '0');
- free_last_usecnt <= (others => '0');
+ alloc_done_feedback <= (others => '0');
+ free_done_feedback <= (others => '0');
+ set_usecnt_req_finished_feedback <= (others => '0');
+ set_usecnt_req_succeeded_feedback <= (others => '0');
+ force_free_done_feedback <= (others => '0');
+
else
-- recognizing on which port the allocation/deallocation/freeing process
@@ -287,9 +369,11 @@ begin -- syn
end if;
if(request_grant(1 downto 0) = b"10") then
- set_usecnt_done_feedback(i) <= '1';
+ set_usecnt_req_finished_feedback(i) <= '1';
+ set_usecnt_req_succeeded_feedback(i)<= pg_set_usecnt_succeeded;
else
- set_usecnt_done_feedback(i) <= '0';
+ set_usecnt_req_finished_feedback(i) <= '0';
+ set_usecnt_req_succeeded_feedback(i)<= '0';
end if;
if(request_grant(1 downto 0) = b"11") then
@@ -299,28 +383,89 @@ begin -- syn
end if;
else
- alloc_done_feedback(i) <= '0';
- free_done_feedback(i) <= '0';
- free_last_usecnt_feedback(i) <= '0';
- set_usecnt_done_feedback(i) <= '0';
- force_free_done_feedback(i) <= '0';
+ alloc_done_feedback(i) <= '0';
+ free_done_feedback(i) <= '0';
+ free_last_usecnt_feedback(i) <= '0';
+ set_usecnt_req_finished_feedback(i) <= '0';
+ set_usecnt_req_succeeded_feedback(i) <= '0';
+ force_free_done_feedback(i) <= '0';
end if;
end loop; -- i
- alloc_done <= alloc_done_feedback;
- free_done <= free_done_feedback;
- free_last_usecnt <= free_last_usecnt_feedback;
- -- set_usecnt_done <= set_usecnt_done_feedback;
- force_free_done <= force_free_done_feedback;
+ alloc_done <= alloc_done_feedback;
+ free_done <= free_done_feedback;
+ free_last_usecnt <= free_last_usecnt_feedback;
+ force_free_done <= force_free_done_feedback;
+ set_usecnt_succeeded <= set_usecnt_req_succeeded_feedback;
+
+
+ end if;
+ end if;
+ end process MUX1;
+
+ alloc_done_o <= alloc_done;
+ free_done_o <= free_done;
+ free_last_usecnt_o <= free_last_usecnt;
+ set_usecnt_done_o <= set_usecnt_req_finished_feedback;--set_usecnt_done;
+ force_free_done_o <= force_free_done;
+ nomem_o <= pg_nomem;
+ set_usecnt_succeeded_o <= set_usecnt_req_succeeded_feedback;--set_usecnt_succeeded;
+
+ --------------------------------------------------------------------------------------------------
+ -- Resource Manager logic and instantiation
+ --------------------------------------------------------------------------------------------------
+
+ pg_alloc_usecnt_resource <= resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
+ pg_free_resource <= free_resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
+ pg_force_free_resource <= force_free_resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
+ pg_resource_in <= pg_force_free_resource when (pg_force_free = '1') else
+ pg_free_resource when (pg_free = '1') else
+ pg_alloc_usecnt_resource;
+ pg_free_resource_valid <= force_free_resource_valid_i(in_sel) when (pg_force_free = '1') else
+ free_resource_valid_i (in_sel) when (pg_free = '1') else
+ '0';
+ pg_rescnt_page_num <= rescnt_page_num_i ((in_sel+1)*g_page_addr_width-1 downto in_sel*g_page_addr_width);
+
+
+ MUX2: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ L0: for i in 0 to g_num_ports-1 loop
+
+ resources_out(i).resource <= (others => '0');
+ resources_out(i).full <= (others => '0');
+ resources_out(i).almost_full <= (others => '0');
+
+ resources_feedback(i).resource <= (others => '0');
+ resources_feedback(i).full <= (others => '0');
+ resources_feedback(i).almost_full <= (others => '0');
+
+ end loop L0;
+ else
+
+ -- recognizing on which port the allocation/deallocation/freeing process
+ -- is about to finish. It's solely for request vector composition purpose
+ L1: for i in 0 to g_num_ports-1 loop
+ if(pg_done = '1' and (in_sel = i)) then
+ resources_feedback(i).resource <= pg_resource_out;
+ else
+ resources_feedback(i).resource <= (others => '0');
+ end if;
+ resources_feedback(i).full <= pg_res_full;
+ resources_feedback(i).almost_full <= pg_res_almost_full;
+ end loop L1; -- i
+
+ resources_out <= resources_feedback;
+
end if;
end if;
- end process;
-
- alloc_done_o <= alloc_done;
- free_done_o <= free_done;
- free_last_usecnt_o<= free_last_usecnt;
- set_usecnt_done_o <= set_usecnt_done_feedback;--set_usecnt_done;
- force_free_done_o <= force_free_done;
- nomem_o <= pg_nomem;
+ end process MUX2;
+
+ resource_OUT: for i in g_num_ports-1 downto 0 generate
+ resource_o ((i+1)*g_resource_num_width-1 downto i*g_resource_num_width) <= resources_out(i).resource;
+ res_full_o ((i+1)*g_resource_num -1 downto i*g_resource_num) <= resources_out(i).full;
+ res_almost_full_o((i+1)*g_resource_num -1 downto i*g_resource_num) <= resources_out(i).almost_full;
+ end generate resource_OUT;
end syn;
diff --git a/modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd b/modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
index b31f99a835cfb610c120b58549643ff231a1e727..909a75a026a18399fbf212f9611cb0718a952659 100644
--- a/modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
+++ b/modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
@@ -94,6 +94,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
@@ -112,7 +113,16 @@ entity swc_page_allocator is
g_num_ports : integer := 7;--:= c_swc_num_ports
-- number of bits of the user count value
- g_usecount_width: integer := 4 --g_use_count_bits
+ g_usecount_width: integer := 4; --g_use_count_bits ;
+
+ --- management
+ g_page_size : integer := 64;
+ g_max_pck_size : integer := 759; -- in 16 bit words (1518 [octets])/(2 [octets])
+ g_special_res_num_pages : integer := 256;
+ g_resource_num : integer := 3; -- this include: unknown, special and x* normal , so
+ -- g_resource_num = 2+x
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer
);
port (
@@ -167,7 +177,36 @@ entity swc_page_allocator is
-- multiport scheduler can optimize
-- it's performance
- nomem_o : out std_logic
+
+ nomem_o : out std_logic;
+
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- outputed when freeing
+ resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- used only when freeing page,
+ -- if HIGH then the input resource_i value will be used
+ -- if LOW then the value read from memory will be used (stored along with usecnt)
+ free_resource_valid_i : in std_logic;
+
+ -- number of pages added to the resurce
+ rescnt_page_num_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+
+ -- valid when (done_o and usecnt_i) = HIGH
+ -- set_usecnt_succeeded_o = LOW ->> indicates that the usecnt was not set and the resources
+ -- were not moved from unknown to resource_o because there is
+ -- not enough resources
+ -- set_usecnt_succeeded_o = HIGH->> indicates that usecnt_i requres was handled successfully
+ set_usecnt_succeeded_o : out std_logic;
+
+
+ res_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
);
end swc_page_allocator;
@@ -183,18 +222,14 @@ architecture syn of swc_page_allocator is
tmp(to_integer(unsigned(x))) := '1';
return tmp;
- end function;
-
-
-
-
+ end function f_onehot_decode;
constant c_l1_bitmap_size : integer := g_num_pages/32;
constant c_l1_bitmap_addrbits : integer := g_page_addr_width - 5;
type t_state is (IDLE, ALLOC_LOOKUP_L1, ALLOC_LOOKUP_L0_UPDATE,
FREE_CHECK_USECNT, FREE_RELEASE_PAGE, FREE_DECREASE_UCNT,
- SET_UCNT, NASTY_WAIT, DUMMY --, FORCE_FREE_RELEASE_PAGE
+ SET_UCNT,NOT_SET_UCNT, NASTY_WAIT, DUMMY --, FORCE_FREE_RELEASE_PAGE
);
-- this represents high part of the page address (bit mapping)
@@ -229,6 +264,13 @@ architecture syn of swc_page_allocator is
signal usecnt_mem_rddata : std_logic_vector(g_usecount_width-1 downto 0);
signal usecnt_mem_wrdata : std_logic_vector(g_usecount_width-1 downto 0);
+ signal rescnt_mem_rddata : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal rescnt_mem_wrdata : std_logic_vector(g_resource_num_width-1 downto 0);
+
+ signal mem_rddata : std_logic_vector(g_resource_num_width+g_usecount_width-1 downto 0);
+ signal mem_wrdata : std_logic_vector(g_resource_num_width+g_usecount_width-1 downto 0);
+
+
signal pgaddr_to_free : std_logic_vector(g_page_addr_width -1 downto 0);
signal page_freeing_in_last_operation : std_logic;
@@ -244,7 +286,20 @@ architecture syn of swc_page_allocator is
signal first_addr : std_logic;
signal ones : std_logic_vector(c_l1_bitmap_addrbits-1 downto 0);
--- signal tmp_dbg_alloc : std_logic;
+ signal done : std_logic;
+
+ signal free_last_usecnt : std_logic;
+
+-------------------------- resource management
+
+ signal res_mgr_alloc : std_logic;
+ signal res_mgr_free : std_logic;
+ signal res_mgr_res_num : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal res_mgr_rescnt_set : std_logic;
+ signal set_usecnt_succeeded : std_logic;
+ signal res_almost_full : std_logic_vector(g_resource_num -1 downto 0);
+-----------------------------
+
begin -- syn
ones <= (others => '1');
@@ -274,32 +329,6 @@ begin -- syn
onehot_o => l0_mask,
out_o => l0_first_free);
-
- --L0_LUT : generic_dpram
- -- generic map (
- -- g_data_width => 32,
- -- -- g_addr_bits => c_l1_bitmap_addrbits,
- -- g_size => c_l1_bitmap_size,
- -- g_dual_clock => false,
- -- g_addr_conflict_resolution => "read_first")
- -- port map (
- -- clka_i => clk_i,
- -- clkb_i => clk_i,
-
- -- aa_i => l0_wr_addr,
- -- da_i => l0_wr_data,
- -- qa_o => open,
- -- bwea_i => x"0",
- -- wea_i => l0_wr,
-
- -- ab_i => l0_rd_addr,
- -- db_i => x"00000000",
- -- qb_o => l0_rd_data,
- -- bweb_i => x"0",
- -- web_i => '0');
-
-
-
L0_LUT: swc_rd_wr_ram
generic map (
g_data_width => 32,
@@ -313,46 +342,27 @@ begin -- syn
wd_i => l0_wr_data,
ra_i => l0_rd_addr,
rd_o => l0_rd_data);
--- L0_UCNTMEM : generic_dpram
--- generic map (
--- g_data_width => g_usecount_width,
----- g_addr_bits => g_page_addr_width,
--- g_size => g_num_pages,
--- g_dual_clock => false,
--- g_addr_conflict_resolution => "read_first")
--- port map (
--- clka_i => clk_i,
--- clkb_i => clk_i,
-
--- da_i => usecnt_mem_wrdata,
--- aa_i => usecnt_mem_wraddr,
--- qa_o => open,
--- wea_i => usecnt_mem_wr,
--- bwea_i => ones((g_usecount_width+7)/8 -1 downto 0),--ones((g_usecount_width+7)/8 -1 downto 0),
-
--- ab_i => usecnt_mem_rdaddr,
--- qb_o => usecnt_mem_rddata,
--- db_i => ones(g_usecount_width-1 downto 0),
--- bweb_i => ones((g_usecount_width+7)/8-1 downto 0), --ones((g_usecount_width+7)/8-1 downto 0),
--- web_i => '0'
--- );
L0_UCNTMEM: swc_rd_wr_ram
generic map (
- g_data_width => g_usecount_width,
+ g_data_width => g_resource_num_width+g_usecount_width,
g_size => g_num_pages)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
we_i => usecnt_mem_wr,
wa_i => usecnt_mem_wraddr,
- wd_i => usecnt_mem_wrdata,
+ wd_i => mem_wrdata,
ra_i => usecnt_mem_rdaddr,
- rd_o => usecnt_mem_rddata);
+ rd_o => mem_rddata);
+
+
+ usecnt_mem_rddata <= mem_rddata(g_usecount_width-1 downto 0);
+ rescnt_mem_rddata <= mem_rddata(g_resource_num_width+g_usecount_width-1 downto g_usecount_width);
+
+ mem_wrdata <= rescnt_mem_wrdata & usecnt_mem_wrdata ;
fsm : process(clk_i, rst_n_i)
--- variable l:line;
--- file fout:text open write_mode is "dupa.txt";--"stdout" ;
variable cnt : integer := -1;
variable usecnt_mem_rdaddr_v : integer := 0;
@@ -367,13 +377,14 @@ begin -- syn
--usecnt_mem_rdaddr <= (others => '0');
usecnt_mem_wraddr <= (others => '0');
free_blocks <= to_unsigned(g_num_pages, free_blocks'length);
- done_o <= '0';
+ done <= '0';
l0_wr_addr <= (others => '0');
l0_rd_addr <= (others => '0');
l0_wr_data <= (others => '0');
pgaddr_valid_o <= '0';
nomem <= '0';
usecnt_mem_wrdata <= (others => '0');
+ rescnt_mem_wrdata <= (others => '0');
pgaddr_o <= (others => '0');
tmp_page <= (others => '0'); -- used for symulation debugging, don't remove
--tmp_pgs <= (others => '0');
@@ -384,7 +395,7 @@ begin -- syn
was_reset <= '1';
first_addr <= '1';
-
+ set_usecnt_succeeded <= '0';
elsif(was_reset = '1') then
@@ -400,8 +411,6 @@ begin -- syn
l0_wr_data <= (others => '1'); -- tom
l0_wr_addr <= std_logic_vector(unsigned(l0_wr_addr) + 1);
end if;
-
-
else
-- main finite state machine
@@ -410,16 +419,15 @@ begin -- syn
-- idle state: wait for alloc/release requests
when IDLE =>
- done_o <= '0';
+ done <= '0';
idle_o <= '1';
l0_wr <= '0';
pgaddr_valid_o <= '0';
usecnt_mem_wr <= '0';
-
page_freeing_in_last_operation <= '0';
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
-
+ set_usecnt_succeeded <= '0';
-- check if we have any free blocks and drive the nomem_o line.
-- last address (all '1') reserved for end-of-page marker in
-- linked list
@@ -442,7 +450,7 @@ begin -- syn
l0_rd_addr <= l1_first_free;
idle_o <= '0';
state <= ALLOC_LOOKUP_L1;
- done_o <= '1';
+ done <= '1';
end if;
-- got page release request
@@ -466,7 +474,7 @@ begin -- syn
l0_rd_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
- done_o <= '1'; -- assert the done signal early enough
+ done <= '1'; -- assert the done signal early enough
-- so the multiport allocator will also
-- take 3 cycles per request
@@ -490,7 +498,7 @@ begin -- syn
l0_rd_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
- done_o <= '1'; -- assert the done signal early enough
+ done <= '1'; -- assert the done signal early enough
-- so the multiport allocator will also
-- take 3 cycles per request
end if;
@@ -498,10 +506,22 @@ begin -- syn
if(set_usecnt_i = '1') then
idle_o <= '0';
- state <= SET_UCNT;
- usecnt_mem_wrdata <= usecnt_i;
- usecnt_mem_wraddr <= pgaddr_i;
- done_o <= '1'; -- assert the done signal early enough
+
+ -- check if we have enough resources !!!!
+ if(res_almost_full(to_integer(unsigned(resource_i))) = '1') then
+ -- not enough to accommodate max size frame, sorry we cannot serve the request
+ state <= NOT_SET_UCNT;
+ set_usecnt_succeeded <= '0';
+ else
+ -- enough resources
+ state <= SET_UCNT;
+ usecnt_mem_wrdata <= usecnt_i;
+ rescnt_mem_wrdata <= resource_i;
+ usecnt_mem_wraddr <= pgaddr_i;
+ set_usecnt_succeeded <= '1';
+
+ end if;
+ done <= '1'; -- assert the done signal early enough
-- so the multiport allocator will also
-- take 3 cycles per request
end if;
@@ -509,7 +529,7 @@ begin -- syn
when DUMMY =>
state <= FREE_RELEASE_PAGE;
- done_o <= '0';
+ done <= '0';
when NASTY_WAIT =>
@@ -523,7 +543,7 @@ begin -- syn
l0_rd_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
- done_o <= '1'; -- assert the done signal early enough
+ done <= '1'; -- assert the done signal early enough
-- so the multiport allocator will also
-- take 3 cycles per request
@@ -538,7 +558,7 @@ begin -- syn
-- drive "done" output early, so the arbiter will now that it can initiate
-- another operation in the next cycle.
- done_o <= '0';
+ done <= '0';
when ALLOC_LOOKUP_L0_UPDATE =>
@@ -562,6 +582,7 @@ begin -- syn
pgaddr_o <= l1_first_free & l0_first_free;
usecnt_mem_wraddr <= l1_first_free & l0_first_free;
usecnt_mem_wrdata <= usecnt_i;
+ rescnt_mem_wrdata <= resource_i;
usecnt_mem_wr <= '1';
pgaddr_valid_o <= '1';
free_blocks <= free_blocks-1;
@@ -570,12 +591,12 @@ begin -- syn
--if(l1_first_free & l0_first_free = x"0E5")
-- fprint(fout, l, "==> Allocate page %d , usecnt %d, free blocks: %d \n", fo(l1_first_free & l0_first_free),fo(usecnt_i), fo(free_blocks-1));
-- tmp_pgs(to_integer(unsigned(l1_first_free & l0_first_free))) <= '1';
- -- done_o <= '0';
+ -- done <= '0';
when FREE_CHECK_USECNT =>
-- use count = 1 - release the page
- done_o <= '0';
+ done <= '0';
-- last user, free page
if(usecnt_mem_rddata = std_logic_vector(to_unsigned(1, usecnt_mem_rddata'length))) then
@@ -599,33 +620,42 @@ begin -- syn
-- l1_bitmap <= l1_bitmap or f_onehot_decode(pgaddr_i(g_page_addr_width-1 downto 5));
free_blocks <= free_blocks+ 1;
usecnt_mem_wrdata <= (others => '0');
+ rescnt_mem_wrdata <= (others => '0');
usecnt_mem_wr <= '1';
state <= IDLE;
- done_o <= '0';
+ done <= '0';
-- fprint(fout, l, "<== Release page: %d, free blocks: %d \n",fo(tmp_page),fo(free_blocks+ 1));
--tmp_pgs(to_integer(unsigned(tmp_page))) <= '0';
when FREE_DECREASE_UCNT =>
usecnt_mem_wrdata <= std_logic_vector(unsigned(usecnt_mem_rddata) - 1);
+ rescnt_mem_wrdata <= rescnt_mem_rddata;
usecnt_mem_wr <= '1';
state <= IDLE;
-- fprint(fout, l, " Free page: %d (usecnt = %d)\n",fo(tmp_page),fo(std_logic_vector(unsigned(usecnt_mem_rddata) - 1)));
-
when SET_UCNT =>
- usecnt_mem_wrdata <= usecnt_i;
- usecnt_mem_wr <= '1';
- state <= IDLE;
- done_o <= '0';
+ usecnt_mem_wrdata <= usecnt_i;
+ rescnt_mem_wrdata <= resource_i;
+ usecnt_mem_wr <= '1';
+ state <= IDLE;
+ done <= '0';
+ set_usecnt_succeeded <= '0';
-- fprint(fout, l, " Usecnt set: %d (usecnt = %d)\n",fo(tmp_page),fo(usecnt_i));
-
+
+ when NOT_SET_UCNT =>
+
+ state <= IDLE;
+ done <= '0';
+ set_usecnt_succeeded <= '0';
+
when others =>
state <= IDLE;
- done_o <= '0';
+ done <= '0';
end case;
--usecnt_mem_rdaddr <= pgaddr_i;
@@ -641,10 +671,50 @@ begin -- syn
-- so that the data is available at the end of the first stata after IDLE
usecnt_mem_rdaddr <= pgaddr_i;
- nomem_o <= nomem;
-
- free_last_usecnt_o <= '1' when (state = FREE_CHECK_USECNT and
+ free_last_usecnt<= '1' when (state = FREE_CHECK_USECNT and
usecnt_mem_rddata = std_logic_vector(to_unsigned(1, usecnt_mem_rddata'length ))) else
- '0';
-
+ '0';
+
+ nomem_o <= nomem;
+ done_o <= done;
+ free_last_usecnt_o <= free_last_usecnt;
+ resource_o <= rescnt_mem_rddata;
+ set_usecnt_succeeded_o <= set_usecnt_succeeded;
+ res_almost_full_o <= res_almost_full;
+ --------------------------------------------------------------------------------------------------
+ -- Resource Manager logic and instantiation
+ --------------------------------------------------------------------------------------------------
+
+ res_mgr_alloc <= alloc_i and done;
+ res_mgr_free <= ((free_i and free_last_usecnt) or force_free_i) and done;
+ res_mgr_res_num <= rescnt_mem_rddata when (free_resource_valid_i='0' and (free_i='1' or force_free_i='1')) else
+ resource_i;
+ res_mgr_rescnt_set <= set_usecnt_i and done and set_usecnt_succeeded;
+
+ ------ resource management
+ RESOURCE_MANAGEMENT: swc_alloc_resource_manager
+ generic map(
+ g_num_ports => g_num_ports,
+ g_max_pck_size => g_max_pck_size,
+ g_page_size => g_page_size,
+ g_total_num_pages => g_num_pages,
+ g_total_num_pages_width => g_page_addr_width,
+ g_special_res_num_pages => g_special_res_num_pages,
+ g_resource_num => g_resource_num,
+ g_resource_num_width => g_resource_num_width,
+ g_num_dbg_vector_width => g_num_dbg_vector_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ resource_i => res_mgr_res_num,
+ alloc_i => res_mgr_alloc,
+ free_i => res_mgr_free,
+ rescnt_set_i => res_mgr_rescnt_set,
+ rescnt_page_num_i => rescnt_page_num_i,
+ res_full_o => res_full_o,
+ res_almost_full_o => res_almost_full,
+ dbg_o => dbg_o
+ );
+
end syn;
diff --git a/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd b/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90669dc0b9b77a2e39a4d9c14d089f330afc6213
--- /dev/null
+++ b/modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd
@@ -0,0 +1,632 @@
+-------------------------------------------------------------------------------
+-- Title : multiport page allocator
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_multiport_page_allocator.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN BE-Co-HT
+-- Created : 2010-04-08
+-- Last update: 2012-03-15
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This is a wrapper and arbiter for multi-access to a single
+-- page allocation core. Some highlights:
+-- * theere are 4 kinds of requrest which are however grouped into two groups:
+-- (1) input port requirests
+-- alloc_i -- request to allocate new page
+-- set_usecnt_i -- request to set usecount of already allocated page
+-- (2) output port requests:
+-- free_i -- request to decrease usecnt of page (if uscnt=1, page is deallocated)
+-- force_free_i -- request to deallocated a page regardless of usecnt
+-- * output port requests (2) cannot be done by a single port at the same time,
+-- this means that a port can either request free_i or force_free_i
+-- * input port requets (1) can be done in two fasions
+-- -> not simultaneously (like output)
+-- -> simultaneously and synchronized - so the data and request input is set/deset
+-- at the same time
+-- * internally, the arbitration is done between 2*num_port requests
+-- -> num_port for input port requests
+-- -> num_port for output port requests
+-- this means that the upper bound latency for handling request is:
+-- max_time= 2*num_ports + 2 (time needed for handling by core) + 1 (arbitration)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 Tomasz Wlostowski, Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-04-08 1.0 twlostow Created
+-- 2010-10-11 1.1 mlipinsk comments added !!!!!
+-- 2010-10-11 1.1 twlostow changed allocator
+-- 2012-02-02 2.0 mlipinsk generic-azed
+-- 2013-10-17 3.0 mlipinsk addapted to new optimized page_allocaotr core
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.swc_swcore_pkg.all;
+use work.genram_pkg.all;
+use work.gencores_pkg.all;
+
+entity swc_multiport_page_allocator is
+ generic (
+ g_page_addr_width : integer := 10; --:= c_swc_page_addr_width;
+ g_num_ports : integer := 7; --:= c_swc_num_ports
+ g_page_num : integer := 1024; --:= c_swc_packet_mem_num_pages
+ g_usecount_width : integer := 3; --:= c_swc_usecount_width
+ --- resource manager
+ g_max_pck_size : integer := 759 ;
+ g_page_size : integer := 66;
+ g_special_res_num_pages : integer := 256;
+ g_resource_num : integer := 3; -- this include 1 for unknown
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer := 10*3;
+ g_with_RESOURCE_MGR : boolean := false
+ );
+ port (
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ alloc_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ free_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ set_usecnt_i : in std_logic_vector(g_num_ports - 1 downto 0);
+
+ alloc_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ free_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ set_usecnt_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
+
+
+ pgaddr_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
+ pgaddr_force_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
+ pgaddr_usecnt_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
+
+ usecnt_set_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+ usecnt_alloc_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+
+ pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
+
+ free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
+
+ nomem_o : out std_logic;
+
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ resource_i : in std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+
+ -- outputed when freeing
+ resource_o : out std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+
+ -- used only when freeing page,
+ -- if HIGH then the input resource_i value will be used
+ -- if LOW then the value read from memory will be used (stored along with usecnt)
+ free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ force_free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+
+ -- number of pages added to the resurce
+ rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+
+ -- indicates whether the resources where re-located to the proper resource, if not, then the
+ -- whole usecnt operation is abandoned
+ set_usecnt_succeeded_o : out std_logic_vector(g_num_ports -1 downto 0);
+ res_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
+
+-- tap_out_o : out std_logic_vector(62 + 49 downto 0)
+ );
+
+end swc_multiport_page_allocator;
+
+architecture syn of swc_multiport_page_allocator is
+
+
+ component swc_page_allocator_new
+ generic (
+ g_num_pages : integer;
+ g_page_addr_width : integer;
+ g_num_ports : integer;
+ g_usecount_width : integer;
+ --- management
+ g_with_RESOURCE_MGR : boolean := false;
+ g_page_size : integer := 64;
+ g_max_pck_size : integer := 759; -- in 16 bit words (1518 [octets])/(2 [octets])
+ g_special_res_num_pages : integer := 256;
+ g_resource_num : integer := 3; -- this include: unknown, special and x* normal , so
+ -- g_resource_num = 2+x
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ alloc_i : in std_logic;
+ free_i : in std_logic;
+ force_free_i : in std_logic;
+ set_usecnt_i : in std_logic;
+ usecnt_set_i : in std_logic_vector(g_usecount_width-1 downto 0);
+ usecnt_alloc_i : in std_logic_vector(g_usecount_width-1 downto 0);
+ pgaddr_free_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+ pgaddr_usecnt_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+ req_vec_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rsp_vec_o : out std_logic_vector(g_num_ports-1 downto 0);
+ pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ free_last_usecnt_o : out std_logic;
+ done_o : out std_logic;
+ done_alloc_o : out std_logic;
+ done_usecnt_o : out std_logic;
+ done_free_o : out std_logic;
+ done_force_free_o : out std_logic;
+ nomem_o : out std_logic;
+ -------- resource management --------
+ resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+ resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
+ free_resource_valid_i : in std_logic;
+ rescnt_page_num_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+ set_usecnt_succeeded_o : out std_logic;
+ res_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
+ -----------------------
+ dbg_double_free_o : out std_logic;
+ dbg_double_force_free_o : out std_logic;
+ dbg_q_write_o : out std_logic;
+ dbg_q_read_o : out std_logic;
+ dbg_initializing_o : out std_logic);
+ end component;
+
+ type t_port_state is record
+ req_ib : std_logic;
+ req_ob : std_logic;
+ req_alloc : std_logic;
+ req_free : std_logic;
+ req_set_usecnt : std_logic;
+ req_force_free : std_logic;
+ req_addr_usecnt : std_logic_vector(g_page_addr_width-1 downto 0);
+ req_addr_free : std_logic_vector(g_page_addr_width-1 downto 0);
+ req_addr_f_free : std_logic_vector(g_page_addr_width-1 downto 0);
+ req_ucnt_set : std_logic_vector(g_usecount_width-1 downto 0);
+ req_ucnt_alloc : std_logic_vector(g_usecount_width-1 downto 0);
+ req_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ req_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ req_free_res_valid : std_logic;
+ req_f_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ req_f_free_res_valid : std_logic;
+ req_rescnt_pg_num : std_logic_vector(g_page_addr_width -1 downto 0);
+
+ grant_ib_d : std_logic_vector(2 downto 0);
+ grant_ob_d : std_logic_vector(2 downto 0);
+
+ done_alloc : std_logic;
+ done_free : std_logic;
+ done_set_usecnt : std_logic;
+ done_force_free : std_logic;
+ end record;
+ type t_port_state_array is array(0 to g_num_ports-1) of t_port_state;
+
+ signal ports : t_port_state_array;
+ signal arb_req, arb_grant : std_logic_vector(2*g_num_ports-1 downto 0);
+ signal arb_req_d0 : std_logic_vector(2*g_num_ports-1 downto 0);
+
+
+ signal pg_alloc : std_logic;
+ signal pg_free : std_logic;
+ signal pg_force_free : std_logic;
+ signal pg_set_usecnt : std_logic;
+ signal pg_usecnt_set : std_logic_vector(g_usecount_width-1 downto 0);
+ signal pg_usecnt_alloc : std_logic_vector(g_usecount_width-1 downto 0);
+ signal pg_addr_ucnt_set : std_logic_vector(g_page_addr_width -1 downto 0);
+ signal pg_addr_free : std_logic_vector(g_page_addr_width -1 downto 0);
+ signal pg_addr_alloc : std_logic_vector(g_page_addr_width -1 downto 0);
+ signal pg_free_last_usecnt : std_logic;
+ signal pg_done : std_logic;
+ signal done_alloc : std_logic;
+ signal done_usecnt : std_logic;
+ signal done_free : std_logic;
+ signal done_force_free : std_logic;
+
+ signal pg_nomem : std_logic;
+ signal pg_req_vec : std_logic_vector(g_num_ports-1 downto 0);
+ signal pg_rsp_vec : std_logic_vector(g_num_ports-1 downto 0);
+ signal grant_ob_d0 : std_logic_vector(g_num_ports-1 downto 0);
+ signal grant_ib_d0 : std_logic_vector(g_num_ports-1 downto 0);
+
+ signal alloc_done : std_logic_vector(g_num_ports - 1 downto 0);
+ signal free_done : std_logic_vector(g_num_ports - 1 downto 0);
+ signal force_free_done : std_logic_vector(g_num_ports - 1 downto 0);
+ signal set_usecnt_done : std_logic_vector(g_num_ports - 1 downto 0);
+
+ signal dbg_double_force_free, dbg_double_free : std_logic;
+ signal dbg_q_read, dbg_q_write, dbg_initializing : std_logic;
+
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ signal pg_resource_in : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_alloc_usecnt_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_force_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_resource_out : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pg_free_resource_valid : std_logic;
+ signal pg_rescnt_page_num : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal pg_res_full : std_logic_vector(g_resource_num -1 downto 0);
+ signal pg_res_almost_full : std_logic_vector(g_resource_num -1 downto 0);
+
+ type t_port_resource_out is record
+ resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ full : std_logic_vector(g_resource_num-1 downto 0);
+ almost_full : std_logic_vector(g_resource_num-1 downto 0);
+ end record;
+
+ type t_port_resource_out_array is array(integer range <>) of t_port_resource_out;
+
+ signal resources_feedback : t_port_resource_out_array(g_num_ports-1 downto 0);
+ signal resources_out : t_port_resource_out_array(g_num_ports-1 downto 0);
+ signal pg_set_usecnt_succeeded : std_logic;
+ signal set_usecnt_succeeded : std_logic_vector(g_num_ports -1 downto 0);
+
+ function f_bool_2_sl (x : boolean) return std_logic is
+ begin
+ if(x) then
+ return '1';
+ else
+ return '0';
+ end if;
+ end f_bool_2_sl;
+
+ function f_slv_resize(x : std_logic_vector; len : natural) return std_logic_vector is
+ variable tmp : std_logic_vector(len-1 downto 0);
+ begin
+ tmp := (others => '0');
+ tmp(x'length-1 downto 0) := x;
+ return tmp;
+ end f_slv_resize;
+
+
+begin -- syn
+
+ gen_records : for i in 0 to g_num_ports-1 generate
+ ports(i).req_force_free <= force_free_i(i);
+ ports(i).req_free <= free_i(i);
+ ports(i).req_alloc <= alloc_i(i) and (not pg_nomem);
+ ports(i).req_set_usecnt <= set_usecnt_i(i);
+ ports(i).req_free_res_valid <= free_resource_valid_i(i);
+ ports(i).req_f_free_res_valid <= force_free_resource_valid_i(i);
+
+ ports(i).req_addr_usecnt <= pgaddr_usecnt_i (g_page_addr_width *(i+1)-1 downto g_page_addr_width *i);
+ ports(i).req_addr_free <= pgaddr_free_i (g_page_addr_width *(i+1)-1 downto g_page_addr_width *i);
+ ports(i).req_addr_f_free <= pgaddr_force_free_i (g_page_addr_width *(i+1)-1 downto g_page_addr_width *i);
+ ports(i).req_ucnt_set <= usecnt_set_i (g_usecount_width *(i+1)-1 downto g_usecount_width *i);
+ ports(i).req_ucnt_alloc <= usecnt_alloc_i (g_usecount_width *(i+1)-1 downto g_usecount_width *i);
+ ports(i).req_resource <= resource_i (g_resource_num_width*(i+1)-1 downto g_resource_num_width*i);
+ ports(i).req_free_resource <= free_resource_i (g_resource_num_width*(i+1)-1 downto g_resource_num_width*i);
+ ports(i).req_f_free_resource <= force_free_resource_i(g_resource_num_width*(i+1)-1 downto g_resource_num_width*i);
+ ports(i).req_rescnt_pg_num <= rescnt_page_num_i (g_page_addr_width *(i+1)-1 downto g_page_addr_width *i);
+ end generate gen_records;
+
+ -- MUXes
+ gen_arbiter : for i in 0 to g_num_ports-1 generate
+ process(ports, arb_req, arb_grant, pg_done, pg_nomem,arb_req_d0, grant_ob_d0, grant_ib_d0)
+ begin
+ ports(i).grant_ib_d(0) <= arb_grant(2 * i);
+ ports(i).grant_ob_d(0) <= arb_grant(2 * i + 1);
+ ports(i).req_ib <= (ports(i).req_alloc or ports(i).req_set_usecnt);
+ ports(i).req_ob <= (ports(i).req_free or ports(i).req_force_free);
+ arb_req(2 * i) <= ports(i).req_ib and not (ports(i).grant_ib_d(0) or grant_ib_d0(i));
+ arb_req(2 * i + 1) <= ports(i).req_ob and not (ports(i).grant_ob_d(0) or grant_ob_d0(i));
+ end process;
+ end generate gen_arbiter;
+
+ p_gen_pg_reqs : process(ports)
+ variable alloc, free, force_free, set_usecnt : std_logic;
+ variable tmp_addr_ucnt : std_logic_vector(g_page_addr_width-1 downto 0);
+ variable tmp_addr_free : std_logic_vector(g_page_addr_width-1 downto 0);
+ variable tmp_ucnt_set : std_logic_vector(g_usecount_width-1 downto 0);
+ variable tmp_ucnt_alloc : std_logic_vector(g_usecount_width-1 downto 0);
+ begin
+ alloc := '0';
+ free := '0';
+ force_free := '0';
+ set_usecnt := '0';
+ tmp_addr_ucnt := (others => 'X');
+ tmp_addr_free := (others => 'X');
+ tmp_ucnt_set := (others => 'X');
+ tmp_ucnt_alloc := (others => 'X');
+
+ for i in 0 to g_num_ports-1 loop
+ if(ports(i).grant_ib_d(0) = '1') then
+ alloc := ports(i).req_alloc;
+ set_usecnt := ports(i).req_set_usecnt;
+ tmp_addr_ucnt := ports(i).req_addr_usecnt;
+ tmp_addr_free := (others => 'X');
+ if(ports(i).req_alloc = '1' ) then
+ tmp_ucnt_alloc := ports(i).req_ucnt_alloc;
+ else
+ tmp_ucnt_alloc := (others => 'X');
+ end if;
+ if(ports(i).req_set_usecnt = '1') then
+ tmp_ucnt_set := ports(i).req_ucnt_set;
+ else
+ tmp_ucnt_set := (others => 'X');
+ end if;
+ elsif(ports(i).grant_ob_d(0) = '1') then
+ free := ports(i).req_free;
+ force_free := ports(i).req_force_free;
+ tmp_addr_ucnt := (others => 'X');
+ if(ports(i).req_free = '1') then
+ tmp_addr_free := ports(i).req_addr_free;
+ tmp_ucnt_set := (others => 'X');
+ tmp_ucnt_alloc := (others => 'X');
+ elsif(ports(i).req_force_free = '1') then
+ tmp_addr_free := ports(i).req_addr_f_free;
+ tmp_ucnt_set := (others => 'X');
+ tmp_ucnt_alloc := (others => 'X');
+ end if;
+ end if;
+ pg_req_vec(i) <= ports(i).grant_ib_d(0) or ports(i).grant_ob_d(0);
+ end loop; -- i
+
+ pg_alloc <= alloc;
+ pg_free <= free;
+ pg_force_free <= force_free;
+ pg_set_usecnt <= set_usecnt;
+ pg_addr_ucnt_set <= tmp_addr_ucnt;
+ pg_addr_free <= tmp_addr_free;
+ pg_usecnt_set <= tmp_ucnt_set;
+ pg_usecnt_alloc <= tmp_ucnt_alloc;
+
+ end process;
+
+
+ p_arbitrate : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0'then
+ arb_grant <= (others => '0');
+ else
+ f_rr_arbitrate(arb_req, arb_grant, arb_grant);
+ end if;
+ end if;
+ end process;
+
+ p_req_vec_reg : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0'then
+ grant_ob_d0 <= (others => '0');
+ grant_ib_d0 <= (others => '0');
+ else
+ for i in 0 to g_num_ports-1 loop
+
+ -- input
+ if(ports(i).grant_ib_d(0) = '1') then
+ grant_ib_d0(i) <= '1';
+ elsif(pg_rsp_vec(i)='1' and (alloc_done(i) ='1' or set_usecnt_done(i) ='1')) then
+ grant_ib_d0(i) <= '0';
+ end if;
+ -- output
+ if(ports(i).grant_ob_d(0) = '1') then
+ grant_ob_d0(i) <= '1';
+ elsif(pg_rsp_vec(i)='1' and (free_done(i) ='1' or force_free_done(i) ='1')) then
+ grant_ob_d0(i) <= '0';
+ end if;
+
+ end loop; -- i
+ end if;
+ end if;
+ end process;
+
+ -- one allocator/deallocator for all ports
+ --ALLOC_CORE : swc_page_allocator_new -- tom's new allocator, not debugged, looses pages :(
+ ALLOC_CORE : swc_page_allocator_new
+ generic map (
+ g_num_pages => g_page_num,
+ g_page_addr_width => g_page_addr_width,
+ g_num_ports => g_num_ports,
+ g_usecount_width => g_usecount_width,
+ --- management
+ g_with_RESOURCE_MGR => g_with_RESOURCE_MGR,
+ g_page_size => g_page_size,
+ g_max_pck_size => g_max_pck_size,
+ g_special_res_num_pages => g_special_res_num_pages,
+ g_resource_num => g_resource_num,
+ g_resource_num_width => g_resource_num_width,
+ g_num_dbg_vector_width => g_num_dbg_vector_width)
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ alloc_i => pg_alloc,
+ free_i => pg_free,
+ free_last_usecnt_o => pg_free_last_usecnt,
+ force_free_i => pg_force_free,
+ set_usecnt_i => pg_set_usecnt,
+ usecnt_set_i => pg_usecnt_set,
+ usecnt_alloc_i => pg_usecnt_alloc,
+ pgaddr_free_i => pg_addr_free,
+ pgaddr_usecnt_i => pg_addr_ucnt_set,
+ req_vec_i => pg_req_vec,
+ rsp_vec_o => pg_rsp_vec,
+ pgaddr_o => pg_addr_alloc,
+ done_o => pg_done,
+ done_alloc_o => done_alloc,
+ done_usecnt_o => done_usecnt,
+ done_free_o => done_free,
+ done_force_free_o => done_force_free,
+ nomem_o => pg_nomem,
+ -------- resource management --------
+ set_usecnt_succeeded_o => pg_set_usecnt_succeeded,
+ resource_i => pg_resource_in,
+ resource_o => pg_resource_out,
+ free_resource_valid_i => pg_free_resource_valid,
+ rescnt_page_num_i => pg_rescnt_page_num,
+ res_full_o => pg_res_full,
+ res_almost_full_o => pg_res_almost_full,
+ dbg_o => dbg_o,
+ -------------------------------
+ dbg_double_force_free_o => dbg_double_force_free,
+ dbg_double_free_o => dbg_double_free,
+ dbg_q_read_o => dbg_q_read,
+ dbg_q_write_o => dbg_q_write,
+ dbg_initializing_o => dbg_initializing);
+
+ nomem_o <= pg_nomem;
+ pgaddr_alloc_o <= pg_addr_alloc;
+
+ gen_done : for i in 0 to g_num_ports-1 generate
+-- when nomem it got lost -> the req_alloc is forced LOW by nomam HIGH, so the alloc which happened just before nomem
+-- was not answered...
+-- alloc_done(i) <= '1' when (ports(i).req_alloc ='1' and pg_rsp_vec(i)='1' and done_alloc ='1') else '0';
+-- free_done(i) <= '1' when (ports(i).req_free ='1' and pg_rsp_vec(i)='1' and done_free ='1') else '0';
+-- force_free_done(i) <= '1' when (ports(i).req_force_free='1' and pg_rsp_vec(i)='1' and done_force_free='1') else '0';
+-- set_usecnt_done(i) <= '1' when (ports(i).req_set_usecnt='1' and pg_rsp_vec(i)='1' and done_usecnt ='1') else '0';
+ alloc_done(i) <= '1' when (pg_rsp_vec(i)='1' and done_alloc ='1') else '0';
+ free_done(i) <= '1' when (pg_rsp_vec(i)='1' and done_free ='1') else '0';
+ force_free_done(i) <= '1' when (pg_rsp_vec(i)='1' and done_force_free='1') else '0';
+ set_usecnt_done(i) <= '1' when (pg_rsp_vec(i)='1' and done_usecnt ='1') else '0';
+ end generate gen_done;
+
+ alloc_done_o <= alloc_done;
+ free_done_o <= free_done;
+ force_free_done_o <= force_free_done;
+ set_usecnt_done_o <= set_usecnt_done;
+ free_last_usecnt_o <= (others => pg_free_last_usecnt);
+
+ p_assertions : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ for i in 0 to g_num_ports-1 loop
+-- if(ports(i).req_alloc = '1' and ports(i).req_set_usecnt = '1') then
+-- report "simultaneous alloc/set_usecnt" severity failure;
+--
+-- elsif (ports(i).req_free = '1' and ports(i).req_force_free = '1') then
+-- report "simultaneous free/force_free" severity failure;
+
+ if (ports(i).req_free = '1' and ports(i).req_force_free = '1') then
+ report "simultaneous free/force_free" severity failure;
+ end if;
+
+ end loop; -- i
+ end if;
+ end process;
+
+ --------------------------------------------------------------------------------------------------
+ -- Resource Manager logic and instantiation
+ --------------------------------------------------------------------------------------------------
+ gen_no_RESOURCE_MGR: if (g_with_RESOURCE_MGR = false) generate -- so we don't want resource gnr
+ set_usecnt_succeeded_o <= (others => '1');
+ res_full_o <= (others => '0');
+ res_almost_full_o <= (others => '0');
+ resource_o <= (others => '0');
+
+ pg_resource_in <= (others => '0');
+ pg_free_resource_valid <= '0';
+ pg_rescnt_page_num <= (others => '0');
+ end generate gen_no_RESOURCE_MGR;
+
+ gen_RESOURCE_MGR: if (g_with_RESOURCE_MGR = true) generate -- so we do want resource gnr
+
+ -- input mux
+ p_gen_resource_reqs : process(ports)
+ variable tmp_resource_in : std_logic_vector(g_resource_num_width-1 downto 0);
+ variable tmp_free_res_valid : std_logic;
+ variable tmp_rescnt_pg_num : std_logic_vector(g_page_addr_width -1 downto 0);
+ begin
+ tmp_resource_in := (others => 'X');
+ tmp_free_res_valid := '0';
+ tmp_rescnt_pg_num := (others => 'X');
+
+ for i in 0 to g_num_ports-1 loop
+ if(ports(i).grant_ib_d(0) = '1') then
+ tmp_resource_in := ports(i).req_resource;
+ tmp_free_res_valid := '0';
+ if(ports(i).req_set_usecnt = '1') then
+ tmp_rescnt_pg_num := ports(i).req_rescnt_pg_num;
+ else
+ tmp_rescnt_pg_num := (others => 'X'); -- to see red in simulation when data not used
+ end if;
+ elsif(ports(i).grant_ob_d(0) = '1') then
+ if(ports(i).req_free = '1' and ports(i).req_free_res_valid = '1') then -- way to enable X if else
+ tmp_resource_in := ports(i).req_free_resource;
+ tmp_free_res_valid := '1';
+ elsif(ports(i).req_force_free = '1' and ports(i).req_f_free_res_valid ='1') then
+ tmp_resource_in := ports(i).req_f_free_resource;
+ tmp_free_res_valid := '1';
+ else -- to see problems in red on simulation
+ tmp_resource_in := (others =>'X');
+ tmp_free_res_valid := '0';
+ end if;
+ tmp_rescnt_pg_num := (others =>'X');
+ end if;
+ end loop; -- i
+
+ pg_resource_in <= tmp_resource_in;
+ pg_free_resource_valid <= tmp_free_res_valid;
+ pg_rescnt_page_num <= tmp_rescnt_pg_num;
+
+ end process p_gen_resource_reqs;
+
+ -- output de-mux
+ gen_res_out : for i in 0 to g_num_ports-1 generate
+ resource_o ((i+1)*g_resource_num_width-1 downto i*g_resource_num_width) <= pg_resource_out when (free_done(i) ='1' or force_free_done(i) ='1') else
+ (others => '0');
+ res_full_o ((i+1)*g_resource_num -1 downto i*g_resource_num) <= pg_res_full;
+ res_almost_full_o((i+1)*g_resource_num -1 downto i*g_resource_num) <= pg_res_almost_full;
+
+ set_usecnt_succeeded_o(i) <= pg_set_usecnt_succeeded when (set_usecnt_done(i) ='1') else '0';
+ end generate gen_res_out;
+ end generate gen_RESOURCE_MGR;
+
+ --------------------------------------------------------------------------------------------------
+
+-- tap_out_o <= f_slv_resize
+-- (
+-- dbg_q_write &
+-- dbg_q_read &
+-- dbg_initializing &
+-- alloc_i &
+-- free_i &
+-- force_free_i &
+-- set_usecnt_i &
+--
+-- alloc_done&
+-- free_done &
+-- force_free_done& -- 56
+-- set_usecnt_done & -- 48
+-- pg_alloc & -- 47
+-- pg_free & -- 46
+-- pg_free_last_usecnt & -- 45
+-- pg_force_free & -- 44
+-- pg_set_usecnt & -- 43
+-- pg_usecnt & -- 40
+-- pg_addr & -- 30
+-- pg_addr_alloc & -- 20
+-- pg_done & -- 19
+-- pg_nomem & -- 18
+-- dbg_double_free & -- 17
+-- dbg_double_force_free , -- 16
+-- 50 + 62);
+
+end syn;
diff --git a/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd b/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8b78efa9fa2bc7570d25c199f669df6b3ec65b55
--- /dev/null
+++ b/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc.vhd
@@ -0,0 +1,375 @@
+-------------------------------------------------------------------------------
+-- Title : Fast page allocator/deallocator
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_page_allocator.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN BE-Co-HT
+-- Created : 2010-04-08
+-- Last update: 2013-10-11
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Module implements a fast (2 cycle) paged memory allocator.
+-- The allocator can serve 4 types of requests:
+-- - Allocate a page with given use count (alloc_i = 1). The use count tells
+-- the allocator how many clients requested that page (and hence, how many free
+-- requests are required to return the page to free pages poll)
+-- - Free a page (free_i = 1) - check the use count stored for the page. If it's
+-- bigger than 1, decrease the use count, if it's 1 mark the page as free.
+-- - Force free a page (force_free_i = 1): immediately frees the page regardless
+-- of its current use_count.
+-- - Set use count (set_usecnt_i = 1): sets the use count value for the given page.
+-- Used to define the reference count for pages pre-allocated in advance by
+-- the input blocks.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 Tomasz Wlostowski, Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-04-08 1.0 twlostow Created
+-- 2010-10-11 1.1 mlipinsk comments added !!!!!
+-- 2012-01-24 2.0 twlostow completely changed (uses FIFO)
+-- 2012-03-05 2.1 mlipinsk added debugging stuff + made interchangeable with old (still buggy)
+-- 2012-03-15 2.2 twlostow fixed really ugly missing pages bug
+-- 2012-10-11 3.0 mlipinsk optimized to work in single cycle + pipelined
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.swc_swcore_pkg.all;
+use work.genram_pkg.all;
+
+entity swc_page_allocator_new is
+ generic (
+ -- number of pages in the allocator pool
+ g_num_pages : integer := 2048;
+
+ -- number of bits of the page address
+ g_page_addr_width : integer := 11;
+
+ g_num_ports : integer := 10;
+
+ -- number of bits of the user (reference) count value
+ g_usecount_width : integer := 4
+ );
+
+ port (
+ clk_i : in std_logic; -- clock & reset
+ rst_n_i : in std_logic;
+
+ -- "Allocate" command strobe (active HI), starts allocation process of a page with use
+ -- count given on usecnt_i. Address of the allocated page is returned on
+ -- pgaddr_o and is valid when done_o is HI.
+ alloc_i : in std_logic;
+
+ -- "Free" command strobe (active HI), releases the page at address pgaddr_i if it's current
+ -- use count is equal to 1, otherwise decreases the page's use count.
+ free_i : in std_logic;
+
+ force_free_i : in std_logic; -- free strobe (active HI), releases the page
+ -- at address pgaddr_i regardless of the user
+ -- count of the page
+ -- it is used in case a package is corrupted
+ -- and what have already been
+ -- saved, needs to be released
+
+
+ set_usecnt_i : in std_logic; -- enables to set user count to already
+ -- alocated page, used in the case of the
+ -- address of the first page of a package,
+ -- we need to allocate this page in advance
+ -- not knowing the user count, so the user count
+ -- needs to be set to already allocated page
+
+ -- "Use count" value for the page to be allocated. If the page is to be
+ -- used by multiple output queues, each of them will attempt to free it.
+
+ usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
+
+ pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+
+ req_vec_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rsp_vec_o : out std_logic_vector(g_num_ports-1 downto 0);
+
+ pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+
+ free_last_usecnt_o : out std_logic;
+
+ done_o : out std_logic; -- "early" done output (active HI).
+ -- Indicates that
+ -- the alloc/release cycle is going to
+ -- end 1 cycle in advance, so the
+ -- multiport scheduler can optimize
+ -- it's performance
+
+ nomem_o : out std_logic;
+
+ dbg_double_free_o : out std_logic;
+ dbg_double_force_free_o : out std_logic;
+ dbg_q_write_o : out std_logic;
+ dbg_q_read_o : out std_logic;
+ dbg_initializing_o : out std_logic
+ );
+
+end swc_page_allocator_new;
+
+architecture syn of swc_page_allocator_new is
+
+ -- convention used in the naming:
+ -- *_in - means that the signal is input
+ -- *_p0 or *_d0 - means that the signal is used in the first stage of the pipe
+ -- *_p1 or *_d1 - means that the signal is used in the second stage of the pipe
+ --
+ -- *_p0 or *_p1 - is a signal which results from some logic (either registered or not) or
+ -- output from RAM
+ -- *_p0 or *_p1 - is a registered signal - a copy with no chagnes
+
+ signal real_nomem, out_nomem : std_logic;
+
+ signal rd_ptr_p0 : unsigned(g_page_addr_width-1 downto 0);
+ signal wr_ptr_p1 : unsigned(g_page_addr_width-1 downto 0);
+ signal free_pages : unsigned(g_page_addr_width downto 0);
+
+ signal q_write_p1 : std_logic;
+ signal q_read_p0 : std_logic;
+
+ signal initializing : std_logic;
+
+ signal usecnt_ena_wr_p1 : std_logic;
+ signal usecnt_addr_rd_p0,usecnt_addr_wr_p1: std_logic_vector(g_page_addr_width-1 downto 0);
+ signal usecnt_rddata_p1, usecnt_data_wr_p1 : std_logic_vector(g_usecount_width-1 downto 0);
+
+ signal q_output_addr_p1 : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal done_p1 : std_logic;
+ signal ram_ones : std_logic_vector(g_page_addr_width + g_usecount_width -1 downto 0);
+
+
+ --debuggin sygnals
+ signal tmp_dbg_dealloc : std_logic; -- used for symulation debugging, don't remove
+ signal tmp_page : std_logic_vector(g_page_addr_width -1 downto 0);
+ signal free_blocks : unsigned(g_page_addr_width downto 0);
+ signal usecnt_not_zero : std_logic;
+ signal real_nomem_d0 : std_logic;
+
+ type t_alloc_req is record
+ alloc : std_logic;
+ free : std_logic;
+ f_free : std_logic;
+ set_usecnt : std_logic;
+ usecnt : std_logic_vector(g_usecount_width-1 downto 0);
+ pgaddr : std_logic_vector(g_page_addr_width -1 downto 0);
+ grant_vec : std_logic_vector(g_num_ports-1 downto 0);
+ end record;
+
+ constant c_pipeline_depth : integer := 2;
+
+ type t_alloc_req_pipe is array(integer range <>) of t_alloc_req;
+ signal alloc_req_in : t_alloc_req;
+ signal alloc_req_d0 : t_alloc_req;
+ signal alloc_req_d1 : t_alloc_req;
+
+ constant alloc_req_zero : t_alloc_req := (
+ alloc => '0',
+ free => '0',
+ f_free => '0',
+ set_usecnt => '0',
+ usecnt => (others => '0'),
+ pgaddr => (others => '0'),
+ grant_vec => (others => '0'));
+
+
+begin -- syn
+ ram_ones <= (others => '1');
+ alloc_req_in.alloc <= alloc_i;
+ alloc_req_in.free <= free_i;
+ alloc_req_in.f_free <= force_free_i;
+ alloc_req_in.set_usecnt <= set_usecnt_i;
+ alloc_req_in.usecnt <= usecnt_i;
+ alloc_req_in.pgaddr <= pgaddr_i;
+ alloc_req_in.grant_vec <= req_vec_i;
+
+ p_pipe: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ alloc_req_d0 <= alloc_req_zero;
+ alloc_req_d1 <= alloc_req_zero;
+ else
+ alloc_req_d0 <= alloc_req_in;
+ alloc_req_d1 <= alloc_req_d0;
+ end if;
+ end if;
+
+ end process;
+
+ -- write queue when freeing and not initializing (because when initializing we use other
+ -- port of this memory)
+ q_write_p1 <= (not initializing) when
+ (alloc_req_d1.free = '1' and unsigned(usecnt_rddata_p1) = 1) or
+ (alloc_req_d1.f_free = '1') else '0';
+
+ -- increaze pointer to next address -> it stores next freee page, we use the currently read
+ -- and increase for next usage
+ q_read_p0 <= '1' when (alloc_req_d0.alloc = '1') else '0';-- and (real_nomem_d0 = '0') else '0'; -- TODO: real_nomem
+
+ U_Queue_RAM : generic_dpram
+ generic map (
+ g_data_width => g_page_addr_width,
+ g_size => 2**g_page_addr_width,
+ g_with_byte_enable => false,
+ g_dual_clock => false)
+ port map (
+ rst_n_i => rst_n_i,
+ clka_i => clk_i,
+ bwea_i => ram_ones((g_page_addr_width+7)/8 - 1 downto 0),
+ wea_i => q_write_p1,
+ aa_i => std_logic_vector(wr_ptr_p1), -- pointer increase on each q_write_p1=HIGH
+ da_i => alloc_req_d1.pgaddr,
+
+ clkb_i => clk_i,
+ bweb_i => ram_ones((g_page_addr_width+7)/8 - 1 downto 0),
+ web_i => initializing,
+ ab_i => std_logic_vector(rd_ptr_p0), -- pointer increase on each q_read_p0=HIGH
+ db_i => std_logic_vector(rd_ptr_p0), -- pointer increase on each q_read_p0=HIGH
+ qb_o => q_output_addr_p1);
+
+
+ usecnt_addr_wr_p1 <= q_output_addr_p1 when alloc_req_d1.alloc = '1' else alloc_req_d1.pgaddr;
+
+ usecnt_ena_wr_p1 <= (alloc_req_d1.alloc or
+ alloc_req_d1.set_usecnt or
+ alloc_req_d1.free or
+ alloc_req_d1.f_free) and not initializing;
+
+ usecnt_data_wr_p1 <= alloc_req_d1.usecnt when alloc_req_d1.set_usecnt = '1' else
+ alloc_req_d1.usecnt when alloc_req_d1.alloc = '1' else
+ f_gen_dummy_vec('0', g_usecount_width) when alloc_req_d1.f_free = '1' else
+ std_logic_vector(unsigned(usecnt_rddata_p1) - 1);
+
+ usecnt_addr_rd_p0<= std_logic_vector(rd_ptr_p0) when initializing = '1' else alloc_req_d0.pgaddr;
+
+ U_UseCnt_RAM : generic_dpram
+ generic map (
+ g_data_width => g_usecount_width,
+ g_size => 2**g_page_addr_width,
+ g_with_byte_enable => false,
+ g_dual_clock => false)
+ port map (
+ rst_n_i => rst_n_i,
+ clka_i => clk_i,
+ wea_i => usecnt_ena_wr_p1,
+ bwea_i => ram_ones((g_usecount_width+7)/8 - 1 downto 0),
+ aa_i => usecnt_addr_wr_p1,
+ da_i => usecnt_data_wr_p1,
+
+ clkb_i => clk_i,
+ bweb_i => ram_ones((g_usecount_width+7)/8 - 1 downto 0),
+ web_i => initializing,
+ ab_i => usecnt_addr_rd_p0,--std_logic_vector(rd_ptr_p0),
+ db_i => f_gen_dummy_vec('0', g_usecount_width),
+ qb_o => usecnt_rddata_p1);
+
+ p_pointers : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ initializing <= '1';
+ rd_ptr_p0 <= (others => '0');
+ real_nomem <= '0';
+ else
+
+ real_nomem_d0 <= real_nomem;
+
+ if(initializing = '1') then
+ free_pages <= to_unsigned(g_num_pages-1, free_pages'length);
+ wr_ptr_p1 <= to_unsigned(g_num_pages-1, wr_ptr_p1'length);
+ rd_ptr_p0 <= rd_ptr_p0 + 1;
+ if(rd_ptr_p0 = g_num_pages-2) then
+ initializing <= '0';
+ rd_ptr_p0 <= (others => '0');
+ end if;
+ else
+ -- just increaing the pointerst to end/beginning of the queue
+ if(q_write_p1 = '1') then
+ wr_ptr_p1 <= wr_ptr_p1 + 1;
+ end if;
+
+ if(q_read_p0 = '1') then
+ rd_ptr_p0 <= rd_ptr_p0 + 1;
+ end if;
+
+ -- counting the usage of pages
+ if(q_write_p1 = '1' and q_read_p0 = '0') then
+ real_nomem <= '0';
+ free_pages <= free_pages + 1;
+ elsif (q_write_p1 = '0' and q_read_p0 = '1') then
+ if(free_pages = 1) then
+ real_nomem <= '1';
+ end if;
+ free_pages <= free_pages - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_gen_done : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if (rst_n_i = '0') or (initializing = '1') then
+ done_p1 <= '0';
+ else
+ if(((alloc_req_d0.alloc = '1' and real_nomem = '0') or
+ alloc_req_d0.set_usecnt = '1' or alloc_req_d0.free = '1' or
+ alloc_req_d0.f_free = '1') and initializing = '0') then
+ done_p1 <= '1';
+ else
+ done_p1 <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_gen_nomem_output : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ out_nomem <= '0';
+ else
+ if(out_nomem = '0' and (free_pages < to_unsigned(3, free_blocks'length))) then
+ out_nomem <= '1';
+ elsif(out_nomem = '1' and (free_pages > to_unsigned((3*g_num_ports), free_blocks'length))) then
+ out_nomem <= real_nomem;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ pgaddr_o <= q_output_addr_p1;
+ done_o <= done_p1;
+ rsp_vec_o <= alloc_req_d1.grant_vec;
+ nomem_o <= out_nomem;
+ free_last_usecnt_o <= (not initializing) when (alloc_req_d1.free = '1' and unsigned(usecnt_rddata_p1) = 1) else '0';
+
+end syn;
diff --git a/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd b/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8911142b1d8dac68b70a0593e09c64d1d5ce085c
--- /dev/null
+++ b/modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
@@ -0,0 +1,622 @@
+-------------------------------------------------------------------------------
+-- Title : Fast page allocator/deallocator
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_page_allocator.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN BE-Co-HT
+-- Created : 2010-04-08
+-- Last update: 2013-10-23
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Module implements a fast (2 cycle) paged memory allocator.
+-- The allocator can serve 4 types of requests:
+-- - Allocate a page with given use count (alloc_i = 1). The use count tells
+-- the allocator how many clients requested that page (and hence, how many free
+-- requests are required to return the page to free pages poll)
+-- - Free a page (free_i = 1) - check the use count stored for the page. If it's
+-- bigger than 1, decrease the use count, if it's 1 mark the page as free.
+-- - Force free a page (force_free_i = 1): immediately frees the page regardless
+-- of its current use_count.
+-- - Set use count (set_usecnt_i = 1): sets the use count value for the given page.
+-- Used to define the reference count for pages pre-allocated in advance by
+-- the input blocks.
+--
+-- Allocation request (alloc_i = 1) and setting use count (set_usecnt_i = 1) can
+-- be done simultaneously whereas Free (free_i = 1) and Force Free (force_free_i = 1)
+-- must be done separately then each other and the allocation/usecnat request.
+-- In other words, the core can accept:
+-- - allocate request or
+-- - usecant request or
+-- - allocate and usecnt request or
+-- - free request or
+-- - force free request
+--
+-- The core accepts one request per single cycle. The request input signal must
+-- be a sigle-cycle strobe.
+--
+-- Any of the requests is alwyas handled 2 cycles. The output done_{} at the second
+-- cycle from the request, i.e.
+-- clk _|-|_|-|_|-|_|-|_
+-- alloc_i _ _|-|_ _ _ _ _ _
+-- done_o _ _ _ _|-|_ _ _ _
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 Tomasz Wlostowski, Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-04-08 1.0 twlostow Created
+-- 2010-10-11 1.1 mlipinsk comments added !!!!!
+-- 2012-01-24 2.0 twlostow completely changed (uses FIFO)
+-- 2012-03-05 2.1 mlipinsk added debugging stuff + made interchangeable with old (still buggy)
+-- 2012-03-15 2.2 twlostow fixed really ugly missing pages bug
+-- 2013-10-11 3.1 mlipinsk optimized to work in single cycle + pipelined
+-- 2013-10-22 3.2 mlipinsk parallel usecnt/alloc
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.swc_swcore_pkg.all;
+use work.genram_pkg.all;
+
+entity swc_page_allocator_new is
+ generic (
+ -- number of pages in the allocator pool
+ g_num_pages : integer := 2048;
+
+ -- number of bits of the page address
+ g_page_addr_width : integer := 11;
+
+ g_num_ports : integer := 10;
+
+ -- number of bits of the user (reference) count value
+ g_usecount_width : integer := 4;
+
+ --- management
+ g_with_RESOURCE_MGR : boolean := false;
+ g_page_size : integer := 64;
+ g_max_pck_size : integer := 759; -- in 16 bit words (1518 [octets])/(2 [octets])
+ g_special_res_num_pages : integer := 256;
+ g_resource_num : integer := 3; -- this include: unknown, special and x* normal , so
+ -- g_resource_num = 2+x
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer
+ );
+
+ port (
+ clk_i : in std_logic; -- clock & reset
+ rst_n_i : in std_logic;
+
+ -- "Allocate" command strobe (active HI), starts allocation process of a page with use
+ -- count given on usecnt_i. Address of the allocated page is returned on
+ -- pgaddr_o and is valid when done_o is HI.
+ alloc_i : in std_logic;
+
+ -- "Free" command strobe (active HI), releases the page at address pgaddr_i if it's current
+ -- use count is equal to 1, otherwise decreases the page's use count.
+ free_i : in std_logic;
+
+ force_free_i : in std_logic; -- free strobe (active HI), releases the page
+ -- at address pgaddr_i regardless of the user
+ -- count of the page
+ -- it is used in case a package is corrupted
+ -- and what have already been
+ -- saved, needs to be released
+
+
+ set_usecnt_i : in std_logic; -- enables to set user count to already
+ -- alocated page, used in the case of the
+ -- address of the first page of a package,
+ -- we need to allocate this page in advance
+ -- not knowing the user count, so the user count
+ -- needs to be set to already allocated page
+
+ -- "Use count" value for the page to be allocated. If the page is to be
+ -- used by multiple output queues, each of them will attempt to free it.
+ -- read when alloc_i is HIGH
+ usecnt_alloc_i : in std_logic_vector(g_usecount_width-1 downto 0);
+
+ -- "Use count" value for the page already allocated. If the page is to be
+ -- used by multiple output queues, each of them will attempt to free it.
+ -- read when set_usecnt_i is HIGH
+ usecnt_set_i : in std_logic_vector(g_usecount_width-1 downto 0);
+
+ -- page address to be freed (uscnt descreased or deallocated when uscnt=1)
+ pgaddr_free_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+
+ -- page address to set its usecnt
+ pgaddr_usecnt_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+
+ -- the core is multiplexed between many ports, this is the information about
+ -- the currently handled port. The input vector is just delayed by 2 cycls and
+ -- outputd as output vector
+ req_vec_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rsp_vec_o : out std_logic_vector(g_num_ports-1 downto 0);
+
+ -- allocated page
+ pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+
+ free_last_usecnt_o : out std_logic;
+
+ done_o : out std_logic;
+ done_alloc_o : out std_logic;
+ done_usecnt_o : out std_logic;
+ done_free_o : out std_logic;
+ done_force_free_o : out std_logic;
+
+ -- indicate that there is no more pages left. We use some kind of Hysteresis here, or
+ -- in other words: the threshold for decideng on nomem going HIGH and LOW is different.
+ -- nomem goes HIGH when memory will be empty after accepting the first request on
+ -- the first cycle it is HIGH. Also it goes up at initialization
+ -- nomem goes LOW when there is more then 3*num_port number of free pages,
+ -- this prevents trashing, I need to check but 3 might be also because
+ -- of the number of resources...
+ nomem_o : out std_logic;
+
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- outputed when freeing
+ resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- used only when freeing page,
+ -- if HIGH then the input resource_i value will be used
+ -- if LOW then the value read from memory will be used (stored along with usecnt)
+ free_resource_valid_i : in std_logic;
+
+ -- number of pages added to the resource - understanding how counting the usage of
+ -- pages for different resources is (hell) tricky --> I have problems ... ;-p See
+ -- swc_alloc_resource_manager.vhd for details
+ rescnt_page_num_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+
+ -- valid when (done_o and usecnt_i) = HIGH
+ -- set_usecnt_succeeded_o = LOW ->> indicates that the usecnt was not set and the resources
+ -- were not moved from unknown to resource_o because there is
+ -- not enough resources
+ -- set_usecnt_succeeded_o = HIGH->> indicates that usecnt_i requres was handled successfully
+ set_usecnt_succeeded_o : out std_logic;
+
+
+ res_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
+
+ ----------------------------------------------------------------------
+
+ dbg_double_free_o : out std_logic;
+ dbg_double_force_free_o : out std_logic;
+ dbg_q_write_o : out std_logic;
+ dbg_q_read_o : out std_logic;
+ dbg_initializing_o : out std_logic
+ );
+
+end swc_page_allocator_new;
+
+architecture syn of swc_page_allocator_new is
+
+ -- convention used in the naming:
+ -- *_in - means that the signal is input
+ -- *_p0 or *_d0 - means that the signal is used in the first stage of the pipe
+ -- *_p1 or *_d1 - means that the signal is used in the second stage of the pipe
+ --
+ -- *_p0 or *_p1 - is a signal which results from some logic (either registered or not) or
+ -- output from RAM
+ -- *_p0 or *_p1 - is a registered signal - a copy with no chagnes
+
+ signal real_nomem, out_nomem : std_logic;
+
+ signal rd_ptr_p0 : unsigned(g_page_addr_width-1 downto 0);
+ signal wr_ptr_p1 : unsigned(g_page_addr_width-1 downto 0);
+ signal free_pages : unsigned(g_page_addr_width downto 0);
+
+ signal q_write_p1 : std_logic;
+ signal q_read_p0 : std_logic;
+ signal q_read_d1 : std_logic;
+
+ signal initializing : std_logic;
+
+
+ signal usecnt_addr_rd_p0 : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal usecnt_rddata_p1 : std_logic_vector(g_usecount_width-1 downto 0);
+ signal rescnt_rddata_p1 : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal ena_wr_p1_ram1, ena_wr_p1_ram2 : std_logic;
+ signal rddata_p1_ram1, rddata_p1_ram2 : std_logic_vector(g_usecount_width+1+g_resource_num_width-1 downto 0);
+ signal addr_wr_p1_ram1,addr_wr_p1_ram2 : std_logic_vector(g_page_addr_width-1 downto 0);
+
+ signal usecnt_wrdata_p1_ram1, usecnt_wrdata_p1_ram2 : std_logic_vector(g_usecount_width+1-1 downto 0);
+ signal rescnt_wrdata_p1_ram1, rescnt_wrdata_p1_ram2 : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal wrdata_p1_ram1, wrdata_p1_ram2 : std_logic_vector(g_usecount_width+1+g_resource_num_width-1 downto 0);
+
+ signal q_output_addr_p1 : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal q_input_addr_p1 : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal done_p1 : std_logic;
+ signal ram_ones : std_logic_vector(g_page_addr_width + g_usecount_width -1 downto 0);
+ signal free_last_usecnt : std_logic;
+
+ --debuggin sygnals
+ signal tmp_dbg_dealloc : std_logic; -- used for symulation debugging, don't remove
+ signal tmp_page : std_logic_vector(g_page_addr_width -1 downto 0);
+ signal free_blocks : unsigned(g_page_addr_width downto 0);
+ signal usecnt_not_zero : std_logic;
+ signal out_nomem_d0 : std_logic;
+ signal out_nomem_d1 : std_logic;
+
+ -------------------------- resource management
+ signal res_mgr_alloc : std_logic;
+ signal res_mgr_free : std_logic;
+ signal res_mgr_res_num : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal res_mgr_rescnt_set : std_logic;
+ signal set_usecnt_allowed_p1 : std_logic;
+ signal res_almost_full : std_logic_vector(g_resource_num -1 downto 0);
+ -----------------------------
+
+
+ type t_alloc_req is record
+ alloc : std_logic;
+ free : std_logic;
+ f_free : std_logic;
+ set_usecnt : std_logic;
+ usecnt_set : std_logic_vector(g_usecount_width-1 downto 0); -- input when setting usecnt
+ usecnt_alloc : std_logic_vector(g_usecount_width-1 downto 0); -- input when allocating usecnt
+ pgaddr_free : std_logic_vector(g_page_addr_width -1 downto 0);
+ pgaddr_usecnt : std_logic_vector(g_page_addr_width -1 downto 0);
+ grant_vec : std_logic_vector(g_num_ports-1 downto 0);
+ resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ free_res_valid : std_logic;
+ rescnt_page_num : std_logic_vector(g_page_addr_width -1 downto 0);
+ end record;
+
+ constant c_pipeline_depth : integer := 2;
+
+ type t_alloc_req_pipe is array(integer range <>) of t_alloc_req;
+ signal alloc_req_in : t_alloc_req;
+ signal alloc_req_d0 : t_alloc_req;
+ signal alloc_req_d1 : t_alloc_req;
+
+ constant alloc_req_zero : t_alloc_req := (
+ alloc => '0',
+ free => '0',
+ f_free => '0',
+ set_usecnt => '0',
+ usecnt_set => (others => '0'),
+ usecnt_alloc => (others => '0'),
+ pgaddr_free => (others => '0'),
+ pgaddr_usecnt => (others => '0'),
+ grant_vec => (others => '0'),
+ resource => (others => '0'),
+ free_res_valid => '0',
+ rescnt_page_num => (others => '0'));
+
+
+begin -- syn
+ ram_ones <= (others => '1');
+ alloc_req_in.alloc <= alloc_i;
+ alloc_req_in.free <= free_i;
+ alloc_req_in.f_free <= force_free_i;
+ alloc_req_in.set_usecnt <= set_usecnt_i;
+ alloc_req_in.usecnt_set <= usecnt_set_i;
+ alloc_req_in.usecnt_alloc <= usecnt_alloc_i;
+ alloc_req_in.pgaddr_free <= pgaddr_free_i;
+ alloc_req_in.pgaddr_usecnt <= pgaddr_usecnt_i;
+ alloc_req_in.grant_vec <= req_vec_i;
+ alloc_req_in.resource <= resource_i;
+ alloc_req_in.free_res_valid <= free_resource_valid_i;
+ alloc_req_in.rescnt_page_num<= rescnt_page_num_i;
+
+ p_pipe: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ alloc_req_d0 <= alloc_req_zero;
+ alloc_req_d1 <= alloc_req_zero;
+ else
+ alloc_req_d0 <= alloc_req_in;
+ alloc_req_d1 <= alloc_req_d0;
+ end if;
+ end if;
+
+ end process;
+
+ -- write queue when freeing and not initializing (because when initializing we use other
+ -- port of this memory)
+ q_write_p1 <= '1' when (alloc_req_d1.free = '1' and unsigned(usecnt_rddata_p1) = 1) or
+ (alloc_req_d1.f_free = '1') else initializing;
+
+ -- increase pointer to next address -> it stores next freee page, we use the currently read
+ -- and increase for next usage
+ -- The core accepts requsts which occure at the fist cycle of nomem HIGH -> this is because
+ -- we cannot stop once granted access based on the request in the previous cycle:
+ -- CLK : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|
+ -- alloc_in : _|----|_____ <= this request needs to be handled because granted access below
+ -- grant : ______|-|___ <= this grant needs to be handled
+ -- nomem : ______|-------
+ -- nomem_d0 : _______|-------
+ -- alloc_d0 " _______|-|____ <= this need to be handled
+ -- nomem_d1 : ________|-------
+ q_read_p0 <= '1' when (alloc_req_d0.alloc = '1') and (out_nomem_d1 = '0') else '0';
+
+ -- address of page stored in the memory (queue)
+ q_input_addr_p1 <= std_logic_vector(wr_ptr_p1) when initializing = '1' else alloc_req_d1.pgaddr_free;
+
+ -- memeory in which list of addresses of available pages is stored
+ -- rd_ptr points to the address of next available page_addr
+ -- wr_ptr points to the address where a freed page can be written
+ U_Queue_RAM : swc_rd_wr_ram
+ generic map (
+ g_data_width => g_page_addr_width,
+ g_size => 2**g_page_addr_width)
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ we_i => q_write_p1,
+ wa_i => std_logic_vector(wr_ptr_p1),
+ wd_i => q_input_addr_p1,
+ ra_i => std_logic_vector(rd_ptr_p0),
+ rd_o => q_output_addr_p1);
+
+ addr_wr_p1_ram1 <= std_logic_vector(rd_ptr_p0) when initializing = '1' else
+ q_output_addr_p1 when alloc_req_d1.alloc = '1' else
+ alloc_req_d1.pgaddr_free;
+
+
+ addr_wr_p1_ram2 <= std_logic_vector(rd_ptr_p0) when initializing = '1' else
+ alloc_req_d1.pgaddr_usecnt when alloc_req_d1.set_usecnt = '1' else
+ alloc_req_d1.pgaddr_free;
+
+
+ ena_wr_p1_ram1 <= alloc_req_d1.alloc or
+ alloc_req_d1.free or
+ alloc_req_d1.f_free or
+ initializing;
+
+ ena_wr_p1_ram2 <= (alloc_req_d1.set_usecnt and set_usecnt_allowed_p1) or
+ alloc_req_d1.free or -- zero when free (later RAM1 will be used)
+ alloc_req_d1.f_free or
+ initializing;
+
+ ----------------------------------- form write RAM data ------------------------------------
+ ----------------------------------- (a bit complex) ------------------------------------
+ usecnt_wrdata_p1_ram1 <= '1' & alloc_req_d1.usecnt_alloc when alloc_req_d1.alloc = '1' else
+ '0' & f_gen_dummy_vec('0', g_usecount_width) when alloc_req_d1.f_free = '1' else
+ '0' & f_gen_dummy_vec('0', g_usecount_width) when initializing = '1' else
+ '1' & std_logic_vector(unsigned(usecnt_rddata_p1) - 1);
+
+ usecnt_wrdata_p1_ram2 <= '1' & alloc_req_d1.usecnt_set when alloc_req_d1.set_usecnt = '1' else
+ '0' & f_gen_dummy_vec('0', g_usecount_width);
+
+ rescnt_wrdata_p1_ram1 <= alloc_req_d1.resource when (alloc_req_d1.alloc = '1' and alloc_req_d1.set_usecnt = '0') else
+ f_gen_dummy_vec('0', g_resource_num_width) ;
+ rescnt_wrdata_p1_ram2 <= alloc_req_d1.resource when alloc_req_d1.set_usecnt = '1' else
+ f_gen_dummy_vec('0', g_resource_num_width) ;
+
+ wrdata_p1_ram1 <= rescnt_wrdata_p1_ram1 & usecnt_wrdata_p1_ram1;
+ wrdata_p1_ram2 <= rescnt_wrdata_p1_ram2 & usecnt_wrdata_p1_ram2;
+
+ usecnt_addr_rd_p0 <= alloc_req_d0.pgaddr_free;
+
+ usecnt_rddata_p1 <= rddata_p1_ram2(g_usecount_width-1 downto 0) when (rddata_p1_ram2(g_usecount_width) = '1') else
+ rddata_p1_ram1(g_usecount_width-1 downto 0);
+
+ rescnt_rddata_p1 <= rddata_p1_ram2(g_resource_num_width+g_usecount_width downto g_usecount_width+1) when (rddata_p1_ram2(g_usecount_width) = '1') else
+ rddata_p1_ram1(g_resource_num_width+g_usecount_width downto g_usecount_width+1);
+
+ -- stores usecnts of pages, the addres is the page_addr (not ptr)
+ U_UseCnt_RAM_1 : swc_rd_wr_ram
+ generic map (
+ g_data_width => g_usecount_width+1+g_resource_num_width,
+ g_size => 2**g_page_addr_width)
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ we_i => ena_wr_p1_ram1,
+ wa_i => addr_wr_p1_ram1,
+ wd_i => wrdata_p1_ram1,--usecnt_wrdata_p1_ram1,
+ ra_i => usecnt_addr_rd_p0,
+ rd_o => rddata_p1_ram1);
+
+ -- stores usecnts of pages, the addres is the page_addr (not ptr)
+ U_UseCnt_RAM_2 : swc_rd_wr_ram
+ generic map (
+ g_data_width => g_usecount_width+1+g_resource_num_width,
+ g_size => 2**g_page_addr_width)
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ we_i => ena_wr_p1_ram2,
+ wa_i => addr_wr_p1_ram2,
+ wd_i => wrdata_p1_ram2,--usecnt_wrdata_p1_ram2,
+ ra_i => usecnt_addr_rd_p0,
+ rd_o => rddata_p1_ram2);
+
+ p_pointers : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ initializing <= '1';
+ rd_ptr_p0 <= (others => '0');
+ wr_ptr_p1 <= (others => '0');
+ real_nomem <= '0';
+ out_nomem_d0 <= '0';
+ out_nomem_d1 <= '0';
+ free_pages <= to_unsigned(g_num_pages-1, free_pages'length);
+ q_read_d1 <= '0';
+ else
+ q_read_d1 <= q_read_p0;
+ -- so.. we remember the outputed nomem info and use it later to process allocations
+ -- which happened in the first cycle of nomem output
+ out_nomem_d0 <= out_nomem;
+ out_nomem_d1 <= out_nomem_d0;
+
+ if(initializing = '1') then
+ if(wr_ptr_p1 = g_num_pages-1) then
+ initializing <= '0';
+ wr_ptr_p1 <= to_unsigned(g_num_pages-1, wr_ptr_p1'length);
+ else
+ wr_ptr_p1 <= wr_ptr_p1 + 1;
+ end if;
+ else
+ -- just increaing the pointerst to end/beginning of the queue
+ if(q_write_p1 = '1') then
+ wr_ptr_p1 <= wr_ptr_p1 + 1;
+ end if;
+
+ if(q_read_p0 = '1') then
+ rd_ptr_p0 <= rd_ptr_p0 + 1;
+ end if;
+
+ -- counting the usage of pages
+ if(q_write_p1 = '1' and q_read_p0 = '0') then
+ if(free_pages = 3) then
+ real_nomem <= '0';
+ end if;
+ free_pages <= free_pages + 1;
+ elsif (q_write_p1 = '0' and q_read_p0 = '1') then
+ if(free_pages = 3) then
+ real_nomem <= '1';
+ end if;
+ free_pages <= free_pages - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_gen_done : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if (rst_n_i = '0') or (initializing = '1') then
+ done_p1 <= '0';
+ else
+ if(((alloc_req_d0.alloc = '1' and out_nomem_d1 = '0') or
+ alloc_req_d0.set_usecnt = '1' or alloc_req_d0.free = '1' or
+ alloc_req_d0.f_free = '1') and initializing = '0') then
+ done_p1 <= '1';
+ else
+ done_p1 <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_gen_nomem_output : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ out_nomem <= '0';
+ else
+ if(out_nomem = '0' and (free_pages < to_unsigned(3, free_blocks'length))) then
+ out_nomem <= '1';
+ elsif(out_nomem = '1' and (free_pages > to_unsigned((3*g_num_ports), free_blocks'length))) then
+ out_nomem <= real_nomem;
+ end if;
+ end if;
+ end if;
+ end process;
+-- out_nomem <= real_nomem;
+ free_last_usecnt <= (not initializing) when (alloc_req_d1.free = '1' and unsigned(usecnt_rddata_p1) = 1) else '0';
+ pgaddr_o <= q_output_addr_p1;
+ done_o <= done_p1;
+ done_alloc_o <= done_p1 and alloc_req_d1.alloc;
+ done_usecnt_o <= done_p1 and alloc_req_d1.set_usecnt;
+ done_free_o <= done_p1 and alloc_req_d1.free;
+ done_force_free_o <= done_p1 and alloc_req_d1.f_free;
+ rsp_vec_o <= alloc_req_d1.grant_vec;
+ nomem_o <= out_nomem or initializing;
+ free_last_usecnt_o <= free_last_usecnt;
+
+ gen_no_RESOURCE_MGR: if (g_with_RESOURCE_MGR = false) generate
+ resource_o <= (others => '0');
+ set_usecnt_succeeded_o <= '1';
+ res_full_o <= (others => '0');
+ res_almost_full_o <= (others => '0');
+ dbg_o (g_page_addr_width+1-1 downto 0) <= std_logic_vector(free_pages);
+ dbg_o (g_num_dbg_vector_width-1 downto g_page_addr_width+1) <= (others =>'0');
+ set_usecnt_allowed_p1 <= '1';
+ end generate;
+
+ gen_RESOURCE_MGR: if (g_with_RESOURCE_MGR = true) generate
+ --------------------------------------------------------------------------------------------------
+ -- Resource Manager logic and instantiation
+ --------------------------------------------------------------------------------------------------
+ p_usecnt_set_allow : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ set_usecnt_allowed_p1 <= '0';
+ else
+ if(alloc_req_d0.set_usecnt ='1') then
+ if(res_almost_full(to_integer(unsigned(alloc_req_d0.resource))) = '1') then
+ -- not enough to accommodate max size frame, sorry we cannot serve the request
+ set_usecnt_allowed_p1 <= '0';
+ else
+ set_usecnt_allowed_p1 <= '1';
+ end if;
+ else
+ set_usecnt_allowed_p1 <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+ res_mgr_alloc <= alloc_req_d1.alloc and done_p1;
+ res_mgr_free <= ((alloc_req_d1.free and free_last_usecnt) or alloc_req_d1.f_free) and done_p1;
+ res_mgr_res_num <= rescnt_rddata_p1 when (alloc_req_d1.free_res_valid='0' and
+ (alloc_req_d1.free='1' or alloc_req_d1.f_free='1')) else
+ alloc_req_d1.resource;
+ res_mgr_rescnt_set <= done_p1 and alloc_req_d1.set_usecnt and set_usecnt_allowed_p1;
+
+ ------ resource management
+ RESOURCE_MANAGEMENT: swc_alloc_resource_manager
+ generic map(
+ g_num_ports => g_num_ports,
+ g_max_pck_size => g_max_pck_size,
+ g_page_size => g_page_size,
+ g_total_num_pages => g_num_pages,
+ g_total_num_pages_width => g_page_addr_width,
+ g_special_res_num_pages => g_special_res_num_pages,
+ g_resource_num => g_resource_num,
+ g_resource_num_width => g_resource_num_width,
+ g_num_dbg_vector_width => g_num_dbg_vector_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ resource_i => res_mgr_res_num,
+ alloc_i => res_mgr_alloc,
+ free_i => res_mgr_free,
+ rescnt_set_i => res_mgr_rescnt_set,
+ rescnt_page_num_i => alloc_req_d1.rescnt_page_num,
+ res_full_o => res_full_o,
+ res_almost_full_o => res_almost_full,
+ dbg_o => dbg_o
+ );
+
+ resource_o <= rescnt_rddata_p1;
+ set_usecnt_succeeded_o <= res_mgr_rescnt_set;
+ res_almost_full_o <= res_almost_full;
+ end generate;
+end syn;
diff --git a/modules/wrsw_swcore/swc_alloc_resource_manager.vhd b/modules/wrsw_swcore/swc_alloc_resource_manager.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dde3f64b2b760a37f5238ba81d86d93a2e46a5c3
--- /dev/null
+++ b/modules/wrsw_swcore/swc_alloc_resource_manager.vhd
@@ -0,0 +1,347 @@
+-------------------------------------------------------------------------------
+-- Title : Alloc Resource Manager
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_alloc_resource_manager.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2012-03-30
+-- Last update: 2012-03-30
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description:
+-- The available pool of pages can be divided into different resources, e.g:
+-- * there will be a reserved number of pages for WR High Priority Traffic
+-- * there will be a reserved number of pages for "standard" traffic
+--
+-- This module manages the count of the useage of different resources:
+--
+-- The pool of all pages is devided into [resource_num]:
+-- 1) [resource_num = 0]
+-- unknown resource: unknown_res = (port_number*(max_frame_size/(2*page_size)+2*port_number), where:
+-- max_frame_size is in bytes, i.e.: 1518 + oob
+-- 2*page_size is in bytes, i.e.: page_size is in 16bits
+-- (word written to FBM), so 2 bytes
+-- (max_frame_size/(2*page_size) is the number of pgaes used by max size frame
+-- 2*port_number is to be able to allocate in advance first page
+-- (pckstart_pageaddr) and intermediate page
+-- (pckinter_pageaddr) for each port
+--
+-- [requested number of separate resources, e.g]
+-- 2) [resource_num = 1]
+-- High priority traffic (e.g broadcast & 7th prio), e.g.: prio_res = page_num -(unknown_res/2)
+-- 3) [resource_num = 2]
+-- Standard traffic, e.g.: prio_res = page_num -(unknown_res/2)
+--
+-- If the resource is not known during allocation (which is very likely because we allocte
+-- pages in advance), the default resource number (unknown resource, [resource_num = 0])
+-- shall be used.
+--
+-- The information about the resource needs to be stored with the first page of the frame, the
+-- inter_pages does not need to store this info
+--
+-- If page is allocated and the resource number is known, it shall be indicated and an appropriate
+-- counter will be changes
+--
+-- If we make usecnt, it is used only for the first page of the frame. during usecnt also
+-- resource_cnt is done, which includes:
+-- * resource num - to which resource a provided page should be allocated
+-- * resource_cnt - how many pages from the unknown resource ([resource_num = 0]) shall be
+-- allocated to the new resource
+--
+-- In the input block the usecnt is set only for the first page, so this is also the "must" for
+-- resource number
+--
+-- The deallocating process (when deallocating the last usecnt), will receive the information that :
+-- * the usecnt is 0 (last_usecnt)
+-- * the resource number,
+-- so, when freeing the rest of the frame, it will indicate the resource number.
+--
+-- When freeing page, two sources of resource number can be used:
+-- * the one stored in the memory (when res_num_valid_i = LOW) - this should be used for
+-- the first page of the frame
+-- * the one provided by external soruce (when res_num_valid_i = HIGH) - this should be used for
+-- the inter-pages of the frame
+--
+--
+-- resource page count - tricky (!!!!)
+-- * the count is not really for the page being allocated by for the request for allocation
+-- * the pages are being requested in advance, so it would be hard to associate the
+-- the allocated page with the cnt because we allocate and later we use it or not for
+-- a given frame
+-- * however, when we receive frame, we do alloc requests (i.e. we had in advance allocated
+-- first page, we use it, and as soon as we can, we allcote again page in advance....)
+-- and we actually count how many alloc requets we did for a given frame, even if the pages
+-- we allocate now will be used for the next frame... -> it works, it seems
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012, Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-03-30 1.0 mlipinsk Created
+-- 2013-10-30 1.1 mlipinsk adapted to optimized alloc (alloc & usecnt at
+-- same time must be handled)
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.FLOOR;
+
+use work.swc_swcore_pkg.all;
+use work.genram_pkg.all;
+
+entity swc_alloc_resource_manager is
+ generic (
+
+ --
+ g_num_ports : integer ;
+
+ -- max pck size
+ g_max_pck_size : integer;
+
+ -- page size
+ g_page_size : integer;
+
+ -- number of pages in the allocator pool - total number of pages in all resource pools
+ g_total_num_pages : integer := 2048;
+
+ g_total_num_pages_width : integer := 11;
+
+ -- here we define the number of pages in a special resource pool [resource = 1]
+ g_special_res_num_pages : integer :=248;
+
+ -- number of separate resources, the number of areas the page pool is divided is always one more
+ -- (g_resource_num + 1) since we need to have a number of "unknown source" pages
+ g_resource_num : integer := 3; -- this include 1 for unknown
+
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer
+ );
+
+ port (
+ clk_i : in std_logic; -- clock & reset
+ rst_n_i : in std_logic;
+
+ -- indicates the resource to which the page shall be allocated or from which it shall be
+ -- deallocated (freed). it is used:
+ -- * when alloc_i HIGH - to indicate to which resource add single page
+ -- * when rescnt_set_i HIGH - to indicate to which resource set a number (rescnt_page_num_i)
+ -- pages from unknown (num=0) resource (regardless whether
+ -- alloc_i is HIGH or LOW
+ -- * when free_i HIGH - to indicate from which resource to substract a single page
+ --
+ -- When both, alloc_i and rescnt_set_i are HIGH, the resource_i is used by the latter
+ -- to re-allocate rescnt_page_num_i number of pages from the unknown resource (num=0) to
+ -- the resource_i resource. In such case, alloc_i allocates a single page to unknown
+ -- resource (num = 0). It might have been done more universal but I found it a waste
+ -- of resources, if such solution is sufficient.
+ --
+ resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- indicate that is allocated
+ alloc_i : in std_logic;
+
+ -- freeing (completely) page
+ free_i : in std_logic;
+
+ -- setting resource cnt to already allocated pages (strobe)
+ rescnt_set_i : in std_logic;
+
+ -- the of pages number to be added to the resource number indicated by resource_i (and
+ -- substracted from resource number=0 [unknown]). It is used only when rescnt_set_i is HIGH
+ -- (whether alloc_i is HIGH or LOW)
+ rescnt_page_num_i : in std_logic_vector(g_total_num_pages_width-1 downto 0);
+
+ res_full_o : out std_logic_vector(g_resource_num- 1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_resource_num- 1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
+ );
+
+end swc_alloc_resource_manager;
+
+architecture syn of swc_alloc_resource_manager is
+
+ -- the number of pages reserved for unknown source (happens because we allocate pages in advance
+ -- we don't know RTU decision when we do that, and sometimes we store pages before receiving
+ -- RTU decision). It should be enough for all the ports to receive single max_size frame and
+ -- all ports to be ready to receive new pcks
+ constant c_unknown_res_page_num : integer := integer(CEIL(real(g_num_ports * (g_max_pck_size/g_page_size)))) +
+ integer(g_num_ports * 2) ; --98
+
+ constant c_special_res_page_num : integer := g_special_res_num_pages; -- 256
+
+ -- we can have as many resources as we want, the division of the page pool is following:
+ -- 0) unknow resources : number of pages = c_unknown_res_page_num
+ -- 1) special resources : number of pages = c_special_res_page_num
+ -- 2) normal resources 1 : number of pages = (total - unknown - special)/(resource_num - 1)
+ -- 3) normal resources 2 : number of pages = (total - unknown - special)/(resource_num - 1)
+ -- [...]
+ constant c_normal_res_page_num : integer := integer(FLOOR(real((g_total_num_pages -
+ c_unknown_res_page_num -
+ c_special_res_page_num)/(g_resource_num-2)))); -- 670
+
+ -- tells how many pages we need to have for a single max ethernet frame to be stored in FBM
+ constant c_page_num_for_max_pck : integer := integer(CEIL(real(g_max_pck_size/g_page_size))); -- 12
+
+ type t_resource is record
+ cnt : unsigned(g_total_num_pages_width-1 downto 0);
+ full : std_logic;
+ almost_full : std_logic;
+ end record;
+
+ type t_resource_array is array(integer range <>) of t_resource;
+
+ signal resources : t_resource_array(g_resource_num-1 downto 0);
+ signal cur_res : integer range 0 to g_resource_num-1;
+
+ -- debugging;
+ signal res_page_sum : unsigned(g_total_num_pages_width-1 downto 0);
+ signal res_free_blocks : unsigned(g_total_num_pages_width-1 downto 0);
+
+begin
+
+ cur_res <= to_integer(unsigned(resource_i));
+
+ process(clk_i)
+ variable sum : unsigned(g_total_num_pages_width-1 downto 0);
+ begin
+
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+
+ for i in g_resource_num-1 downto 0 loop
+ resources(i).cnt <= (others => '0');
+ resources(i).full <= '0';
+ resources(i).almost_full <= '0';
+ end loop;
+
+ else
+ -----------------------------------------------------------------------------------------
+ -- "resource count set" is used to move a number of pages from "unknown" resources
+ -- to any other resource pool. Therefore, if the cur_res is different then "unknown" (0),
+ -- we subtract from unknown pool
+ -----------------------------------------------------------------------------------------
+
+ if(alloc_i = '1' and rescnt_set_i = '1') then
+ -- here we allocate the first page of frame, so it's always to unknown resource num=0
+ -- and we also, at the same time, set usecnt (i.e. take pages from unknown to other
+ -- resource), so we need to:
+ -- * add to the indicated resource (cur_res) the number of set pages
+ -- (rescnt_page_num_i) - rescnt_set request)
+ -- * add to the unknown resources a single page - allocation request
+ -- * substract from unknown resource the number of set pages (rescnt_page_num) and
+ -- add single page for the allocation
+ -- ... SIMPLE...;-p
+ if(cur_res = 0) then
+ resources(0).cnt <= resources(0).cnt + 1;
+ else
+ resources(0).cnt <= resources(0).cnt - unsigned(rescnt_page_num_i) + 1;
+ resources(cur_res).cnt <= resources(cur_res).cnt + unsigned(rescnt_page_num_i);
+ end if;
+ elsif(alloc_i = '1') then
+ -- we are allocating a page, it can be the first page (so unknow resource) but
+ -- it can also be inter-frame page (known resource...)
+ resources(cur_res).cnt <= resources(cur_res).cnt + 1;
+ elsif(free_i = '1') then
+ -- freeing page from some resource
+ resources(cur_res).cnt <= resources(cur_res).cnt - 1;
+ elsif(rescnt_set_i = '1') then
+ -- setting page usecnt and moving a number of pages from unknown resource to
+ -- a known one
+ resources(cur_res).cnt <= resources(cur_res).cnt + unsigned(rescnt_page_num_i);
+ if(cur_res /= 0) then
+ resources(0).cnt <= resources(0).cnt - unsigned(rescnt_page_num_i);
+ end if;
+ end if;
+
+ --------------------- generat ---------------------------------
+ -- control "unknown" resources
+ if(resources(0).cnt > to_unsigned(c_unknown_res_page_num - 1,g_total_num_pages_width)) then
+ resources(0).full <='1';
+ else
+ resources(0).full <= '0';
+ end if;
+ if(resources(0).cnt > to_unsigned(c_unknown_res_page_num - c_page_num_for_max_pck ,g_total_num_pages_width)) then
+ resources(0).almost_full <= '1';
+ else
+ resources(0).almost_full <= '0';
+ end if;
+
+ -- control special resources
+ if(resources(1).cnt > to_unsigned(c_special_res_page_num - 1,g_total_num_pages_width)) then
+ resources(1).full <='1';
+ else
+ resources(1).full <= '0';
+ end if;
+ if(resources(1).cnt > to_unsigned(c_special_res_page_num - c_page_num_for_max_pck, g_total_num_pages_width)) then
+ resources(1).almost_full <= '1';
+ else
+ resources(1).almost_full <= '0';
+ end if;
+
+ -- control "normal" resources
+ for i in 2 to g_resource_num-1 loop
+ if(resources(i).cnt > to_unsigned(c_normal_res_page_num - 1,g_total_num_pages_width)) then
+ resources(i).full <='1';
+ else
+ resources(i).full <='0';
+ end if;
+ if(resources(i).cnt > to_unsigned(c_normal_res_page_num - c_page_num_for_max_pck, g_total_num_pages_width)) then
+ resources(i).almost_full <= '1';
+ else
+ resources(i).almost_full <= '0';
+ end if;
+ end loop;
+
+ ------------------------------ debug: ----------------------------------------
+ sum := to_unsigned(0, g_total_num_pages_width);
+ for i in 0 to g_resource_num-1 loop
+ sum := sum + resources(i).cnt;
+ end loop;
+ res_page_sum <= sum;
+ res_free_blocks <= to_unsigned(1024, g_total_num_pages_width) - sum;
+ -------------------------------------------------------------------------------
+ end if;
+ end if;
+
+ end process;
+
+ FULL_OUT: for i in 0 to g_resource_num-1 generate
+ res_full_o(i) <= resources(i).full;
+ res_almost_full_o(i) <= resources(i).almost_full;
+ end generate FULL_OUT;
+
+ -- debugging stuff
+ GEN_DEBUG: if ((g_total_num_pages_width*g_resource_num) <= g_num_dbg_vector_width) generate
+ DBG: for i in 0 to g_resource_num-1 generate
+ dbg_o((i+1)*g_total_num_pages_width-1 downto i*g_total_num_pages_width) <= std_logic_vector(resources(i).cnt);
+ end generate DBG;
+ end generate GEN_DEBUG;
+ GEN_NO_DEBUG: if ((g_total_num_pages_width*g_resource_num) > g_num_dbg_vector_width) generate
+ dbg_o <= (others =>'0');
+ assert true report "g_num_dbg_vector_width to small for the defined number debug bits";
+ end generate GEN_NO_DEBUG;
+
+
+end syn;
diff --git a/modules/wrsw_swcore/swc_core.vhd b/modules/wrsw_swcore/swc_core.vhd
index 328fa222465deebec868341ca24a594a77e70a67..0c52efc7987cb905a8c21e036c068031248110e7 100644
--- a/modules/wrsw_swcore/swc_core.vhd
+++ b/modules/wrsw_swcore/swc_core.vhd
@@ -55,12 +55,13 @@ use work.wrsw_shared_types_pkg.all;
entity swc_core is
generic(
g_prio_num : integer ;--:= c_swc_output_prio_num;
+ g_output_queue_num : integer ;
g_max_pck_size : integer ;--:= 2^c_swc_max_pck_size
g_max_oob_size : integer ;
g_num_ports : integer ;--:= c_swc_num_ports
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
- g_output_block_per_prio_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
+ g_output_block_per_queue_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
-- new
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
@@ -70,7 +71,10 @@ entity swc_core is
g_mpm_page_size : integer ;
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
- g_mpm_fetch_next_pg_in_advance : boolean
+ g_mpm_fetch_next_pg_in_advance : boolean ;
+ g_drop_outqueue_head_on_full : boolean ;
+ g_num_global_pause : integer ;
+ g_num_dbg_vector_width : integer
);
port (
clk_i : in std_logic;
@@ -105,7 +109,7 @@ entity swc_core is
src_ack_i : in std_logic_vector( g_num_ports-1 downto 0);
src_err_i : in std_logic_vector( g_num_ports-1 downto 0);
--------------------------------------------------------------------------------
+------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
@@ -113,8 +117,29 @@ entity swc_core is
rtu_rsp_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
rtu_dst_port_mask_i : in std_logic_vector(g_num_ports * g_num_ports - 1 downto 0);
rtu_drop_i : in std_logic_vector(g_num_ports - 1 downto 0);
- rtu_prio_i : in std_logic_vector(g_num_ports * integer(CEIL(LOG2(real(g_prio_num-1)))) - 1 downto 0)
+ rtu_prio_i : in std_logic_vector(g_num_ports * integer(CEIL(LOG2(real(g_prio_num-1)))) - 1 downto 0);
+
+------------------------------------------------------------------------------
+-- I/F global pause
+-------------------------------------------------------------------------------
+
+ gp_req_i : in std_logic_vector(g_num_global_pause - 1 downto 0);
+ gp_quanta_i : in std_logic_vector(g_num_global_pause*16 - 1 downto 0);
+ gp_classes_i : in std_logic_vector(g_num_global_pause*8 - 1 downto 0);
+ gp_ports_i : in std_logic_vector(g_num_global_pause*g_num_ports- 1 downto 0);
+------------------------------------------------------------------------------
+-- I/F per port
+-------------------------------------------------------------------------------
+ pp_req_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ pp_quanta_i : in std_logic_vector(g_num_ports*16 - 1 downto 0);
+ pp_classes_i : in std_logic_vector(g_num_ports*8 - 1 downto 0);
+------------------------------------------------------------------------------
+-- I/F misc
+-------------------------------------------------------------------------------
+
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width -1 downto 0);
+ shaper_drop_at_hp_ena_i : in std_logic
);
end swc_core;
@@ -126,20 +151,22 @@ architecture rtl of swc_core is
signal src_i : t_wrf_source_in_array(g_num_ports-1 downto 0);
signal src_o : t_wrf_source_out_array(g_num_ports-1 downto 0);
- signal rtu_rsp_i : t_rtu_response_array(g_num_ports - 1 downto 0);
-
+ signal rtu_rsp_i : t_rtu_response_array(g_num_ports - 1 downto 0);
+ signal global_pause_i : t_global_pause_request_array(g_num_global_pause-1 downto 0);
+ signal perport_pause_i : t_pause_request_array(g_num_ports-1 downto 0);
begin --rtl
xswcore: xswc_core
generic map(
g_prio_num => g_prio_num,
+ g_output_queue_num => g_output_queue_num,
g_max_pck_size => g_max_pck_size,
g_max_oob_size => g_max_oob_size,
g_num_ports => g_num_ports,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
g_input_block_cannot_accept_data => g_input_block_cannot_accept_data,
- g_output_block_per_prio_fifo_size => g_output_block_per_prio_fifo_size,
+ g_output_block_per_queue_fifo_size => g_output_block_per_queue_fifo_size,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
@@ -149,7 +176,10 @@ architecture rtl of swc_core is
g_mpm_page_size => g_mpm_page_size,
g_mpm_ratio => g_mpm_ratio,
g_mpm_fifo_size => g_mpm_fifo_size,
- g_mpm_fetch_next_pg_in_advance => g_mpm_fetch_next_pg_in_advance
+ g_mpm_fetch_next_pg_in_advance => g_mpm_fetch_next_pg_in_advance,
+ g_drop_outqueue_head_on_full => g_drop_outqueue_head_on_full,
+ g_num_global_pause => g_num_global_pause,
+ g_num_dbg_vector_width => g_num_dbg_vector_width
)
port map(
clk_i => clk_i,
@@ -161,7 +191,14 @@ architecture rtl of swc_core is
src_i => src_i,
src_o => src_o,
-
+
+ shaper_drop_at_hp_ena_i => shaper_drop_at_hp_ena_i,
+
+ global_pause_i => global_pause_i,
+ perport_pause_i=> perport_pause_i,
+
+ dbg_o => dbg_o,
+
rtu_rsp_i => rtu_rsp_i,
rtu_ack_o => rtu_rsp_ack_o
);
@@ -190,9 +227,23 @@ architecture rtl of swc_core is
src_i(i).err <= src_err_i(i);
rtu_rsp_i(i).valid <= rtu_rsp_valid_i(i);
- rtu_rsp_i(i).port_mask(g_num_ports - 1 downto 0) <= rtu_dst_port_mask_i((i+1)*g_num_ports - 1downto i*g_num_ports);
+ rtu_rsp_i(i).port_mask(g_num_ports - 1 downto 0) <= rtu_dst_port_mask_i((i+1)*g_num_ports - 1 downto i*g_num_ports);
rtu_rsp_i(i).drop <= rtu_drop_i(i);
rtu_rsp_i(i).prio(integer(CEIL(LOG2(real(g_prio_num-1)))) - 1 downto 0) <= rtu_prio_i((i+1)*integer(CEIL(LOG2(real(g_prio_num-1)))) -1 downto i*integer(CEIL(LOG2(real(g_prio_num-1)))));
+
+ perport_pause_i(i).req <= pp_req_i(i);
+ perport_pause_i(i).quanta <= pp_quanta_i((i+1)*16-1 downto i*16);
+ perport_pause_i(i).classes <= pp_classes_i((i+1)*8-1 downto i*8);
+
end generate;
+ vectorize_gp: for i in 0 to g_num_global_pause-1 generate
+
+ global_pause_i(i).req <= gp_req_i(i);
+ global_pause_i(i).quanta <= gp_quanta_i((i+1)*16-1 downto i*16);
+ global_pause_i(i).classes <= gp_classes_i((i+1)*8-1 downto i*8);
+ global_pause_i(i).ports(g_num_ports-1 downto 0) <= gp_ports_i((i+1)*g_num_ports-1 downto i*g_num_ports);
+
+ end generate;
+
end rtl;
diff --git a/modules/wrsw_swcore/swc_ll_read_data_validation.vhd b/modules/wrsw_swcore/swc_ll_read_data_validation.vhd
index 9dc33e9477c6e6b25958a998641a68283583fc3c..3180dc66d45dfa9e0feffb108ffcd2dfa6be17e2 100644
--- a/modules/wrsw_swcore/swc_ll_read_data_validation.vhd
+++ b/modules/wrsw_swcore/swc_ll_read_data_validation.vhd
@@ -114,7 +114,7 @@ begin
-- the data being written to the Linked List DPRAM is what we are wating for and it's valid.
valid_data_write <= '1' when (read_addr_i = write_addr_i and write_data_valid_i = '1' and write_data_ready_i = '1') else '0';
- process(clk_i, rst_n_i)
+ process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
diff --git a/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd b/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
index 4b77fd8e63833402d9a5685ecafe44c6906a61f1..57b3e5c69e845c5c4a2dd187a93c841ad52f64db 100644
--- a/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
+++ b/modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
@@ -53,35 +53,41 @@ entity swc_multiport_pck_pg_free_module is
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
- g_data_width : integer
+ g_data_width : integer ;
+ g_resource_num_width : integer
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
- ib_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
- ib_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
- ib_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
+ ib_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
+ ib_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
+ ib_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
- ob_free_i : in std_logic_vector(g_num_ports-1 downto 0);
- ob_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
- ob_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
+ ob_free_i : in std_logic_vector(g_num_ports-1 downto 0);
+ ob_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
+ ob_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
- ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
- ll_read_data_i : in std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
- --ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
- ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
- ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
-
- mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
- mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
- mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
- mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
-
-
- mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
- mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
- mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
+ ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+ ll_read_data_i : in std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
+ --ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
+ ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
+ ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
+
+ mmu_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
+
+ mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
+ mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+ mmu_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
+ mmu_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
+
+ mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
+ mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+ mmu_force_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
+ mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0)
);
end swc_multiport_pck_pg_free_module;
@@ -97,36 +103,42 @@ begin -- syn
LPD: swc_pck_pg_free_module
generic map(
- g_page_addr_width => g_page_addr_width,
- g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
- g_data_width => g_data_width
+ g_page_addr_width => g_page_addr_width,
+ g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
+ g_data_width => g_data_width,
+ g_resource_num_width => g_resource_num_width
)
port map(
- clk_i => clk_i,
- rst_n_i => rst_n_i,
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
- ib_force_free_i => ib_force_free_i(i),
- ib_force_free_done_o => ib_force_free_done_o(i),
- ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
+ ib_force_free_i => ib_force_free_i(i),
+ ib_force_free_done_o => ib_force_free_done_o(i),
+ ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
- ob_free_i => ob_free_i(i),
- ob_free_done_o => ob_free_done_o(i),
- ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
+ ob_free_i => ob_free_i(i),
+ ob_free_done_o => ob_free_done_o(i),
+ ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
- ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
- ll_read_data_i => ll_read_data_i((i+1)*g_data_width - 1 downto i * g_data_width),
- ll_read_req_o => ll_read_req_o(i),
- ll_read_valid_data_i => ll_read_valid_data_i(i),
-
- mmu_free_o => mmu_free_o(i),
- mmu_free_done_i => mmu_free_done_i(i),
- mmu_free_last_usecnt_i => mmu_free_last_usecnt_i(i),
- mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
-
- mmu_force_free_o => mmu_force_free_o(i),
- mmu_force_free_done_i => mmu_force_free_done_i(i),
- mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width)
-
+ ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
+ ll_read_data_i => ll_read_data_i((i+1)*g_data_width - 1 downto i * g_data_width),
+ ll_read_req_o => ll_read_req_o(i),
+ ll_read_valid_data_i => ll_read_valid_data_i(i),
+
+ mmu_resource_i => mmu_resource_i((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
+
+ mmu_free_o => mmu_free_o(i),
+ mmu_free_done_i => mmu_free_done_i(i),
+ mmu_free_last_usecnt_i => mmu_free_last_usecnt_i(i),
+ mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
+ mmu_free_resource_o => mmu_free_resource_o((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
+ mmu_free_resource_valid_o => mmu_free_resource_valid_o(i),
+
+ mmu_force_free_o => mmu_force_free_o(i),
+ mmu_force_free_done_i => mmu_force_free_done_i(i),
+ mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
+ mmu_force_free_resource_o => mmu_force_free_resource_o((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
+ mmu_force_free_resource_valid_o => mmu_force_free_resource_valid_o(i)
);
end generate lpd_gen;
diff --git a/modules/wrsw_swcore/swc_ob_prio_queue.vhd b/modules/wrsw_swcore/swc_ob_prio_queue.vhd
index edf4068c821e4d30c12e4cbda5cc76514eb500a6..5f4fc5bac521c6531dcc6999ee842ec5f24f97a0 100644
--- a/modules/wrsw_swcore/swc_ob_prio_queue.vhd
+++ b/modules/wrsw_swcore/swc_ob_prio_queue.vhd
@@ -48,7 +48,7 @@ use work.swc_swcore_pkg.all;
entity swc_ob_prio_queue is
generic(
- g_per_prio_fifo_size_width : integer --:= c_swc_output_fifo_addr_width
+ g_per_queue_fifo_size_width : integer --:= c_swc_output_fifo_addr_width
);
port (
clk_i : in std_logic;
@@ -69,8 +69,8 @@ entity swc_ob_prio_queue is
-------------------------------------------------------------------------------
wr_en_o : out std_logic;
- wr_addr_o : out std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
- rd_addr_o : out std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0)
+ wr_addr_o : out std_logic_vector(g_per_queue_fifo_size_width - 1 downto 0);
+ rd_addr_o : out std_logic_vector(g_per_queue_fifo_size_width - 1 downto 0)
);
end swc_ob_prio_queue;
@@ -78,8 +78,8 @@ end swc_ob_prio_queue;
architecture behavoural of swc_ob_prio_queue is
- signal head : std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
- signal tail : std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
+ signal head : std_logic_vector(g_per_queue_fifo_size_width - 1 downto 0);
+ signal tail : std_logic_vector(g_per_queue_fifo_size_width - 1 downto 0);
signal not_full : std_logic;
signal not_empty : std_logic;
diff --git a/modules/wrsw_swcore/swc_output_queue_scheduler.vhd b/modules/wrsw_swcore/swc_output_queue_scheduler.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ae734f674b3977fa35585cdd19b0bad78c6bff16
--- /dev/null
+++ b/modules/wrsw_swcore/swc_output_queue_scheduler.vhd
@@ -0,0 +1,157 @@
+-------------------------------------------------------------------------------
+-- Title : Output queue scheduler
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_output_queue_scheduler.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2012-04-19
+-- Last update: 2012-04-19
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: this module implements output queue scheduling algorithms
+-- currently the strict priority policy is used
+--
+-- This module schedules two "processes":
+-- 1) sending - decides the queue from which the next frame shall be sent
+-- 2) dropping - decides the queue from which the oldest frame shall be dropped if more then
+-- single queue is full (very unlikely)
+--
+-- ---------------
+-- ad 1 (sending)
+-- ---------------
+-- On the input we receive a vector which indicates which output queues are not empty
+-- if the vector is 010100, it means that output queues number 2 and 4 have something to be sent.
+--
+-- the mapping of queues (so, what actually goes to each queue) is defined elsewhere, in
+-- swc_swcore_pkg.vhd in function: f_map_rtu_rsp_to_mmu_res().
+--
+-- > currenlty the strict scheduling policy is implemented: we always send the next frame from the <
+-- > higherst queue (presumably, with the higherst priority, but this depends on mapping) <
+--
+-- ---------------
+-- ad 2 (dropping)
+-- ---------------
+-- on the input we receive a vector which indicates which output queues are full
+-- if the vector is 010100, it means that output queues 2 and 4 are full
+--
+-- > currently, we always drop in the first place a frame from the lowest full queue, this means <
+-- > that for dropping we use also strict scheduling but reverse order compared to the sending <
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-04-19 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.swc_swcore_pkg.all;
+
+entity swc_output_queue_scheduler is
+
+ generic (
+ g_queue_num : integer range 2 to 64 := 32;
+ g_queue_num_width : integer range 1 to 6 := 5);
+ port (
+
+ -- not needed in the simple implementation of strict priority
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ----------------- reading head of the queue -----------------------
+ -- indicates which output queues are not empty
+ not_empty_array_i : in std_logic_vector(g_queue_num-1 downto 0);
+
+ -- index of the next output queue to read
+ read_queue_index_o : out std_logic_vector(g_queue_num_width-1 downto 0);
+
+ -- vector with '1' at the position of the output queue to read
+ read_queue_onehot_o: out std_logic_vector(g_queue_num-1 downto 0);
+
+ ----------------- dropping head of the queue -----------------------
+ full_array_i : in std_logic_vector(g_queue_num-1 downto 0);
+
+ -- index of the queue in which the first (head) data shall be dropped
+ drop_queue_index_o : out std_logic_vector(g_queue_num_width-1 downto 0);
+
+ -- vector with '1' at the possition(index) of the queue in which the first (head)
+ -- data shall be dropped
+ drop_queue_onehot_o: out std_logic_vector(g_queue_num-1 downto 0)
+ );
+
+end swc_output_queue_scheduler;
+
+architecture syn of swc_output_queue_scheduler is
+
+ signal not_empty_array : std_logic_vector(g_queue_num-1 downto 0);
+ signal queue_index : std_logic_vector(g_queue_num_width-1 downto 0);
+ signal queue_onehot : std_logic_vector(g_queue_num-1 downto 0);
+
+begin
+
+ ------------------------------------------------------------------------------------------
+ ------------------------------------- READ -----------------------------------------------
+ ------------------------------------------------------------------------------------------
+
+ -- converting so that I can use the swc_prio_encoder module as-is
+ L0: for i in 0 to g_queue_num-1 generate
+ not_empty_array(i) <= not_empty_array_i(g_queue_num - 1 - i);
+ read_queue_onehot_o(i) <= queue_onehot (g_queue_num - 1 - i);
+ end generate;
+
+ read_queue_index_o <= not queue_index;
+
+ -- strict priority scheduling for reading from output queues
+ READ_STRICT_PRIORIY_POLICY : swc_prio_encoder
+ generic map (
+ g_num_inputs => g_queue_num,
+ g_output_bits => g_queue_num_width)
+ port map (
+ in_i => not_empty_array,
+ onehot_o => queue_onehot,
+ out_o => queue_index);
+
+ ------------------------------------------------------------------------------------------
+ ------------------------------------- DROP -----------------------------------------------
+ ------------------------------------------------------------------------------------------
+
+ -- (reverted) strict priority scheduling for dropping frames if output queues
+ -- are full. It means that if all the queues are full, we will first drop frames from the
+ -- lowest (priority) queue. this is because, this one will get emptied by the sedning
+ -- mechanims in the last place..
+ DROP_STRICT_PRIORIY_POLICY : swc_prio_encoder
+ generic map (
+ g_num_inputs => g_queue_num,
+ g_output_bits => g_queue_num_width)
+ port map (
+ in_i => full_array_i,
+ onehot_o => drop_queue_onehot_o,
+ out_o => drop_queue_index_o);
+
+end syn;
\ No newline at end of file
diff --git a/modules/wrsw_swcore/swc_output_traffic_shaper.vhd b/modules/wrsw_swcore/swc_output_traffic_shaper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d6ba9299fc45cfda56e50f3f69041b8d9a1d66f8
--- /dev/null
+++ b/modules/wrsw_swcore/swc_output_traffic_shaper.vhd
@@ -0,0 +1,198 @@
+-------------------------------------------------------------------------------
+-- Title : Output Traffic Shaper
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_output_traffic_shaper.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2013-02-26
+-- Last update: 2013-04-26
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module produces masks used for blocking output traffic
+-- on different output queues (classes). It implements two functionalities:
+-- * per-priority (CoS) PAUSE
+-- * time-aware-shaping (allow only chosen output queues for given time)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2013-02-026 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.swc_swcore_pkg.all;
+use work.wrsw_shared_types_pkg.all;
+
+entity swc_output_traffic_shaper is
+
+ generic (
+ g_num_ports : integer := 32;
+ g_num_global_pause : integer := 2
+ );
+
+ port (
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ -------------------------------------------------------------------------------
+ -- per-port PAUSE request
+ -- * semi-priority-based - defines which priorities (output queues) to block
+ -- * has the same pause time (quanta) for all priorities
+ -- * expected to come from Endpoints which parse PAUSE frames and provide info
+ -------------------------------------------------------------------------------
+ perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
+
+ -------------------------------------------------------------------------------
+ -- global PAUSE request
+ -- * semi-priority-based - defines which priorities (output queues) to block
+ -- * has the same pause time (quanta) for all priorities
+ -- * a single pause for a number of indicated ports:
+ -- we say which priorities on which ports shall be blocked (globally)
+ -- * many modules can huck to this - it's an array of global PAUSEs
+ -------------------------------------------------------------------------------
+ global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
+
+ -------------------------------------------------------------------------------
+ -- Masks (per-port) which are used to block the output queues:
+ -- * '1' indicates that a queue of class X shall be blocked
+ -- * 'by default 0000...00 (no queues blocked)
+ -------------------------------------------------------------------------------
+ output_masks_o : out t_classes_array(g_num_ports-1 downto 0)
+ );
+end swc_output_traffic_shaper;
+
+architecture syn of swc_output_traffic_shaper is
+
+ type t_pause_array is array(integer range <>) of unsigned(15 downto 0);
+
+ signal div512 : unsigned(4 downto 0);
+ signal advance_counter : std_logic;
+
+ -- per-port pause
+ signal pp_pause_counters : t_pause_array(g_num_ports-1 downto 0);
+ signal pp_pause_classes : t_classes_array(g_num_ports-1 downto 0);
+
+ -- global pause
+ signal gl_pause_counters : t_pause_array(g_num_global_pause-1 downto 0);
+ signal gl_pause_classes : t_classes_array(g_num_global_pause-1 downto 0);
+ signal gl_pause_ports : t_ports_masks(g_num_global_pause-1 downto 0);
+ signal zeros : std_logic_vector(15 downto 0);
+
+begin -- behavioral
+
+ zeros <= (others =>'0');
+ -- process to generate "tic" every "quanta" whic is equal to 512 bit times
+ -- (62.5MHz => 16ns cycle, each processing 16 bit word, 512/16 = 32 = 2^5.
+ -- This tic is used by the rest of processes
+ gen_pause_timing : process (clk_i, rst_n_i)
+ begin -- process
+ if rising_edge(clk_i) then
+ if (rst_n_i = '0') then
+ div512 <= (others => '0');
+ advance_counter <= '0';
+ else
+ div512 <= div512 + 1;
+ if(div512 = to_unsigned(0, div512'length)) then
+ advance_counter <= '1';
+ else
+ advance_counter <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- generating per-port PAUSE
+ per_port_pause: for i in 0 to g_num_ports-1 generate
+ -- per-port process to handle (class selectable) pause =
+ pp_pause_proc : process (clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ pp_pause_counters(i) <= (others => '0');
+ pp_pause_classes(i) <= (others => '0');
+ else
+ if (perport_pause_i(i).req = '1') then
+ pp_pause_counters(i) <= unsigned(perport_pause_i(i).quanta);
+ if(perport_pause_i(i).quanta = zeros) then -- resetting PAUSE
+ pp_pause_classes(i) <= (others =>'0');
+ else
+ pp_pause_classes(i) <= perport_pause_i(i).classes;
+ end if;
+ elsif (advance_counter = '1') then
+ if(pp_pause_counters(i) = to_unsigned(0, pp_pause_counters(i)'length)) then
+ pp_pause_classes(i) <= (others => '0');
+ else
+ pp_pause_counters(i) <= pp_pause_counters(i) - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate per_port_pause;
+
+ -- generating a configurable (generic) number of global pauses
+ global_pause: for i in 0 to g_num_global_pause -1 generate
+ gl_pause_proc : process (clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ gl_pause_counters(i) <= (others => '0');
+ gl_pause_classes(i) <= (others => '0');
+ gl_pause_ports(i) <= (others => '0');
+ else
+ if (global_pause_i(i).req = '1') then
+ gl_pause_counters(i) <= unsigned(global_pause_i(i).quanta);
+ if(global_pause_i(i).quanta = zeros) then -- resetting PAUSE
+ gl_pause_classes(i) <= (others => '0');
+ gl_pause_ports(i) <= (others => '0');
+ else
+ gl_pause_classes(i) <= global_pause_i(i).classes;
+ gl_pause_ports(i) <= global_pause_i(i).ports;
+ end if;
+ elsif (advance_counter = '1') then
+ if(gl_pause_counters(i) = to_unsigned(0, gl_pause_counters(i)'length)) then
+ gl_pause_classes(i) <= (others => '0');
+ gl_pause_ports(i) <= (others => '0');
+ else
+ gl_pause_counters(i) <= gl_pause_counters(i) - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate global_pause;
+
+ -- generating final masks to be used on different swcore's ports to decide which
+ -- queue shall be used for next forward
+ gen_output_masks: for i in 0 to g_num_ports-1 generate
+ output_masks_o(i) <= pp_pause_classes(i) or
+ f_global_pause_mask(gl_pause_classes,gl_pause_ports, i, g_num_global_pause);
+ end generate gen_output_masks;
+
+end syn;
diff --git a/modules/wrsw_swcore/swc_pck_pg_free_module.vhd b/modules/wrsw_swcore/swc_pck_pg_free_module.vhd
index 5c5ed1bd5584d0062ab0c9475a0be6f1eaebbd87..33358ce9d33a29800172e0f2cc3f2227de620125 100644
--- a/modules/wrsw_swcore/swc_pck_pg_free_module.vhd
+++ b/modules/wrsw_swcore/swc_pck_pg_free_module.vhd
@@ -55,33 +55,40 @@ entity swc_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
- g_data_width : integer
+ g_data_width : integer ;
+ g_resource_num_width : integer
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
- ib_force_free_i : in std_logic;
- ib_force_free_done_o : out std_logic;
- ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
+ ib_force_free_i : in std_logic;
+ ib_force_free_done_o : out std_logic;
+ ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
- ob_free_i : in std_logic;
- ob_free_done_o : out std_logic;
- ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
+ ob_free_i : in std_logic;
+ ob_free_done_o : out std_logic;
+ ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
- ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
- ll_read_data_i : in std_logic_vector(g_data_width - 1 downto 0);
- ll_read_req_o : out std_logic;
- ll_read_valid_data_i : in std_logic;
-
- mmu_free_o : out std_logic;
- mmu_free_done_i : in std_logic;
- mmu_free_last_usecnt_i : in std_logic;
- mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ ll_read_data_i : in std_logic_vector(g_data_width - 1 downto 0);
+ ll_read_req_o : out std_logic;
+ ll_read_valid_data_i : in std_logic;
+
+ mmu_resource_i : in std_logic_vector(g_resource_num_width -1 downto 0);
+
+ mmu_free_o : out std_logic;
+ mmu_free_done_i : in std_logic;
+ mmu_free_last_usecnt_i : in std_logic;
+ mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ mmu_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
+ mmu_free_resource_valid_o : out std_logic;
- mmu_force_free_o : out std_logic;
- mmu_force_free_done_i : in std_logic;
- mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
+ mmu_force_free_o : out std_logic;
+ mmu_force_free_done_i : in std_logic;
+ mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ mmu_force_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
+ mmu_force_free_resource_valid_o : out std_logic
);
@@ -125,8 +132,16 @@ architecture syn of swc_pck_pg_free_module is
signal ones : std_logic_vector(g_page_addr_width - 1 downto 0);
signal freeing_mode : std_logic_vector(1 downto 0);
- signal fifo_clear_n : std_logic;
- signal eof : std_logic;
+ signal fifo_clear_n : std_logic;
+ signal eof : std_logic;
+
+ signal free_resource : std_logic_vector(g_resource_num_width -1 downto 0);
+ signal free_resource_valid : std_logic;
+
+ signal force_free_resource : std_logic_vector(g_resource_num_width -1 downto 0);
+ signal force_free_resource_valid : std_logic;
+
+
begin -- syn
@@ -219,6 +234,12 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_free <= '0';
freeing_mode <= (others => '0');
eof <= '0';
+
+ free_resource <= (others => '0');
+ free_resource_valid <= '0';
+
+ force_free_resource <= (others => '0');
+ force_free_resource_valid <= '0';
--================================================
else
@@ -231,6 +252,11 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_force_free <= '0';
mmu_free <= '0';
eof <= '0';
+ free_resource <= (others => '0');
+ free_resource_valid <= '0';
+ force_free_resource <= (others => '0');
+ force_free_resource_valid <= '0';
+
if(fifo_empty = '0') then
fifo_rd <= '1';
@@ -309,6 +335,13 @@ fsm_force_free : process(clk_i, rst_n_i)
--current_page <= next_page;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
+
+ -- the first page only
+ if(free_resource_valid = '0') then
+ free_resource <= mmu_resource_i ;
+ free_resource_valid <= '1';
+ end if;
+
end if;
end if;
@@ -329,6 +362,12 @@ fsm_force_free : process(clk_i, rst_n_i)
--current_page <= next_page;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
+
+ -- the first page only
+ if(free_resource_valid = '0') then
+ free_resource <= mmu_resource_i ;
+ free_resource_valid <= '1';
+ end if;
end if;
end if;
@@ -363,5 +402,11 @@ fsm_force_free : process(clk_i, rst_n_i)
ib_force_free_done_o <= ib_force_free_done;
ob_free_done_o <= ob_free_done;
-
+ mmu_free_resource_o <= free_resource;
+ mmu_free_resource_valid_o <= free_resource_valid;
+
+ mmu_force_free_resource_o <= force_free_resource;
+ mmu_force_free_resource_valid_o <= force_free_resource_valid;
+
+
end syn;
diff --git a/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd b/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
index 125b40e6408b24bbcc0cc72e615d094dabff37a0..0c73e6e8aafb2e1f7db672733cea5a06403d5b13 100644
--- a/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
+++ b/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
--- Last update: 2012-02-02
+-- Last update: 2013-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -36,6 +36,7 @@
-- Date Version Author Description
-- 2010-11-03 1.0 mlipinsk created
-- 2012-02-02 2.0 mlipinsk generic-azed
+-- 2013-03-05 2.1 mlipinsk added hp, removed pck_size
-------------------------------------------------------------------------------
@@ -51,7 +52,7 @@ entity swc_pck_transfer_arbiter is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
+-- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer --:= c_swc_num_ports
);
port (
@@ -66,7 +67,8 @@ entity swc_pck_transfer_arbiter is
ob_ack_i : in std_logic_vector(g_num_ports -1 downto 0);
ob_pageaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ob_prio_o : out std_logic_vector(g_num_ports * g_prio_width - 1 downto 0);
- ob_pck_size_o : out std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+-- ob_pck_size_o : out std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+ ob_hp_o : out std_logic_vector(g_num_ports -1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Input Block
@@ -75,7 +77,8 @@ entity swc_pck_transfer_arbiter is
ib_transfer_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
ib_busy_o : out std_logic_vector(g_num_ports - 1 downto 0);
- ib_pck_size_i : in std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+-- ib_pck_size_i : in std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+ ib_hp_i : in std_logic_vector(g_num_ports - 1 downto 0);
ib_pageaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
@@ -105,12 +108,12 @@ architecture syn of swc_pck_transfer_arbiter is
subtype t_pageaddr is std_logic_vector(g_page_addr_width - 1 downto 0);
subtype t_prio is std_logic_vector(g_prio_width - 1 downto 0);
subtype t_mask is std_logic_vector(g_num_ports - 1 downto 0);
- subtype t_pck_size is std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- subtype t_pck_size is std_logic_vector(g_max_pck_size_width - 1 downto 0);
type t_pageaddr_array is array (g_num_ports - 1 downto 0) of t_pageaddr;
type t_prio_array is array (g_num_ports - 1 downto 0) of t_prio;
type t_mask_array is array (g_num_ports - 1 downto 0) of t_mask;
- type t_pck_size_array is array (g_num_ports - 1 downto 0) of t_pck_size;
+-- type t_pck_size_array is array (g_num_ports - 1 downto 0) of t_pck_size;
---------------------------------------------------------------------------
-- signals outputed from Pck Transfer Input (PTI)
@@ -120,7 +123,8 @@ architecture syn of swc_pck_transfer_arbiter is
signal pto_output_mask : t_mask_array;
signal pto_read_mask : t_mask_array;
signal pto_prio : t_prio_array;
- signal pto_pck_size : t_pck_size_array;
+ signal pto_hp : std_logic_vector(g_num_ports - 1 downto 0);
+-- signal pto_pck_size : t_pck_size_array;
---------------------------------------------------------------------------
-- signals inputed to Pck Transfer Output (PTO) from Pck Transfer Input (TPI)
@@ -130,7 +134,8 @@ architecture syn of swc_pck_transfer_arbiter is
signal pti_transfer_data_ack : std_logic_vector(g_num_ports - 1 downto 0);
signal pti_pageaddr : t_pageaddr_array;
signal pti_prio : t_prio_array;
- signal pti_pck_size : t_pck_size_array;
+-- signal pti_pck_size : t_pck_size_array;
+ signal pti_hp : std_logic_vector(g_num_ports - 1 downto 0);
signal sync_sreg : std_logic_vector(g_num_ports - 1 downto 0);
signal sync_cntr : integer range 0 to g_num_ports - 1;
signal sync_cntr_ack : integer range 0 to g_num_ports-1;
@@ -173,14 +178,16 @@ begin --arch
-- multiplex mask from input to output
--multimux_out : process(sync_cntr,pto_output_mask,pto_pageaddr,pto_prio)
- multimux_out : process(sync_cntr, pto_output_mask, pto_pageaddr, pto_prio, pto_pck_size)
+-- multimux_out : process(sync_cntr, pto_output_mask, pto_pageaddr, pto_prio, pto_pck_size)
+ multimux_out : process(sync_cntr, pto_output_mask, pto_pageaddr, pto_prio, pto_hp)
begin
for i in 0 to g_num_ports - 1 loop
pti_transfer_data_valid(i) <= pto_output_mask(f_modulo_numports(sync_cntr + i))(i);
pti_pageaddr (i) <= pto_pageaddr (f_modulo_numports(sync_cntr + i));
pti_prio (i) <= pto_prio (f_modulo_numports(sync_cntr + i));
- pti_pck_size (i) <= pto_pck_size (f_modulo_numports(sync_cntr + i));
+-- pti_pck_size (i) <= pto_pck_size (f_modulo_numports(sync_cntr + i));
+ pti_hp (i) <= pto_hp (f_modulo_numports(sync_cntr + i));
end loop;
end process;
@@ -227,7 +234,7 @@ begin --arch
generic map(
g_page_addr_width => g_page_addr_width,
g_prio_width => g_prio_width,
- g_max_pck_size_width => g_max_pck_size_width,
+-- g_max_pck_size_width => g_max_pck_size_width,
g_num_ports => g_num_ports
)
port map (
@@ -238,12 +245,14 @@ begin --arch
pto_output_mask_o => pto_output_mask (i),
pto_read_mask_i => pto_read_mask (i),
pto_prio_o => pto_prio (i),
- pto_pck_size_o => pto_pck_size (i),
+-- pto_pck_size_o => pto_pck_size (i),
+ pto_hp_o => pto_hp (i),
ib_transfer_pck_i => ib_transfer_pck_i (i),
ib_pageaddr_i => ib_pageaddr_i ((i + 1)*g_page_addr_width - 1 downto i*g_page_addr_width),
ib_mask_i => ib_mask_i ((i + 1)*g_num_ports - 1 downto i*g_num_ports),
ib_prio_i => ib_prio_i ((i + 1)*g_prio_width - 1 downto i*g_prio_width),
- ib_pck_size_i => ib_pck_size_i ((i + 1)*g_max_pck_size_width - 1 downto i*g_max_pck_size_width),
+-- ib_pck_size_i => ib_pck_size_i ((i + 1)*g_max_pck_size_width - 1 downto i*g_max_pck_size_width),
+ ib_hp_i => ib_hp_i(i),
ib_transfer_ack_o => ib_transfer_ack_o (i),
ib_busy_o => ib_busy_o (i)
@@ -254,8 +263,8 @@ begin --arch
TRANSFER_OUTPUT : swc_pck_transfer_output
generic map(
g_page_addr_width => g_page_addr_width,
- g_prio_width => g_prio_width,
- g_max_pck_size_width => g_max_pck_size_width
+ g_prio_width => g_prio_width
+-- g_max_pck_size_width => g_max_pck_size_width
)
port map(
clk_i => clk_i,
@@ -263,14 +272,15 @@ begin --arch
ob_transfer_data_valid_o => ob_data_valid_o (i),
ob_pageaddr_o => ob_pageaddr_o ((i + 1)*g_page_addr_width - 1 downto i*g_page_addr_width),
ob_prio_o => ob_prio_o ((i + 1)*g_prio_width - 1 downto i*g_prio_width),
- ob_pck_size_o => ob_pck_size_o ((i + 1)*g_max_pck_size_width - 1 downto i*g_max_pck_size_width),
+-- ob_pck_size_o => ob_pck_size_o ((i + 1)*g_max_pck_size_width - 1 downto i*g_max_pck_size_width),
+ ob_hp_o => ob_hp_o (i),
ob_transfer_data_ack_i => ob_ack_i (i),
pti_transfer_data_valid_i => pti_transfer_data_valid(i),
pti_transfer_data_ack_o => pti_transfer_data_ack (i),
pti_pageaddr_i => pti_pageaddr (i),
pti_prio_i => pti_prio (i),
- pti_pck_size_i => pti_pck_size (i)
-
+ pti_hp_i => pti_hp (i)
+-- pti_pck_size_i => pti_pck_size (i)
);
end generate gen_output;
diff --git a/modules/wrsw_swcore/swc_pck_transfer_input.vhd b/modules/wrsw_swcore/swc_pck_transfer_input.vhd
index 829e4af384e17d9c0ff7558ac87a2d89fe506147..4d78d04c81589f834362651632a83c56bc544a8d 100644
--- a/modules/wrsw_swcore/swc_pck_transfer_input.vhd
+++ b/modules/wrsw_swcore/swc_pck_transfer_input.vhd
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
--- Last update: 2012-02-02
+-- Last update: 2013-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -36,6 +36,7 @@
-- Date Version Author Description
-- 2010-11-03 1.0 mlipinsk created
-- 2012-02-02 2.0 mlipinsk generic-azed
+-- 2013-03-05 2.1 mlipinsk added hp, removed pck_size
-------------------------------------------------------------------------------
@@ -51,7 +52,7 @@ entity swc_pck_transfer_input is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
+-- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer --:= c_swc_num_ports
);
port (
@@ -72,7 +73,9 @@ entity swc_pck_transfer_input is
pto_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
- pto_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- pto_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+
+ pto_hp_o : out std_logic;
-------------------------------------------------------------------------------
-- I/F with Input Block (IB)
@@ -89,7 +92,9 @@ entity swc_pck_transfer_input is
ib_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
- ib_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- ib_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
+
+ ib_hp_i : in std_logic;
ib_transfer_ack_o : out std_logic;
@@ -103,7 +108,8 @@ architecture syn of swc_pck_transfer_input is
signal ib_transfer_ack: std_logic;
signal ib_pageaddr : std_logic_vector(g_page_addr_width - 1 downto 0);
signal ib_prio : std_logic_vector(g_prio_width - 1 downto 0);
- signal ib_pck_size : std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- signal ib_pck_size : std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ signal ib_hp : std_logic;
signal ib_mask : std_logic_vector(g_num_ports - 1 downto 0);
--signal pto_read_mask : std_logic_vector(g_num_ports - 1 downto 0);
signal pto_output_mask : std_logic_vector(g_num_ports - 1 downto 0);
@@ -124,7 +130,8 @@ begin --arch
--pto_read_mask <= (others => '0');
pto_output_mask <= (others => '0');
ib_prio <= (others => '0');
- ib_pck_size <= (others => '0');
+-- ib_pck_size <= (others => '0');
+ ib_hp <= '0';
ib_pageaddr <= (others => '0');
ib_transfer_ack <= '0';
--===================================================
@@ -135,7 +142,8 @@ begin --arch
ib_mask <= ib_mask_i;
ib_prio <= ib_prio_i;
ib_pageaddr <= ib_pageaddr_i;
- ib_pck_size <= ib_pck_size_i;
+-- ib_pck_size <= ib_pck_size_i;
+ ib_hp <= ib_hp_i;
end if;
@@ -177,7 +185,8 @@ begin --arch
pto_transfer_pck_o <= '0';
pto_pageaddr_o <= ib_pageaddr;
pto_prio_o <= ib_prio;
- pto_pck_size_o <= ib_pck_size;
+-- pto_pck_size_o <= ib_pck_size;
+ pto_hp_o <= ib_hp;
ib_transfer_ack_o <= ib_transfer_ack;
ib_busy_o <= '0' when (pto_output_mask = zeros) else '1';
diff --git a/modules/wrsw_swcore/swc_pck_transfer_output.vhd b/modules/wrsw_swcore/swc_pck_transfer_output.vhd
index a0ea7752d8577302275d6fefa750cad3c853fd41..e137d4ed0f10b74d289345c44380fd834c823e3f 100644
--- a/modules/wrsw_swcore/swc_pck_transfer_output.vhd
+++ b/modules/wrsw_swcore/swc_pck_transfer_output.vhd
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
--- Last update: 2012-02-02
+-- Last update: 2013-03-05
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -36,7 +36,7 @@
-- Date Version Author Description
-- 2010-11-03 1.0 mlipinsk created
-- 2012-02-02 2.0 mlipinsk generic-azed
-
+-- 2013-03-05 2.1 mlipinsk added hp, removed pck_size
-------------------------------------------------------------------------------
@@ -51,8 +51,8 @@ use ieee.numeric_std.all;
entity swc_pck_transfer_output is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
- g_prio_width : integer ;--:= c_swc_prio_width;
- g_max_pck_size_width : integer --:= c_swc_max_pck_size_width
+ g_prio_width : integer --:= c_swc_prio_width;
+-- g_max_pck_size_width : integer --:= c_swc_max_pck_size_width
);
port (
clk_i : in std_logic;
@@ -65,7 +65,8 @@ entity swc_pck_transfer_output is
ob_transfer_data_valid_o : out std_logic;
ob_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
ob_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
- ob_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- ob_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ ob_hp_o : out std_logic;
ob_transfer_data_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with Page Transfer Input (PTI)
@@ -75,7 +76,8 @@ entity swc_pck_transfer_output is
pti_transfer_data_ack_o : out std_logic;
pti_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
pti_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
- pti_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0)
+-- pti_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0)
+ pti_hp_i : in std_logic
);
end swc_pck_transfer_output;
@@ -86,7 +88,8 @@ architecture syn of swc_pck_transfer_output is
signal ob_transfer_data_valid : std_logic;
signal ob_pageaddr : std_logic_vector(g_page_addr_width - 1 downto 0);
signal ob_prio : std_logic_vector(g_prio_width - 1 downto 0);
- signal ob_pck_size : std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- signal ob_pck_size : std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ signal ob_hp : std_logic;
begin --arch
@@ -100,7 +103,8 @@ begin --arch
--===================================================
ob_pageaddr <= (others => '0');
ob_prio <= (others => '0');
- ob_pck_size <= (others => '0');
+-- ob_pck_size <= (others => '0');
+ ob_hp <= '0';
ob_transfer_data_valid <= '0';
pti_transfer_data_ack <= '0';
--===================================================
@@ -110,7 +114,8 @@ begin --arch
ob_pageaddr <= pti_pageaddr_i;
ob_prio <= pti_prio_i;
- ob_pck_size <= pti_pck_size_i;
+-- ob_pck_size <= pti_pck_size_i;
+ ob_hp <= pti_hp_i;
end if;
@@ -136,6 +141,7 @@ begin --arch
ob_transfer_data_valid_o <= ob_transfer_data_valid;
ob_pageaddr_o <= ob_pageaddr;
ob_prio_o <= ob_prio;
- ob_pck_size_o <= ob_pck_size;
+-- ob_pck_size_o <= ob_pck_size;
+ ob_hp_o <= ob_hp;
end syn; -- arch
\ No newline at end of file
diff --git a/modules/wrsw_swcore/swc_prio_encoder.vhd b/modules/wrsw_swcore/swc_prio_encoder.vhd
index 3d263b6cea01755e862d53651b1e04b252d432ac..6930b118225ed62d41959b2838f110890f6563cf 100644
--- a/modules/wrsw_swcore/swc_prio_encoder.vhd
+++ b/modules/wrsw_swcore/swc_prio_encoder.vhd
@@ -10,7 +10,9 @@
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
--- Description:
+-- Description: this module is used in :
+-- * old page allocator
+-- * output block as a queue scheduler (strick priority policy)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Tomasz Wlostowski, Maciej Lipinski / CERN
diff --git a/modules/wrsw_swcore/swc_swcore_pkg.vhd b/modules/wrsw_swcore/swc_swcore_pkg.vhd
index 698390627f5c8fc87f2555582c4054f470a23cb1..e074a65159e6d2d89829fa9a445859a43d106841 100644
--- a/modules/wrsw_swcore/swc_swcore_pkg.vhd
+++ b/modules/wrsw_swcore/swc_swcore_pkg.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
--- Last update: 2012-07-10
+-- Last update: 2012-06-25
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -41,6 +41,7 @@
library ieee;
use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
use ieee.math_real.CEIL;
use ieee.math_real.log2;
@@ -60,6 +61,9 @@ package swc_swcore_pkg is
type t_slv_array is array(integer range <>, integer range <>) of std_logic;
+ type t_classes_array is array(integer range <>) of std_logic_vector(7 downto 0);
+
+ type t_ports_masks is array(integer range <>) of std_logic_vector(c_RTU_MAX_PORTS+1-1 downto 0);
component swc_prio_encoder
generic (
g_num_inputs : integer range 2 to 80;
@@ -89,10 +93,18 @@ package swc_swcore_pkg is
component swc_page_allocator
generic (
- g_num_pages : integer;
- g_page_addr_width : integer;
- g_num_ports : integer;
- g_usecount_width : integer);
+ g_num_pages : integer;
+ g_page_addr_width : integer;
+ g_num_ports : integer;
+ g_usecount_width : integer;
+ --- management
+ g_page_size : integer := 64;
+ g_max_pck_size : integer := 759;
+ g_special_res_num_pages : integer := 256;
+ g_resource_num : integer := 3;
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer
+);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
@@ -107,7 +119,17 @@ package swc_swcore_pkg is
free_last_usecnt_o : out std_logic;
idle_o : out std_logic;
done_o : out std_logic;
- nomem_o : out std_logic);
+ nomem_o : out std_logic;
+ resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+ resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
+ free_resource_valid_i : in std_logic;
+ rescnt_page_num_i : in std_logic_vector(g_page_addr_width -1 downto 0);
+ set_usecnt_succeeded_o : out std_logic;
+ res_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_resource_num -1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
+ );
+
end component;
--component swc_page_allocator
@@ -190,7 +212,10 @@ package swc_swcore_pkg is
g_page_size : integer ;
g_partial_select_width : integer ;
g_ll_data_width : integer ;
- g_port_index : integer
+ g_port_index : integer ;
+ --- resource management
+ g_resource_num : integer;
+ g_resource_num_width : integer
);
port (
clk_i : in std_logic;
@@ -208,12 +233,24 @@ package swc_swcore_pkg is
mmu_force_free_addr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
mmu_set_usecnt_o : out std_logic;
mmu_set_usecnt_done_i : in std_logic;
- mmu_usecnt_o : out std_logic_vector(g_usecount_width - 1 downto 0);
+ mmu_usecnt_set_o : out std_logic_vector(g_usecount_width - 1 downto 0);
+ mmu_usecnt_alloc_o : out std_logic_vector(g_usecount_width - 1 downto 0);
mmu_nomem_i : in std_logic;
+ --- management
+-- mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+ mmu_resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
+ mmu_rescnt_page_num_o : out std_logic_vector(g_page_addr_width-1 downto 0);
+ mmu_set_usecnt_succeeded_i : in std_logic;
+ mmu_res_almost_full_i : in std_logic_vector(g_resource_num -1 downto 0);
+ mmu_res_full_i : in std_logic_vector(g_resource_num -1 downto 0);
+
+
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
+ rtu_rsp_abort_o : out std_logic;
rtu_dst_port_mask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_hp_i : in std_logic;
rtu_drop_i : in std_logic;
rtu_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
@@ -235,10 +272,17 @@ package swc_swcore_pkg is
pta_transfer_ack_i : in std_logic;
pta_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
pta_mask_o : out std_logic_vector(g_num_ports - 1 downto 0);
- pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- pta_resource_o : out std_logic_vector(g_resource_num_width - 1 downto 0);
+ pta_hp_o : out std_logic;
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
- tap_out_o : out std_logic_vector(49+62 downto 0)
+ dbg_hwdu_o : out std_logic_vector(15 downto 0);
+
+ tap_out_o : out std_logic_vector(49+62 downto 0);
+
+ dbg_pckstart_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
+ dbg_pckinter_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0)
);
end component;
@@ -248,7 +292,15 @@ package swc_swcore_pkg is
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_num_ports : integer ;--:= c_swc_num_ports
g_page_num : integer ;--:= c_swc_packet_mem_num_pages
- g_usecount_width : integer --:= c_swc_usecount_width
+ g_usecount_width : integer ;--:= c_swc_usecount_width
+ --- resource manager
+ g_max_pck_size : integer ;
+ g_page_size : integer ;
+ g_special_res_num_pages : integer ;
+ g_resource_num : integer ; -- this include 1 for unknown
+ g_resource_num_width : integer ;
+ g_num_dbg_vector_width : integer ;
+ g_with_RESOURCE_MGR : boolean := false
);
port (
rst_n_i : in std_logic;
@@ -264,11 +316,23 @@ package swc_swcore_pkg is
pgaddr_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
pgaddr_force_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
pgaddr_usecnt_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
- usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+-- usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+ usecnt_set_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
+ usecnt_alloc_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
- nomem_o : out std_logic
--- tap_out_o :out std_logic_vector(62 + 49 downto 0)
+ nomem_o : out std_logic;
+ resource_i : in std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+ resource_o : out std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
+ free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ force_free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
+ force_free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width-1 downto 0);
+ set_usecnt_succeeded_o : out std_logic_vector(g_num_ports -1 downto 0);
+ res_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
);
end component;
@@ -277,7 +341,7 @@ package swc_swcore_pkg is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
+-- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer --:= c_swc_num_ports
);
port (
@@ -289,13 +353,15 @@ package swc_swcore_pkg is
pto_output_mask_o : out std_logic_vector(g_num_ports - 1 downto 0);
pto_read_mask_i : in std_logic_vector(g_num_ports - 1 downto 0);
pto_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
- pto_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- pto_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ pto_hp_o : out std_logic;
ib_transfer_pck_i : in std_logic;
ib_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ib_mask_i : in std_logic_vector(g_num_ports - 1 downto 0);
ib_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
- ib_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- ib_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ ib_hp_i : in std_logic;
ib_transfer_ack_o : out std_logic;
ib_busy_o : out std_logic
@@ -305,8 +371,8 @@ package swc_swcore_pkg is
component swc_pck_transfer_output is
generic(
g_page_addr_width : integer ;--:= g_page_addr_width;
- g_prio_width : integer ;--:= c_swc_prio_width;
- g_max_pck_size_width : integer --:= c_swc_max_pck_size_width
+ g_prio_width : integer --:= c_swc_prio_width;
+-- g_max_pck_size_width : integer --:= c_swc_max_pck_size_width
);
port (
clk_i : in std_logic;
@@ -315,14 +381,16 @@ package swc_swcore_pkg is
ob_transfer_data_valid_o : out std_logic;
ob_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
ob_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
- ob_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- ob_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ ob_hp_o : out std_logic;
ob_transfer_data_ack_i : in std_logic;
pti_transfer_data_valid_i: in std_logic;
pti_transfer_data_ack_o : out std_logic;
pti_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
pti_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
- pti_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0)
+-- pti_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0)
+ pti_hp_i : in std_logic
);
end component;
@@ -331,7 +399,7 @@ package swc_swcore_pkg is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
+-- g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer --:= c_swc_num_ports
);
port (
@@ -342,7 +410,8 @@ package swc_swcore_pkg is
ob_ack_i : in std_logic_vector(g_num_ports - 1 downto 0);
ob_pageaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ob_prio_o : out std_logic_vector(g_num_ports * g_prio_width - 1 downto 0);
- ob_pck_size_o : out std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+-- ob_pck_size_o : out std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+ ob_hp_o : out std_logic_vector(g_num_ports - 1 downto 0);
ib_transfer_pck_i : in std_logic_vector(g_num_ports - 1 downto 0);
ib_transfer_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
@@ -350,13 +419,14 @@ package swc_swcore_pkg is
ib_pageaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ib_mask_i : in std_logic_vector(g_num_ports * g_num_ports - 1 downto 0);
ib_prio_i : in std_logic_vector(g_num_ports * g_prio_width - 1 downto 0);
- ib_pck_size_i : in std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0)
+-- ib_pck_size_i : in std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0)
+ ib_hp_i : in std_logic_vector(g_num_ports - 1 downto 0)
);
end component;
component swc_ob_prio_queue is
generic(
- g_per_prio_fifo_size_width : integer --:= c_swc_output_fifo_addr_width
+ g_per_queue_fifo_size_width : integer --:= c_swc_output_fifo_addr_width
);
port (
clk_i : in std_logic;
@@ -366,38 +436,43 @@ package swc_swcore_pkg is
not_full_o : out std_logic;
not_empty_o : out std_logic;
wr_en_o : out std_logic;
- wr_addr_o : out std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
- rd_addr_o : out std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0)
+ wr_addr_o : out std_logic_vector(g_per_queue_fifo_size_width - 1 downto 0);
+ rd_addr_o : out std_logic_vector(g_per_queue_fifo_size_width - 1 downto 0)
);
end component;
component xswc_output_block is
generic (
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
- g_output_block_per_prio_fifo_size : integer ;--:= c_swc_output_fifo_size
- g_prio_width : integer ;--:= c_swc_prio_width;, c_swc_output_prio_num_width
- g_prio_num : integer ;--:= c_swc_output_prio_num
+ g_output_block_per_queue_fifo_size : integer ;--:= c_swc_output_fifo_size
+ g_queue_num_width : integer ;--
+ g_queue_num : integer ;--
+ g_prio_num_width : integer ;--
-- new stuff
g_mpm_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_mpm_data_width : integer ;--:= c_swc_page_addr_width;
g_mpm_partial_select_width : integer ;
g_mpm_fetch_next_pg_in_advance : boolean := false;
+ g_mmu_resource_num_width : integer;
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
- g_wb_ob_ignore_ack : boolean := true
+ g_wb_ob_ignore_ack : boolean := true;
+ g_drop_outqueue_head_on_full : boolean := true
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pta_transfer_data_valid_i : in std_logic;
pta_pageaddr_i : in std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
- pta_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
+ pta_prio_i : in std_logic_vector(g_prio_num_width - 1 downto 0);
+ pta_hp_i : in std_logic;
+ pta_resource_i : in std_logic_vector(g_mmu_resource_num_width - 1 downto 0);
pta_transfer_data_ack_o : out std_logic;
mpm_d_i : in std_logic_vector (g_mpm_data_width -1 downto 0);
mpm_dvalid_i : in std_logic;
mpm_dlast_i : in std_logic;
--- mpm_dsel_i : in std_logic_vector (g_mpm_partial_select_width -1 downto 0);
+ mpm_dsel_i : in std_logic_vector (g_mpm_partial_select_width -1 downto 0);
mpm_dreq_o : out std_logic;
mpm_abort_o : out std_logic;
mpm_pg_addr_o : out std_logic_vector (g_mpm_page_addr_width -1 downto 0);
@@ -413,12 +488,64 @@ package swc_swcore_pkg is
);
end component;
+ component xswc_output_block_new is
+ generic (
+ g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
+ g_output_block_per_queue_fifo_size : integer ;--:= c_swc_output_fifo_size
+ g_queue_num_width : integer ;--
+ g_queue_num : integer ;--
+ g_prio_num_width : integer ;--
+ -- new stuff
+ g_mpm_page_addr_width : integer ;--:= c_swc_page_addr_width;
+ g_mpm_data_width : integer ;--:= c_swc_page_addr_width;
+ g_mpm_partial_select_width : integer ;
+ g_mpm_fetch_next_pg_in_advance : boolean := false;
+ g_mmu_resource_num_width : integer;
+ g_hwdu_output_block_width : integer :=8;
+ g_wb_data_width : integer ;
+ g_wb_addr_width : integer ;
+ g_wb_sel_width : integer ;
+ g_wb_ob_ignore_ack : boolean := true;
+ g_drop_outqueue_head_on_full : boolean := true
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ pta_transfer_data_valid_i : in std_logic;
+ pta_pageaddr_i : in std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ pta_prio_i : in std_logic_vector(g_prio_num_width - 1 downto 0);
+ pta_hp_i : in std_logic;
+-- pta_resource_i : in std_logic_vector(g_mmu_resource_num_width - 1 downto 0);
+ pta_transfer_data_ack_o : out std_logic;
+ mpm_d_i : in std_logic_vector (g_mpm_data_width -1 downto 0);
+ mpm_dvalid_i : in std_logic;
+ mpm_dlast_i : in std_logic;
+--dsel-- mpm_dsel_i : in std_logic_vector (g_mpm_partial_select_width -1 downto 0);
+ mpm_dreq_o : out std_logic;
+ mpm_abort_o : out std_logic;
+ mpm_pg_addr_o : out std_logic_vector (g_mpm_page_addr_width -1 downto 0);
+ mpm_pg_valid_o : out std_logic;
+ mpm_pg_req_i : in std_logic;
+ ppfm_free_o : out std_logic;
+ ppfm_free_done_i : in std_logic;
+ ppfm_free_pgaddr_o : out std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ ots_output_mask_i : in std_logic_vector(7 downto 0);
+ ots_output_drop_at_rx_hp_i : in std_logic;
+ src_i : in t_wrf_source_in;
+ src_o : out t_wrf_source_out;
+ dbg_hwdu_o : out std_logic_vector(g_hwdu_output_block_width -1 downto 0);
+ tap_out_o : out std_logic_vector(15 downto 0)
+
+ );
+ end component;
+
component swc_multiport_pck_pg_free_module is
generic(
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
- g_data_width : integer
+ g_data_width : integer ;
+ g_resource_num_width : integer
);
port (
clk_i : in std_logic;
@@ -438,14 +565,20 @@ component swc_multiport_pck_pg_free_module is
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
- mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
- mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
- mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
- mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
+
+ mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
+ mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+ mmu_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
+ mmu_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
- mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
- mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
- mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
+ mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
+ mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
+ mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
+ mmu_force_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
+ mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0)
);
end component;
@@ -453,7 +586,8 @@ component swc_multiport_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
- g_data_width : integer
+ g_data_width : integer ;
+ g_resource_num_width : integer
);
port (
clk_i : in std_logic;
@@ -472,26 +606,33 @@ component swc_multiport_pck_pg_free_module is
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
- mmu_free_o : out std_logic;
- mmu_free_done_i : in std_logic;
- mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
- mmu_free_last_usecnt_i : in std_logic;
-
- mmu_force_free_o : out std_logic;
- mmu_force_free_done_i : in std_logic;
- mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
+ mmu_resource_i : in std_logic_vector(g_resource_num_width -1 downto 0);
+
+ mmu_free_o : out std_logic;
+ mmu_free_done_i : in std_logic;
+ mmu_free_last_usecnt_i : in std_logic;
+ mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ mmu_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
+ mmu_free_resource_valid_o : out std_logic;
+
+ mmu_force_free_o : out std_logic;
+ mmu_force_free_done_i : in std_logic;
+ mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+ mmu_force_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
+ mmu_force_free_resource_valid_o : out std_logic
);
end component;
component xswc_core is
generic(
g_prio_num : integer ;--:= c_swc_output_prio_num;
+ g_output_queue_num : integer ;
g_max_pck_size : integer ;--:= c_swc_max_pck_size
g_max_oob_size : integer ;
g_num_ports : integer ;--:= c_swc_num_ports
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
- g_output_block_per_prio_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
+ g_output_block_per_queue_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
-- new
g_wb_data_width : integer ;
@@ -503,7 +644,10 @@ component swc_multiport_pck_pg_free_module is
g_mpm_page_size : integer ;
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
- g_mpm_fetch_next_pg_in_advance : boolean
+ g_mpm_fetch_next_pg_in_advance : boolean ;
+ g_drop_outqueue_head_on_full : boolean ;
+ g_num_global_pause : integer ;
+ g_num_dbg_vector_width : integer
);
port (
clk_i : in std_logic;
@@ -515,11 +659,88 @@ component swc_multiport_pck_pg_free_module is
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
-
+
+ global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
+ perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
+
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
- rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
+ rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
+
+
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width -1 downto 0);
+ shaper_drop_at_hp_ena_i : in std_logic
);
end component;
+
+ component swc_core is
+ generic(
+ g_prio_num : integer ;--:= c_swc_output_prio_num;
+ g_output_queue_num : integer ;
+ g_max_pck_size : integer ;--:= 2^c_swc_max_pck_size
+ g_max_oob_size : integer ;
+ g_num_ports : integer ;--:= c_swc_num_ports
+ g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
+ g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
+ g_output_block_per_queue_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
+ -- new
+ g_wb_data_width : integer ;
+ g_wb_addr_width : integer ;
+ g_wb_sel_width : integer ;
+ g_wb_ob_ignore_ack : boolean ;
+ g_mpm_mem_size : integer ;
+ g_mpm_page_size : integer ;
+ g_mpm_ratio : integer ;
+ g_mpm_fifo_size : integer ;
+ g_mpm_fetch_next_pg_in_advance : boolean ;
+ g_drop_outqueue_head_on_full : boolean ;
+ g_num_global_pause : integer ;
+ g_num_dbg_vector_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ clk_mpm_core_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ snk_dat_i : in std_logic_vector(g_wb_data_width*g_num_ports-1 downto 0);
+ snk_adr_i : in std_logic_vector(g_wb_addr_width*g_num_ports-1 downto 0);
+ snk_sel_i : in std_logic_vector(g_wb_sel_width *g_num_ports-1 downto 0);
+ snk_cyc_i : in std_logic_vector( g_num_ports-1 downto 0);
+ snk_stb_i : in std_logic_vector( g_num_ports-1 downto 0);
+ snk_we_i : in std_logic_vector( g_num_ports-1 downto 0);
+ snk_stall_o : out std_logic_vector( g_num_ports-1 downto 0);
+ snk_ack_o : out std_logic_vector( g_num_ports-1 downto 0);
+ snk_err_o : out std_logic_vector( g_num_ports-1 downto 0);
+ snk_rty_o : out std_logic_vector( g_num_ports-1 downto 0);
+
+ src_dat_o : out std_logic_vector(g_wb_data_width*g_num_ports-1 downto 0);
+ src_adr_o : out std_logic_vector(g_wb_addr_width*g_num_ports-1 downto 0);
+ src_sel_o : out std_logic_vector(g_wb_sel_width *g_num_ports-1 downto 0);
+ src_cyc_o : out std_logic_vector( g_num_ports-1 downto 0);
+ src_stb_o : out std_logic_vector( g_num_ports-1 downto 0);
+ src_we_o : out std_logic_vector( g_num_ports-1 downto 0);
+ src_stall_i : in std_logic_vector( g_num_ports-1 downto 0);
+ src_ack_i : in std_logic_vector( g_num_ports-1 downto 0);
+ src_err_i : in std_logic_vector( g_num_ports-1 downto 0);
+
+ rtu_rsp_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_rsp_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_dst_port_mask_i : in std_logic_vector(g_num_ports * g_num_ports - 1 downto 0);
+ rtu_drop_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_prio_i : in std_logic_vector(g_num_ports * integer(CEIL(LOG2(real(g_prio_num-1)))) - 1 downto 0);
+
+ gp_req_i : in std_logic_vector(g_num_global_pause - 1 downto 0);
+ gp_quanta_i : in std_logic_vector(g_num_global_pause*16 - 1 downto 0);
+ gp_classes_i : in std_logic_vector(g_num_global_pause*8 - 1 downto 0);
+ gp_ports_i : in std_logic_vector(g_num_global_pause*g_num_ports- 1 downto 0);
+
+ pp_req_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ pp_quanta_i : in std_logic_vector(g_num_ports*16 - 1 downto 0);
+ pp_classes_i : in std_logic_vector(g_num_ports*8 - 1 downto 0);
+
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width -1 downto 0);
+ shaper_drop_at_hp_ena_i : in std_logic
+ );
+ end component;
component swc_ll_read_data_validation is
generic(
@@ -542,14 +763,113 @@ component swc_multiport_pck_pg_free_module is
write_data_valid_i : in std_logic;
write_data_ready_i : in std_logic;
- read_data_o : out std_logic_vector(g_data_width - 1 downto 0);
- read_data_valid_o : out std_logic
+ read_data_o : out std_logic_vector(g_data_width - 1 downto 0);
+ read_data_valid_o : out std_logic
);
end component;
+
+ component swc_alloc_resource_manager is
+ generic (
+ g_num_ports : integer ;
+ g_max_pck_size : integer;
+ g_page_size : integer;
+ g_total_num_pages : integer := 2048;
+ g_total_num_pages_width : integer := 11;
+ g_special_res_num_pages : integer := 248;
+ g_resource_num : integer := 3; -- this include 1 for unknown
+ g_resource_num_width : integer := 2;
+ g_num_dbg_vector_width : integer
+ );
+ port (
+ clk_i : in std_logic; -- clock & reset
+ rst_n_i : in std_logic;
+ resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+ alloc_i : in std_logic;
+ free_i : in std_logic;
+ rescnt_set_i : in std_logic;
+ rescnt_page_num_i : in std_logic_vector(g_total_num_pages_width-1 downto 0);
+ res_full_o : out std_logic_vector(g_resource_num- 1 downto 0);
+ res_almost_full_o : out std_logic_vector(g_resource_num- 1 downto 0);
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0)
+ );
+ end component;
+
+
+ component swc_output_queue_scheduler is
+ generic (
+ g_queue_num : integer range 2 to 64 := 32;
+ g_queue_num_width : integer range 1 to 6 := 5);
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ not_empty_array_i : in std_logic_vector(g_queue_num-1 downto 0);
+ read_queue_index_o : out std_logic_vector(g_queue_num_width-1 downto 0);
+ read_queue_onehot_o: out std_logic_vector(g_queue_num-1 downto 0);
+ full_array_i : in std_logic_vector(g_queue_num-1 downto 0);
+ drop_queue_index_o : out std_logic_vector(g_queue_num_width-1 downto 0);
+ drop_queue_onehot_o: out std_logic_vector(g_queue_num-1 downto 0)
+ );
+ end component;
+
+ component swc_output_traffic_shaper is
+ generic (
+ g_num_ports : integer := 32;
+ g_num_global_pause : integer := 2);
+ port (
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+-- shaper_request_i : in t_pause_request ;
+-- shaper_ports_i : in std_logic_vector(g_num_ports-1 downto 0);
+-- pause_requests_i : in t_pause_request_array(g_num_ports-1 downto 0);
+
+ perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
+ global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
+
+ output_masks_o : out t_classes_array(g_num_ports-1 downto 0)
+ );
+ end component;
+
+
+ component swc_core_vectorized_top is
+ generic(
+ g_num_ports : integer;
+ g_in_bits : integer;
+ g_out_bits : integer;
+ g_wb_data_width : integer := 8;
+ g_wb_addr_width : integer := 16;
+ g_wb_sel_width : integer := 2;
+ g_prio_num : integer := 2;
+ g_num_global_pause : integer := 2;
+ g_prio_width : integer -- : integer(CEIL(LOG2(real(g_prio_num-1)))) ;
+ );
+ port (
+ clk_i : in std_logic;
+ clk_mpm_core_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ input_vector_i : in std_logic_vector(g_in_bits - 1 downto 0);
+ output_vector_o : out std_logic_vector(g_out_bits - 1 downto 0)
+
+ );
+ end component;
function f_sel2partialSel(sel : std_logic_vector; partialSelWidth: integer) return std_logic_vector;
function f_partialSel2sel(partialSel: std_logic_vector; selWidth : integer) return std_logic_vector;
-
+-- function f_map_rtu_rsp_to_mmu_res(rtu_prio : std_logic_vector;
+-- rtu_broadcast: std_logic;
+-- res_num_width: integer) return std_logic_vector;
+ function f_map_rtu_rsp_and_mmu_res_to_out_queue(rtu_prio : std_logic_vector;
+ rtu_hp : std_logic;
+ queue_full : std_logic_vector;
+ queue_num : integer) return std_logic_vector;
+ function f_slv_resize(x : std_logic_vector; len : natural) return std_logic_vector;
+ function f_onehot_decode(x : std_logic_vector) return std_logic_vector;
+ function f_global_pause_mask(class_mask : t_classes_array;
+ port_mask : t_ports_masks;
+ port_id : integer;
+ gl_pause_num: integer
+ ) return std_logic_vector;
+
end swc_swcore_pkg;
package body swc_swcore_pkg is
@@ -582,5 +902,112 @@ package body swc_swcore_pkg is
end if;
return tmp;
end function;
+
+ --------------------------------------------------------------------------------------------------
+ -- Mapping of RTU decision into available memory resources
+ --------------------------------------------------------------------------------------------------
+ -- here we can map, as we please the {priority,broadcast} pair into memory resources, i.e.
+ -- we define HighPriority traffic which shall have separate resources, so
+ -- if (rtu_prio = 7 and broadcast=1) then we assign "special resource" (number 1)
+ -- else we assign "normal resource" (number 2)
+ --
+ --------------------------------------------------------------------------------------------------
+ -- ML (20 Aug 2013): the HP mapping configurable in RTU and propagated with decision (rtu_rsp)
+ -- to SWcore
+-- function f_map_rtu_rsp_to_mmu_res(rtu_prio : std_logic_vector;
+-- rtu_broadcast: std_logic;
+-- res_num_width: integer) return std_logic_vector is
+-- variable tmp : std_logic_vector(7 downto 0); -- assuming max resource number of 8 (far over-estimated)
+-- variable ones : std_logic_vector(rtu_prio'length - 1 downto 0);
+-- begin
+-- ones := (others => '1');
+-- ---------- the mapping as you please ------------------
+-- if(rtu_prio = ones and rtu_broadcast = '0') then -- todo: change when RTU changed
+-- tmp := x"01";
+-- else
+-- tmp := x"02";
+-- end if;
+-- -------------------------------------------------------
+--
+-- return tmp(res_num_width-1 downto 0);-- adjust the vector width
+-- end function;
+
+ --------------------------------------------------------------------------------------------------
+ -- Mapping of RTU decision and resources and output queues availability into output queue
+ --------------------------------------------------------------------------------------------------
+ -- Here we decide to which output queue a given frame to-be-sent shall be assigned, i.e.
+ -- we assign special resource (nr=1) to output queue number 7 and the rest we distribute
+ -- over 6 other output queues, so
+ -- queue[7] <= resource number 1 (prio=7 and broadcast=1)
+ -- queue[6] <= resource number 0 (prio=7 and broadcast=0)
+ -- queue[5] <= resource number 0 (prio=6 and (broadcast=0 or broadcast=1))
+ -- queue[4] <= resource number 0 (prio=5 and (broadcast=0 or broadcast=1))
+ -- queue[3] <= resource number 0 (prio=4 and (broadcast=0 or broadcast=1))
+ -- queue[2] <= resource number 0 (prio=3 and (broadcast=0 or broadcast=1))
+ -- queue[1] <= resource number 0 (prio=2 and (broadcast=0 or broadcast=1))
+ -- queue[0] <= resource number 0 (prio=1 or prio = 0 and (broadcast=0 or broadcast=1))
+ -- and we ignore whether the queue is full or not
+ --
+ --------------------------------------------------------------------------------------------------
+ function f_map_rtu_rsp_and_mmu_res_to_out_queue(rtu_prio : std_logic_vector;
+ rtu_hp : std_logic;
+ queue_full : std_logic_vector;
+ queue_num : integer) return std_logic_vector is
+ variable tmp : unsigned(integer(CEIL(LOG2(real(queue_num-1))))-1 downto 0);
+ variable resSpecial : std_logic_vector(7 downto 0);
+ begin
+ resSpecial := x"01";
+
+ return rtu_prio; -- tmp solution
+
+ -------------------- the correct one
+-- if(resource = resSpecial(resource'length -1 downto 0)) then
+-- tmp := to_unsigned(7,tmp'length );
+-- else
+--
+-- if(unsigned(rtu_prio) > to_unsigned(0,rtu_prio'length)) then
+-- tmp := unsigned(rtu_prio) - 1;
+-- else
+-- tmp := to_unsigned(0,tmp'length);
+-- end if;
+--
+-- end if;
+--
+-- return std_logic_vector(tmp);
+ end function;
+
+ function f_slv_resize(x : std_logic_vector; len : natural) return std_logic_vector is
+ variable tmp : std_logic_vector(len-1 downto 0);
+ begin
+ tmp := (others => '0');
+ tmp(x'length-1 downto 0) := x;
+ return tmp;
+ end f_slv_resize;
+
+ function f_onehot_decode(x : std_logic_vector) return std_logic_vector is
+ variable tmp : std_logic_vector(2**x'length-1 downto 0);
+ begin
+ tmp := (others => '0');
+ tmp(to_integer(unsigned(x))) := '1';
+
+ return tmp;
+ end function f_onehot_decode;
+
+ function f_global_pause_mask(class_mask : t_classes_array;
+ port_mask : t_ports_masks;
+ port_id : integer;
+ gl_pause_num: integer
+ ) return std_logic_vector is
+ variable tmp : std_logic_vector(7 downto 0);
+ begin
+ tmp := (others => '0');
+
+ for i in 0 to gl_pause_num-1 loop
+ if (port_mask(i)(port_id) = '1' ) then
+ tmp := tmp or class_mask(i);
+ end if;
+ end loop;
+ return tmp;
+ end f_global_pause_mask;
end swc_swcore_pkg;
diff --git a/modules/wrsw_swcore/xswc_core.vhd b/modules/wrsw_swcore/xswc_core.vhd
index fe7048597a38fe6a0d80adafcc1f16ca455ae0be..2a6f33e15aec4dc13e0946378844e7344472ccb4 100644
--- a/modules/wrsw_swcore/xswc_core.vhd
+++ b/modules/wrsw_swcore/xswc_core.vhd
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-29
--- Last update: 2012-07-10
+-- Last update: 2012-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -57,23 +57,27 @@ entity xswc_core is
generic(
g_prio_num : integer ;--:= c_swc_output_prio_num; [works only for value of 8, output_block-causes problem]
- g_max_pck_size : integer ;--:= c_swc_max_pck_size
+ g_output_queue_num : integer ;
+ g_max_pck_size : integer ;-- in 16bits words --:= c_swc_max_pck_size
g_max_oob_size : integer ;
g_num_ports : integer ;--:= c_swc_num_ports
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
- g_output_block_per_prio_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
+ g_output_block_per_queue_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
-- new
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
g_wb_ob_ignore_ack : boolean := true ;
- g_mpm_mem_size : integer ;
- g_mpm_page_size : integer ;
+ g_mpm_mem_size : integer ; -- in 16bits words
+ g_mpm_page_size : integer ; -- in 16bits words
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
- g_mpm_fetch_next_pg_in_advance : boolean
+ g_mpm_fetch_next_pg_in_advance : boolean ;
+ g_drop_outqueue_head_on_full : boolean ;
+ g_num_global_pause : integer := 2;
+ g_num_dbg_vector_width : integer := 8
);
port (
clk_i : in std_logic;
@@ -93,13 +97,34 @@ entity xswc_core is
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- I/F with Traffich shaper
+-------------------------------------------------------------------------------
+
+ global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
+ shaper_drop_at_hp_ena_i : in std_logic := '0';
+
+-------------------------------------------------------------------------------
+-- I/F with Tx PAUSE triggers (i.e. Endpoints)
+-------------------------------------------------------------------------------
+
+ perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- Debug vector
+-------------------------------------------------------------------------------
+
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
+
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
- rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
- rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
+ rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
+ rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
end xswc_core;
@@ -107,6 +132,7 @@ end xswc_core;
architecture rtl of xswc_core is
constant c_usecount_width : integer := integer(CEIL(LOG2(real(g_num_ports+1))));
constant c_prio_width : integer := integer(CEIL(LOG2(real(g_prio_num-1)))); -- g_prio_width
+ constant c_output_queue_num_width: integer := integer(CEIL(LOG2(real(g_output_queue_num-1))));
constant c_max_pck_size_width : integer := integer(CEIL(LOG2(real(g_max_pck_size-1)))); -- c_swc_max_pck_size_width
constant c_max_oob_size_width : integer := integer(CEIL(LOG2(real(g_max_oob_size + 1))));
@@ -116,10 +142,19 @@ architecture rtl of xswc_core is
constant c_mpm_partial_sel_width : integer := integer(g_wb_sel_width-1);
constant c_mpm_page_size_width : integer := integer(CEIL(LOG2(real(g_mpm_page_size-1))));
-
-
constant c_ll_addr_width : integer := c_mpm_page_addr_width;
constant c_ll_data_width : integer := c_mpm_page_addr_width + c_max_oob_size_width + 3;
+
+ -- resource management -----------------------
+ constant c_res_mmu_max_pck_size : integer := 759; -- in 16 bit words (1518 [octets])/(2 [octets])
+ constant c_res_mmu_special_res_num_pages : integer := 256;
+ constant c_res_mmu_resource_num : integer := 3; -- (1) unknown; (2) special; (3) normal
+ constant c_res_mmu_resource_num_width : integer := 2;
+ ----------------------------------------------
+ constant c_hwdu_input_block_width : integer := 16;
+ constant c_hwdu_mmu_width : integer := 10*3;
+ constant c_hwdu_output_block_width : integer := 8;
+
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block<< with >>Memory Management Unit<<
----------------------------------------------------------------------------------------------------
@@ -127,7 +162,8 @@ architecture rtl of xswc_core is
signal ib_page_alloc_req : std_logic_vector(g_num_ports - 1 downto 0);
signal ib_pageaddr_output : std_logic_vector(g_num_ports * c_mpm_page_addr_width - 1 downto 0);
signal ib_set_usecnt : std_logic_vector(g_num_ports - 1 downto 0);
- signal ib_usecnt : std_logic_vector(g_num_ports * c_usecount_width - 1 downto 0);
+ signal ib_usecnt_set : std_logic_vector(g_num_ports * c_usecount_width - 1 downto 0);
+ signal ib_usecnt_alloc : std_logic_vector(g_num_ports * c_usecount_width - 1 downto 0);
-- Memory Management Unit -> Input Block
signal mmu_page_alloc_done : std_logic_vector(g_num_ports - 1 downto 0);
@@ -156,7 +192,8 @@ architecture rtl of xswc_core is
signal ib_pageaddr_to_pta : std_logic_vector(g_num_ports * c_mpm_page_addr_width - 1 downto 0);
signal ib_mask : std_logic_vector(g_num_ports * g_num_ports - 1 downto 0);
signal ib_prio : std_logic_vector(g_num_ports * c_prio_width - 1 downto 0);
- signal ib_pck_size : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
+-- signal ib_pck_size : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
+ signal ib_hp : std_logic_vector(g_num_ports -1 downto 0);
-- Pck Transfer Arbiter -> Input Block
signal pta_transfer_ack : std_logic_vector(g_num_ports - 1 downto 0);
@@ -169,7 +206,10 @@ architecture rtl of xswc_core is
signal pta_data_valid : std_logic_vector(g_num_ports -1 downto 0);
signal pta_pageaddr : std_logic_vector(g_num_ports * c_mpm_page_addr_width- 1 downto 0);
signal pta_prio : std_logic_vector(g_num_ports * c_prio_width - 1 downto 0);
- signal pta_pck_size : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
+-- signal pta_pck_size : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
+
+ signal pta2ob_hp : std_logic_vector(g_num_ports -1 downto 0);
+ signal pta2ob_resource : std_logic_vector(g_num_ports *c_res_mmu_resource_num_width -1 downto 0);
-- Input Block -> Pck Transfer Arbiter
signal ob_ack : std_logic_vector(g_num_ports -1 downto 0);
@@ -265,8 +305,10 @@ architecture rtl of xswc_core is
signal mmu_free_done : std_logic_vector(g_num_ports-1 downto 0);
signal mmu2ppfm_free_last_usecnt : std_logic_vector(g_num_ports-1 downto 0);
- ---- end tmp
-
+ -- output_traffic_shaper -> output_block
+ signal ots2ob_output_masks : t_classes_array(g_num_ports-1 downto 0);
+
+ --
type t_tap_ib_array is array(0 to g_num_ports-1) of std_logic_vector(49+62 downto 0);
type t_tap_ob_array is array(0 to g_num_ports-1) of std_logic_vector(15 downto 0);
signal tap_mpm : std_logic_vector(61 downto 0);
@@ -291,6 +333,35 @@ architecture rtl of xswc_core is
signal CONTROL0 : std_logic_vector(35 downto 0);
signal tap : std_logic_vector(127 downto 0);
+
+
+ signal ppfm2mmu_free_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
+ signal ppfm2mmu_free_resource_valid : std_logic_vector(g_num_ports -1 downto 0);
+ signal ppfm2mmu_force_free_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
+ signal ppfm2mmu_force_free_resource_valid : std_logic_vector(g_num_ports -1 downto 0);
+
+ signal mmu2ppfm_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
+ ----------------------------------------------------------------------------------------------------
+ -- signals connecting >>Input Block (IB) << with >>Page allocator (MMU)<< -- resource management
+ ----------------------------------------------------------------------------------------------------
+
+ signal mmu2ib_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
+ signal ib2mmu_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
+ signal ib2mmu_rescnt_page_num : std_logic_vector(g_num_ports*c_mpm_page_addr_width -1 downto 0);
+ signal mmu2ib_res_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
+ signal mmu2ib_res_almost_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
+ signal mmu2ib_set_usecnt_succeeded : std_logic_vector(g_num_ports -1 downto 0);
+
+ type t_hwdu_input_block_array is array(0 to g_num_ports-1) of std_logic_vector(c_hwdu_input_block_width-1 downto 0);
+ type t_hwdu_output_block_array is array(0 to g_num_ports-1) of std_logic_vector(c_hwdu_output_block_width-1 downto 0);
+
+ signal hwdu_input_block : t_hwdu_input_block_array;
+ signal hwdu_output_block : t_hwdu_output_block_array;
+ signal hwdu_mmu : std_logic_vector(c_hwdu_mmu_width -1 downto 0);
+
+ signal dbg_pckstart_pageaddr : std_logic_vector(g_num_ports*c_mpm_page_addr_width - 1 downto 0);
+ signal dbg_pckinter_pageaddr : std_logic_vector(g_num_ports*c_mpm_page_addr_width - 1 downto 0);
+
begin --rtl
--chipscope_icon_1: chipscope_icon
@@ -324,7 +395,10 @@ architecture rtl of xswc_core is
g_page_size => g_mpm_page_size,
g_partial_select_width => c_mpm_partial_sel_width,
g_ll_data_width => c_ll_data_width,
- g_port_index => i
+ g_port_index => i,
+ -- resource management
+ g_resource_num => c_res_mmu_resource_num,
+ g_resource_num_width => c_res_mmu_resource_num_width
)
port map (
clk_i => clk_i,
@@ -345,10 +419,19 @@ architecture rtl of xswc_core is
mmu_set_usecnt_o => ib_set_usecnt(i),
mmu_set_usecnt_done_i => mmu_set_usecnt_done(i),
- mmu_usecnt_o => ib_usecnt((i + 1) * c_usecount_width -1 downto i * c_usecount_width),
+ mmu_usecnt_set_o => ib_usecnt_set((i + 1) * c_usecount_width -1 downto i * c_usecount_width),
+ mmu_usecnt_alloc_o => ib_usecnt_alloc((i + 1) * c_usecount_width -1 downto i * c_usecount_width),
mmu_nomem_i => mmu_nomem,
mmu_pageaddr_o => ib_pageaddr_output((i + 1) * c_mpm_page_addr_width - 1 downto i * c_mpm_page_addr_width),
+ -- resource management
+-- mmu_resource_i => mmu2ib_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
+ mmu_resource_o => ib2mmu_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
+ mmu_rescnt_page_num_o => ib2mmu_rescnt_page_num ((i+1)*c_mpm_page_addr_width -1 downto i*c_mpm_page_addr_width),
+ mmu_set_usecnt_succeeded_i => mmu2ib_set_usecnt_succeeded(i),
+ mmu_res_full_i => mmu2ib_res_full ((i+1)*c_res_mmu_resource_num -1 downto i*c_res_mmu_resource_num),
+ mmu_res_almost_full_i => mmu2ib_res_almost_full ((i+1)*c_res_mmu_resource_num -1 downto i*c_res_mmu_resource_num),
+
-------------------------------------------------------------------------------
-- I/F with Pck's Pages Freeing Module (PPFM)
-------------------------------------------------------------------------------
@@ -359,9 +442,11 @@ architecture rtl of xswc_core is
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
- rtu_rsp_ack_o => rtu_ack_o(i),
- rtu_rsp_valid_i => rtu_rsp_i(i).valid,
+ rtu_rsp_ack_o => rtu_ack_o(i),
+ rtu_rsp_abort_o => rtu_abort_o(i),
+ rtu_rsp_valid_i => rtu_rsp_i(i).valid,
rtu_dst_port_mask_i => rtu_rsp_i(i).port_mask(g_num_ports - 1 downto 0),
+ rtu_hp_i => rtu_rsp_i(i).hp, --'0', -- TODO: add stuff to RTU
rtu_drop_i => rtu_rsp_i(i).drop,
rtu_prio_i => rtu_rsp_i(i).prio(c_prio_width - 1 downto 0),
@@ -397,29 +482,39 @@ architecture rtl of xswc_core is
pta_pageaddr_o => ib_pageaddr_to_pta((i + 1) * c_mpm_page_addr_width-1 downto i * c_mpm_page_addr_width),
pta_mask_o => ib_mask ((i + 1) * g_num_ports -1 downto i * g_num_ports),
pta_prio_o => ib_prio ((i + 1) * c_prio_width -1 downto i * c_prio_width),
- pta_pck_size_o => ib_pck_size ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
-
- tap_out_o => tap_ib(i)
+-- pta_pck_size_o => ib_pck_size ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
+-- pta_resource_o => open,
+ pta_hp_o => ib_hp (i),
+ dbg_hwdu_o => hwdu_input_block(i),
+ tap_out_o => tap_ib(i),
+
+ dbg_pckstart_pageaddr_o => dbg_pckstart_pageaddr((i+1)*c_mpm_page_addr_width-1 downto i*c_mpm_page_addr_width),
+ dbg_pckinter_pageaddr_o => dbg_pckinter_pageaddr((i+1)*c_mpm_page_addr_width-1 downto i*c_mpm_page_addr_width)
);
--- OUTPUT_BLOCK: swc_output_block
- OUTPUT_BLOCK: xswc_output_block
+ OUTPUT_BLOCK: xswc_output_block_new
+-- OUTPUT_BLOCK: xswc_output_block
generic map(
g_max_pck_size_width => c_max_pck_size_width,
- g_output_block_per_prio_fifo_size => g_output_block_per_prio_fifo_size,
- g_prio_width => c_prio_width,
- g_prio_num => g_prio_num,
+ g_output_block_per_queue_fifo_size => g_output_block_per_queue_fifo_size,
+ g_queue_num_width => c_output_queue_num_width,
+ g_queue_num => g_output_queue_num,
+
+ g_prio_num_width => c_prio_width,
g_mpm_page_addr_width => c_mpm_page_addr_width,
g_mpm_data_width => c_mpm_data_width,
g_mpm_partial_select_width => c_mpm_partial_sel_width,
g_mpm_fetch_next_pg_in_advance => g_mpm_fetch_next_pg_in_advance,
+ g_mmu_resource_num_width => c_res_mmu_resource_num_width,
+
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_wb_sel_width => g_wb_sel_width,
- g_wb_ob_ignore_ack => g_wb_ob_ignore_ack
+ g_wb_ob_ignore_ack => g_wb_ob_ignore_ack,
+ g_drop_outqueue_head_on_full => g_drop_outqueue_head_on_full
)
port map (
clk_i => clk_i,
@@ -430,6 +525,9 @@ architecture rtl of xswc_core is
pta_transfer_data_valid_i=> pta_data_valid(i),
pta_pageaddr_i => pta_pageaddr((i + 1) * c_mpm_page_addr_width-1 downto i * c_mpm_page_addr_width),
pta_prio_i => pta_prio ((i + 1) * c_prio_width -1 downto i * c_prio_width),
+
+ pta_hp_i => pta2ob_hp(i),
+-- pta_resource_i => pta2ob_resource((i + 1) * c_res_mmu_resource_num_width -1 downto i * c_res_mmu_resource_num_width),
-- pta_pck_size_i => pta_pck_size((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
pta_transfer_data_ack_o => ob_ack(i),
-------------------------------------------------------------------------------
@@ -439,6 +537,7 @@ architecture rtl of xswc_core is
mpm_d_i => mpm2ob_d((i+1)*c_mpm_data_width-1 downto i*c_mpm_data_width),
mpm_dvalid_i => mpm2ob_dvalid(i),
mpm_dlast_i => mpm2ob_dlast(i),
+--dsel-- mpm_dsel_i => mpm2ob_dsel((i+1)*c_mpm_partial_sel_width -1 downto i*c_mpm_partial_sel_width),
mpm_dreq_o => ob2mpm_dreq(i),
mpm_abort_o => ob2mpm_abort(i),
mpm_pg_addr_o => ob2mpm_pg_addr((i+1)*c_mpm_page_addr_width -1 downto i*c_mpm_page_addr_width),
@@ -451,51 +550,78 @@ architecture rtl of xswc_core is
ppfm_free_done_i => ppfm_free_done_to_ob(i),
ppfm_free_pgaddr_o => ob_free_pgaddr((i + 1) * c_mpm_page_addr_width -1 downto i * c_mpm_page_addr_width),
+ -------------------------------------------------------------------------------
+ --: output traffic shaper (PAUSE + time-aware-shaper)
+ -------------------------------------------------------------------------------
+ ots_output_mask_i => ots2ob_output_masks(i),
+ ots_output_drop_at_rx_hp_i=> shaper_drop_at_hp_ena_i,
+
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i => src_i(i),
src_o => src_o(i),
-
- tap_out_o => tap_ob(i)
+ dbg_hwdu_o => hwdu_output_block(i),
+ tap_out_o => tap_ob(i)
);
end generate gen_blocks;
+ OUTPUT_TRAFFIC_SHAPER: swc_output_traffic_shaper
+ generic map (
+ g_num_ports => g_num_ports,
+ g_num_global_pause => g_num_global_pause)
+ port map(
+ rst_n_i => rst_n_i,
+ clk_i => clk_i,
+-- shaper_request_i => shaper_request_i,
+-- shaper_ports_i => shaper_ports_i,
+-- pause_requests_i => pause_requests_i,
+ global_pause_i => global_pause_i,
+ perport_pause_i => perport_pause_i,
+ output_masks_o => ots2ob_output_masks
+ );
PCK_PAGES_FREEEING_MODULE: swc_multiport_pck_pg_free_module
generic map(
- g_num_ports => g_num_ports,
- g_page_addr_width => c_mpm_page_addr_width,
- g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
- g_data_width => c_ll_data_width
+ g_num_ports => g_num_ports,
+ g_page_addr_width => c_mpm_page_addr_width,
+ g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
+ g_data_width => c_ll_data_width,
+ g_resource_num_width => c_res_mmu_resource_num_width
)
port map(
- clk_i => clk_i,
- rst_n_i => rst_n_i,
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
- ib_force_free_i => ib_force_free,
- ib_force_free_done_o => ppfm_force_free_done_to_ib,
- ib_force_free_pgaddr_i => ib_force_free_pgaddr,
+ ib_force_free_i => ib_force_free,
+ ib_force_free_done_o => ppfm_force_free_done_to_ib,
+ ib_force_free_pgaddr_i => ib_force_free_pgaddr,
- ob_free_i => ob_free,
- ob_free_done_o => ppfm_free_done_to_ob,
- ob_free_pgaddr_i => ob_free_pgaddr,
+ ob_free_i => ob_free,
+ ob_free_done_o => ppfm_free_done_to_ob,
+ ob_free_pgaddr_i => ob_free_pgaddr,
- ll_read_addr_o => fp2ll_addr, --ppfm_read_addr,
- ll_read_data_i => ll2fp_data, --ll_data,
- ll_read_req_o => fp2ll_rd_req, --ppfm_read_req,
- ll_read_valid_data_i => ll2fp_read_done, --ll_read_valid_data,
+ ll_read_addr_o => fp2ll_addr, --ppfm_read_addr,
+ ll_read_data_i => ll2fp_data, --ll_data,
+ ll_read_req_o => fp2ll_rd_req, --ppfm_read_req,
+ ll_read_valid_data_i => ll2fp_read_done, --ll_read_valid_data,
- mmu_force_free_o => ppfm_force_free,
- mmu_force_free_done_i => mmu_force_free_done,
- mmu_force_free_pgaddr_o => ppfm_force_free_pgaddr,
+ mmu_resource_i => mmu2ppfm_resource,
+
+ mmu_force_free_o => ppfm_force_free,
+ mmu_force_free_done_i => mmu_force_free_done,
+ mmu_force_free_pgaddr_o => ppfm_force_free_pgaddr,
+ mmu_free_resource_o => ppfm2mmu_free_resource,
+ mmu_free_resource_valid_o => ppfm2mmu_free_resource_valid,
- mmu_free_o => ppfm_free,
- mmu_free_done_i => mmu_free_done,
- mmu_free_pgaddr_o => ppfm_free_pgaddr,
- mmu_free_last_usecnt_i => mmu2ppfm_free_last_usecnt
+ mmu_free_o => ppfm_free,
+ mmu_free_done_i => mmu_free_done,
+ mmu_free_pgaddr_o => ppfm_free_pgaddr,
+ mmu_free_last_usecnt_i => mmu2ppfm_free_last_usecnt,
+ mmu_force_free_resource_o => ppfm2mmu_force_free_resource,
+ mmu_force_free_resource_valid_o => ppfm2mmu_force_free_resource_valid
);
@@ -543,7 +669,15 @@ architecture rtl of xswc_core is
g_page_addr_width => c_mpm_page_addr_width,
g_num_ports => g_num_ports,
g_page_num => c_mpm_page_num,
- g_usecount_width => c_usecount_width
+ g_usecount_width => c_usecount_width,
+ -- management
+ g_with_RESOURCE_MGR => false, --true,
+ g_max_pck_size => c_res_mmu_max_pck_size,
+ g_page_size => g_mpm_page_size,
+ g_special_res_num_pages => c_res_mmu_special_res_num_pages,
+ g_resource_num => c_res_mmu_resource_num,
+ g_resource_num_width => c_res_mmu_resource_num_width,
+ g_num_dbg_vector_width => c_hwdu_mmu_width
)
port map (
rst_n_i => rst_n_i,
@@ -555,7 +689,10 @@ architecture rtl of xswc_core is
set_usecnt_i => ib_set_usecnt,
set_usecnt_done_o => mmu_set_usecnt_done,
- usecnt_i => ib_usecnt,
+
+ usecnt_set_i => ib_usecnt_set,
+ usecnt_alloc_i => ib_usecnt_alloc,
+
pgaddr_usecnt_i => ib_pageaddr_output,
free_i => ppfm_free,
@@ -567,8 +704,23 @@ architecture rtl of xswc_core is
force_free_done_o => mmu_force_free_done,
pgaddr_force_free_i => ppfm_force_free_pgaddr,
+ nomem_o => mmu_nomem,
+ --------------------------- resource management ----------------------------------
+ resource_i => ib2mmu_resource,
+ resource_o => mmu2ppfm_resource,
+
+ free_resource_i => ppfm2mmu_free_resource,
+ free_resource_valid_i => ppfm2mmu_free_resource_valid,
+ force_free_resource_i => ppfm2mmu_force_free_resource,
+ force_free_resource_valid_i=> ppfm2mmu_force_free_resource_valid,
+
+ rescnt_page_num_i => ib2mmu_rescnt_page_num,
+ set_usecnt_succeeded_o => mmu2ib_set_usecnt_succeeded,
- nomem_o => mmu_nomem
+ res_full_o => mmu2ib_res_full,
+ res_almost_full_o => mmu2ib_res_almost_full,
+
+ dbg_o => hwdu_mmu
-- tap_out_o => tap_alloc
);
@@ -619,7 +771,7 @@ architecture rtl of xswc_core is
generic map(
g_page_addr_width => c_mpm_page_addr_width,
g_prio_width => c_prio_width,
- g_max_pck_size_width => c_max_pck_size_width,
+-- g_max_pck_size_width => c_max_pck_size_width,
g_num_ports => g_num_ports
)
port map(
@@ -632,7 +784,8 @@ architecture rtl of xswc_core is
ob_ack_i => ob_ack,
ob_pageaddr_o => pta_pageaddr,
ob_prio_o => pta_prio,
- ob_pck_size_o => pta_pck_size,
+-- ob_pck_size_o => pta_pck_size,
+ ob_hp_o => pta2ob_hp,
-------------------------------------------------------------------------------
-- I/F with Input Block (IB)
-------------------------------------------------------------------------------
@@ -642,9 +795,18 @@ architecture rtl of xswc_core is
ib_pageaddr_i => ib_pageaddr_to_pta,
ib_mask_i => ib_mask,
ib_prio_i => ib_prio,
- ib_pck_size_i => ib_pck_size
+-- ib_pck_size_i => ib_pck_size
+ ib_hp_i => ib_hp
);
+ dbg_o(31 downto 0) <= "00" & hwdu_mmu;
+
+ hwdu_gen: for i in 0 to (g_num_ports-1) generate --19 ports for 18-port switch
+ dbg_o((i+1)*c_hwdu_input_block_width+32-1 downto
+ i*c_hwdu_input_block_width+32) <= hwdu_input_block(i);
+ dbg_o((i+1)*c_hwdu_output_block_width+(g_num_ports*c_hwdu_input_block_width)+32-1 downto
+ i*c_hwdu_output_block_width+(g_num_ports*c_hwdu_input_block_width)+32) <= hwdu_output_block(i);
+ end generate hwdu_gen;
end rtl;
diff --git a/modules/wrsw_swcore/xswc_input_block.vhd b/modules/wrsw_swcore/xswc_input_block.vhd
index 593e091f66c18ce55f51303fc723f9a7cfeaed71..cea11fa9c96d8f0d3d5d9c3544cb00a5fdcb0071 100644
--- a/modules/wrsw_swcore/xswc_input_block.vhd
+++ b/modules/wrsw_swcore/xswc_input_block.vhd
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-28
--- Last update: 2012-07-10
+-- Last update: 2012-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -74,6 +74,7 @@
-- 2012-01-20 3.0 mlipinsk wisbhonized
-- 2012-02-02 4.0 mlipinsk generic-azed
-- 2012-02-15 5.0 mlipinsk adapted to the new (async) MPM
+-- 2013-03-08 5.1 mlipinsk removed dsel
-------------------------------------------------------------------------------
-- TODO:
-- 1) think about enabling reception of new pck when still waiting for the transfer,
@@ -113,7 +114,12 @@ entity xswc_input_block is
g_partial_select_width : integer;
g_ll_data_width : integer;
g_max_oob_size : integer; -- on words (16 bits)
- g_port_index : integer -- ID of this port
+ g_port_index : integer; -- ID of this port
+
+ --- resource management
+ g_resource_num : integer;
+ g_resource_num_width : integer
+
);
port (
clk_i : in std_logic;
@@ -155,18 +161,35 @@ entity xswc_input_block is
-- user count to be set (associated with an allocated page) in two cases:
-- * mmu_pagereq_o is HIGH - normal allocation
+ mmu_usecnt_alloc_o : out std_logic_vector(g_usecount_width - 1 downto 0);
-- * mmu_set_usecnt_o is HIGH - force user count to existing page alloc
- mmu_usecnt_o : out std_logic_vector(g_usecount_width - 1 downto 0);
+ mmu_usecnt_set_o : out std_logic_vector(g_usecount_width - 1 downto 0);
-- memory full
mmu_nomem_i : in std_logic;
+
+ --------------------------- resource management ----------------------------------
+ -- resource number
+ --mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- outputed when freeing
+ mmu_resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- number of pages added to the resurce
+ mmu_rescnt_page_num_o : out std_logic_vector(g_page_addr_width-1 downto 0);
+ mmu_set_usecnt_succeeded_i : in std_logic;
+ mmu_res_full_i : in std_logic_vector(g_resource_num -1 downto 0);
+ mmu_res_almost_full_i : in std_logic_vector(g_resource_num -1 downto 0);
+
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
+ rtu_rsp_abort_o : out std_logic;
rtu_dst_port_mask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_hp_i : in std_logic;
rtu_drop_i : in std_logic;
rtu_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
@@ -222,11 +245,22 @@ entity xswc_input_block is
-- forwarded
pta_mask_o : out std_logic_vector(g_num_ports - 1 downto 0);
- pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+-- pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+
+ -- information about resoruce allocation
+-- pta_resource_o : out std_logic_vector(g_resource_num_width - 1 downto 0);
+
+ -- htraffic
+ pta_hp_o : out std_logic;
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
- tap_out_o : out std_logic_vector(49 + 62 downto 0)
+ dbg_hwdu_o : out std_logic_vector(15 downto 0);
+
+ tap_out_o: out std_logic_vector(49 + 62 downto 0);
+
+ dbg_pckstart_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
+ dbg_pckinter_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0)
);
end xswc_input_block;
@@ -241,20 +275,22 @@ architecture syn of xswc_input_block is
constant c_max_transfer_delay_width : integer := integer(CEIL(LOG2(real(c_max_transfer_delay + 1))));
- type t_page_alloc is(S_IDLE, -- waiting for some work :)
- S_PCKSTART_SET_USECNT, -- setting usecnt to a page which was allocated
- -- in advance to be used for the first page of
- -- the pck
- -- (only in case of the initially allocated usecnt
- -- is different than required)
- S_PCKSTART_PAGE_REQ, -- allocating in advnace first page of the pck
- S_PCKINTER_PAGE_REQ); -- allocating in advance page to be used by
- -- all but first page of the pck (inter-packet)
+ type t_page_alloc is( S_IDLE, -- waiting for some work :)
+ S_PCKSTART_SET_AND_REQ, -- new state to do setting usecnt and requesting
+ -- new page at the same time
+ S_PCKSTART_SET_USECNT, -- setting usecnt to a page which was allocated
+ -- in advance to be used for the first page of
+ -- the pck
+ -- (only in case of the initially allocated usecnt
+ -- is different than required)
+ S_PCKSTART_PAGE_REQ, -- allocating in advnace first page of the pck
+ S_PCKINTER_PAGE_REQ); -- allocating in advance page to be used by
+ -- all but first page of the pck (inter-packet)
type t_transfer_pck is(S_IDLE, -- wait for some work :), it is used only after reset
S_READY, -- being in S_READY state means that we are in sync with rcv_pck
S_WAIT_RTU_VALID, -- Started receiving pck, wait for RTU decision
S_WAIT_SOF, -- received RTU decision but new pck has not been started
- -- still receiving the old one, or non
+ -- still receiving the old one, or non
S_SET_USECNT, -- set usecnt of the first page
S_WAIT_WITH_TRANSFER, -- waits for ll_write to clear the first page
S_TOO_LONG_TRANSFER,
@@ -262,38 +298,38 @@ architecture syn of xswc_input_block is
S_TRANSFERED, -- transfer has been done, waiting for the end of pck (EOF
S_DROP -- after receiving RTU decision to drop the pck,
- -- it still needs to be received
+ -- it still needs to be received
);
type t_rcv_pck is(S_IDLE, -- wait for some work :)
- S_READY, -- Can accept new pck (i.e. the previous pck has been transfered
- S_PAUSE, -- need to pause reception (internal reason, e.g.: next page not allocated)
- -- still receiving the old one, or non
- S_RCV_DATA, -- accepting pck
- S_DROP, -- if
- S_WAIT_FORCE_FREE, -- waits for the access to the force freeing process (it
- -- only happens when the previous request has not been handled
- -- (in theory, hardly possible, so it will happen for sure ;=))
- S_INPUT_STUCK -- it might happen that the SWcore gets stack, in such case we need
- -- to decide what to do (drop/stall/etc), it is recognzied and done
- -- here
- );
+ S_READY, -- Can accept new pck (i.e. the previous pck has been transfered
+ S_PAUSE, -- need to pause reception (internal reason, e.g.: next page not allocated)
+ -- still receiving the old one, or non
+ S_RCV_DATA, -- accepting pck
+ S_DROP, -- if
+ S_WAIT_FORCE_FREE, -- waits for the access to the force freeing process (it
+ -- only happens when the previous request has not been handled
+ -- (in theory, hardly possible, so it will happen for sure ;=))
+ S_INPUT_STUCK -- it might happen that the SWcore gets stack, in such case we need
+ -- to decide what to do (drop/stall/etc), it is recognzied and done
+ -- here
+ );
type t_ll_write is(S_IDLE, -- wait for some work :)
- S_READY_FOR_PGR_AND_DLAST, -- can write both:
- -- (1) request of inter-pck page (mpm_pg_req_i)
- -- (2) request of last page write (dlast)
- S_READY_FOR_DLAST_ONLY, -- can write only last page (dlast) since the
- -- inter-pck page has not been allocated yet
- S_WRITE, -- write Linked List (either double write (with
- -- clearing the next page to be used) or just
- -- one page (if next page not allocated yet)
- S_EOF_ON_WR, -- request for writting the last page (dlast)
- -- received while writting to Linked List
- S_SOF_ON_WR -- reception of new PCK received while writting
- ); -- this might require some work (if the next
- -- first page is not cleard) but it also might
- -- require no work
+ S_READY_FOR_PGR_AND_DLAST, -- can write both:
+ -- (1) request of inter-pck page (mpm_pg_req_i)
+ -- (2) request of last page write (dlast)
+ S_READY_FOR_DLAST_ONLY, -- can write only last page (dlast) since the
+ -- inter-pck page has not been allocated yet
+ S_WRITE, -- write Linked List (either double write (with
+ -- clearing the next page to be used) or just
+ -- one page (if next page not allocated yet)
+ S_EOF_ON_WR, -- request for writting the last page (dlast)
+ -- received while writting to Linked List
+ S_SOF_ON_WR -- reception of new PCK received while writting
+ ); -- this might require some work (if the next
+ -- first page is not cleard) but it also might
+ -- require no work
-- state machines
signal s_page_alloc : t_page_alloc; -- page allocation and usecnt setting
signal s_transfer_pck : t_transfer_pck; -- reception of RTU decision, its transfer to outputs
@@ -326,10 +362,12 @@ architecture syn of xswc_input_block is
signal rtu_rsp_ack : std_logic;
-- rtu decision stored for the current pck
- signal current_prio : std_logic_vector(g_prio_width - 1 downto 0);
- signal current_mask : std_logic_vector(g_num_ports - 1 downto 0);
- signal current_usecnt : std_logic_vector(g_usecount_width - 1 downto 0);
- signal current_drop : std_logic;
+ signal current_prio : std_logic_vector(g_prio_width - 1 downto 0);
+ signal current_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal current_res_info : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal current_hp : std_logic;
+ signal current_usecnt : std_logic_vector(g_usecount_width - 1 downto 0);
+ signal current_drop : std_logic;
-- this is stored when first page is taken from the allocated in advanced register
signal current_pckstart_pageaddr : std_logic_vector(g_page_addr_width - 1 downto 0);
@@ -340,6 +378,8 @@ architecture syn of xswc_input_block is
signal pta_transfer_pck : std_logic;
signal pta_pageaddr : std_logic_vector(g_page_addr_width - 1 downto 0);
signal pta_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal pta_resource : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal pta_hp : std_logic;
signal pta_prio : std_logic_vector(g_prio_width - 1 downto 0);
-- signal pta_pck_size : std_logic_vector(g_max_pck_size_width - 1 downto 0);
@@ -362,7 +402,6 @@ architecture syn of xswc_input_block is
signal snk_we_int : std_logic;
signal snk_stall_int : std_logic;
-- outputs
- signal snk_err_int : std_logic;
signal snk_ack_int : std_logic;
signal snk_rty_int : std_logic;
signal snk_stall_force_h : std_logic;
@@ -394,7 +433,6 @@ architecture syn of xswc_input_block is
-- used to produce delayed in_pck_sof -- basically, this is illegal by pWB standard, but
-- if it happens, we loose, pck, why not to take care of this?
signal in_pck_sof_on_stall : std_logic;
- signal in_pck_delayed_sof : std_logic;
-- indicates that the reception of pck finishes due to :
-- (1) eof, error (by in_pck_*)
@@ -426,10 +464,7 @@ architecture syn of xswc_input_block is
next_page : std_logic_vector(g_page_addr_width - 1 downto 0);
next_page_valid : std_logic;
addr : std_logic_vector(g_page_addr_width - 1 downto 0);
--- dsel : std_logic_vector(g_partial_select_width - 1 downto 0);
size : std_logic_vector(c_page_size_width - 1 downto 0);
--- oob_size : std_logic_vector(c_max_oob_size_width - 1 downto 0);
--- oob_dsel : std_logic_vector(g_partial_select_width - 1 downto 0);
first_page_clr : std_logic;
end record;
@@ -502,7 +537,20 @@ architecture syn of xswc_input_block is
signal lw_pckstart_pg_clred : std_logic;
signal pckstart_pg_clred : std_logic;
+ signal alloc_FSM : std_logic_vector(2 downto 0);
+ signal trans_FSM : std_logic_vector(3 downto 0);
+ signal rcv_p_FSM : std_logic_vector(3 downto 0);
+ signal linkl_FSM : std_logic_vector(3 downto 0);
+
signal zeros : std_logic_vector(g_num_ports - 1 downto 0);
+
+ constant c_wrf_status_error : t_wrf_status_reg := (
+ '0', -- is_hp
+ '0', -- has_smac
+ '0', -- has_crc
+ '1', -- error
+ '0', -- tag_me
+ x"00");-- match_class
-------------------------------------------------------------------------------
-- Function which calculates number of 1's in a vector
-------------------------------------------------------------------------------
@@ -526,67 +574,95 @@ architecture syn of xswc_input_block is
function f_gen_mask(index : integer; length : integer)
return std_logic_vector is
- variable tmp : std_logic_vector(length-1 downto 0);
+ variable tmp : std_logic_vector(length-1 downto 0);
begin
- tmp := (others => '0');
+ tmp := (others => '0');
tmp(index) := '1';
return tmp;
- end f_gen_mask;
-
- function f_slv_resize(x : std_logic_vector; len : natural) return std_logic_vector is
+ end function f_gen_mask;
+
+ function f_slv_resize(x: std_logic_vector; len: natural) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
- tmp := (others => '0');
+ tmp := (others => '0');
tmp(x'length-1 downto 0) := x;
return tmp;
- end f_slv_resize;
+ end function f_slv_resize;
-
-
-
- function f_enum2nat (enum_arg : t_page_alloc) return std_logic_vector is
- begin
- for t in t_page_alloc loop
- if(enum_arg = t) then
- return std_logic_vector(to_unsigned(t_page_alloc'pos(t), 4));
- end if;
- end loop; -- i
- return "0000";
- end function f_enum2nat;
- function f_enum2nat (enum_arg : t_rcv_pck) return std_logic_vector is
- begin
- for t in t_rcv_pck loop
- if(enum_arg = t) then
- return std_logic_vector(to_unsigned(t_rcv_pck'pos(t), 4));
- end if;
- end loop; -- i
- return "0000";
- end function f_enum2nat;
- function f_enum2nat (enum_arg : t_ll_write) return std_logic_vector is
- begin
- for t in t_ll_write loop
- if(enum_arg = t) then
- return std_logic_vector(to_unsigned(t_ll_write'pos(t), 4));
- end if;
- end loop; -- i
- return "0000";
- end function f_enum2nat;
- function f_enum2nat (enum_arg : t_transfer_pck) return std_logic_vector is
- begin
- for t in t_transfer_pck loop
- if(enum_arg = t) then
- return std_logic_vector(to_unsigned(t_transfer_pck'pos(t), 4));
- end if;
- end loop; -- i
- return "0000";
- end function f_enum2nat;
-
- constant c_force_usecnt : boolean := true;
-
-begin --arch
+function f_enum2nat (enum_arg :t_page_alloc) return std_logic_vector is
+begin
+ for t in t_page_alloc loop
+ if(enum_arg = t) then
+ return std_logic_vector(to_unsigned(t_page_alloc'pos(t),4));
+ end if;
+ end loop; -- i
+ return "0000";
+end function f_enum2nat;
+function f_enum2nat (enum_arg :t_rcv_pck) return std_logic_vector is
+begin
+ for t in t_rcv_pck loop
+ if(enum_arg = t) then
+ return std_logic_vector(to_unsigned(t_rcv_pck'pos(t),4));
+ end if;
+ end loop; -- i
+ return "0000";
+end function f_enum2nat;
+function f_enum2nat (enum_arg :t_ll_write) return std_logic_vector is
+begin
+ for t in t_ll_write loop
+ if(enum_arg = t) then
+ return std_logic_vector(to_unsigned(t_ll_write'pos(t),4));
+ end if;
+ end loop; -- i
+ return "0000";
+end function f_enum2nat;
+function f_enum2nat (enum_arg :t_transfer_pck) return std_logic_vector is
+begin
+ for t in t_transfer_pck loop
+ if(enum_arg = t) then
+ return std_logic_vector(to_unsigned(t_transfer_pck'pos(t),4));
+ end if;
+ end loop; -- i
+ return "0000";
+end function f_enum2nat;
+
+constant c_force_usecnt : boolean := TRUE;
+ constant c_special_res : std_logic_vector(7 downto 0) := x"01";
+ constant c_normal_res : std_logic_vector(7 downto 0) := x"02";
+-- resource management
+ signal mmu_resource_out : std_logic_vector(g_resource_num_width-1 downto 0);
+ signal mmu_rescnt_page_num : std_logic_vector(g_page_addr_width-1 downto 0);
+ signal mmu_res_full : std_logic_vector(g_resource_num -1 downto 0);
+ signal mmu_res_almost_full : std_logic_vector(g_resource_num -1 downto 0);
+
+ signal unknown_res_page_cnt : unsigned(g_page_addr_width-1 downto 0);
+
+ signal res_info_valid : std_logic;
+ signal res_info : std_logic_vector(g_resource_num_width-1 downto 0);
+
+ -- the number of pages reserved for a given resource (res_num) is not enough to accommodate
+ -- max_size ethernet frame. In most cases we don't know what the received frame's sie will be
+ -- (unless we needed to wait for RTU's decision to the end of reception) so we drop the frame
+ -- if the resoruce is almost full
+ signal res_info_almsot_full : std_logic;
+ signal cur_res_info_almsot_full : std_logic;
+
+ -- a currently requested resource is full
+ signal res_info_full : std_logic;
+ signal cur_res_info_full : std_logic;
+ signal mem_full_dump : std_logic;
+
+ -- synchronizing 4 FSMs to work together is not easy....:
+ signal tp_transfer_ready : std_logic;
+ signal tp_transfer_rtu_valid : std_logic;
+ signal tp_transfer_wait_sof : std_logic;
+ signal tp_transfer_set_usecnt : std_logic;
- zeros <= (others => '0');
+ signal dbg_dropped_on_res_full : std_logic;
+begin --archS_PCKSTART_SET_AND_REQ
+
+ zeros <= (others => '0');
--================================================================================================
--------------------------------------------------------------------------------------------------
----------------------- Receiving the PCK and writting to MPM -------------------------------
@@ -611,7 +687,7 @@ begin --arch
-- we store in FBM addr and data
in_pck_dat <= snk_adr_int & snk_dat_int;
-
+
-- detecting the end of the pck
-- it is enough always, except special case when we receive eof during PAUSE state,
-- in this case,we come back to RCV_DATA and regenerate EOF (this is to make things simpler,
@@ -622,21 +698,29 @@ begin --arch
in_pck_eof <= in_pck_eof_normal or in_pck_eof_on_pause;
-- detecting error
- in_pck_err <= '1' when in_pck_dvalid = '1' and
- (snk_adr_int = c_WRF_STATUS) and
- (f_unmarshall_wrf_status(snk_dat_int).error = '1') else
+ in_pck_err <= '1' when in_pck_dvalid = '1' and
+ (snk_adr_int = c_WRF_STATUS) and
+ (f_unmarshall_wrf_status(snk_dat_int).error = '1') else
'0';
-
- --detecting end of data in the received frame, the data shall be followed by
- -- (1) nothing (end of frame)
- -- (2) OOB
- -- (3) USER data
- -- so end of data is most often not equal to end of frame
-
- -- indicaste that the current input is data or status,
-
+
+ -- this indicates that a memory-full happens when the frame has been already tranfsered
+ -- to output (probably already being send out...) so we need to handled this properly, i.e.:
+ -- * write to MPM error status for the output
+ -- * stop receving
+ mem_full_dump <= '1' when (lw_sync_2nd_stage_chk = '1' and
+ lw_sync_second_stage = '0' and
+ (mmu_nomem_i = '1' or cur_res_info_full = '1') and
+ tp_transfer_valid = '1') else
+ '0';
+-- -- this indicates that frame has not been yet transfered, we are lucky, we can
+-- -- just drop receving the frame with no extra magic
+-- mem_full_drop <= '1' when (lw_sync_2nd_stage_chk = '1' and
+-- lw_sync_second_stage = '0' and
+-- (mmu_nomem_i = '1' or cur_res_info_full = '1') and
+-- tp_transfer_valid = '1') else
+-- '0';
-- to simplify stuff:
- finish_rcv_pck <= '1' when (in_pck_eof = '1' or in_pck_err = '1' or tp_drop = '1') else '0';
+ finish_rcv_pck <= '1' when (in_pck_eof = '1' or in_pck_err = '1' or tp_drop = '1' or mem_full_dump ='1') else '0';
--==================================================================================================
-- FSM to receive pcks, it translates pWB I/F into MPM I/F
--==================================================================================================
@@ -663,7 +747,8 @@ begin --arch
-- tracks start of frame on the stall (not allowed, but sometimes happen)
if(snk_cyc_int = '1' and snk_cyc_d0 = '0' and snk_stall_int = '1') then
in_pck_sof_on_stall <= '1';
- elsif(in_pck_delayed_sof = '1' and in_pck_sof_on_stall = '1') then
+-- elsif(in_pck_delayed_sof = '1' and in_pck_sof_on_stall = '1') then
+ elsif(in_pck_sof_delayed = '1' and in_pck_sof_on_stall = '1') then
in_pck_sof_on_stall <= '0';
end if;
@@ -712,7 +797,8 @@ begin --arch
rp_in_pck_err <= '0';
rp_accept_rtu <= '1';
- rp_rcv_first_page <= '0';
+ rp_rcv_first_page <= '0';
+ rtu_rsp_abort_o <= '0';
--========================================
else
@@ -720,7 +806,9 @@ begin --arch
mpm_dlast <= '0';
mpm_dvalid <= '0';
in_pck_eof_on_pause <= '0';
- new_pck_first_page <= '0';
+ --if(s_ll_write = S_WRITE) then
+ new_pck_first_page <= '0';
+ --end if;
case s_rcv_pck is
--===========================================================================================
@@ -730,6 +818,7 @@ begin --arch
snk_stall_force_l <= '1';
in_pck_dvalid_d0 <= '0';
in_pck_dat_d0 <= (others => '0');
+ rtu_rsp_abort_o <= '0';
-- Sync with trasnfer_pck FSM and ll_write FSM:
if(lw_sync_first_stage = '1' and rp_sync = '1' and tp_sync = '1') then
@@ -742,9 +831,9 @@ begin --arch
-- received when we get the RTU decision, so we are waiting in IDLE.
-- in such case, we will get tp_drop before getting tp_sync, but we will
-- still have tp_drop when finally tp_sync is HIGH, so this is why the order of if's
- elsif(tp_drop = '1' and -- transfer_pck state indicates the drop decision
+ elsif(tp_drop = '1' and -- transfer_pck state indicates the drop decision
mmu_force_free_req = '0') then -- the pck is not being freed yet
-
+
mmu_force_free_addr <= current_pckstart_pageaddr;
if(mmu_force_free_req = '1') then -- it means that the previous request is still
@@ -761,7 +850,7 @@ begin --arch
snk_stall_force_l <= '0';
snk_stall_force_h <= '1';
rp_drop_on_stuck <= '1';
- rp_accept_rtu <= '1';
+ rp_accept_rtu <= '0'; -- high one cycle later (in drop)
else -- by default: stall when stuck
snk_stall_force_h <= '1';
snk_stall_force_l <= '1';
@@ -797,6 +886,10 @@ begin --arch
--===========================================================================================
when S_RCV_DATA =>
--===========================================================================================
+ -- to extend the span of new_pck_first_page into s_ll_write = S_IDLE, when there is S_SOF
+ if(s_ll_write = S_SOF_ON_WR and new_pck_first_page = '1') then
+ new_pck_first_page <='1';
+ end if;
if(in_pck_dvalid = '1') then
in_pck_dvalid_d0 <= in_pck_dvalid;
in_pck_dat_d0 <= in_pck_dat;
@@ -808,11 +901,30 @@ begin --arch
mpm_dlast <= '1';
end if;
- -- write to MPM data only if you know two consequtive WB writes, this is to detect EOF and
- -- set HIGH dlast at an appropriate time
- if((in_pck_dvalid = '1' and in_pck_dvalid_d0 = '1') or finish_rcv_pck = '1') then
+ if(in_pck_err = '1' and tp_drop = '0') then
+ -- write the error status to the memory (so it's properly sent -- with error)
+ -- and indicate that the error needs to be handled in the next cycle
+ rp_in_pck_err <= '1';
+ mpm_dvalid <= '1';
+ mpm_data <= in_pck_dat;
+ elsif(mem_full_dump = '1')then
+ -- this is an exceptional situatio when
+ -- 1) we've already transfered RTU decision (so output is tx-ing) AND
+ -- 2) memory is full, so we cannot store the rx-ed frame AND
+ -- 3) we cannot pause, if we do, we will create holse on the output
+ -- so we dump the frame, by writing to memory error status (so tx will dump) and
+ -- we stop rx-ing
+ -- We set rp_in_pck_err so it is handled in the next cycle as error
+-- rp_in_pck_err <= '1';
+ mpm_dvalid <= '1';
+ mpm_data <= c_WRF_STATUS & -- generate error msg for out_block
+ f_marshall_wrf_status(c_wrf_status_error);
+ elsif((in_pck_dvalid = '1' and in_pck_dvalid_d0 = '1') or finish_rcv_pck = '1') then
+ -- write to MPM data only if you know two consequtive WB writes, this is to detect EOF and
+ -- set HIGH dlast at an appropriate time
mpm_dvalid <= '1';
mpm_data <= in_pck_dat_d0;
+
end if;
-- here we count the size of page and oob
@@ -827,8 +939,7 @@ begin --arch
end if;
--- below deciding on the next state:
-
- if(in_pck_err = '1') then
+ if(rp_in_pck_err = '1') then
snk_stall_force_h <= '1';
snk_stall_force_l <= '1';
@@ -855,7 +966,7 @@ begin --arch
-- decision from RTU to drop, PCK has not been transfered at all, so we need
-- to handle freeing. we also need to receive the rest of the pck
-- TODO(1.0): throw error????
- elsif(tp_drop = '1') then
+ elsif(tp_drop = '1' ) then
mmu_force_free_addr <= current_pckstart_pageaddr;
@@ -864,14 +975,23 @@ begin --arch
s_rcv_pck <= S_WAIT_FORCE_FREE;
else
mmu_force_free_req <= '1';
- s_rcv_pck <= S_DROP;
+
+ -- it might happen that drop decision comes in the cycle when EOF - can go
+ -- straight to IDLE
+ if(in_pck_eof = '1') then
+ snk_stall_force_h <= '0';
+ snk_stall_force_l <= '1';
+ s_rcv_pck <= S_IDLE;
+ else
+ s_rcv_pck <= S_DROP;
+ end if;
end if;
snk_stall_force_l <= '0';
elsif(in_pck_eof = '1') then
- snk_stall_force_h <= '1';
+ snk_stall_force_h <= '0';
snk_stall_force_l <= '1';
s_rcv_pck <= S_IDLE;
@@ -890,9 +1010,17 @@ begin --arch
-- sync with (expliclitely) with ll_write and (implicitely) with transfer_pck
-- (transfer waits for first page to be cleared (which is condition of sync_2nd_stage,
elsif(lw_sync_2nd_stage_chk = '1' and lw_sync_second_stage = '0') then
-
- snk_stall_force_h <= '1';
- s_rcv_pck <= S_PAUSE;
+
+ if(mem_full_dump ='1') then
+ -- stay in the the same state, we already set rp_in_pck_err and the problem
+ -- will be handled in the next cycle as error.
+ -- if this happens when EOF, we are fine cause EOF was already handled
+ s_rcv_pck <= S_DROP;
+ else
+ -- hopefully will not happen
+ snk_stall_force_h <= '1';
+ s_rcv_pck <= S_PAUSE;
+ end if;
end if;
@@ -900,11 +1028,19 @@ begin --arch
when S_DROP =>
--===========================================================================================
+
if (in_pck_eof = '1' or in_pck_err = '1') then
rp_drop_on_stuck <= '0';
snk_stall_force_h <= '1';
snk_stall_force_l <= '1';
s_rcv_pck <= S_IDLE;
+
+ if(rp_accept_rtu = '1' and rtu_rsp_valid_i = '0' ) then
+ -- no RTU decision for the frame, abort rtu match
+ rp_accept_rtu <= '0';
+ rtu_rsp_abort_o <= '1';
+ end if;
+
end if;
--===========================================================================================
@@ -951,7 +1087,10 @@ begin --arch
when S_INPUT_STUCK =>
--===========================================================================================
- if(tp_stuck = '0') then -- un-stuck the input :)
+ if(tp_stuck = '0' and -- un-stuck the input :)
+ in_pck_sof = '0') then -- could be solved better (more optimal: remember sof), but this will work
+ -- it happened that new frame came when transfer was acked (stuck signal UP..>)
+ -- in such case we were missing SOF and the frame)
s_rcv_pck <= S_IDLE;
@@ -961,7 +1100,8 @@ begin --arch
if(g_input_block_cannot_accept_data = "drop_pck") then
snk_stall_force_l <= '0';
if (in_pck_sof = '1') then
- s_rcv_pck <= S_DROP;
+ rp_accept_rtu <= '1';
+ s_rcv_pck <= S_DROP;
end if;
-- by default: stall when stuck
@@ -992,7 +1132,7 @@ begin --arch
-- requestd, but the request takes time (more then 1 cycle). so we delay setting of
-- *rp_rcv_first_page* to be able to copie the addr to be clearted (in ll_write FSM) from
-- current_pckstart_pageaddr in case *rp_rcv_first_page* is asserted
- if(new_pck_first_page = '1') then
+ if(new_pck_first_page = '1' and rp_rcv_first_page = '0') then
rp_rcv_first_page <= '1';
elsif((mpm_pg_req_i = '1' or mpm_dlast = '1') and rp_rcv_first_page = '1') then
rp_rcv_first_page <= '0';
@@ -1071,11 +1211,16 @@ begin
pckstart_usecnt_write <= (others => '0');
pckstart_usecnt_prev <= (others => '0');
pckstart_usecnt_pgaddr <= (others => '0');
+
+ --- management
+ mmu_resource_out <= (others => '0');
+ mmu_rescnt_page_num <= (others => '0');
--========================================
else
- -- main finite state machine
+ -- main finite state machine
+ --
case s_page_alloc is
--===========================================================================================
@@ -1085,27 +1230,103 @@ begin
pckstart_page_alloc_req <= '0';
pckstart_usecnt_req <= '0';
+--------------------------------------------new crap ---------------------------------------------------
+ if(tp_need_pckstart_usecnt_set = '1' and pckstart_page_in_advance = '0') then
+
+ s_page_alloc <= S_PCKSTART_SET_AND_REQ;
+ pckstart_usecnt_req <= '1';
+ pckstart_page_alloc_req <= '1';
+ pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
+ pckstart_usecnt_write <= current_usecnt;
+ pckstart_usecnt_prev <= current_usecnt;
+ ---------- source management --------------
+ mmu_resource_out <= current_res_info; --res_info;
+ mmu_rescnt_page_num <= std_logic_vector(unknown_res_page_cnt);
+ -------------------------------------------
- if(tp_need_pckstart_usecnt_set = '1') then
+ elsif(tp_need_pckstart_usecnt_set = '1' and pckstart_page_in_advance = '1') then
s_page_alloc <= S_PCKSTART_SET_USECNT;
pckstart_usecnt_req <= '1';
pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
pckstart_usecnt_write <= current_usecnt;
pckstart_usecnt_prev <= current_usecnt;
+ ---------- source management --------------
+ mmu_resource_out <= current_res_info; --res_info;
+ mmu_rescnt_page_num <= std_logic_vector(unknown_res_page_cnt);
+ -------------------------------------------
- elsif(pckstart_page_in_advance = '0') then
+ elsif(pckstart_page_in_advance = '0' and
+ rtu_rsp_ack = '0') then -- added to give precedence to usecnt set
pckstart_page_alloc_req <= '1';
s_page_alloc <= S_PCKSTART_PAGE_REQ;
pckstart_usecnt_write <= pckstart_usecnt_prev;
+ ---------- source management --------------
+ mmu_resource_out <= (others => '0'); -- always zero, even if we know (rare case)
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -----------------------------------------
- elsif(pckinter_page_in_advance = '0') then
+ elsif(pckinter_page_in_advance = '0' and
+ rtu_rsp_ack = '0') then -- added to give precedence to usecnt set
pckinter_page_alloc_req <= '1';
s_page_alloc <= S_PCKINTER_PAGE_REQ;
pckstart_usecnt_write <= std_logic_vector(to_unsigned(1, g_usecount_width));
+ ---------- source management --------------
+ if(res_info_valid = '1') then
+ mmu_resource_out <= current_res_info;--res_info;
+ else
+ mmu_resource_out <= (others => '0');
+ end if;
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -------------------------------------------
+
+ end if;
+
+ --===========================================================================================
+ when S_PCKSTART_SET_AND_REQ =>
+ --===========================================================================================
+
+ if(mmu_set_usecnt_done_i = '1') then
+ pckstart_usecnt_req <= '0';
+ end if;
+ if(mmu_page_alloc_done_i = '1') then
+ pckstart_page_alloc_req <= '0';
+ -- remember the page start addr
+ pckstart_pageaddr <= mmu_pageaddr_i;
+ pckstart_usecnt <= pckstart_usecnt_write;
+ end if;
+
+ -- it might happen that there is no more pages (but should not) and the usecnt_done
+ -- comes earlier then alloc_done. This is why we consider two cases for usecnt.
+ if((mmu_set_usecnt_done_i = '1' or pckstart_usecnt_req ='0') and mmu_page_alloc_done_i = '1') then
+
+ if(pckinter_page_in_advance = '0') then
+
+ pckinter_page_alloc_req <= '1';
+ s_page_alloc <= S_PCKINTER_PAGE_REQ;
+ pckstart_usecnt_write <= std_logic_vector(to_unsigned(1, g_usecount_width));
+ ---------- source management --------------
+
+-- -------------------------------- 01/11/2013: possible bug: --------------------------------
+-- see note below
+-- -------------------------------- ------------------------- --------------------------------
+-- if(res_info_valid = '1') then
+-- mmu_resource_out <= current_res_info; --res_info;
+-- else
+-- mmu_resource_out <= (others => '0');
+-- end if;
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -------------------------------------------
+
+ else
+
+ s_page_alloc <= S_IDLE;
+
+ end if;
+
end if;
--===========================================================================================
@@ -1120,12 +1341,33 @@ begin
pckstart_page_alloc_req <= '1';
s_page_alloc <= S_PCKSTART_PAGE_REQ;
pckstart_usecnt_write <= pckstart_usecnt_prev;
+ ---------- source management --------------
+ mmu_resource_out <= (others => '0'); -- always zero, even if we know (rare case)
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -------------------------------------------
elsif(pckinter_page_in_advance = '0') then
pckinter_page_alloc_req <= '1';
s_page_alloc <= S_PCKINTER_PAGE_REQ;
pckstart_usecnt_write <= std_logic_vector(to_unsigned(1, g_usecount_width));
+ ---------- source management --------------
+-- -------------------------------- 01/11/2013: possible bug: --------------------------------
+-- when we get RTU decision at the last page
+-- 1) we start S_PCKSTART_SET_USECNT
+-- 2) before the SET_USECNT state is exited, the frame finishes... the res_info_valid goes LOW
+-- 3) so when we allocate the next inter-frame page, we need to allocated it to the resource
+-- of the finished frame, but the res_info is LOW, so we set mm_resource_out to zero....
+-- and we are f-ed with the page count.
+-- this is why, if we enter S_PCKINTER_PAGE_REQ we remember the mm_resurce_out (not update)
+-- -------------------------------- ---------------------------------- -----------------------
+-- if(res_info_valid = '1') then
+-- mmu_resource_out <= current_res_info; --res_info;
+-- else
+-- mmu_resource_out <= (others => '0');
+-- end if;
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -------------------------------------------
else
@@ -1153,13 +1395,25 @@ begin
pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
pckstart_usecnt_write <= current_usecnt;
pckstart_usecnt_prev <= current_usecnt;
+ ---------- source management --------------
+ mmu_resource_out <= current_res_info; --res_info;
+ mmu_rescnt_page_num <= std_logic_vector(unknown_res_page_cnt);
+ -------------------------------------------
elsif(pckinter_page_in_advance = '0') then
pckinter_page_alloc_req <= '1';
s_page_alloc <= S_PCKINTER_PAGE_REQ;
pckstart_usecnt_write <= std_logic_vector(to_unsigned(1, g_usecount_width));
-
+ ---------- source management --------------
+ if(res_info_valid = '1') then
+ mmu_resource_out <= current_res_info; --res_info;
+ else
+ mmu_resource_out <= (others => '0');
+ end if;
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -------------------------------------------
+
else
s_page_alloc <= S_IDLE;
@@ -1176,20 +1430,43 @@ begin
pckinter_page_alloc_req <= '0';
pckinter_pageaddr <= mmu_pageaddr_i;
- if(tp_need_pckstart_usecnt_set = '1') then
+ if(tp_need_pckstart_usecnt_set = '1' and pckstart_page_in_advance = '0') then
+
+ s_page_alloc <= S_PCKSTART_SET_AND_REQ;
+ pckstart_usecnt_req <= '1';
+ pckstart_page_alloc_req <= '1';
+ pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
+ pckstart_usecnt_write <= current_usecnt;
+ pckstart_usecnt_prev <= current_usecnt;
+ ---------- source management --------------
+ mmu_resource_out <= current_res_info; --res_info;
+ mmu_rescnt_page_num <= std_logic_vector(unknown_res_page_cnt);
+ -------------------------------------------
+
+ elsif(tp_need_pckstart_usecnt_set = '1' and pckstart_page_in_advance = '1') then
s_page_alloc <= S_PCKSTART_SET_USECNT;
pckstart_usecnt_req <= '1';
pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
pckstart_usecnt_write <= current_usecnt;
pckstart_usecnt_prev <= current_usecnt;
-
- elsif(pckstart_page_in_advance = '0') then
+ ---------- source management --------------
+ mmu_resource_out <= current_res_info;--res_info;
+ mmu_rescnt_page_num <= std_logic_vector(unknown_res_page_cnt);
+ -------------------------------------------
+
+
+ elsif(pckstart_page_in_advance = '0' and
+ rtu_rsp_ack = '0') then -- added to give precedence to usecnt set
pckstart_page_alloc_req <= '1';
s_page_alloc <= S_PCKSTART_PAGE_REQ;
pckstart_usecnt_write <= pckstart_usecnt_prev;
-
+ ---------- source management --------------
+ mmu_resource_out <= (others => '0'); -- always zero, even if we know (rare case)
+ mmu_rescnt_page_num <= (others => '0'); -- we don't use it here
+ -------------------------------------------
+
else
s_page_alloc <= S_IDLE;
@@ -1218,21 +1495,26 @@ begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
--========================================
- current_mask <= (others => '0');
- current_drop <= '0';
- current_usecnt <= (others => '0');
- current_prio <= (others => '0');
- current_usecnt <= (others => '0');
- rtu_rsp_ack <= '0';
+ current_mask <= (others => '0');
+ current_res_info <= (others => '0');
+ current_hp <= '0';
+ current_drop <= '0';
+ current_usecnt <= (others => '0');
+ current_prio <= (others => '0');
+ current_usecnt <= (others => '0');
+ rtu_rsp_ack <= '0';
--========================================
else
-- remember input rtu decision
if(rtu_rsp_valid_i = '1' and rtu_rsp_ack = '0' and rp_accept_rtu = '1') then
-- make sure we're not forwarding packets to ourselves.
- current_mask <= rtu_dst_port_mask_i; -- and (not f_gen_mask(g_port_index, current_mask'length));
- current_prio <= rtu_prio_i;
- current_drop <= rtu_drop_i;
- current_usecnt <= rtu_dst_port_usecnt;
+ current_mask <= rtu_dst_port_mask_i; -- and (not f_gen_mask(g_port_index, current_mask'length));
+ current_res_info <= res_info;
+ current_hp <= rtu_hp_i;
+ current_prio <= rtu_prio_i;
+ current_drop <= rtu_drop_i or -- RTU decides to dump the frame
+ (res_info_almsot_full and not rtu_hp_i); -- the frame is not HP and we ar running our of memory
+ current_usecnt <= rtu_dst_port_usecnt;
rtu_rsp_ack <= '1';
else
@@ -1350,6 +1632,8 @@ begin
pta_transfer_pck <= '0';
pta_pageaddr <= (others => '0');
pta_mask <= (others => '0');
+ pta_resource <= (others => '0');
+ pta_hp <= '0';
pta_prio <= (others => '0');
--========================================
else
@@ -1376,7 +1660,7 @@ begin
elsif(rtu_rsp_ack = '1' and in_pck_sof = '1') then
-- don't need to set usecnt
- if(current_usecnt = current_pckstart_usecnt and c_force_usecnt = false) then
+ if(current_usecnt = current_pckstart_usecnt and c_force_usecnt=FALSE) then
-- if(current_usecnt = pckstart_usecnt_prev) then
-- first page is cleared in the Linked List
@@ -1385,6 +1669,8 @@ begin
s_transfer_pck <= S_TRANSFER;
pta_transfer_pck <= '1';
pta_mask <= current_mask;
+ pta_resource <= current_res_info;
+ pta_hp <= current_hp;
pta_prio <= current_prio;
-- we take stright from allocated in
-- advance because we are on SOF
@@ -1414,15 +1700,19 @@ begin
when S_WAIT_RTU_VALID =>
--===========================================================================================
+ -- error coming from rcv_pck FSM, ignore transfer
+ if (rp_in_pck_error = '1') then
+ s_transfer_pck <= S_DROP;
+
-- RTU decision received
- if(rtu_rsp_ack = '1') then
+ elsif(rtu_rsp_ack = '1') then
-- error coming from rcv_pck FSM or RTU decisio no drop, both cases, ignore transfer
if (rp_in_pck_error = '1' or tp_drop = '1') then
s_transfer_pck <= S_DROP;
-- don't need to set usecnt
- elsif(current_usecnt = current_pckstart_usecnt and c_force_usecnt = false) then
+ elsif(current_usecnt = current_pckstart_usecnt and c_force_usecnt=FALSE) then
-- elsif(current_usecnt = pckstart_usecnt_prev) then
-- first page is cleared in the Linked List
@@ -1431,6 +1721,8 @@ begin
pta_transfer_pck <= '1';
pta_pageaddr <= current_pckstart_pageaddr;
pta_mask <= current_mask;
+ pta_resource <= current_res_info;
+ pta_hp <= current_hp;
pta_prio <= current_prio;
-- wait for the first page to be cleard, sync-ing transfer_pck and rcv_pck and ll_wrie
else
@@ -1446,10 +1738,11 @@ begin
--===========================================================================================
when S_WAIT_SOF =>
--===========================================================================================
+
if(in_pck_sof = '1') then
-- don't need to set usecnt
- if(current_usecnt = current_pckstart_usecnt and c_force_usecnt = false) then
+ if(current_usecnt = current_pckstart_usecnt and c_force_usecnt=FALSE) then
-- if(current_usecnt = pckstart_usecnt_prev) then
-- first page is cleared in the Linked List
@@ -1457,6 +1750,8 @@ begin
s_transfer_pck <= S_TRANSFER;
pta_transfer_pck <= '1';
pta_mask <= current_mask;
+ pta_resource <= current_res_info;
+ pta_hp <= current_hp;
pta_prio <= current_prio;
-- take directly from allocation in advanc !!!
pta_pageaddr <= pckstart_pageaddr;
@@ -1481,12 +1776,19 @@ begin
-- error coming from rcv_pck FSM, ignore transfer
if (rp_in_pck_error = '1') then
s_transfer_pck <= S_DROP;
+
+ -- there is no resources available so the set_usecnt operation was not successfull
+ -- we need to drop the pck
+ elsif(mmu_set_usecnt_succeeded_i = '0') then
+ s_transfer_pck <= S_DROP;
else
-- first page is cleared in the Linked List
if(lw_pckstart_pg_clred = '1') then
s_transfer_pck <= S_TRANSFER;
pta_transfer_pck <= '1';
pta_mask <= current_mask;
+ pta_resource <= current_res_info;
+ pta_hp <= current_hp;
pta_prio <= current_prio;
pta_pageaddr <= current_pckstart_pageaddr;
else
@@ -1514,6 +1816,8 @@ begin
s_transfer_pck <= S_TRANSFER;
pta_transfer_pck <= '1';
pta_mask <= current_mask;
+ pta_resource <= current_res_info;
+ pta_hp <= current_hp;
pta_prio <= current_prio;
pta_pageaddr <= current_pckstart_pageaddr;
end if;
@@ -1540,11 +1844,11 @@ begin
if(lw_sync_first_stage = '1' and rp_sync = '1' and tp_sync = '1') then
s_transfer_pck <= S_READY;
- -- this is to prevent trashing of the drop process (it happened that force_free was
- -- re-done many times by rcv_pck FSM when transfer_pck FSM stayed in DROP state waiting
- -- for global sync
+ -- this is to prevent trashing of the drop process (it happened that force_free was
+ -- re-done many times by rcv_pck FSM when transfer_pck FSM stayed in DROP state waiting
+ -- for global sync
elsif(mmu_force_free_req = '1' and mmu_force_free_done_i = '1') then
- s_transfer_pck <= S_IDLE;
+ s_transfer_pck <= S_IDLE;
end if;
--===========================================================================================
@@ -1697,6 +2001,7 @@ begin
ll_entry.eof <= '1';
ll_entry.addr <= rp_ll_entry_addr;
ll_entry.size <= rp_ll_entry_size;
+ -- we use the space of next_page for dsel/size ..
ll_entry.next_page <= (others => '0');
ll_entry.next_page_valid <= '0';
ll_entry.first_page_clr <= '0';
@@ -1827,9 +2132,9 @@ lw_sync_second_stage <= '1' when (s_ll_write = S_READY_FOR_PGR_AND_DLAST and lw_
lw_sync_2nd_stage_chk <= '1' when (page_word_cnt = to_unsigned(g_page_size - 3, c_page_size_width)) else '0';
-- transfer_pck FSM sync (tp): needs to be true for rcv_pck to enter READY state
-tp_sync <= '1' when (s_transfer_pck = S_IDLE or --
- s_transfer_pck = S_DROP or --
- s_transfer_pck = S_TRANSFERED) else '0';
+tp_sync <= '1' when (s_transfer_pck = S_IDLE or --
+ -- s_transfer_pck = S_DROP or --
+ s_transfer_pck = S_TRANSFERED) else '0';
-- rcv_pck FSM is sync-ed
rp_sync <= '1' when (s_rcv_pck = S_IDLE) else '0';
@@ -1839,37 +2144,150 @@ tp_stuck <= '1' when (s_transfer_pck = S_TOO_LONG_TRANSFER) else '0';
-- transfer_pck FSM indicates that the frame should be dropped
tp_drop <= '1' when ((s_transfer_pck = S_DROP) or
- ((current_drop = '1' or current_mask = zeros) and rtu_rsp_ack = '1')) else '0';
+ ((current_drop = '1' or current_mask = zeros) and rtu_rsp_ack = '1')) else '0';
-- transfer_pck FSM indicates that transfer already started or is finished,
-tp_transfer_valid <= '1' when (s_transfer_pck = S_TRANSFERED or
- s_transfer_pck = S_TRANSFER or
- s_transfer_pck = S_TOO_LONG_TRANSFER) else '0';
-
+tp_transfer_valid <= '1' when (s_transfer_pck = S_TRANSFERED or
+ s_transfer_pck = S_TRANSFER or
+ s_transfer_pck = S_TOO_LONG_TRANSFER or
+ tp_transfer_ready = '1' or
+ tp_transfer_rtu_valid = '1' or
+ tp_transfer_wait_sof = '1' or
+ tp_transfer_set_usecnt = '1') else
+ '0';
+
+----------------------------------- this is nasty but should work.... ------------------------
+-- we need to detect cases where the decision about entering transfer state is being made...
+-- so I recreate the "if" statement which can cause the s_transfer_pck FSM to enter
+-- the S_TRANSFER state. THIS IS NASTY but tell me better way....
+tp_transfer_ready <= '1' when ( s_transfer_pck = S_READY and
+ (rtu_rsp_ack = '0' or tp_drop = '0') and
+ rtu_rsp_ack = '1' and
+ in_pck_sof = '1' and
+ current_usecnt = current_pckstart_usecnt and
+ c_force_usecnt = FALSE and
+ lw_pckstart_pg_clred = '1') else
+ '0';
+
+tp_transfer_rtu_valid <= '1' when ( s_transfer_pck = S_WAIT_RTU_VALID and
+ rp_in_pck_error = '0' and
+ rtu_rsp_ack = '1' and
+ tp_drop = '0' and
+ current_usecnt = current_pckstart_usecnt and
+ c_force_usecnt = FALSE and
+ lw_pckstart_pg_clred = '1') else
+ '0';
+tp_transfer_wait_sof <= '1' when ( s_transfer_pck = S_WAIT_SOF and
+ in_pck_sof = '1' and
+ current_usecnt = current_pckstart_usecnt and
+ c_force_usecnt = FALSE and
+ lw_pckstart_pg_clred = '1') else
+ '0';
+tp_transfer_set_usecnt<= '1' when ( s_transfer_pck = S_SET_USECNT and
+ mmu_set_usecnt_done_i = '1' and
+ tp_need_pckstart_usecnt_set = '1' and
+ rp_in_pck_error = '0' and
+ mmu_set_usecnt_succeeded_i = '1' and
+ lw_pckstart_pg_clred = '1') else
+ '0';
+
-- rcv_pck FSM indicates that there is or was error on the received pck
rp_in_pck_error <= '1' when (rp_in_pck_err = '1' or in_pck_err = '1') else '0';
+
+--================================================================================================
+--------------------------------------------------------------------------------------------------
+-------------------------------- resource management --------------------------------
+--------------------------------------------------------------------------------------------------
+--================================================================================================
+
+ -- generate signal indicating that the inforamtion about resource number for a given
+ -- pck is valid (based on RTU decision), it is used during allocation of a new
+ -- inter-pck page to indicate that the previous page was allocated to a give resource
+ res_info_valid <= '1' when ((s_transfer_pck = S_WAIT_SOF or
+ s_transfer_pck = S_SET_USECNT or
+ s_transfer_pck = S_WAIT_WITH_TRANSFER or
+ s_transfer_pck = S_TOO_LONG_TRANSFER or
+ s_transfer_pck = S_TRANSFER or
+ s_transfer_pck = S_TRANSFERED ) and
+ (s_rcv_pck = S_RCV_DATA or
+ s_rcv_pck = S_PAUSE ))else
+ '0';
+
+ ---------------------------------------------
+ -- mapping of RTU decision into resources
+-- res_info <= f_map_rtu_rsp_to_mmu_res(rtu_prio_i, rtu_hp_i , g_resource_num_width);
+
+ res_info <= c_special_res(g_resource_num_width-1 downto 0) when rtu_hp_i = '1' else
+ c_normal_res (g_resource_num_width-1 downto 0);
+
+ res_info_almsot_full <= mmu_res_almost_full_i(to_integer(unsigned(res_info)));
+ res_info_full <= mmu_res_full_i(to_integer(unsigned(res_info)));
+
+ cur_res_info_almsot_full <= mmu_res_almost_full_i(to_integer(unsigned(current_res_info)));
+ cur_res_info_full <= mmu_res_full_i(to_integer(unsigned(current_res_info)));
+
+ ---------------------------------------------
+
+ p_cnt_unused_pages: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ --================================================
+ unknown_res_page_cnt <= to_unsigned(0,unknown_res_page_cnt'length);
+ --================================================
+ else
+
+ -- reset the count of pages allocated to unknown resource when sync-ing FSMs
+ if(lw_sync_first_stage = '1' and rp_sync = '1' and tp_sync = '1') then
+ unknown_res_page_cnt <= to_unsigned(1,unknown_res_page_cnt'length);
+-- elsif(mpm_pg_req_i = '1' and mpm_dlast = '0' and s_transfer_pck = S_WAIT_RTU_VALID) then
+ -- counting how many pages has been used before usecnt_set
+-- elsif((pckstart_page_in_advance = '0' or pckinter_page_in_advance ='0') and rtu_rsp_ack = '0' and -- the very same condition to enter S_PCKINTER_PAGE_REQ
+ elsif(pckinter_page_in_advance ='0' and rtu_rsp_ack = '0' and -- the very same condition to enter S_PCKINTER_PAGE_REQ
+ s_transfer_pck = S_WAIT_RTU_VALID and pckstart_page_alloc_req ='0' and pckinter_page_alloc_req ='0') then
+ unknown_res_page_cnt <= unknown_res_page_cnt + 1;
+ end if;
+
+ end if; -- if(rst_n_i = '0') then
+ end if; --rising_edge(clk_i) then
+
+ end process;
+
+
+ mmu_resource_o <= mmu_resource_out;
+ mmu_rescnt_page_num_o <= mmu_rescnt_page_num;
+
+
+
+--================================================================================================
+--------------------------------------------------------------------------------------------------
+-------------------------------- inputs/outputs --------------------------------
+--------------------------------------------------------------------------------------------------
+--================================================================================================
+
--================================================================================================
-- Input signals
--================================================================================================
rtu_dst_port_usecnt <= std_logic_vector(to_unsigned(cnt(rtu_dst_port_mask_i), g_usecount_width));
-- generating output STALL: fifo_full or stall_after_err or stall_when_stuck;
+-- snk_stall_int <= ((not mpm_dreq_i) or snk_stall_force_h or in_pck_eof) and snk_stall_force_l;
snk_stall_int <= ((not mpm_dreq_i) or snk_stall_force_h) and snk_stall_force_l;
snk_o.stall <= snk_stall_int;
snk_o.err <= '0';
snk_o.ack <= snk_ack_int;
-snk_o.rty <= '0'; --snk_rty_int; --'0';
+snk_o.rty <= '0';--snk_rty_int; --'0';
--================================================================================================
-- Output signals
--================================================================================================
rtu_rsp_ack_o <= rtu_rsp_ack;
-
mmu_set_usecnt_o <= pckstart_usecnt_req;
-mmu_usecnt_o <= pckstart_usecnt_write;
+mmu_usecnt_set_o <= pckstart_usecnt_write;
+mmu_usecnt_alloc_o <= pckstart_usecnt_write;--std_logic_vector(to_unsigned(1,g_usecount_width));
mmu_page_alloc_req_o <= pckinter_page_alloc_req or pckstart_page_alloc_req;
mmu_force_free_o <= mmu_force_free_req;
@@ -1885,17 +2303,20 @@ mpm_data_o <= mpm_data;
pta_transfer_pck_o <= pta_transfer_pck;
pta_pageaddr_o <= pta_pageaddr;
pta_mask_o <= pta_mask; --current_mask;
+-- pta_resource_o <= pta_resource;
+pta_hp_o <= pta_hp;
pta_prio_o <= pta_prio; --current_prio;
-pta_pck_size_o <= (others => '0'); -- unused
+-- pta_pck_size_o <= (others => '0'); -- unused
-- pWB
---snk_dat_int <= snk_i.dat;
---snk_adr_int <= snk_i.adr;
+-- snk_dat_int <= snk_i.dat;
+-- snk_adr_int <= snk_i.adr;
snk_sel_int <= snk_i.sel;
snk_cyc_int <= snk_i.cyc;
snk_stb_int <= snk_i.stb;
snk_we_int <= snk_i.we;
+--dsel--
p_encode_byte_selects : process(snk_i)
begin
if(unsigned(not snk_i.sel) /= 0) then
@@ -1910,13 +2331,6 @@ begin
end if;
end process;
-
-
--- old
--- ll_data_eof(g_page_addr_width-1 downto g_page_addr_width-g_partial_select_width) <= ll_entry.dsel;
--- ll_data_eof(c_page_size_width-1 downto 0) <= ll_entry.size;
--- ll_data_eof(g_page_addr_width-g_partial_select_width-1 downto c_page_size_width) <= (others =>'0');
-
ll_data_eof(c_page_size_width-1 downto 0) <= ll_entry.size;
ll_data_eof(g_page_addr_width-g_partial_select_width-1 downto c_page_size_width) <= (others => '0');
@@ -1929,43 +2343,83 @@ ll_next_addr_o <= ll_entry.next_page;
ll_next_addr_valid_o <= ll_entry.next_page_valid;
ll_wr_req_o <= ll_wr_req;
-
-
-
---tap_out_o <= f_slv_resize( --
+alloc_FSM <= "000" when (s_page_alloc = S_IDLE) else
+ "001" when (s_page_alloc = S_PCKSTART_SET_USECNT) else
+ "010" when (s_page_alloc = S_PCKSTART_PAGE_REQ) else
+ "011" when (s_page_alloc = S_PCKINTER_PAGE_REQ) else
+ "100" when (s_page_alloc = S_PCKSTART_SET_AND_REQ) else
+ "101" ;
+trans_FSM <= x"0" when (s_transfer_pck = S_IDLE) else
+ x"1" when (s_transfer_pck = S_READY) else
+ x"2" when (s_transfer_pck = S_WAIT_RTU_VALID) else
+ x"3" when (s_transfer_pck = S_WAIT_SOF) else
+ x"4" when (s_transfer_pck = S_SET_USECNT) else
+ x"5" when (s_transfer_pck = S_WAIT_WITH_TRANSFER) else
+ x"6" when (s_transfer_pck = S_TOO_LONG_TRANSFER) else
+ x"7" when (s_transfer_pck = S_TRANSFER) else
+ x"8" when (s_transfer_pck = S_TRANSFERED) else
+ x"9" when (s_transfer_pck = S_DROP) else
+ x"A";
+
+rcv_p_FSM <= x"0" when (s_rcv_pck = S_IDLE) else
+ x"1" when (s_rcv_pck = S_READY) else
+ x"2" when (s_rcv_pck = S_PAUSE) else
+ x"3" when (s_rcv_pck = S_RCV_DATA) else
+ x"4" when (s_rcv_pck = S_DROP) else
+ x"5" when (s_rcv_pck = S_WAIT_FORCE_FREE) else
+ x"6" when (s_rcv_pck = S_INPUT_STUCK) else
+ x"7";
+
+linkl_FSM <= x"0" when (s_ll_write = S_IDLE) else
+ x"1" when (s_ll_write = S_READY_FOR_PGR_AND_DLAST) else
+ x"2" when (s_ll_write = S_READY_FOR_DLAST_ONLY) else
+ x"3" when (s_ll_write = S_WRITE) else
+ x"4" when (s_ll_write = S_EOF_ON_WR) else
+ x"5" when (s_ll_write = S_SOF_ON_WR) else
+ x"6";
+
+dbg_hwdu_o <= rtu_rsp_valid_i & alloc_FSM & trans_FSM & rcv_p_FSM & linkl_FSM;
+
+dbg_dropped_on_res_full <= pckstart_usecnt_req and mmu_set_usecnt_done_i and (not mmu_set_usecnt_succeeded_i);
+
+dbg_pckstart_pageaddr_o <= pckstart_pageaddr;
+dbg_pckinter_pageaddr_o <= pckinter_pageaddr;
+
+-- tap_out_o <= f_slv_resize( --
-- -- f_enum2nat(s_rcv_pck) & --
--- (mmu_nomem_i) &
--- (mmu_page_alloc_done_i) &
--- (pckinter_page_alloc_req or pckstart_page_alloc_req) &
--- snk_stall_int &
--- in_pck_sof_allowed &
--- in_pck_sof_on_stall &
--- snk_stall_d0 &
--- snk_cyc_int & -- 94
--- in_pck_sof_delayed & -- 93
--- f_enum2nat(s_transfer_pck) & -- 89
--- lw_sync_second_stage & -- 88
--- in_pck_err & -- 87
--- in_pck_eof & -- 86
--- in_pck_sof & -- 85
--- f_enum2nat(s_ll_write) & -- 81
--- f_enum2nat(s_page_alloc) & -- 77
--- pckinter_pageaddr & -- 67
--- pckinter_page_in_advance & -- 66
--- '1' & -- 65
-
--- ll_wr_req & -- 64
--- ll_wr_done_i & -- 63
--- ll_entry.addr & -- 54
--- ll_entry.valid & -- 53
--- ll_entry.eof & -- 52
--- ll_entry.oob_size & -- 49
--- ll_entry.next_page & -- 39
--- ll_entry.next_page_valid & -- 38
--- "0000000000" & --pta_pageaddr & -- 28
--- pta_transfer_pck & -- 27
--- "0000000000" & --mpm_pg_addr & -- 17
--- mpm_pg_req_i, -- 16
--- 50 + 62);
+-- (mmu_nomem_i) &
+-- (mmu_page_alloc_done_i) &
+-- (pckinter_page_alloc_req or pckstart_page_alloc_req) &
+-- snk_stall_int &
+-- in_pck_sof_allowed &
+-- in_pck_sof_on_stall &
+-- snk_stall_d0 &
+-- snk_cyc_int & -- 94
+-- in_pck_sof_delayed & -- 93
+-- f_enum2nat(s_transfer_pck) & -- 89
+-- lw_sync_second_stage & -- 88
+-- in_pck_err & -- 87
+-- in_pck_eof & -- 86
+-- in_pck_sof & -- 85
+-- f_enum2nat(s_ll_write) & -- 81
+-- f_enum2nat(s_page_alloc) & -- 77
+-- pckinter_pageaddr & -- 67
+-- pckinter_page_in_advance & -- 66
+-- '1' & -- 65
+--
+-- ll_wr_req & -- 64
+-- ll_wr_done_i & -- 63
+-- ll_entry.addr & -- 54
+-- ll_entry.valid & -- 53
+-- ll_entry.eof & -- 52
+-- ll_entry.dsel & -- 51
+-- ll_entry.oob_size & -- 49
+-- ll_entry.next_page & -- 39
+-- ll_entry.next_page_valid & -- 38
+-- "0000000000" & --pta_pageaddr & -- 28
+-- pta_transfer_pck & -- 27
+-- "0000000000" & --mpm_pg_addr & -- 17
+-- mpm_pg_req_i, -- 16
+-- 50 + 62);
end syn; -- arch
diff --git a/modules/wrsw_swcore/xswc_output_block.vhd b/modules/wrsw_swcore/xswc_output_block.vhd
index 6a52acfb9cb10bd1e411193ec5a8033650000ef3..2ea2414f53748fc8375f0f1d595bde414f5cc927 100644
--- a/modules/wrsw_swcore/xswc_output_block.vhd
+++ b/modules/wrsw_swcore/xswc_output_block.vhd
@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
--- Last update: 2012-07-10
+-- Last update: 2012-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -39,8 +39,11 @@
-- 2012-01-19 2.0 twlostow added buffer-FIFO
-- 2012-02-02 3.0 mlipinsk generic-azed
-- 2012-02-16 4.0 mlipinsk adapted to the new (async) MPM
+-- 2012-04-19 4.1 mlipinsk adapted to muti-resource MMU implementation
+-- 2012-04-20 4.2 mlipinsk added dropping of frames from queues which are full
-------------------------------------------------------------------------------
-- TODO:
+-- 1) mpm_dsel_i - needs to be made it generic
-- 2) mpm_abort_o - implement
-------------------------------------------------------------------------------
@@ -61,18 +64,20 @@ entity xswc_output_block is
generic (
g_max_pck_size_width : integer; --:= c_swc_max_pck_size_width
- g_output_block_per_prio_fifo_size : integer; --:= c_swc_output_fifo_size
- g_prio_width : integer; --:= c_swc_prio_width;, c_swc_output_prio_num_width
- g_prio_num : integer; --:= c_swc_output_prio_num
- -- new stuff
+ g_output_block_per_queue_fifo_size : integer; --:= c_swc_output_fifo_size
+ g_queue_num_width : integer; --
+ g_queue_num : integer; --
+ g_prio_num_width : integer; --
g_mpm_page_addr_width : integer; --:= c_swc_page_addr_width;
g_mpm_data_width : integer; --:= c_swc_page_addr_width;
g_mpm_partial_select_width : integer;
g_mpm_fetch_next_pg_in_advance : boolean := false;
+ g_mmu_resource_num_width : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_wb_sel_width : integer;
- g_wb_ob_ignore_ack : boolean := true
+ g_wb_ob_ignore_ack : boolean := true;
+ g_drop_outqueue_head_on_full : boolean := true
);
port (
clk_i : in std_logic;
@@ -83,9 +88,10 @@ entity xswc_output_block is
-------------------------------------------------------------------------------
pta_transfer_data_valid_i : in std_logic;
- pta_pageaddr_i : in std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
- pta_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
--- pta_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
+ pta_pageaddr_i : in std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ pta_prio_i : in std_logic_vector(g_prio_num_width - 1 downto 0);
+ pta_broadcast_i : in std_logic;
+ pta_resource_i : in std_logic_vector(g_mmu_resource_num_width - 1 downto 0);
pta_transfer_data_ack_o : out std_logic;
-------------------------------------------------------------------------------
@@ -95,6 +101,7 @@ entity xswc_output_block is
mpm_d_i : in std_logic_vector (g_mpm_data_width -1 downto 0);
mpm_dvalid_i : in std_logic;
mpm_dlast_i : in std_logic;
+ mpm_dsel_i : in std_logic_vector (g_mpm_partial_select_width -1 downto 0);
mpm_dreq_o : out std_logic;
mpm_abort_o : out std_logic;
mpm_pg_addr_o : out std_logic_vector (g_mpm_page_addr_width -1 downto 0);
@@ -121,36 +128,39 @@ end xswc_output_block;
architecture behavoural of xswc_output_block is
- constant c_per_prio_fifo_size_width : integer := integer(CEIL(LOG2(real(g_output_block_per_prio_fifo_size-1)))); -- c_swc_output_fifo_addr_width
+ constant c_per_queue_fifo_size_width : integer := integer(CEIL(LOG2(real(g_output_block_per_queue_fifo_size-1)))); -- c_swc_output_fifo_addr_width
signal pta_transfer_data_ack : std_logic;
- signal wr_addr : std_logic_vector(g_prio_width + c_per_prio_fifo_size_width -1 downto 0);
- signal rd_addr : std_logic_vector(g_prio_width + c_per_prio_fifo_size_width -1 downto 0);
+ signal wr_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal rd_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
-- drop_imp:
--- signal drop_addr : std_logic_vector(g_prio_width + c_per_prio_fifo_size_width -1 downto 0);
--- signal ram_rd_addr : std_logic_vector(g_prio_width + c_per_prio_fifo_size_width -1 downto 0);
--- signal drop_index : std_logic_vector(g_prio_width - 1 downto 0);
--- signal drop_array : std_logic_vector(g_prio_num - 1 downto 0);
-
- signal wr_prio : std_logic_vector(g_prio_width - 1 downto 0);
- signal rd_prio : std_logic_vector(g_prio_width - 1 downto 0);
- signal not_full_array : std_logic_vector(g_prio_num - 1 downto 0);
- signal full_array : std_logic_vector(g_prio_num - 1 downto 0);
- signal not_empty_array : std_logic_vector(g_prio_num - 1 downto 0);
- signal read_array : std_logic_vector(g_prio_num - 1 downto 0);
- signal read : std_logic_vector(g_prio_num - 1 downto 0);
- signal write_array : std_logic_vector(g_prio_num - 1 downto 0);
- signal write : std_logic_vector(g_prio_num - 1 downto 0);
+ signal dp_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal ram_rd_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal ram_rd_addr_d0 : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal drop_index : std_logic_vector(g_queue_num_width - 1 downto 0);
+ signal drop_array : std_logic_vector(g_queue_num - 1 downto 0);
+
+ signal write_index : std_logic_vector(g_queue_num_width - 1 downto 0);
+ signal read_index : std_logic_vector(g_queue_num_width - 1 downto 0);
+ signal not_full_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal full_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal not_empty_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal read_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal read_array_d0 : std_logic_vector(g_queue_num - 1 downto 0);
+ signal read : std_logic_vector(g_queue_num - 1 downto 0);
+ signal write_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal write : std_logic_vector(g_queue_num - 1 downto 0);
signal wr_en : std_logic;
signal rd_data_valid : std_logic;
signal drop_data_valid : std_logic;
- signal zeros : std_logic_vector(g_prio_num - 1 downto 0);
+ signal drop_data_valid_raw : std_logic;
+ signal zeros : std_logic_vector(g_queue_num - 1 downto 0);
- subtype t_head_and_head is std_logic_vector(c_per_prio_fifo_size_width - 1 downto 0);
+ subtype t_head_and_head is std_logic_vector(c_per_queue_fifo_size_width - 1 downto 0);
- type t_addr_array is array (g_prio_num - 1 downto 0) of t_head_and_head;
+ type t_addr_array is array (g_queue_num - 1 downto 0) of t_head_and_head;
signal wr_array : t_addr_array;
signal rd_array : t_addr_array;
@@ -203,9 +213,9 @@ architecture behavoural of xswc_output_block is
signal s_send_pck : t_send_pck;
signal s_prep_to_send : t_prep_to_send;
- signal wr_data : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
- signal rd_data : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
-
+ signal wr_data : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ signal rd_data : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+
signal ppfm_free : std_logic;
signal ppfm_free_pgaddr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
@@ -228,6 +238,7 @@ architecture behavoural of xswc_output_block is
signal src_cyc_int : std_logic;
signal src_stb_int : std_logic;
signal src_we_int : std_logic;
+ signal src_sel_int : std_logic_vector(1 downto 0);
signal out_dat_err : std_logic;
-- source in
signal src_ack_int : std_logic;
@@ -243,9 +254,9 @@ architecture behavoural of xswc_output_block is
signal mpm_pg_addr : std_logic_vector (g_mpm_page_addr_width -1 downto 0);
signal mpm_pg_valid : std_logic;
- signal mpm2wb_dat_int, mpm2wb_dat_int_pre : std_logic_vector (g_wb_data_width -1 downto 0);
- signal mpm2wb_sel_int : std_logic_vector (g_wb_sel_width -1 downto 0);
- signal mpm2wb_adr_int, mpm2wb_adr_int_pre : std_logic_vector (g_wb_addr_width -1 downto 0);
+ signal mpm2wb_dat_int : std_logic_vector (g_wb_data_width -1 downto 0);
+ signal mpm2wb_sel_int : std_logic_vector (g_wb_sel_width -1 downto 0);
+ signal mpm2wb_adr_int : std_logic_vector (g_wb_addr_width -1 downto 0);
signal src_out_int : t_wrf_source_out;
signal tmp_sel : std_logic_vector(g_wb_sel_width - 1 downto 0);
@@ -258,11 +269,11 @@ architecture behavoural of xswc_output_block is
signal not_set_next_pg_addr : std_logic;
signal wr_en_reg : std_logic;
- signal wr_addr_reg : std_logic_vector(g_prio_width + c_per_prio_fifo_size_width -1 downto 0);
+ signal wr_addr_reg : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
signal wr_data_reg : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
- signal rd_addr_reg : std_logic_vector(g_prio_width + c_per_prio_fifo_size_width -1 downto 0);
-
+ signal rd_addr_reg : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+
signal cycle_frozen : std_logic;
signal cycle_frozen_cnt : unsigned(5 downto 0);
@@ -274,7 +285,27 @@ architecture behavoural of xswc_output_block is
return tmp;
end f_slv_resize;
+ -- supresses rd_data_valid after new rd_addr is provided, otherwise we would read
+ -- old data but update new counters in the PRIO_QUEUE_CTRL. We always want to read data
+ -- from updated address, even if we need to wait one cycle. This is because, if the address
+ -- changes, it means that queue with higher priority was received (so we want to send it as soon
+ -- as possible. If we just read old data (from old address), the data with the higher priority
+ -- would need to wait for the frame to be sent out (this increases the switch latency)
+ signal rd_data_valid_supress : std_logic;
+ signal rd_data_valid_raw : std_logic;
+
+ -- indicates that there is full queue(s) and it is OK to drop frame (it is not OK if i.e.
+ -- some other frame is being dropped (memory free))
+ signal drop_ready : std_logic;
+ function f_onehot_decode(x : std_logic_vector) return std_logic_vector is
+ variable tmp : std_logic_vector(2**x'length-1 downto 0);
+ begin
+ tmp := (others => '0');
+ tmp(to_integer(unsigned(x))) := '1';
+
+ return tmp;
+ end function f_onehot_decode;
begin -- behavoural
@@ -309,135 +340,97 @@ begin -- behavoural
ram_zeros <= (others => '0');
ram_ones <= (others => '1');
- wr_prio <= not pta_prio_i;
+-- write_index <= pta_prio_i;
+
+ -- here we map the RTU+resource info into output queues
+ write_index <= f_map_rtu_rsp_and_mmu_res_to_out_queue(pta_prio_i,
+ pta_broadcast_i,
+ full_array,
+ g_queue_num);
+
+ wr_data <= pta_pageaddr_i;
+ wr_addr <= write_index & wr_array(to_integer(unsigned(write_index)));
+ wr_en <= write(to_integer(unsigned(write_index))) and not_full_array(to_integer(unsigned(write_index)));
- wr_data <= pta_pageaddr_i;
+ rd_addr <= read_index & rd_array(to_integer(unsigned(read_index)));
+ dp_addr <= drop_index & rd_array(to_integer(unsigned(drop_index)));
- wr_addr <= wr_prio & wr_array(0) when wr_prio = "000" else
- wr_prio & wr_array(1) when wr_prio = "001" else
- wr_prio & wr_array(2) when wr_prio = "010" else
- wr_prio & wr_array(3) when wr_prio = "011" else
- wr_prio & wr_array(4) when wr_prio = "100" else
- wr_prio & wr_array(5) when wr_prio = "101" else
- wr_prio & wr_array(6) when wr_prio = "110" else
- wr_prio & wr_array(7) when wr_prio = "111" else
- (others => 'X');
- rd_addr <= rd_prio & rd_array(0) when rd_prio = "000" else
- rd_prio & rd_array(1) when rd_prio = "001" else
- rd_prio & rd_array(2) when rd_prio = "010" else
- rd_prio & rd_array(3) when rd_prio = "011" else
- rd_prio & rd_array(4) when rd_prio = "100" else
- rd_prio & rd_array(5) when rd_prio = "101" else
- rd_prio & rd_array(6) when rd_prio = "110" else
- rd_prio & rd_array(7) when rd_prio = "111" else
- (others => 'X');
-
--- drop_imp:
--- drop_addr <= drop_index & rd_array(0) when drop_index = "000" else
--- drop_index & rd_array(1) when drop_index = "001" else
--- drop_index & rd_array(2) when drop_index = "010" else
--- drop_index & rd_array(3) when drop_index = "011" else
--- drop_index & rd_array(4) when drop_index = "100" else
--- drop_index & rd_array(5) when drop_index = "101" else
--- drop_index & rd_array(6) when drop_index = "110" else
--- drop_index & rd_array(7) when drop_index = "111" else
--- (others => 'X');
-
--- ram_rd_addr <= rd_addr when (mpm_pg_valid = '1') else drop_addr;
+
+ drop_ready <= '1' when ( g_drop_outqueue_head_on_full = true and -- dropping is enagbled
+ drop_array /= zeros and -- one of queues is full and we
+ -- decide to drop frame from there
+ ( ppfm_free = '0' or -- we are not corrently freeing
+ -- other frame, in such case no sense to drop unless
+ (ppfm_free='1' and ppfm_free_done_i='1')))-- the previous freeing is done
+ else '0';
+ ram_rd_addr <= dp_addr when (drop_ready = '1') else rd_addr;
- RD_ENCODE : swc_prio_encoder
+ write_array <= f_onehot_decode(write_index);
+
+ -- here we instantiate a module responsible for output queue scheduling (policy)
+ OUTPUT_SCHEDULER: swc_output_queue_scheduler
generic map (
- g_num_inputs => g_prio_num,
- g_output_bits => g_prio_width)
+ g_queue_num => g_queue_num,
+ g_queue_num_width => g_queue_num_width)
port map (
- in_i => not_empty_array,
- onehot_o => read_array,
- out_o => rd_prio);
-
- write_array <= "00000001" when wr_prio = "000" else
- "00000010" when wr_prio = "001" else
- "00000100" when wr_prio = "010" else
- "00001000" when wr_prio = "011" else
- "00010000" when wr_prio = "100" else
- "00100000" when wr_prio = "101" else
- "01000000" when wr_prio = "110" else
- "10000000" when wr_prio = "111" else
- "00000000";
-
- wr_en <= write(0) and not_full_array(0) when wr_prio = "000" else
- write(1) and not_full_array(1) when wr_prio = "001" else
- write(2) and not_full_array(2) when wr_prio = "010" else
- write(3) and not_full_array(3) when wr_prio = "011" else
- write(4) and not_full_array(4) when wr_prio = "100" else
- write(5) and not_full_array(5) when wr_prio = "101" else
- write(6) and not_full_array(6) when wr_prio = "110" else
- write(7) and not_full_array(7) when wr_prio = "111" else
- '0';
- -- I don't like this
- pta_transfer_data_ack_o <= not_full_array(0) when wr_prio = "000" else
- not_full_array(1) when wr_prio = "001" else
- not_full_array(2) when wr_prio = "010" else
- not_full_array(3) when wr_prio = "011" else
- not_full_array(4) when wr_prio = "100" else
- not_full_array(5) when wr_prio = "101" else
- not_full_array(6) when wr_prio = "110" else
- not_full_array(7) when wr_prio = "111" else
- '0';
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ not_empty_array_i => not_empty_array, -- vector with '1' bit corresponding to non_empty queue
+ read_queue_index_o => read_index, -- decision which queue read now (unsigned)
+ read_queue_onehot_o => read_array, -- the above decision in vector form
+ full_array_i => full_array, -- indicates which queue(s) is full (vector)
+ drop_queue_index_o => drop_index, -- indicate from from which queue the oldest entry shall be dropped (unsinged)
+ drop_queue_onehot_o => drop_array -- the above in vector form
+ );
+
+ pta_transfer_data_ack_o <= not_full_array(to_integer(unsigned(write_index)));
- prio_ctrl : for i in 0 to g_prio_num - 1 generate
-
+ --------------------------------------------------------------------------------------------------
+ -- generating control for each output queue
+ --------------------------------------------------------------------------------------------------
+ queue_ctrl : for i in 0 to g_queue_num - 1 generate
+ --------------------------------------------------------------------------------------------------
write(i) <= write_array(i) and pta_transfer_data_valid_i;
- read(i) <= read_array(i) and mpm_pg_valid;
--- drop_imp:
--- read(i) <= (read_array(i) and mpm_pg_valid) or (drop_array(i) and not mpm_pg_valid);
+ read(i) <= drop_array(i) when (drop_data_valid = '1') else
+ (read_array(i) and mpm_pg_valid);
- PRIO_QUEUE_CTRL : swc_ob_prio_queue
+ QUEUE_CTRL : swc_ob_prio_queue
generic map(
- g_per_prio_fifo_size_width => c_per_prio_fifo_size_width -- c_swc_output_fifo_addr_width
+ g_per_queue_fifo_size_width => c_per_queue_fifo_size_width -- c_swc_output_fifo_addr_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
- write_i => write(i),
- read_i => read(i),
- not_full_o => not_full_array(i),
- not_empty_o => not_empty_array(i),
- wr_en_o => open, --wr_en_array(i),
- wr_addr_o => wr_array(i),
- rd_addr_o => rd_array(i)
+ write_i => write(i), -- strobe to indicate we wrote one entry (increment head)
+ read_i => read(i), -- strobe to indicate we read one entry (increment tail)
+ not_full_o => not_full_array(i),-- indicates we can add entries (tail < head-1
+ not_empty_o => not_empty_array(i),-- tail != head
+ wr_en_o => open, --wr_en_array(i),
+ wr_addr_o => wr_array(i), -- head (which is used to create addresse to which we write in RAM)
+ rd_addr_o => rd_array(i) -- tail (which is used to create addresse from which we aread from RAM)
);
--- drop_imp:
--- full_array(i) <= not not_full_array(i);
- end generate prio_ctrl;
-
--- drop_imp:
--- DROP_ENCODE : swc_prio_encoder
--- generic map (
--- g_num_inputs => g_prio_num,
--- g_output_bits => g_prio_width)
--- port map (
--- in_i => full_array,
--- onehot_o => drop_array,
--- out_o => drop_index);
-
- PRIO_QUEUE : swc_rd_wr_ram
+ full_array(i) <= not not_full_array(i);
+ --------------------------------------------------------------------------------------------------
+ end generate queue_ctrl ;
+ --------------------------------------------------------------------------------------------------
+
+ PRIO_QUEUE: swc_rd_wr_ram
generic map (
g_data_width => g_mpm_page_addr_width, -- + g_max_pck_size_width,
- g_size => (g_prio_num * g_output_block_per_prio_fifo_size))
+ g_size => (g_queue_num * g_output_block_per_queue_fifo_size))
port map (
clk_i => clk_i,
we_i => wr_en_reg,
wa_i => wr_addr_reg,
wd_i => wr_data_reg,
- ra_i => rd_addr,
+ ra_i => ram_rd_addr, --rd_addr,
rd_o => rd_data);
-
-
+
--PRIO_QUEUE : generic_dpram
-- generic map (
-- g_data_width => g_mpm_page_addr_width, -- + g_max_pck_size_width,
- -- g_size => (g_prio_num * g_output_block_per_prio_fifo_size)
+ -- g_size => (g_queue_num * g_output_block_per_queue_fifo_size)
-- )
-- port map (
-- -- Port A -- writing
@@ -482,37 +475,47 @@ begin -- behavoural
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
- rd_data_valid <= '0';
- drop_data_valid <= '0';
+ rd_data_valid_raw <= '0';
+ drop_data_valid_raw <= '0';
+ read_array_d0 <= (others =>'0');
+ ram_rd_addr_d0 <= (others =>'0');
else
- if(not_empty_array = zeros) then
- rd_data_valid <= '0';
+ --if(not_empty_array = zeros) then
+ if(read_array = zeros) then
+ rd_data_valid_raw <= '0';
else
- rd_data_valid <= '1';
+ rd_data_valid_raw <= '1';
end if;
--- drop_imp :
--- if(full_array = zeros) then
--- drop_data_valid <= '0';
--- else
--- drop_data_valid <= '1';
--- end if;
+
+ read_array_d0 <= read_array;
+ ram_rd_addr_d0 <= ram_rd_addr;
+
+ if(drop_array /= zeros and g_drop_outqueue_head_on_full = true) then
+ drop_data_valid_raw <= '1';
+ else
+ drop_data_valid_raw <= '0';
+ end if;
end if;
end if;
end process;
+ -- we need one cycle to read new data from the new address
+ -- after read array (so the rd_addr) changes
+ -- rd_data_valid_supress <= '1' when (read_array_d0 /=read_array) else '0';
+ rd_data_valid_supress <= '1' when (ram_rd_addr_d0 /=ram_rd_addr) else '0';
--==================================================================================================
-- FSM to prepare next pck to be send
--==================================================================================================
- -- This state machine takes data, if available) from the output queue. The data is only the
+ -- This state machine takes data (if available) from the output queue. The data is only the
-- pckfirst_page address (this is all we need).
- -- It dane makes the page available for the MPM, once it's set to the MPM, the FSM waits until
+ -- It then makes the page available for the MPM, once it's set to the MPM, the FSM waits until
-- the MPM is ready to set pckstart_page for the next pck (in current implementation, this can
-- happen when reading the last word). The pckstart_page is made available to the MPM, and
-- so again and again...
-- The fun starts when the Endpoint requests retry of sending. we need to abort the current
-- MPM readout (currently not implemented in the MPM) and set again the same pckstart_page
- -- (this needs we need to put aside and remember the page which we've already read from the
+ -- (this requires that we need to put aside and remember the page which we've already read from the
-- output queue, if any). once, done, we need to come to the rememberd pckstart_page.
--
-- REMARK:
@@ -637,6 +640,11 @@ begin -- behavoural
end if;
end if;
end process p_prep_to_send_fsm;
+
+ -- this is to prevent reading in the cycle following read_array change.
+ -- In other words, we need to give memory one cycle to update output (read) data after changing input address
+ rd_data_valid <= rd_data_valid_raw and (not rd_data_valid_supress) and (not drop_data_valid_raw);
+ drop_data_valid <= drop_data_valid_raw and (not rd_data_valid_supress);
next_page_set_in_advance : if (g_mpm_fetch_next_pg_in_advance = true) generate
set_next_pg_addr <= '1' when (rd_data_valid = '1' and mpm_pg_req_i = '1' and mpm_pg_valid = '0') else '0';
@@ -680,14 +688,17 @@ begin -- behavoural
--========================================
else
-- default values
- start_free_pck <= '0';
- request_retry <= '0';
+ if(start_free_pck = '1' and ppfm_free = '1') then
+ start_free_pck <= '0';
+ end if;
+
case s_send_pck is
--===========================================================================================
when S_IDLE =>
--===========================================================================================
-
+ request_retry <= '0';
+
if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0' and src_i.stall = '0') then
src_out_int.cyc <= '1';
s_send_pck <= S_DATA;
@@ -776,8 +787,10 @@ begin -- behavoural
--===========================================================================================
when S_RETRY =>
--===========================================================================================
+ request_retry <= '1';
if(s_prep_to_send = S_RETRY_READY) then
src_out_int.cyc <= '1';
+ request_retry <= '0';
s_send_pck <= S_DATA;
pck_start_pgaddr <= mpm_pg_addr;
end if;
@@ -829,14 +842,14 @@ begin -- behavoural
ppfm_free <= '0';
ppfm_free_pgaddr <= (others => '0');
else
- if(start_free_pck = '1') then
+ if(start_free_pck = '1' and ppfm_free = '0') then
ppfm_free <= '1';
ppfm_free_pgaddr <= start_free_pck_addr;
-- drop_imp:
--- elsif(drop_data_valid = '1') then
--- ppfm_free <= '1';
--- ppfm_free_pgaddr <= rd_data(g_mpm_page_addr_width - 1 downto 0);
- elsif(ppfm_free_done_i = '1') then
+ elsif(drop_data_valid = '1' and ppfm_free = '0') then
+ ppfm_free <= '1';
+ ppfm_free_pgaddr <= rd_data(g_mpm_page_addr_width - 1 downto 0);
+ elsif(ppfm_free_done_i = '1' and ppfm_free = '1') then
ppfm_free <= '0';
ppfm_free_pgaddr <= (others => '0');
end if;
@@ -858,23 +871,9 @@ begin -- behavoural
(f_unmarshall_wrf_status(src_out_int.dat).error = '1') else -- the status indicates error
'0';
- mpm2wb_adr_int_pre <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width);
- mpm2wb_dat_int_pre <= mpm_d_i(g_wb_data_width -1 downto 0);
-
- p_decode_sel : process(mpm2wb_dat_int_pre, mpm2wb_adr_int_pre)
- begin
- if(mpm2wb_adr_int_pre = c_WRF_USER) then
- mpm2wb_dat_int(15 downto 8) <= mpm2wb_dat_int_pre(15 downto 8);
- mpm2wb_dat_int(7 downto 0) <= (others => 'X');
- mpm2wb_adr_int <= mpm2wb_dat_int_pre(7 downto 6);
- mpm2wb_sel_int <= mpm2wb_dat_int_pre(5 downto 4);
- else
- mpm2wb_dat_int <= mpm2wb_dat_int_pre;
- mpm2wb_adr_int <= mpm2wb_adr_int_pre;
- mpm2wb_sel_int <= (others => '1');
- end if;
- end process;
-
+ mpm2wb_adr_int <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width);
+ mpm2wb_sel_int <= '1' & mpm_dsel_i; -- TODO: something generic
+ mpm2wb_dat_int <= mpm_d_i(g_wb_data_width -1 downto 0);
-- source out
src_o <= src_out_int;
diff --git a/modules/wrsw_swcore/xswc_output_block_new.vhd b/modules/wrsw_swcore/xswc_output_block_new.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..807e70e5e735122b43bc882bb4e89dcc0d3e929d
--- /dev/null
+++ b/modules/wrsw_swcore/xswc_output_block_new.vhd
@@ -0,0 +1,1040 @@
+-------------------------------------------------------------------------------
+-- Title : Output Block
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : swc_output_block.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-Co-HT
+-- Created : 2010-11-03
+-- Last update: 2012-03-16
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-11-09 1.0 mlipinsk created
+-- 2012-01-19 2.0 mlipinsk wisbonized (pipelined WB)
+-- 2012-01-19 2.0 twlostow added buffer-FIFO
+-- 2012-02-02 3.0 mlipinsk generic-azed
+-- 2012-02-16 4.0 mlipinsk adapted to the new (async) MPM
+-- 2012-04-19 4.1 mlipinsk adapted to muti-resource MMU implementation
+-- 2012-04-20 4.2 mlipinsk added dropping of frames from queues which are full
+-------------------------------------------------------------------------------
+-- TODO:
+-- 1) mpm_dsel_i - needs to be made it generic
+-- 2) mpm_abort_o - implement
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.swc_swcore_pkg.all;
+use work.genram_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_private_pkg.all; -- Tom
+use work.ep_wbgen2_pkg.all; -- tom
+
+entity xswc_output_block_new is
+ generic (
+
+ g_max_pck_size_width : integer; --:= c_swc_max_pck_size_width
+ g_output_block_per_queue_fifo_size : integer; --:= c_swc_output_fifo_size
+ g_queue_num_width : integer; --
+ g_queue_num : integer; --
+ g_prio_num_width : integer; --
+ g_mpm_page_addr_width : integer; --:= c_swc_page_addr_width;
+ g_mpm_data_width : integer; --:= c_swc_page_addr_width;
+ g_mpm_partial_select_width : integer;
+ g_mpm_fetch_next_pg_in_advance : boolean := false;
+ g_mmu_resource_num_width : integer;
+ g_wb_data_width : integer;
+ g_wb_addr_width : integer;
+ g_wb_sel_width : integer;
+ g_hwdu_output_block_width : integer := 8;
+ g_wb_ob_ignore_ack : boolean := true;
+ g_drop_outqueue_head_on_full : boolean := true
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+-------------------------------------------------------------------------------
+-- I/F with Pck Transfer Arbiter
+-------------------------------------------------------------------------------
+
+ pta_transfer_data_valid_i : in std_logic;
+ pta_pageaddr_i : in std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ pta_prio_i : in std_logic_vector(g_prio_num_width - 1 downto 0);
+ pta_hp_i : in std_logic;
+-- pta_resource_i : in std_logic_vector(g_mmu_resource_num_width - 1 downto 0);
+ pta_transfer_data_ack_o : out std_logic;
+
+-------------------------------------------------------------------------------
+-- I/F with Multiport Memory's Read Pump (MMP)
+-------------------------------------------------------------------------------
+
+ mpm_d_i : in std_logic_vector (g_mpm_data_width -1 downto 0);
+ mpm_dvalid_i : in std_logic;
+ mpm_dlast_i : in std_logic;
+--dsel-- mpm_dsel_i : in std_logic_vector (g_mpm_partial_select_width -1 downto 0);
+ mpm_dreq_o : out std_logic;
+ mpm_abort_o : out std_logic;
+ mpm_pg_addr_o : out std_logic_vector (g_mpm_page_addr_width -1 downto 0);
+ mpm_pg_valid_o : out std_logic;
+ mpm_pg_req_i : in std_logic;
+-------------------------------------------------------------------------------
+-- I/F with Pck's Pages Free Module(PPFM)
+-------------------------------------------------------------------------------
+ -- correctly read pck
+ ppfm_free_o : out std_logic;
+ ppfm_free_done_i : in std_logic;
+ ppfm_free_pgaddr_o : out std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+
+-------------------------------------------------------------------------------
+--: output traffic shaper (PAUSE + time-aware-shaper)
+-------------------------------------------------------------------------------
+ ots_output_mask_i : in std_logic_vector(7 downto 0) := "00000000"; -- '1' bit indicate
+ -- that queue shall be PAUSED
+ ots_output_drop_at_rx_hp_i : in std_logic := '0'; -- if '1' the currently transmitted non-HP frame
+ -- is dropped (stop transmision) if HP is scheduled
+-------------------------------------------------------------------------------
+-- pWB : output (goes to the Endpoint)
+-------------------------------------------------------------------------------
+
+ src_i : in t_wrf_source_in;
+ src_o : out t_wrf_source_out;
+
+-------------------------------------------------------------------------------
+-- debugging
+-------------------------------------------------------------------------------
+ dbg_hwdu_o : out std_logic_vector(g_hwdu_output_block_width -1 downto 0);
+ tap_out_o : out std_logic_vector(15 downto 0)
+ );
+end xswc_output_block_new;
+
+architecture behavoural of xswc_output_block_new is
+
+ constant c_per_queue_fifo_size_width : integer := integer(CEIL(LOG2(real(g_output_block_per_queue_fifo_size-1)))); -- c_swc_output_fifo_addr_width
+
+ signal pta_transfer_data_ack : std_logic;
+
+ signal wr_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal rd_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+
+-- drop_imp:
+ signal dp_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal ram_rd_addr : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal drop_index : std_logic_vector(g_queue_num_width - 1 downto 0);
+ signal drop_array : std_logic_vector(g_queue_num - 1 downto 0);
+
+ signal write_index : std_logic_vector(g_queue_num_width - 1 downto 0);
+ signal read_index : std_logic_vector(g_queue_num_width - 1 downto 0);
+ signal not_full_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal full_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal not_empty_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal not_empty_and_shaped_array: std_logic_vector(g_queue_num - 1 downto 0);
+ signal read_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal read : std_logic_vector(g_queue_num - 1 downto 0);
+ signal rd_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal write_array : std_logic_vector(g_queue_num - 1 downto 0);
+ signal write : std_logic_vector(g_queue_num - 1 downto 0);
+ signal zeros : std_logic_vector(g_queue_num - 1 downto 0);
+
+ subtype t_head_and_head is std_logic_vector(c_per_queue_fifo_size_width - 1 downto 0);
+
+ type t_addr_array is array (g_queue_num - 1 downto 0) of t_head_and_head;
+
+ signal wr_addr_array : t_addr_array;
+ signal rd_addr_array : t_addr_array;
+
+ type t_prep_to_send is (S_IDLE,
+ S_NEWPCK_PAGE_READY,
+ S_NEWPCK_PAGE_SET_IN_ADVANCE,
+ S_NEWPCK_PAGE_USED,
+ S_RETRY_PREPARE,
+ S_RETRY_READY
+ );
+ type t_send_pck is (S_IDLE,
+ S_DATA,
+ S_FLUSH_STALL,
+ S_FINISH_CYCLE,
+ S_EOF,
+ S_RETRY,
+ S_WAIT_FREE_PCK
+ );
+
+-- function f_prepstate_2_slv (arg : t_prep_to_send) return std_logic_vector is
+-- begin
+-- case arg is
+-- when S_IDLE => return "000";
+-- when S_NEWPCK_PAGE_READY => return "001";
+-- when S_NEWPCK_PAGE_SET_IN_ADVANCE => return "010";
+-- when S_NEWPCK_PAGE_USED => return "011";
+-- when S_RETRY_PREPARE => return "100";
+-- when S_RETRY_READY => return "101";
+-- when others => return "111";
+-- end case;
+-- return "111";
+-- end f_prepstate_2_slv;
+--
+-- function f_sendstate_2_slv (arg : t_send_pck) return std_logic_vector is
+-- begin
+-- case arg is
+-- when S_IDLE => return "000";
+-- when S_DATA => return "001";
+-- when S_FLUSH_STALL => return "010";
+-- when S_FINISH_CYCLE => return "011";
+-- when S_EOF => return "100";
+-- when S_RETRY => return "101";
+-- when S_WAIT_FREE_PCK => return "110";
+-- end case;
+-- return "111";
+-- end f_sendstate_2_slv;
+
+
+ signal s_send_pck : t_send_pck;
+ signal s_prep_to_send : t_prep_to_send;
+
+ signal wr_data : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ signal rd_data : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+
+
+ signal ppfm_free : std_logic;
+ signal ppfm_free_pgaddr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+
+ signal pck_start_pgaddr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+
+ signal free_sent_pck_addr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ signal free_sent_pck_req : std_logic;
+
+ signal free_dped_pck_addr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+ signal free_dped_pck_req : std_logic;
+
+ signal ram_zeros : std_logic_vector(g_mpm_page_addr_width- 1 downto 0);
+ signal ram_ones : std_logic_vector((g_mpm_page_addr_width+7)/8 - 1 downto 0);
+
+ signal request_retry : std_logic;
+ signal out_dat_err : std_logic;
+
+ signal mpm_pg_addr_memorized : std_logic_vector(g_mpm_page_addr_width -1 downto 0);
+ signal mpm_pg_addr_memorized_valid : std_logic;
+
+ signal mpm_dreq : std_logic;
+ signal mpm_abort : std_logic;
+ signal mpm_pg_addr : std_logic_vector (g_mpm_page_addr_width -1 downto 0);
+ signal mpm_pg_valid : std_logic;
+
+ signal mpm2wb_dat_int, mpm2wb_dat_int_pre : std_logic_vector (g_wb_data_width -1 downto 0); --dsel--
+ signal mpm2wb_sel_int : std_logic_vector (g_wb_sel_width -1 downto 0);
+ signal mpm2wb_adr_int, mpm2wb_adr_int_pre : std_logic_vector (g_wb_addr_width -1 downto 0); --dsel--
+
+ signal src_out_int : t_wrf_source_out;
+ signal tmp_sel : std_logic_vector(g_wb_sel_width - 1 downto 0);
+ signal tmp_dat : std_logic_vector(g_wb_data_width - 1 downto 0);
+ signal tmp_adr : std_logic_vector(g_wb_addr_width - 1 downto 0);
+
+ signal ack_count : unsigned(3 downto 0);
+
+ signal set_next_rd_addr : std_logic;
+
+ signal wr_en : std_logic;
+ signal wr_en_reg : std_logic;
+ signal wr_addr_reg : std_logic_vector(g_queue_num_width + c_per_queue_fifo_size_width -1 downto 0);
+ signal wr_data_reg : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
+
+ signal rdy_for_rd_addr : std_logic;
+ signal set_next_mem_addr : std_logic;
+ signal set_next_dp_addr : std_logic;
+ signal rd_valid : std_logic;
+ signal allow_next_newpck_set : std_logic;
+ signal dp_valid : std_logic;
+
+ signal ppfm_free_sent : std_logic;
+ signal ppfm_free_dropped: std_logic;
+
+ signal mm_valid : std_logic;
+
+ signal cycle_frozen : std_logic;
+ signal cycle_frozen_cnt : unsigned(9 downto 0);
+
+ signal current_tx_prio : std_logic_vector(g_queue_num - 1 downto 0);
+
+ signal hp_prio_mask : std_logic_vector(g_queue_num - 1 downto 0);
+ signal zero_prio_mask : std_logic_vector(g_queue_num - 1 downto 0);
+
+ signal hp_in_queuing : std_logic;
+ signal non_hp_txing : std_logic;
+ signal abord_tx_at_hp : std_logic;
+ signal drop_at_hp : std_logic;
+
+ signal wrf_status_err : t_wrf_status_reg;
+
+ signal page_set_in_advance: std_logic;
+
+ signal ifg_count : unsigned(3 downto 0);
+ signal cyc_d0 : std_logic;
+ signal drop_at_retry : std_logic; --
+
+ signal send_FSM : std_logic_vector(3 downto 0);
+ signal prep_FSM : std_logic_vector(3 downto 0);
+
+ -- In theory stall is making sure the proper gap is there,but in case... two cycles
+ -- are needed between falling and rising edge of cyc output signal in order for EP
+ -- to prepare for new frame. actually, it is :
+ -- * one cycle for odd
+ -- * two cycles for even - we make artificially gap more by one, so things work the same
+ -- for odd and even (the same gap between)
+ constant tx_interframe_gap : unsigned(3 downto 0) := x"1";-- x"2"; !!!! changed it on 8-Nov-2013, brave thing to change something that almost works
+
+ -- if TRUE, any time a retry request is received from EP (most probably PCS), the request
+ -- will be ignored and frame dumped
+ -- NOTE: usually, such retry requets comes because there is a problem on input (e.g.: PAUSE
+ -- and a "hole" in memory is created, PCS stops receiving data (unacceptable) so it
+ -- gets lost -> tries again to send out the frame. usually in ends up in infinite
+ -- retry of sending the same frame
+ --
+ -- if FALSE, when a retry requsts comes from EP, it will be handled only if output queues are free
+ constant c_always_drop_at_retry : boolean := true;
+
+begin -- behavoural
+
+ wrf_status_err.is_hp <= '0';
+ wrf_status_err.has_smac <= '0';
+ wrf_status_err.has_crc <= '0';
+ wrf_status_err.error <= '1';
+ wrf_status_err.tag_me <= '0';
+ wrf_status_err.match_class <= (others =>'0');
+
+ zero_prio_mask <= (others => '0');
+
+ --tap_out_o <= f_slv_resize(mpm_d_i & mpm_dvalid_i & mpm_dlast_i & mpm_dreq & mpm_pg_valid & mpm_pg_addr & ppfm_free_pgaddr & ppfm_free
+ -- & f_prepstate_2_slv(s_prep_to_send) & f_sendstate_2_slv(s_send_pck) & cycle_frozen & std_logic_vector(ack_count) & pta_pageaddr_i & pta_transfer_data_ack & pta_transfer_data_valid_i, 80);
+
+ tap_out_o <= f_slv_resize(mpm_dvalid_i & mpm_dlast_i & mpm_dreq & cycle_frozen & pta_pageaddr_i & pta_transfer_data_ack & pta_transfer_data_valid_i, 16);
+
+ p_detect_frozen : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ cycle_frozen <= '0';
+ cycle_frozen_cnt <= (others => '0');
+ else
+
+ if(s_prep_to_send = S_IDLE or -- from here we will enter S_NEWPCK_PAGE_READY
+ (s_prep_to_send = S_IDLE and s_send_pck = S_EOF)) then -- condition of entering S_NEWPCK_PAGE_READY
+ cycle_frozen_cnt <= (others => '0');
+ cycle_frozen <= '0';
+ else
+ cycle_frozen_cnt <= cycle_frozen_cnt + 1;
+ if(cycle_frozen_cnt = to_unsigned(765,10)) then -- waits max frame size... not good
+ cycle_frozen <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ zeros <= (others => '0');
+ ram_zeros <= (others => '0');
+ ram_ones <= (others => '1');
+
+ -- here we map the RTU+resource info into output queues
+ write_index <= f_map_rtu_rsp_and_mmu_res_to_out_queue(pta_prio_i,
+ pta_hp_i,
+ full_array,
+ g_queue_num);
+
+ -- manage writing to output queues
+ write_array <= f_onehot_decode(write_index);
+ wr_data <= pta_pageaddr_i;
+ wr_addr <= write_index & wr_addr_array(to_integer(unsigned(write_index)));
+ wr_en <= write(to_integer(unsigned(write_index)));
+
+ -- create potential address from which the next frame can be read (if there is anything in
+ -- any queue)
+ rd_addr <= read_index & rd_addr_array(to_integer(unsigned(read_index)));
+
+ -- create potential address from which frame shall be dropped (if any queue full)
+ dp_addr <= drop_index & rd_addr_array(to_integer(unsigned(drop_index)));
+
+ -- here we decide when we start next MPM access (and whether it is "in advance"
+ -- TODO: change to do it faster
+ rdy_for_rd_addr <= '1' when (mpm_pg_req_i = '1' and
+ allow_next_newpck_set = '1' and
+-- s_send_pck = S_IDLE and
+ s_prep_to_send = S_IDLE
+ )else -- here we decide whether
+ '0'; -- we allocate in advance
+
+ -- indicates that next frame is ready and should be read from an output queue
+ set_next_rd_addr<= '1' when (read_array /= zeros and
+ mpm_pg_addr_memorized_valid = '0' and
+ rd_valid = '0' and -- to make it a strope (1 cyc)
+ dp_valid = '0' and -- cannot read when we are dropping,
+ rdy_for_rd_addr = '1' )else
+ '0';
+
+ set_next_mem_addr<='1' when (mpm_pg_addr_memorized_valid = '1' and
+ rdy_for_rd_addr = '1' )else
+ '0';
+ -- indicates that a frame should be dropped from the output queue
+ set_next_dp_addr<= '1' when (set_next_rd_addr = '0' and
+ drop_array /= zeros and
+ dp_valid = '0' and -- to make it a strope (1 cyc)
+ rd_valid = '0' and -- cannot drop when we are reading (would drop the same address)
+ free_dped_pck_req = '0' ) else
+ '0';
+
+ -- indicates the address from which next frame should be read/dropped (both operations translate
+ -- into reading from the ram (output queues)
+ ram_rd_addr <= rd_addr when (set_next_rd_addr = '1') else
+ dp_addr when (set_next_dp_addr = '1') else
+ rd_addr;
+ -- generate ack (if not empty, the queue can accommodate next entry)
+ pta_transfer_data_ack_o <= pta_transfer_data_ack;
+ pta_transfer_data_ack <= not_full_array(to_integer(unsigned(write_index)));
+
+ --allow_next_newpck_set <= '1' when (mpm_pg_req_i = '1') else '0';
+
+ -- we make sure that the read-from-ram (for reading=sending or dropping frame from the output
+ -- queue) is atomic (single cycle).
+ rd_or_dp_valid : process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+
+ rd_valid <= '0';
+ dp_valid <= '0';
+ free_dped_pck_req <= '0';
+ free_dped_pck_addr <= (others =>'0');
+ mm_valid <= '0';
+
+ else
+
+ rd_valid <= '0';
+ rd_array <= (others => '0');
+ dp_valid <= '0';
+
+ -- first part of atomic operation: remember from which queue the data is pop-ed
+ if(set_next_rd_addr = '1') then
+ rd_array <= read_array;
+ rd_valid <= '1';
+ elsif(set_next_dp_addr = '1') then
+ rd_array <= drop_array;
+ dp_valid <= '1';
+ end if;
+
+ if(dp_valid = '1') then
+ free_dped_pck_req <= '1';
+ free_dped_pck_addr <= rd_data(g_mpm_page_addr_width - 1 downto 0);
+ elsif(free_dped_pck_req = '1' and ppfm_free_dropped = '1') then
+ free_dped_pck_req <= '0';
+ end if;
+
+ mm_valid <= set_next_mem_addr;
+
+ end if;
+ end if;
+ end process;
+
+ -- here we instantiate a module responsible for output queue scheduling (policy)
+ OUTPUT_SCHEDULER: swc_output_queue_scheduler
+ generic map (
+ g_queue_num => g_queue_num,
+ g_queue_num_width => g_queue_num_width)
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ not_empty_array_i => not_empty_and_shaped_array, -- vector with '1' corresponding to non_empty queue
+ read_queue_index_o => read_index, -- decision which queue read now (unsigned)
+ read_queue_onehot_o => read_array, -- the above decision in vector form
+ full_array_i => full_array, -- indicates which queue(s) is full (vector)
+ drop_queue_index_o => drop_index, -- indicate from from which queue the oldest entry
+ -- shall be dropped (unsinged)
+ drop_queue_onehot_o => drop_array -- the above in vector form
+ );
+
+ not_empty_and_shaped_array <= (not ots_output_mask_i) and not_empty_array;
+ --------------------------------------------------------------------------------------------------
+ -- generating control for each output queue
+ --------------------------------------------------------------------------------------------------
+ queue_ctrl : for i in 0 to g_queue_num - 1 generate
+ --------------------------------------------------------------------------------------------------
+ write(i) <= write_array(i) and not_full_array(i) and pta_transfer_data_valid_i;
+ read(i) <= rd_array(i) and (rd_valid or dp_valid);
+
+ QUEUE_CTRL : swc_ob_prio_queue
+ generic map(
+ g_per_queue_fifo_size_width => c_per_queue_fifo_size_width -- c_swc_output_fifo_addr_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ write_i => write(i), -- strobe to indicate we wrote one entry (increment head)
+ read_i => read(i), -- strobe to indicate we read one entry (increment tail)
+ not_full_o => not_full_array(i), -- indicates we can add entries (tail < head-1
+ not_empty_o => not_empty_array(i),-- tail != head
+ wr_en_o => open, -- wr_en_array(i),
+ wr_addr_o => wr_addr_array(i), -- head (used to create addresse to which we write in RAM)
+ rd_addr_o => rd_addr_array(i) -- tail (used to create addresse from which we read RAM)
+ );
+ full_array(i) <= not not_full_array(i);
+ --------------------------------------------------------------------------------------------------
+ end generate queue_ctrl ;
+ --------------------------------------------------------------------------------------------------
+
+ PRIO_QUEUE: swc_rd_wr_ram
+ generic map (
+ g_data_width => g_mpm_page_addr_width, -- + g_max_pck_size_width,
+ g_size => (g_queue_num * g_output_block_per_queue_fifo_size))
+ port map (
+ clk_i => clk_i,
+ we_i => wr_en_reg,
+ wa_i => wr_addr_reg,
+ wd_i => wr_data_reg,
+ ra_i => ram_rd_addr,
+ rd_o => rd_data);
+
+ wr_ram : process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ wr_en_reg <= '0';
+ wr_addr_reg <= (others => '0');
+ wr_data_reg <= (others => '0');
+ else
+ wr_en_reg <= wr_en;
+ wr_addr_reg <= wr_addr;
+ wr_data_reg <= wr_data;
+ end if;
+ end if;
+ end process wr_ram;
+
+ -- learning which queues are HP
+ -- this is defined in RTU config, based on the config
+ -- RTU provides info which packet is HP. In theory, more queues can be
+ -- defined as HP
+ p_learn_hp_mask: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ hp_prio_mask <= (others => '0');
+ else
+ if(pta_transfer_data_valid_i = '1' and pta_hp_i = '1') then
+ hp_prio_mask <= hp_prio_mask or write_array ; -- add to mask
+ elsif(pta_transfer_data_valid_i = '1' and pta_hp_i = '0') then
+ if((hp_prio_mask and write_array) /= zeros) then -- we recognzie nonHP queu as HP
+ -- remove from hp_prio_mask
+ hp_prio_mask <= hp_prio_mask and (not write_array);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+-- for testing: set HP vector
+-- hp_prio_mask(g_queue_num-2 downto 0) <= (others =>'0');
+-- hp_prio_mask(g_queue_num-1) <= '1'; -- HP
+
+ -- remember info about currently processed prio of the frame. this is needed to
+ -- decide whether the currently tx-ed frame shall be dropped when HP frame is queued
+ p_track_tx_prio: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ current_tx_prio <= (others => '0');
+ else
+ if(rd_valid = '1') then
+ current_tx_prio <= read_array;
+ elsif((s_send_pck = S_EOF) and (s_prep_to_send = S_IDLE)) then
+ current_tx_prio <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process p_track_tx_prio;
+
+ -- deciding whether to drop currently tx-ed frame
+ hp_in_queuing <= '1' when ((read_array and hp_prio_mask) /= zero_prio_mask) else '0';
+ non_hp_txing <= '1' when ((current_tx_prio and (not hp_prio_mask)) /= zero_prio_mask) else '0';
+
+ abord_tx_at_hp <= non_hp_txing and -- we are currently sending frame which is not HP
+ hp_in_queuing and -- we have frame which is in HP output queue
+ drop_at_hp and -- the configuration enable dropping at HP
+ (not mpm_pg_req_i); -- we chack that we are not at the end of sending
+ -- the non-HP frame. There is no sense in dropping
+ -- frame which is almost completely sent
+
+ drop_at_hp <= ots_output_drop_at_rx_hp_i;
+ --==================================================================================================
+ -- FSM to prepare next pck to be send
+ --==================================================================================================
+ -- This state machine takes data (if available) from the output queue. The data is only the
+ -- pckfirst_page address (this is all we need).
+ -- It then makes the page available for the MPM, once it's set to the MPM, the FSM waits until
+ -- the MPM is ready to set pckstart_page for the next pck (in current implementation, this can
+ -- happen when reading the last word). The pckstart_page is made available to the MPM, and
+ -- so again and again...
+ -- The fun starts when the Endpoint requests retry of sending. we need to abort the current
+ -- MPM readout (currently not implemented in the MPM) and set again the same pckstart_page
+ -- (this requires that we need to put aside and remember the page which we've already read from the
+ -- output queue, if any). once, done, we need to come to the rememberd pckstart_page.
+ --
+ -- REMARK:
+ -- we don't want to get a new pckpage_start from the output queue as soon as it has been
+ -- set to MPM, this is becuase, during the transmission of the current pck, a higher
+ -- priority frame can be transfered.... so doing so at the end of pck sending should be better
+ --
+ p_prep_to_send_fsm : process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ --========================================
+ s_prep_to_send <= S_IDLE;
+ mpm_abort <= '0';
+ mpm_pg_addr <= (others => '0');
+ mpm_pg_valid <= '0';
+ mpm_pg_addr_memorized_valid <= '0';
+ mpm_pg_addr_memorized <= (others => '0');
+ allow_next_newpck_set <= '0';
+ --========================================
+ else
+
+ -- default values
+ mpm_abort <= '0';
+ mpm_pg_valid <= '0';
+
+ case s_prep_to_send is
+ --===========================================================================================
+ when S_IDLE =>
+ --===========================================================================================
+ if(rd_valid = '1') then
+ mpm_pg_valid <= '1';
+ mpm_pg_addr <= rd_data(g_mpm_page_addr_width - 1 downto 0);
+ if(s_send_pck = S_DATA or s_send_pck = S_FLUSH_STALL) then
+ s_prep_to_send <= S_NEWPCK_PAGE_SET_IN_ADVANCE;
+ else
+ s_prep_to_send <= S_NEWPCK_PAGE_READY;
+ end if;
+ elsif(mm_valid = '1') then
+ mpm_pg_addr_memorized_valid <= '0';
+ mpm_pg_addr <= mpm_pg_addr_memorized;
+ mpm_pg_valid <= '1';
+ if(s_send_pck = S_DATA or s_send_pck = S_FLUSH_STALL) then
+ s_prep_to_send <= S_NEWPCK_PAGE_SET_IN_ADVANCE;
+ else
+ s_prep_to_send <= S_NEWPCK_PAGE_READY;
+ end if;
+ elsif(request_retry = '1') then
+ -- if retry happens here we don't need to remember the address becasue a new one
+ -- has not been pop-ed from the queue
+ mpm_abort <= '1';
+ s_prep_to_send <= S_RETRY_PREPARE;
+ end if;
+ --===========================================================================================
+ when S_NEWPCK_PAGE_SET_IN_ADVANCE =>
+ --===========================================================================================
+ if(request_retry = '1') then
+ mpm_abort <= '1';
+ s_prep_to_send <= S_RETRY_PREPARE;
+ mpm_pg_addr_memorized_valid <= '1';
+ mpm_pg_addr_memorized <= mpm_pg_addr;
+ --elsif(mpm_dlast_i = '1') then
+ elsif(s_send_pck = S_EOF) then
+ s_prep_to_send <= S_NEWPCK_PAGE_READY;
+ end if;
+ --===========================================================================================
+ when S_NEWPCK_PAGE_READY =>
+ --===========================================================================================
+ if(request_retry = '1') then
+ -- we don't have to remember address here, this is because if we are in thsi state
+ -- it means that we are on the verge of sending new data. request_retry should not
+ -- happen here, but if it does (basically at the very beginning of new data
+ -- that we need to retry sending new address which is stored in mpm_pg_addr and
+ -- pck_start_pgaddr
+ mpm_abort <= '1';
+ s_prep_to_send <= S_RETRY_PREPARE;
+ elsif(s_send_pck = S_DATA) then
+ s_prep_to_send <= S_NEWPCK_PAGE_USED;
+ end if;
+ --===========================================================================================
+ when S_NEWPCK_PAGE_USED =>
+ --===========================================================================================
+ if(request_retry = '1') then
+ -- don't need to remember the address --
+ mpm_abort <= '1';
+ s_prep_to_send <= S_RETRY_PREPARE;
+ elsif(abord_tx_at_hp = '1' and mpm_pg_req_i = '0') then
+ mpm_abort <= '1';
+ s_prep_to_send <= S_IDLE;
+ elsif(mpm_pg_req_i = '1') then
+ s_prep_to_send <= S_IDLE;
+ end if;
+ --===========================================================================================
+ when S_RETRY_PREPARE =>
+ --===========================================================================================
+ if(mpm_pg_req_i = '1') then
+ mpm_pg_addr <= pck_start_pgaddr;
+ mpm_pg_valid <= '1';
+ s_prep_to_send <= S_RETRY_READY;
+ end if;
+ --===========================================================================================
+ when S_RETRY_READY =>
+ --===========================================================================================
+ if(request_retry = '1') then
+ mpm_abort <= '1';
+ s_prep_to_send <= S_RETRY_PREPARE;
+ elsif(s_send_pck = S_DATA) then
+ s_prep_to_send <= S_NEWPCK_PAGE_USED;
+ end if;
+ --===========================================================================================
+ when others =>
+ --===========================================================================================
+ s_prep_to_send <= S_IDLE;
+ end case;
+
+ if(s_prep_to_send = S_NEWPCK_PAGE_READY ) then
+ allow_next_newpck_set <= '0';
+ --elsif(mpm_dlast_i = '1' or s_send_pck = S_IDLE ) then
+ elsif(mpm_pg_req_i = '1') then
+ allow_next_newpck_set <= '1';
+ end if;
+
+ end if;
+ end if;
+ end process p_prep_to_send_fsm;
+
+ --==================================================================================================
+ -- FSM send pck with pWB I/F
+ --==================================================================================================
+ -- Forwarding pck read from MPM to pWB interface.
+ -- 1) we make a 1 cycle or greater gap between pWB cycles (S_EOF)
+ -- 2) when the transfer is finished, we request freeing (decrementing usecnt) the page
+ -- (this is done by separate module)
+ -- 3) if freeing from the previously sent pck has not finished when we reached the end
+ -- (or error/retry happend) of the current pck, we wait patiently. This should not happen
+ -- 4) We re-try sending the same pck if asked for (not implemented yet in the MPM)
+ --
+ p_send_pck_fsm : process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ --========================================
+ s_send_pck <= S_IDLE;
+ src_out_int.stb <= '0';
+ src_out_int.we <= '1';
+ src_out_int.adr <= c_WRF_DATA;
+ src_out_int.dat <= (others => '0');
+ src_out_int.cyc <= '0';
+ src_out_int.sel <= (others => '0');
+ free_sent_pck_req <= '0';
+ free_sent_pck_addr <= (others => '0');
+ tmp_adr <= (others => '0');
+ tmp_dat <= (others => '0');
+ tmp_sel <= (others => '0');
+ page_set_in_advance <= '0';
+ --========================================
+ else
+ -- default values
+ if(free_sent_pck_req = '1' and ppfm_free_sent = '1') then
+ free_sent_pck_req <= '0';
+ end if;
+ request_retry <= '0';
+
+ case s_send_pck is
+ --===========================================================================================
+ when S_IDLE =>
+ --===========================================================================================
+
+ if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0' and src_i.stall = '0' and ifg_count = x"0") then
+ src_out_int.cyc <= '1';
+ s_send_pck <= S_DATA;
+ pck_start_pgaddr <= mpm_pg_addr;
+ end if;
+
+ --===========================================================================================
+ when S_DATA =>
+ --===========================================================================================
+ if(src_i.stall = '0') then
+ if(mpm_dvalid_i = '1') then -- a avoid copying crap (i.e. XXX)
+ src_out_int.adr <= mpm2wb_adr_int;
+ src_out_int.dat <= mpm2wb_dat_int;
+ src_out_int.sel <= mpm2wb_sel_int;
+ end if;
+ src_out_int.stb <= mpm_dvalid_i;
+ end if;
+
+ if(src_i.err = '1' or drop_at_retry = '1') then
+ s_send_pck <= S_EOF; -- we free page in EOF
+ src_out_int.cyc <= '0';
+ src_out_int.stb <= '0';
+ elsif(out_dat_err = '1') then
+ s_send_pck <= S_FINISH_CYCLE; -- to make sure that the error word was sent
+ elsif(src_i.rty = '1') then
+ src_out_int.cyc <= '0';
+ src_out_int.stb <= '0';
+ request_retry <= '1';
+ s_send_pck <= S_RETRY;
+ elsif(abord_tx_at_hp = '1' and mpm_dlast_i = '0') then -- drop at HP in the outqueue
+ s_send_pck <= S_FINISH_CYCLE; -- we free page in EOF
+ src_out_int.adr <= c_WRF_STATUS;
+ src_out_int.dat <= f_marshall_wrf_status(wrf_status_err);
+ src_out_int.sel <= (others => '1');
+ src_out_int.stb <= '1';
+ elsif(src_i.stall = '1' and mpm_dvalid_i = '1') then
+ s_send_pck <= S_FLUSH_STALL;
+ elsif(mpm_dlast_i = '1')then
+ s_send_pck <= S_FINISH_CYCLE; -- we free page in EOF
+ end if;
+
+ if(mpm_dvalid_i = '1') then -- only when dvalid to avoid copying crap (i.e. XXX)
+ tmp_adr <= mpm2wb_adr_int;
+ tmp_dat <= mpm2wb_dat_int;
+ tmp_sel <= mpm2wb_sel_int;
+ end if;
+
+ if(s_prep_to_send = S_NEWPCK_PAGE_SET_IN_ADVANCE) then
+ page_set_in_advance <= '1';
+ else
+ page_set_in_advance <= '0';
+ end if;
+ --===========================================================================================
+ when S_FLUSH_STALL =>
+ --===========================================================================================
+ if(src_i.err = '1') then
+ s_send_pck <= S_EOF; -- we free page in EOF
+ src_out_int.cyc <= '0';
+ src_out_int.stb <= '0';
+ elsif(src_i.stall = '0') then
+ src_out_int.dat <= tmp_dat;
+ src_out_int.adr <= tmp_adr;
+ src_out_int.stb <= '1';
+ src_out_int.sel <= tmp_sel;
+ s_send_pck <= S_DATA;
+ end if;
+ --===========================================================================================
+ when S_FINISH_CYCLE =>
+ --===========================================================================================
+ if(src_i.stall = '0') then
+ src_out_int.stb <= '0';
+ end if;
+
+ -- making the CYCLE signal to go faster down... optimizing (hopefully not breaking)
+ if(g_wb_ob_ignore_ack and src_out_int.stb = '0') then
+ src_out_int.cyc <= '0';
+ s_send_pck <= S_EOF; -- we free page in EOF
+ elsif(ack_count = 1 and src_i.ack = '1' and not (src_out_int.stb = '1' and src_i.stall = '0')) then
+ src_out_int.cyc <= '0';
+ s_send_pck <= S_EOF; -- we free page in EOF
+ end if;
+
+ --===========================================================================================
+ when S_EOF =>
+ --===========================================================================================
+ if(ppfm_free = '0') then
+ free_sent_pck_req <= '1';
+ free_sent_pck_addr <= pck_start_pgaddr;
+
+ if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0' and src_i.stall = '0') then -- stall bug
+ src_out_int.cyc <= '1';
+ s_send_pck <= S_DATA;
+ pck_start_pgaddr <= mpm_pg_addr;
+ else
+ s_send_pck <= S_IDLE;
+ end if;
+ else
+ s_send_pck <= S_WAIT_FREE_PCK;
+ end if;
+ --===========================================================================================
+ when S_RETRY =>
+ --===========================================================================================
+ if(s_prep_to_send = S_RETRY_READY and src_i.stall = '0') then -- stall bug
+ src_out_int.cyc <= '1';
+ s_send_pck <= S_DATA;
+ pck_start_pgaddr <= mpm_pg_addr;
+ end if;
+ --===========================================================================================
+ when S_WAIT_FREE_PCK =>
+ --===========================================================================================
+ if(ppfm_free = '0') then
+ free_sent_pck_req <= '1';
+ free_sent_pck_addr <= pck_start_pgaddr;
+
+ if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0' and src_i.stall = '0') then -- stall bug
+ src_out_int.cyc <= '1';
+ s_send_pck <= S_DATA;
+ pck_start_pgaddr <= mpm_pg_addr;
+ else
+ s_send_pck <= S_IDLE;
+ end if;
+ end if;
+ --===========================================================================================
+ when others =>
+ --===========================================================================================
+ s_send_pck <= S_IDLE;
+ src_out_int.cyc <= '0';
+ src_out_int.stb <= '0';
+ end case;
+ end if;
+ end if;
+ end process p_send_pck_fsm;
+
+ p_count_ifg : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ cyc_d0 <= '0';
+ ifg_count <= (others =>'0');
+ else
+ cyc_d0 <= src_out_int.cyc;
+
+ if(src_out_int.cyc = '1' and cyc_d0 = '0') then
+ ifg_count <= tx_interframe_gap;
+ elsif(src_out_int.cyc = '1' and src_out_int.sel = "10") then
+ ifg_count <= tx_interframe_gap - x"1";
+ elsif(s_send_pck = S_IDLE and ifg_count > x"0") then
+ ifg_count <= ifg_count - x"1";
+ end if;
+ end if;
+ end if;
+ end process p_count_ifg;
+
+
+ p_count_acks : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0' or src_out_int.cyc = '0') then
+ ack_count <= (others => '0');
+ else
+ if(src_out_int.stb = '1' and src_i.stall = '0' and src_i.ack = '0') then
+ ack_count <= ack_count + 1;
+ elsif(src_i.ack = '1' and not(src_out_int.stb = '1' and src_i.stall = '0')) then
+ ack_count <= ack_count - 1;
+ end if;
+ end if;
+ end if;
+ end process p_count_acks;
+
+ -- here we perform the "free pages of the pck" process,
+ -- we do it while reading already the next pck
+ free : process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ ppfm_free <= '0';
+ ppfm_free_sent <= '0';
+ ppfm_free_dropped <= '0';
+ ppfm_free_pgaddr <= (others => '0');
+ else
+ if(free_sent_pck_req = '1' and ppfm_free = '0') then
+ ppfm_free <= '1';
+ ppfm_free_sent <= '1';
+ ppfm_free_pgaddr <= free_sent_pck_addr;
+ elsif(free_dped_pck_req = '1' and ppfm_free = '0') then
+ ppfm_free <= '1';
+ ppfm_free_dropped <= '1';
+ ppfm_free_pgaddr <= free_dped_pck_addr;
+ elsif(ppfm_free_done_i = '1' and ppfm_free = '1') then
+ ppfm_free <= '0';
+ ppfm_free_dropped <= '0';
+ ppfm_free_sent <= '0';
+ ppfm_free_pgaddr <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process free;
+
+ -------------- MPM ---------------------
+ mpm_dreq <= not src_i.stall when (s_send_pck = S_DATA or s_send_pck = S_FLUSH_STALL) else
+--commented out caused it triggered recursive pre-fetching
+-- '1' when ((s_send_pck = S_EOF or s_send_pck = S_IDLE) and
+-- page_set_in_advance = '1') else
+ '0';
+ mpm_dreq_o <= mpm_dreq;
+ mpm_abort_o <= mpm_abort;
+ mpm_pg_addr_o <= mpm_pg_addr;
+ mpm_pg_valid_o <= mpm_pg_valid;
+
+ -------------- pWB ----------------------
+ out_dat_err <= '1' when src_out_int.stb = '1' and -- we have valid data *and*
+ (src_out_int.adr = c_WRF_STATUS) and -- the address indicates status *and*
+ (f_unmarshall_wrf_status(src_out_int.dat).error = '1') else -- the status indicates error
+ '0';
+ drop_at_retry <= '1' when (c_always_drop_at_retry = true and
+ src_i.rty = '1') else
+ '1' when (c_always_drop_at_retry = false and
+ src_i.rty = '1' and
+ not_empty_and_shaped_array = zeros) else
+ '0' ;
+
+--dsel-- mpm2wb_adr_int <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width);
+--dsel-- mpm2wb_sel_int <= '1' & mpm_dsel_i; -- TODO: something generic
+--dsel-- mpm2wb_dat_int <= mpm_d_i(g_wb_data_width -1 downto 0);
+
+ mpm2wb_adr_int_pre <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width);
+ mpm2wb_dat_int_pre <= mpm_d_i(g_wb_data_width -1 downto 0);
+
+ p_decode_sel : process(mpm2wb_dat_int_pre, mpm2wb_adr_int_pre)
+ begin
+ if(mpm2wb_adr_int_pre = c_WRF_USER) then
+ mpm2wb_dat_int(15 downto 8) <= mpm2wb_dat_int_pre(15 downto 8);
+ mpm2wb_dat_int(7 downto 0) <= (others => 'X');
+ mpm2wb_adr_int <= mpm2wb_dat_int_pre(7 downto 6);
+ mpm2wb_sel_int <= mpm2wb_dat_int_pre(5 downto 4);
+ else
+ mpm2wb_dat_int <= mpm2wb_dat_int_pre;
+ mpm2wb_adr_int <= mpm2wb_adr_int_pre;
+ mpm2wb_sel_int <= (others => '1');
+ end if;
+ end process;
+
+ -- source out
+ src_o <= src_out_int;
+ -------------- PPFM ----------------------
+ ppfm_free_o <= ppfm_free;
+ ppfm_free_pgaddr_o <= ppfm_free_pgaddr;
+
+ send_FSM <= x"0" when (s_send_pck = S_IDLE) else
+ x"1" when (s_send_pck = S_DATA) else
+ x"2" when (s_send_pck = S_FLUSH_STALL) else
+ x"3" when (s_send_pck = S_FINISH_CYCLE) else
+ x"4" when (s_send_pck = S_EOF) else
+ x"5" when (s_send_pck = S_RETRY) else
+ x"6" when (s_send_pck = S_WAIT_FREE_PCK) else
+ x"7" ;
+
+ prep_FSM <= x"7" when (cycle_frozen = '1') else
+ x"5" when (s_prep_to_send = S_IDLE) else
+ x"1" when (s_prep_to_send = S_NEWPCK_PAGE_READY) else
+ x"2" when (s_prep_to_send = S_NEWPCK_PAGE_SET_IN_ADVANCE) else
+ x"3" when (s_prep_to_send = S_NEWPCK_PAGE_USED) else
+ x"4" when (s_prep_to_send = S_RETRY_PREPARE) else
+ x"0" when (s_prep_to_send = S_RETRY_READY) else
+ x"6" ;
+ dbg_hwdu_o(7 downto 0)<= send_FSM & prep_FSM;
+end behavoural;
diff --git a/modules/wrsw_tatsu/Manifest.py b/modules/wrsw_tatsu/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..3515d604e6b52dcd89ca81049ab889b885310afa
--- /dev/null
+++ b/modules/wrsw_tatsu/Manifest.py
@@ -0,0 +1,10 @@
+files = [
+ "xwrsw_tatsu.vhd",
+ "wrsw_tatsu_pkg.vhd",
+ "tatsu_wbgen2_pkg.vhd",
+ "tatsu_wishbone_controller.vhd",
+ "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd",
+ "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd",
+ "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd",
+ "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd",
+ ]
\ No newline at end of file
diff --git a/modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd b/modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..23d56565d8a8cc60b17767250c2bcd2ad5d48c54
--- /dev/null
+++ b/modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd
@@ -0,0 +1,113 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR switch Time Aware Traffic Shaper controller
+---------------------------------------------------------------------------------------
+-- File : tatsu_wbgen2_pkg.vhd
+-- Author : auto-generated by wbgen2 from tatsu_wishbone_controller.wb
+-- Created : Sun Mar 3 20:53:36 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tatsu_wishbone_controller.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package tatsu_wbgen2_pkg is
+
+
+ -- Input registers (user design -> WB slave)
+
+ type t_tatsu_in_registers is record
+ tcr_min_rpt_i : std_logic_vector(7 downto 0);
+ tcr_started_i : std_logic;
+ tcr_delayed_i : std_logic;
+ tcr_stg_ok_i : std_logic;
+ tcr_stg_err_i : std_logic;
+ tcr_stg_err_tai_i : std_logic;
+ tcr_stg_err_cyc_i : std_logic;
+ tcr_stg_err_rpt_i : std_logic;
+ tcr_stg_err_snc_i : std_logic;
+ end record;
+
+ constant c_tatsu_in_registers_init_value: t_tatsu_in_registers := (
+ tcr_min_rpt_i => (others => '0'),
+ tcr_started_i => '0',
+ tcr_delayed_i => '0',
+ tcr_stg_ok_i => '0',
+ tcr_stg_err_i => '0',
+ tcr_stg_err_tai_i => '0',
+ tcr_stg_err_cyc_i => '0',
+ tcr_stg_err_rpt_i => '0',
+ tcr_stg_err_snc_i => '0'
+ );
+
+ -- Output registers (WB slave -> user design)
+
+ type t_tatsu_out_registers is record
+ tcr_validate_o : std_logic;
+ tcr_disable_o : std_logic;
+ tcr_drop_ena_o : std_logic;
+ tsr0_qnt_o : std_logic_vector(15 downto 0);
+ tsr0_prio_o : std_logic_vector(7 downto 0);
+ tsr0_htai_o : std_logic_vector(7 downto 0);
+ tsr1_ltai_o : std_logic_vector(31 downto 0);
+ tsr2_cyc_o : std_logic_vector(27 downto 0);
+ tsr3_cyc_o : std_logic_vector(27 downto 0);
+ tsr4_ports_o : std_logic_vector(31 downto 0);
+ end record;
+
+ constant c_tatsu_out_registers_init_value: t_tatsu_out_registers := (
+ tcr_validate_o => '0',
+ tcr_disable_o => '0',
+ tcr_drop_ena_o => '0',
+ tsr0_qnt_o => (others => '0'),
+ tsr0_prio_o => (others => '0'),
+ tsr0_htai_o => (others => '0'),
+ tsr1_ltai_o => (others => '0'),
+ tsr2_cyc_o => (others => '0'),
+ tsr3_cyc_o => (others => '0'),
+ tsr4_ports_o => (others => '0')
+ );
+ function "or" (left, right: t_tatsu_in_registers) return t_tatsu_in_registers;
+ function f_x_to_zero (x:std_logic) return std_logic;
+ function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body tatsu_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if;
+end loop;
+return tmp;
+end function;
+function "or" (left, right: t_tatsu_in_registers) return t_tatsu_in_registers is
+variable tmp: t_tatsu_in_registers;
+begin
+tmp.tcr_min_rpt_i := f_x_to_zero(left.tcr_min_rpt_i) or f_x_to_zero(right.tcr_min_rpt_i);
+tmp.tcr_started_i := f_x_to_zero(left.tcr_started_i) or f_x_to_zero(right.tcr_started_i);
+tmp.tcr_delayed_i := f_x_to_zero(left.tcr_delayed_i) or f_x_to_zero(right.tcr_delayed_i);
+tmp.tcr_stg_ok_i := f_x_to_zero(left.tcr_stg_ok_i) or f_x_to_zero(right.tcr_stg_ok_i);
+tmp.tcr_stg_err_i := f_x_to_zero(left.tcr_stg_err_i) or f_x_to_zero(right.tcr_stg_err_i);
+tmp.tcr_stg_err_tai_i := f_x_to_zero(left.tcr_stg_err_tai_i) or f_x_to_zero(right.tcr_stg_err_tai_i);
+tmp.tcr_stg_err_cyc_i := f_x_to_zero(left.tcr_stg_err_cyc_i) or f_x_to_zero(right.tcr_stg_err_cyc_i);
+tmp.tcr_stg_err_rpt_i := f_x_to_zero(left.tcr_stg_err_rpt_i) or f_x_to_zero(right.tcr_stg_err_rpt_i);
+tmp.tcr_stg_err_snc_i := f_x_to_zero(left.tcr_stg_err_snc_i) or f_x_to_zero(right.tcr_stg_err_snc_i);
+return tmp;
+end function;
+end package body;
diff --git a/modules/wrsw_tatsu/tatsu_wishbone_controller.vhd b/modules/wrsw_tatsu/tatsu_wishbone_controller.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..39568aa320ae20bc025e82e2a2b44148f629ffa2
--- /dev/null
+++ b/modules/wrsw_tatsu/tatsu_wishbone_controller.vhd
@@ -0,0 +1,251 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for WR switch Time Aware Traffic Shaper controller
+---------------------------------------------------------------------------------------
+-- File : tatsu_wishbone_controller.vhd
+-- Author : auto-generated by wbgen2 from tatsu_wishbone_controller.wb
+-- Created : Sun Mar 3 20:53:36 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tatsu_wishbone_controller.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.tatsu_wbgen2_pkg.all;
+
+
+entity tatsu_wishbone_controller is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(2 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ regs_i : in t_tatsu_in_registers;
+ regs_o : out t_tatsu_out_registers
+ );
+end tatsu_wishbone_controller;
+
+architecture syn of tatsu_wishbone_controller is
+
+signal tatsu_tcr_validate_dly0 : std_logic ;
+signal tatsu_tcr_validate_int : std_logic ;
+signal tatsu_tcr_disable_dly0 : std_logic ;
+signal tatsu_tcr_disable_int : std_logic ;
+signal tatsu_tcr_drop_ena_int : std_logic ;
+signal tatsu_tsr0_qnt_int : std_logic_vector(15 downto 0);
+signal tatsu_tsr0_prio_int : std_logic_vector(7 downto 0);
+signal tatsu_tsr0_htai_int : std_logic_vector(7 downto 0);
+signal tatsu_tsr1_ltai_int : std_logic_vector(31 downto 0);
+signal tatsu_tsr2_cyc_int : std_logic_vector(27 downto 0);
+signal tatsu_tsr3_cyc_int : std_logic_vector(27 downto 0);
+signal tatsu_tsr4_ports_int : std_logic_vector(31 downto 0);
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(2 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_dat_i;
+ bwsel_reg <= wb_sel_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ tatsu_tcr_validate_int <= '0';
+ tatsu_tcr_disable_int <= '0';
+ tatsu_tcr_drop_ena_int <= '0';
+ tatsu_tsr0_qnt_int <= "0000000000000000";
+ tatsu_tsr0_prio_int <= "00000000";
+ tatsu_tsr0_htai_int <= "00000000";
+ tatsu_tsr1_ltai_int <= "00000000000000000000000000000000";
+ tatsu_tsr2_cyc_int <= "0000000000000000000000000000";
+ tatsu_tsr3_cyc_int <= "0000000000000000000000000000";
+ tatsu_tsr4_ports_int <= "00000000000000000000000000000000";
+ elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ tatsu_tcr_validate_int <= '0';
+ tatsu_tcr_disable_int <= '0';
+ ack_in_progress <= '0';
+ else
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(2 downto 0) is
+ when "000" =>
+ if (wb_we_i = '1') then
+ tatsu_tcr_validate_int <= wrdata_reg(0);
+ tatsu_tcr_disable_int <= wrdata_reg(1);
+ tatsu_tcr_drop_ena_int <= wrdata_reg(8);
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(8) <= tatsu_tcr_drop_ena_int;
+ rddata_reg(23 downto 16) <= regs_i.tcr_min_rpt_i;
+ rddata_reg(24) <= regs_i.tcr_started_i;
+ rddata_reg(25) <= regs_i.tcr_delayed_i;
+ rddata_reg(26) <= regs_i.tcr_stg_ok_i;
+ rddata_reg(27) <= regs_i.tcr_stg_err_i;
+ rddata_reg(28) <= regs_i.tcr_stg_err_tai_i;
+ rddata_reg(29) <= regs_i.tcr_stg_err_cyc_i;
+ rddata_reg(30) <= regs_i.tcr_stg_err_rpt_i;
+ rddata_reg(31) <= regs_i.tcr_stg_err_snc_i;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ ack_sreg(2) <= '1';
+ ack_in_progress <= '1';
+ when "001" =>
+ if (wb_we_i = '1') then
+ tatsu_tsr0_qnt_int <= wrdata_reg(15 downto 0);
+ tatsu_tsr0_prio_int <= wrdata_reg(23 downto 16);
+ tatsu_tsr0_htai_int <= wrdata_reg(31 downto 24);
+ end if;
+ rddata_reg(15 downto 0) <= tatsu_tsr0_qnt_int;
+ rddata_reg(23 downto 16) <= tatsu_tsr0_prio_int;
+ rddata_reg(31 downto 24) <= tatsu_tsr0_htai_int;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "010" =>
+ if (wb_we_i = '1') then
+ tatsu_tsr1_ltai_int <= wrdata_reg(31 downto 0);
+ end if;
+ rddata_reg(31 downto 0) <= tatsu_tsr1_ltai_int;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "011" =>
+ if (wb_we_i = '1') then
+ tatsu_tsr2_cyc_int <= wrdata_reg(27 downto 0);
+ end if;
+ rddata_reg(27 downto 0) <= tatsu_tsr2_cyc_int;
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "100" =>
+ if (wb_we_i = '1') then
+ tatsu_tsr3_cyc_int <= wrdata_reg(27 downto 0);
+ end if;
+ rddata_reg(27 downto 0) <= tatsu_tsr3_cyc_int;
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "101" =>
+ if (wb_we_i = '1') then
+ tatsu_tsr4_ports_int <= wrdata_reg(31 downto 0);
+ end if;
+ rddata_reg(31 downto 0) <= tatsu_tsr4_ports_int;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Drive the data output bus
+ wb_dat_o <= rddata_reg;
+-- Validate new settings, enable TATSU (if disabled)
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tatsu_tcr_validate_dly0 <= '0';
+ regs_o.tcr_validate_o <= '0';
+ elsif rising_edge(clk_sys_i) then
+ tatsu_tcr_validate_dly0 <= tatsu_tcr_validate_int;
+ regs_o.tcr_validate_o <= tatsu_tcr_validate_int and (not tatsu_tcr_validate_dly0);
+ end if;
+ end process;
+
+
+-- Stop TATSU
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tatsu_tcr_disable_dly0 <= '0';
+ regs_o.tcr_disable_o <= '0';
+ elsif rising_edge(clk_sys_i) then
+ tatsu_tcr_disable_dly0 <= tatsu_tcr_disable_int;
+ regs_o.tcr_disable_o <= tatsu_tcr_disable_int and (not tatsu_tcr_disable_dly0);
+ end if;
+ end process;
+
+
+-- Drop no-HP at HP
+ regs_o.tcr_drop_ena_o <= tatsu_tcr_drop_ena_int;
+-- Min repeat value
+-- TATSU started
+-- Delayed start
+-- Settings OK
+-- Settings Error
+-- Settings Error: TAI value
+-- Settings Error: cycle value
+-- Settings Error: repeat value
+-- Internal Time Sync Error
+-- Quanta
+ regs_o.tsr0_qnt_o <= tatsu_tsr0_qnt_int;
+-- Window Priorit Mask
+ regs_o.tsr0_prio_o <= tatsu_tsr0_prio_int;
+-- Start time (hi_TAI)
+ regs_o.tsr0_htai_o <= tatsu_tsr0_htai_int;
+-- Start time (lo_TAI)
+ regs_o.tsr1_ltai_o <= tatsu_tsr1_ltai_int;
+-- Start time (cycles)
+ regs_o.tsr2_cyc_o <= tatsu_tsr2_cyc_int;
+-- Repeat time (cycle)
+ regs_o.tsr3_cyc_o <= tatsu_tsr3_cyc_int;
+-- Ports mask
+ regs_o.tsr4_ports_o <= tatsu_tsr4_ports_int;
+ rwaddr_reg <= wb_adr_i;
+ wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/modules/wrsw_tatsu/tatsu_wishbone_controller.wb b/modules/wrsw_tatsu/tatsu_wishbone_controller.wb
new file mode 100644
index 0000000000000000000000000000000000000000..aafbc59a4c4674d10ff26683c6aa5ba49a828e4f
--- /dev/null
+++ b/modules/wrsw_tatsu/tatsu_wishbone_controller.wb
@@ -0,0 +1,261 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+-------------------------------------------------------------------------------
+-- Title : Wishbone Register Block (slave)
+-- Project : White Rabbit Time Aware Traffic Shaper
+-------------------------------------------------------------------------------
+-- File : tatsu_wishbone_controller.wb
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2013-03-01
+-- Last update: 2013-03-01
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
+peripheral {
+
+ name = "WR switch Time Aware Traffic Shaper controller";
+ description = "TATSU controller";
+ hdl_entity = "tatsu_wishbone_controller";
+ prefix = "tatsu";
+
+-- ECR
+ reg {
+ name = "TATSU Control Register/Status";
+ prefix = "TCR";
+ description = "General TATSU control and status register";
+
+ field {
+ name = "Validate new settings, enable TATSU (if disabled)";
+ description = "1: validates settings and enables TATSU\
+ 0: does nothing";
+ prefix = "VALIDATE";
+ type = MONOSTABLE;
+ };
+
+ field {
+ name = "Stop TATSU";
+ description = "1: disables Time Aware Traffic Shapper\
+ 0: does nothing ";
+ prefix = "DISABLE";
+ type = MONOSTABLE;
+ };
+ field {
+ name = "Drop no-HP at HP";
+ description = "Drop transmitted frame when frame with high priority awaits transmission\
+ 1: Enable feature\
+ 0: Disable feature";
+ prefix = "DROP_ENA";
+ type = BIT;
+ align = 8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+
+ };
+ field {
+ name = "Min repeat value";
+ description = "Repeats the minimum repeat value which can be set";
+ prefix = "MIN_RPT";
+ type = SLV;
+ size = 8;
+ align = 8;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+ field {
+ name = "TATSU started";
+ description = "1: TATSU is running with the validated settings (the set time has been already reached, now we repeat)\
+ 0: TATSU is not running (probably waiting for the time";
+ prefix = "STARTED";
+ type = BIT;
+ align = 8;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Delayed start";
+ description = "1: The time indicated with the settings as a start has been missed (time adjustment at this particular time) so the start is attempted repeat_cycles later (if attemt successful, the STARTED bit is set)\
+ 0: Normal start";
+ prefix = "DELAYED";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Settings OK";
+ description = "1: The settings has been validated succesfully\
+ 0: If checked after asserting VALIDATE it indicates that settings where not accepted -- the error bit is probably set and indicaes what went wrokng)";
+ prefix = "STG_OK";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Settings Error";
+ description = "1: Indicates Shapers error - check other error bits for details\
+ 0: Shaper seems to be working OK";
+ prefix = "STG_ERR";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Settings Error: TAI value";
+ description = "1: Error triggered by wrong TAI value (probably you tried to set time in the past)\
+ 0: TAI value OK";
+ prefix = "STG_ERR_TAI";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Settings Error: cycle value";
+ description = "1: Error triggered by wrong cycle value\
+ 0: Cycle value OK";
+ prefix = "STG_ERR_CYC";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Settings Error: repeat value";
+ description = "1: Error triggered by wrong repeat value (too small or too big)\
+ 0: Repeat value OK";
+ prefix = "STG_ERR_RPT";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "Internal Time Sync Error";
+ description = "1: Shaper stopped working due to the error with synchronizing internal counter with time soruce (tm_cycle_i), this is because the tm_time_valid_i was too long down)\
+ 0: Time Sync OK";
+ prefix = "STG_ERR_SNC";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+-- TSR
+ reg {
+ name = "TATSU Settings Register 0";
+ prefix = "TSR0";
+ description = "TATSU Settings register 0";
+
+ field {
+ name = "Quanta";
+ description = "Window length (time measured in quanta=512 bits time)";
+ prefix = "QNT";
+ type = SLV;
+ size = 16;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Window Priorit Mask";
+ description = "Mask which indicates which priorities (Classe of Service) are allowed within the window\
+ 1 at bit N - indicates that traffic on priority N is allowed during Window\
+ 0 at bit N - indicates that traffic on priority N is blocked during Window";
+ prefix = "prio";
+ type = SLV;
+ size = 8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Start time (hi_TAI)";
+ description = "Start time: high bits of the TAI value [39:32]";
+ prefix = "hTAI";
+ type = SLV;
+ size = 8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TATSU Settings Register 1";
+ prefix = "TSR1";
+ description = "TATSU Settings register 1";
+
+
+ field {
+ name = "Start time (lo_TAI)";
+ description = "Start timeLow bits of the TAI value [31:0]";
+ prefix = "lTAI";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TATSU Settings Register 2";
+ prefix = "TSR2";
+ description = "TATSU Settings register 2";
+
+
+ field {
+ name = "Start time (cycles)";
+ description = "Start time: cycles part of time";
+ prefix = "cyc";
+ type = SLV;
+ size = 28;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TATSU Settings Register 3";
+ prefix = "TSR3";
+ description = "TATSU Settings register 3";
+
+
+ field {
+ name = "Repeat time (cycle)";
+ description = "Repeat time: defines (in cycles units) how often the window shall be repeated";
+ prefix = "cyc";
+ type = SLV;
+ size = 28;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TATSU Settings Register 4";
+ prefix = "TSR4";
+ description = "TATSU Settings register 4";
+
+
+ field {
+ name = "Ports mask";
+ description = "Mask which indicated which ports shall be affected by the shaper";
+ prefix = "ports";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+};
\ No newline at end of file
diff --git a/modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd b/modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0c871b689c7b94366717aabb78c12bc72a4b568c
--- /dev/null
+++ b/modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd
@@ -0,0 +1,140 @@
+-------------------------------------------------------------------------------
+-- Title : Time-Aware Traffic Shaper Unit: package
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : wrsw_tatsu_pkg.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2013-03-01
+-- Last update: 2012-03-01
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Package with records, function, constants and components
+-- declarations for TATSU module
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-03-01 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+library work;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+use work.wrsw_shared_types_pkg.all;
+use work.tatsu_wbgen2_pkg.all;
+use work.wishbone_pkg.all; -- wishbone_{interface_mode,address_granularity}
+
+package wrsw_tatsu_pkg is
+
+
+ type t_tatsu_config is record
+ start_tm_tai : std_logic_vector(39 downto 0);
+ start_tm_cycles : std_logic_vector(27 downto 0);
+ repeat_cycles : std_logic_vector(27 downto 0);
+ window_quanta : std_logic_vector(15 downto 0);
+ ports_mask : std_logic_vector(31 downto 0);
+ prio_mask : std_logic_vector(7 downto 0);
+ end record;
+
+
+ component tatsu_wishbone_controller is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(2 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ regs_i : in t_tatsu_in_registers;
+ regs_o : out t_tatsu_out_registers
+ );
+ end component;
+
+ component xwrsw_tatsu is
+ generic(
+ g_num_ports : integer := 6;
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_simulation : boolean := false;
+ g_address_granularity: t_wishbone_address_granularity := BYTE
+ );
+ port (
+ clk_sys_i : in std_logic;
+ clk_ref_i : in std_logic;
+
+ rst_n_i : in std_logic;
+
+ shaper_request_o : out t_global_pause_request ;
+ shaper_drop_at_hp_ena_o : out std_logic;
+
+ tm_utc_i : in std_logic_vector(39 downto 0);
+ tm_cycles_i : in std_logic_vector(27 downto 0);
+ tm_time_valid_i : in std_logic;
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+ );
+ end component;
+
+ function f_pick (
+ cond : boolean;
+ if_true : integer;
+ if_false : integer
+ ) return integer;
+
+
+end wrsw_tatsu_pkg;
+
+package body wrsw_tatsu_pkg is
+
+ function f_pick (
+ cond : boolean;
+ if_true : integer;
+ if_false : integer
+ ) return integer is
+ begin
+ if(cond) then
+ return if_true;
+ else
+ return if_false;
+ end if;
+ end f_pick;
+
+end wrsw_tatsu_pkg;
+
diff --git a/modules/wrsw_tatsu/xwrsw_tatsu.vhd b/modules/wrsw_tatsu/xwrsw_tatsu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0cda2065d89d49864ebbbf93a2f5445e1ff1509
--- /dev/null
+++ b/modules/wrsw_tatsu/xwrsw_tatsu.vhd
@@ -0,0 +1,478 @@
+-------------------------------------------------------------------------------
+-- Title : (Extended) Time-Aware Traffic Shapper Unit
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : xwrsw_tatsu.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2013-02-28
+-- Last update: 2012-02-28
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: The module implements simple Time-Aware Traffic Shaper.
+-- It can be configured to start at a given time (TAI+cycles) a time window
+-- of time (quanta). In this window only defined output queues (prio_mask)
+-- are allowed (the others are blocked). This traffic shaping concerns only
+-- defined ports (port_mask).
+--
+-- How it works:
+-- 1) user writes configuration/settings through WB interface
+-- 2) user validates the config/settings by writing proper bit in control reg
+-- through WB I/F : (config:
+-- * start_tm_tai - at which second (in TAI) the Shape shall start
+-- * start_tm_cycles - at which cycle (within second) the Shaper shall strt
+-- * window_quanta - how long shell bhe the window in which only indicated
+-- priorities are allowed
+-- * repeat_cycles - every how many cycles the window shall be repeated
+-- * prio_mask - mask which indicates which priorities are allowed
+-- (at output queues of indicated ports, other priorities
+-- are blocked)
+-- * ports_mask - mask which indicates on which ports the shaper shall
+-- be applied to output queues
+-- 3) if the parameters are incorrect, e.g. stat time in past, too long/short
+-- repeat time), the Shaper is not started but error occurs (type of error
+-- written to status reg)
+-- 4) if parameters are correct, the Shaper waits for preper time (TAI+CYCLE)
+-- to arrive (compare seetings with: tm_tai_i, tm_cycle_i)
+-- 5) if the input time (tm_tai_i,tm_cycles_i) is invalid (tm_time_valid LOW) at
+-- the start time (start_tm_tai, start_tm_cycles), the shaper will start with
+-- the next repeat cycle: start_tm_cycles+repeat_cycles
+-- 6) once the shaper is started, it uses it's internal counter (tm_cycles_int)
+-- to trigger subsequent repeat_cycles. This counter is synched with tm_cycles_i
+-- at Shaper's start
+-- 7) the internal counter (tm_cycles_int) is synched with input time (tm_cycle_i)
+-- periodically: ~ each 1s
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-02-28 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+-- TODOs:
+-- [1]: tm_time_valid only at the end of the second + huge time jump - do we
+-- want to handle this?
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all;
+use work.gencores_pkg.all;
+use work.wrsw_tatsu_pkg.all;
+use work.tatsu_wbgen2_pkg.all;
+use work.wishbone_pkg.all; -- wishbone_{interface_mode,address_granularity}
+
+entity xwrsw_tatsu is
+ generic(
+ g_num_ports : integer := 6;
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_simulation : boolean := false;
+ g_address_granularity: t_wishbone_address_granularity := BYTE
+ );
+ port (
+ clk_sys_i : in std_logic;
+ clk_ref_i : in std_logic;
+
+ rst_n_i : in std_logic;
+
+ -- pause request to SWcore's output queues in output_block of chosen ports
+ -- (req, quanta, classes)
+ shaper_request_o : out t_global_pause_request ;
+
+ -- configuration which causes the the SWcore to drop currently transmitted
+ -- frame if a frame in high queue is waiting for transmission (affects all ports)
+ shaper_drop_at_hp_ena_o : out std_logic;
+
+ -- input WR time
+ tm_utc_i : in std_logic_vector(39 downto 0);
+ tm_cycles_i : in std_logic_vector(27 downto 0);
+ tm_time_valid_i : in std_logic;
+
+ -- WB config I/F
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+ );
+end xwrsw_tatsu;
+
+architecture rtl of xwrsw_tatsu is
+
+ constant c_PERIOD : integer := f_pick(g_simulation, 10000, 62500000);
+ constant c_cycle_width : integer := 28;
+ constant c_cycle_ext_width : integer := c_cycle_width + 2;
+ constant c_min_repeat_cyc : integer := 8;
+
+ type t_tatsu_state is (S_IDLE,
+ S_WAIT_START,
+ S_WAIT_REPEAT,
+ S_PAUSE_REQ,
+ S_LOAD_NEW_CONFIG,
+ S_ERROR);
+
+ type t_tatsu_status is record
+ settings_err : std_logic;
+ settings_err_tai : std_logic;
+ settings_err_cyc : std_logic;
+ settings_err_rpt : std_logic;
+ settings_ok : std_logic;
+ tatsu_started : std_logic;
+ tatsu_delayed : std_logic;
+ tm_sync_err : std_logic;
+ end record;
+
+ constant c_stat_clear : t_tatsu_status := ('0','0','0','0','0','0','0','0');
+ ------------------ sysclk domain ---------------------------------------
+ -- sygnals in sysclk domain only
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+ signal regs_towb : t_tatsu_in_registers;
+ signal regs_fromwb : t_tatsu_out_registers;
+
+ -- loaded in refclk, used in sysclk
+ signal prio_mask : std_logic_vector(7 downto 0);
+ signal window_quanta : std_logic_vector(15 downto 0);
+ signal port_mask : std_logic_vector(g_num_ports-1 downto 0);
+
+ -- loaded in syslk, used in refclk
+ signal config : t_tatsu_config;
+
+ -- signal in sysclk domain synched with refclk domain
+ signal shaper_req_sysclk : std_logic;
+
+ ------------------ refclk domain -----------------------------------
+ -- signals in refclk domained, synced with signals in sysclk
+ signal rst_synced_refclk : std_logic;
+ signal valid_synced_refclk : std_logic;
+ signal disable_synced_refclk: std_logic;
+
+ -- refclk domain only
+ signal start_tm_tai : std_logic_vector(39 downto 0);
+ signal start_tm_cycles : unsigned(c_cycle_ext_width-1 downto 0);
+ signal repeat_cycles : unsigned(c_cycle_ext_width-1 downto 0);
+ signal next_start_tm_cycles : unsigned(c_cycle_ext_width-1 downto 0);
+ signal tm_cycles_int : unsigned(c_cycle_ext_width-1 downto 0);
+ signal tatsu_state : t_tatsu_state;
+
+ -- signal exposed to sysclk domain
+ signal shaper_req_refclk : std_logic;
+ signal status : t_tatsu_status;
+
+begin --rtl
+
+ next_start_tm_cycles <= start_tm_cycles + repeat_cycles;
+
+ shaper_p: process(clk_ref_i,rst_synced_refclk)
+ begin
+ if rising_edge(clk_ref_i) then
+ if (rst_synced_refclk = '0' or disable_synced_refclk ='1') then
+
+ status <= c_stat_clear;
+
+ start_tm_tai <= (others => '0');
+ start_tm_cycles <= (others => '0');
+ tm_cycles_int <= (others => '0');
+ repeat_cycles <= (others => '0');
+
+ shaper_req_refclk <= '0';
+
+ prio_mask <= (others => '0');
+ port_mask <= (others => '0');
+ window_quanta <= (others => '0');
+
+ tatsu_state <= S_IDLE;
+
+ else
+
+ case tatsu_state is
+ --==================================================================================
+ when S_IDLE => -- only after disable or reset
+ --==================================================================================
+
+ if(valid_synced_refclk = '1') then
+ tatsu_state <= S_LOAD_NEW_CONFIG;
+ status <= c_stat_clear;
+ end if;
+
+ --==================================================================================
+ when S_LOAD_NEW_CONFIG => -- validate and remember configuration
+ --==================================================================================
+
+ if(shaper_req_refclk = '1' and shaper_req_sysclk = '1') then
+ shaper_req_refclk <= '0';
+
+ elsif(shaper_req_refclk = '0' and shaper_req_sysclk = '0') then -- make sure that there is no current requests to SWcore
+ if (config.start_tm_tai < tm_utc_i) then
+ tatsu_state <= S_ERROR;
+ status.settings_err_tai <='1';
+ elsif ((config.start_tm_tai = tm_utc_i) and (config.start_tm_cycles < tm_cycles_i)) then
+ tatsu_state <= S_ERROR;
+ status.settings_err_cyc <='1';
+ elsif(config.start_tm_cycles > std_logic_vector(to_unsigned(c_PERIOD, c_cycle_width )) ) then
+ tatsu_state <= S_ERROR;
+ status.settings_err_cyc <='1';
+ elsif(config.repeat_cycles = std_logic_vector(to_unsigned(0,c_cycle_width))) then
+ tatsu_state <= S_ERROR;
+ status.settings_err_rpt <='1';
+ elsif(config.repeat_cycles > std_logic_vector(to_unsigned(c_PERIOD, c_cycle_width )) ) then
+ tatsu_state <= S_ERROR;
+ status.settings_err_rpt <='1';
+ elsif(config.repeat_cycles < std_logic_vector(to_unsigned(c_min_repeat_cyc, c_cycle_width )) ) then
+ tatsu_state <= S_ERROR;
+ status.settings_err_rpt <='1';
+ else
+ start_tm_cycles(c_cycle_width -1 downto 0) <= unsigned(config.start_tm_cycles);
+ repeat_cycles (c_cycle_width -1 downto 0) <= unsigned(config.repeat_cycles);
+ start_tm_cycles(c_cycle_ext_width-1 downto c_cycle_width) <= (others =>'0');
+ repeat_cycles (c_cycle_ext_width-1 downto c_cycle_width) <= (others =>'0');
+
+ tatsu_state <= S_WAIT_START;
+ start_tm_tai <= config.start_tm_tai ;
+
+ port_mask <= config.ports_mask(g_num_ports-1 downto 0);
+ prio_mask <= config.prio_mask;
+ window_quanta <= config.window_quanta;
+
+ status.settings_ok <= '1';
+
+ end if;
+ end if;
+ --==================================================================================
+ when S_WAIT_START => -- wait until the set time (TAI+CYCLE) arrives
+ --==================================================================================
+
+ if(valid_synced_refclk = '1') then
+ tatsu_state <= S_LOAD_NEW_CONFIG;
+ status <= c_stat_clear;
+ elsif(tm_time_valid_i = '1') then
+
+ -- this is standard case: we start when the time matches
+ if((tm_utc_i = start_tm_tai) and
+ (tm_cycles_i = std_logic_vector(start_tm_cycles(c_cycle_width-1 downto 0)))) then
+ shaper_req_refclk <= '1';
+ tatsu_state <= S_PAUSE_REQ;
+ status.tatsu_started <= '1';
+ tm_cycles_int(c_cycle_width-1 downto 0) <= unsigned(tm_cycles_i) + 1;
+ tm_cycles_int(c_cycle_ext_width-1 downto c_cycle_width) <= (others =>'0');
+
+ -- if the tm_time_valid_i was low when we should have started, we have probably
+ -- missed the right moment to start. In such case, we try to start with the next
+ -- cycle and indicate in the status what happened (this is kind-of-recursive if the
+ -- time adjustment was really huge step back, if it was step forward, it's OK)
+ elsif((tm_utc_i = start_tm_tai) and
+ (tm_cycles_i > std_logic_vector(start_tm_cycles(c_cycle_width-1 downto 0)))) then
+
+ status.tatsu_delayed <= '1';
+
+ if(next_start_tm_cycles >= to_unsigned(c_PERIOD,c_cycle_ext_width)) then
+ start_tm_tai <= std_logic_vector(unsigned(start_tm_tai) + 1);
+ start_tm_cycles <= next_start_tm_cycles - to_unsigned(c_PERIOD,c_cycle_ext_width);
+ else
+ start_tm_cycles <= next_start_tm_cycles;
+ end if;
+
+ -- the time adjustment was substantial and we've missed the proper second
+ elsif(tm_utc_i > start_tm_tai) then
+ tatsu_state <= S_ERROR;
+ end if;
+ end if;
+
+ --==================================================================================
+ when S_PAUSE_REQ => -- send request to SWcore to activate pause
+ --==================================================================================
+
+ tm_cycles_int <= tm_cycles_int + 1;
+
+ if(valid_synced_refclk = '1') then
+ tatsu_state <= S_LOAD_NEW_CONFIG;
+ status <= c_stat_clear;
+ elsif(shaper_req_sysclk = '1') then -- request SWcore done
+
+ shaper_req_refclk <= '0';
+ tatsu_state <= S_WAIT_REPEAT;
+ --TODO [1]: if we have tm_time_valid high only at the end of 1sec and we have
+ -- a huge time jump back... we are a bit fucked
+ --
+ if((tm_time_valid_i = '1') and (start_tm_cycles > to_unsigned(2*c_PERIOD,c_cycle_ext_width))) then
+ tatsu_state <= S_ERROR;
+ status.tm_sync_err <= '1';
+ elsif((tm_time_valid_i = '1') and (start_tm_cycles > to_unsigned(c_PERIOD,c_cycle_ext_width))) then
+ start_tm_cycles <= next_start_tm_cycles - to_unsigned(c_PERIOD,c_cycle_ext_width);
+ if(tm_cycles_i = std_logic_vector(to_unsigned(c_PERIOD-1,tm_cycles_i'length))) then
+ tm_cycles_int <= (others => '0');
+ else
+ tm_cycles_int(c_cycle_width-1 downto 0) <= unsigned(tm_cycles_i) + 1;
+ tm_cycles_int(c_cycle_ext_width-1 downto c_cycle_width) <= (others =>'0');
+ end if;
+ else
+ start_tm_cycles <= next_start_tm_cycles;
+ end if;
+ end if;
+
+ --==================================================================================
+ when S_WAIT_REPEAT => -- wait for window_repeat time (cycles)
+ --==================================================================================
+
+ tm_cycles_int <= tm_cycles_int + 1;
+
+ if(valid_synced_refclk = '1') then
+ tatsu_state <= S_LOAD_NEW_CONFIG;
+ status <= c_stat_clear;
+ elsif(tm_cycles_int = start_tm_cycles) then
+ shaper_req_refclk <= '1';
+ tatsu_state <= S_PAUSE_REQ;
+ end if;
+
+ --==================================================================================
+ when S_ERROR => -- something is wrong, the status bits should indicate what it is
+ --==================================================================================
+
+ if(valid_synced_refclk = '1') then
+ tatsu_state <= S_LOAD_NEW_CONFIG;
+ status <= c_stat_clear;
+ else
+ status.settings_err <= '1';
+ status.settings_ok <= '0';
+ start_tm_tai <= (others => '0');
+ start_tm_cycles <= (others => '0');
+ shaper_req_refclk <= '0';
+ end if;
+
+ --==================================================================================
+ when others => --
+ --==================================================================================
+ tatsu_state <= S_ERROR;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+ shaper_request_o.req <= shaper_req_sysclk;
+ shaper_request_o.quanta <= window_quanta;
+ shaper_request_o.classes <= not prio_mask;
+ shaper_request_o.ports(g_num_ports-1 downto 0) <= port_mask;
+ shaper_request_o.ports(shaper_request_o.ports'length-1 downto g_num_ports) <= (others=>'0');
+
+ sync_req_refclk : gc_sync_ffs
+ generic map (
+ g_sync_edge => "positive")
+ port map (
+ clk_i => clk_sys_i,
+ rst_n_i => '1',
+ data_i => shaper_req_refclk,
+ synced_o => open,
+ npulse_o => open,
+ ppulse_o => shaper_req_sysclk);
+
+ sync_valid_refclk : gc_sync_ffs
+ generic map (
+ g_sync_edge => "positive")
+ port map (
+ clk_i => clk_ref_i,
+ rst_n_i => '1',
+ data_i => regs_fromwb.tcr_validate_o,
+ synced_o => valid_synced_refclk,
+ npulse_o => open,
+ ppulse_o => open);
+
+ sync_disable_refclk : gc_sync_ffs
+ generic map (
+ g_sync_edge => "positive")
+ port map (
+ clk_i => clk_ref_i,
+ rst_n_i => '1',
+ data_i => regs_fromwb.tcr_disable_o,
+ synced_o => disable_synced_refclk,
+ npulse_o => open,
+ ppulse_o => open);
+
+ sync_reset_refclk : gc_sync_ffs
+ generic map (
+ g_sync_edge => "positive")
+ port map (
+ clk_i => clk_ref_i,
+ rst_n_i => '1',
+ data_i => rst_n_i,
+ synced_o => rst_synced_refclk,
+ npulse_o => open,
+ ppulse_o => open);
+
+ U_WB_ADAPTER : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => true,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ slave_i => wb_i,
+ slave_o => wb_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ U_WISHBONE_IF: tatsu_wishbone_controller
+ port map(
+ rst_n_i => rst_n_i,
+ clk_sys_i => clk_sys_i,
+ wb_adr_i => wb_in.adr(2 downto 0),
+ wb_dat_i => wb_in.dat,
+ wb_dat_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
+ wb_stall_o => open,
+ regs_i => regs_towb,
+ regs_o => regs_fromwb
+ );
+
+ shaper_drop_at_hp_ena_o <= regs_fromwb.tcr_drop_ena_o;
+
+ config.start_tm_tai <= regs_fromwb.tsr0_htai_o & regs_fromwb.tsr1_ltai_o ;
+ config.start_tm_cycles <= regs_fromwb.tsr2_cyc_o;
+ config.repeat_cycles <= regs_fromwb.tsr3_cyc_o;
+ config.window_quanta <= regs_fromwb.tsr0_qnt_o;
+ config.prio_mask <= regs_fromwb.tsr0_prio_o;
+ config.ports_mask <= regs_fromwb.tsr4_ports_o;
+
+ regs_towb.tcr_min_rpt_i <= std_logic_vector(to_unsigned(c_min_repeat_cyc, regs_towb.tcr_min_rpt_i'length ));
+ regs_towb.tcr_started_i <= status.tatsu_started;
+ regs_towb.tcr_delayed_i <= status.tatsu_delayed;
+ regs_towb.tcr_stg_ok_i <= status.settings_ok;
+ regs_towb.tcr_stg_err_i <= status.settings_err;
+ regs_towb.tcr_stg_err_tai_i<= status.settings_err_tai;
+ regs_towb.tcr_stg_err_cyc_i<= status.settings_err_cyc;
+ regs_towb.tcr_stg_err_rpt_i<= status.settings_err_rpt;
+ regs_towb.tcr_stg_err_snc_i<= status.tm_sync_err;
+
+end rtl;
diff --git a/modules/wrsw_tru/Manifest.py b/modules/wrsw_tru/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..5cafc53d802dc221d427813695db507f7191d6f4
--- /dev/null
+++ b/modules/wrsw_tru/Manifest.py
@@ -0,0 +1,22 @@
+files = [
+ "tru_wbgen2_pkg.vhd",
+ "wrsw_tru_pkg.vhd",
+ "xwrsw_tru.vhd",
+ "wrsw_tru_wb.vhd",
+ "tru_port.vhd",
+ "tru_reconfig_rt_port_handler.vhd",
+ "tru_sub_vlan_pattern.vhd",
+ "tru_wishbone_slave.vhd",
+ "tru_endpoint.vhd",
+ "tru_transition.vhd",
+ "tru_trans_marker_trig.vhd",
+ "tru_trans_lacp_dist.vhd",
+ "tru_trans_lacp_colect.vhd",
+ "../wrsw_shared_types_pkg.vhd",
+ "../wrsw_rtu/rtu_private_pkg.vhd",
+ "../wrsw_rtu/rtu_wbgen2_pkg.vhd",
+ "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd",
+ "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd",
+ "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd",
+ "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd",
+ ]
\ No newline at end of file
diff --git a/modules/wrsw_tru/tru_endpoint.vhd b/modules/wrsw_tru/tru_endpoint.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..53b176c1aa55a10ac47ede319358db55635a644c
--- /dev/null
+++ b/modules/wrsw_tru/tru_endpoint.vhd
@@ -0,0 +1,250 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: endpoint
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_endpoint.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-08-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module interfaces endpoints and provides information
+-- useful for TRU module in a TRU-friendly way.
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+-- It takes care that a port which goes down is killed (turned off) and
+-- prevents throttling of port (going up and down againa and again due to
+-- e.g. bad connection) from affecting TRU.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-30 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_tru_request
+
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_endpoint is
+ generic(
+ g_num_ports : integer;
+ g_pclass_number : integer;
+ g_tru_subentry_num : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer;
+ g_stableUP_treshold: integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ port_if_i : in t_ep2tru; -- info from Endpoints
+ port_if_ctrl_o : out std_logic; -- turn off/on port (info to Endpoints)
+
+
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ rtu_pass_all_i : in std_logic; -- configuration from RTU
+
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoint_o : out t_tru_endpoint; -- this information is used by other submodules
+ -- of TRU (as info about port, it is interpreted
+ -- info about port)
+ -------------------------------global config/variable ----------------------------------
+ reset_rxFlag_i : in std_logic -- from config, reset remembered flag about rx-ed
+ -- frame (s_rxFrameMaskReg)
+ );
+end tru_endpoint;
+
+architecture rtl of tru_endpoint is
+ type t_tru_port_state is(S_DISABLED,
+ S_WORKING,
+ S_BROKEN_LINK);
+
+
+ signal s_zeros : std_logic_vector(31 downto 0);
+ signal s_port_status_d0 : std_logic;
+ signal s_port_status : std_logic;
+ signal s_port_down : std_logic; -- detects edge of the port status signal
+ -- in order to detect the event of "link down"
+ signal s_stableUp_cnt : unsigned(7 downto 0); -- count the number of cycles while which
+ -- a link is up -> to establish whether the
+ -- state is stable
+ signal s_tru_port_state : t_tru_port_state; -- FSM
+ signal s_rxFrameMaskReg : std_logic_vector(g_pclass_number-1 downto 0);-- to remember rx-ed Frame
+ signal s_rxFrameMask : std_logic_vector(g_pclass_number-1 downto 0);
+ signal s_port_if_ctrl : std_logic;
+begin --rtl
+
+ s_zeros <= (others => '0');
+ -- -----------------------------------------------------------------------------------------------
+ --
+ -- tihs FSM controls the information about Endpoint/port as seen by other TRU modules.
+ -- In other words the direct info from Endpoints is "interpreted" and only after this
+ -- "interpretation" it is used in TRU
+ --
+ -- -----------------------------------------------------------------------------------------------
+ FSM: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+
+ s_tru_port_state <= S_DISABLED;
+-- endpoint_o.status <= '0';
+ s_port_status <= '0';
+ s_port_if_ctrl <= '1';
+
+ else
+
+ case s_tru_port_state is
+ --====================================================================================
+ when S_DISABLED => -- port disabled by configuration (that of RTU)
+ --====================================================================================
+
+ -- port can become being seen by TRU modules as "up/working" only while it is
+ -- disabled from traffic forwarding. It is to make sure that everything is
+ -- under control and no "unwanted" forwarding does not take place
+ if(rtu_pass_all_i = '0' and port_if_i.status = '1') then
+ s_tru_port_state <= S_WORKING;
+-- endpoint_o.status <= '1';
+ s_port_status <= '1';
+ else
+-- endpoint_o.status <= '0';
+ s_port_status <= '0';
+ end if;
+
+-- endpoint_o.status <= port_if_i.status; -- when port is disabled we
+ -- forward the real state of the port
+ s_port_if_ctrl <= '1'; -- we always try to re-vive the port
+ -- by turning it ON, it is for
+ -- the case when we are in this state
+ -- because link-broke and was disabled
+ --====================================================================================
+ when S_WORKING =>
+ --====================================================================================
+
+ -- we detect that port went down
+ if(s_port_down = '1') then
+-- endpoint_o.status <= '0'; -- informing other TRU modules that port is down
+ s_port_status <= '0'; -- informing other TRU modules that port is down
+ s_port_if_ctrl <= '0'; -- killing the port to make sure it is down
+ s_tru_port_state <= S_BROKEN_LINK;
+ end if;
+
+ --====================================================================================
+ when S_BROKEN_LINK =>
+ --====================================================================================
+ -- once the port is detected to go down, it is tried to be re-vived only once
+ -- the port is disabled by configuration (so we try re-vive port which will
+ -- not forward anything). If the port is turned on (re-vived) by configuration,
+ -- it is still seen by TRU as down.
+ if(rtu_pass_all_i = '0' ) then
+ s_tru_port_state <= S_DISABLED;
+ s_port_if_ctrl <= '1';
+ end if;
+ --====================================================================================
+ when others =>
+ --====================================================================================
+ s_tru_port_state <= S_DISABLED;
+-- endpoint_o.status <= '0';
+ s_port_status <= '0';
+ s_port_if_ctrl <= '0';
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+ regs: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ s_port_status_d0 <= '0';
+ s_rxFrameMaskReg <= (others => '0');
+ s_rxFrameMask <= (others => '0');
+ else
+
+ s_port_status_d0 <= port_if_i.status;
+
+ -- accommodating information about HW-detected frames (probably in Endpoint)
+ -- we store info about detected frames in the *Reg
+ if(s_tru_port_state = S_WORKING and reset_rxFlag_i = '0' and port_if_i.pfilter_done = '1') then
+ s_rxFrameMaskReg <= s_rxFrameMaskReg or port_if_i.pfilter_pclass;
+ s_rxFrameMask <= port_if_i.pfilter_pclass;
+ elsif(s_tru_port_state = S_WORKING and reset_rxFlag_i = '1' and port_if_i.pfilter_done = '1') then
+ s_rxFrameMaskReg <= port_if_i.pfilter_pclass;
+ s_rxFrameMask <= port_if_i.pfilter_pclass;
+ elsif(reset_rxFlag_i = '1') then
+ s_rxFrameMaskReg <= (others => '0');
+ s_rxFrameMask <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- this is to assess whether a link is stabily UP. This info can be read by SW daemon
+ -- and used in deciding whether start using a port which is disabled (and maybe was down)
+ stableUP: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ endpoint_o.stableUp <= '0';
+ s_stableUp_cnt <= (others => '0');
+ else
+
+ if(s_port_down = '1') then
+ s_stableUp_cnt <= (others =>'0');
+ endpoint_o.stableUp <= '0';
+ elsif(port_if_i.status = '1') then
+ if(s_stableUp_cnt > to_unsigned(g_stableUP_treshold,s_stableUp_cnt'length )) then
+ endpoint_o.stableUp <= '1';
+ else
+ s_stableUp_cnt <= s_stableUp_cnt + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ endpoint_o.status <= s_port_status and rtu_pass_all_i;
+ endpoint_o.rxFrameMask(g_pclass_number-1 downto 0) <= s_rxFrameMask; --port_if_i.pfilter_pclass(g_pclass_number-1 downto 0) when (port_if_i.pfilter_done='1') else (others => '0');--s_rxFrameMask;
+ endpoint_o.rxFrameMaskReg(g_pclass_number-1 downto 0) <= s_rxFrameMaskReg(g_pclass_number-1 downto 0);
+ endpoint_o.inject_ready <= port_if_i.inject_ready;
+ -- detect link down event (edge of input status signal while the control info says port should
+ -- be UP);
+ s_port_down <= (not port_if_i.status) and s_port_status_d0 and s_port_if_ctrl;
+-- s_port_down <= (not port_if_i.status) and s_port_status_d0 and port_if_i.ctrlRd;
+
+ port_if_ctrl_o <= s_port_if_ctrl;
+end rtl;
diff --git a/modules/wrsw_tru/tru_port.vhd b/modules/wrsw_tru/tru_port.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..87d0925d88e3ff0f3cf171c3188f607aa242d1d6
--- /dev/null
+++ b/modules/wrsw_tru/tru_port.vhd
@@ -0,0 +1,287 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: port
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_port.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module is a main request-to-TRU handler.
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-28 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all;
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_port is
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer;
+ g_tru_addr_width : integer -- fid
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ------------------------------- I/F with RTU ----------------------------------
+ tru_req_i : in t_tru_request; -- request from RTU
+ tru_resp_o : out t_tru_response; -- response to RTU
+
+ ------------------------------- I/F with TRU TAB ----------------------------------
+ tru_tab_addr_o : out std_logic_vector(g_tru_addr_width-1 downto 0);
+ tru_tab_entry_i : in t_tru_tab_entry(g_tru_subentry_num - 1 downto 0);
+
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in t_tru_endpoints; -- interpreted (by tru_endpoint module)
+ -- info from endpoints/ports
+ ----------------------------------------------------------------------------------
+ config_i : in t_tru_config; -- WB-accesable configration
+ tru_tab_bank_swap_i: in std_logic;
+ globIngMask_dbg_o : out std_logic_vector(g_num_ports-1 downto 0);
+ txFrameMask_o : out std_logic_vector(g_num_ports - 1 downto 0) -- info to (e.g. Endpoint
+ -- or other module to HW-generate frame)
+ );
+end tru_port;
+
+architecture rtl of tru_port is
+
+ signal s_zeros : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_patternRep : std_logic_vector(g_pattern_width-1 downto 0);
+ signal s_patternAdd : std_logic_vector(g_pattern_width-1 downto 0);
+ signal s_patternSub : std_logic_vector(g_pattern_width-1 downto 0);
+ signal s_patternRep_d0 : std_logic_vector(g_pattern_width-1 downto 0);
+ signal s_patternAdd_d0 : std_logic_vector(g_pattern_width-1 downto 0);
+ signal s_patternSub_d0 : std_logic_vector(g_pattern_width-1 downto 0);
+
+ signal s_resp_masks : t_resp_masks;
+ signal s_backup_masks : t_resp_masks;
+ signal s_self_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_port_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_valid_d0 : std_logic;
+ signal s_valid_d1 : std_logic;
+ signal s_reqMask_d0 : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_reqMask_d1 : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_portID_vec : std_logic_vector(integer(CEIL(LOG2(real(g_num_ports + 1))))-1 downto 0);
+ signal s_drop : std_logic;
+ signal s_status_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_ingress_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_egress_mask : std_logic_vector(g_num_ports - 1 downto 0);
+ signal s_xor_mask : std_logic_vector(g_num_ports - 1 downto 0);
+begin --rtl
+
+ -- inputs
+ s_portID_vec <= std_logic_vector(to_unsigned(f_one_hot_to_binary(tru_req_i.reqMask),s_portID_vec'length )) ;
+ s_zeros <= (others => '0');
+ s_status_mask <= endpoints_i.status(g_num_ports-1 downto 0);
+
+
+ -- generating pattern to be used for replacement match
+ REPLACE_PATTERN: tru_sub_vlan_pattern
+ generic map(
+ g_num_ports => g_num_ports,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_pattern_width
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ portID_i => s_portID_vec,
+ patternID_i => config_i.mcr_pattern_mode_rep,
+ tru_req_i => tru_req_i,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ pattern_o => s_patternRep
+ );
+
+ -- generating pattern to be used in addition matches
+ ADD_PATTERN: tru_sub_vlan_pattern
+ generic map(
+ g_num_ports => g_num_ports,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_pattern_width
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ portID_i => s_portID_vec,
+ patternID_i => config_i.mcr_pattern_mode_add,
+ tru_req_i => tru_req_i,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ pattern_o => s_patternAdd
+ );
+
+
+ -- generating pattern to be used in substraction matches
+ SUB_PATTERN: tru_sub_vlan_pattern
+ generic map(
+ g_num_ports => g_num_ports,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_pattern_width
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ portID_i => s_portID_vec,
+ patternID_i => config_i.mcr_pattern_mode_sub,
+ tru_req_i => tru_req_i,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ pattern_o => s_patternSub
+ );
+
+ -- tracking changes of port configuration due to i.e. link down events (change of port status)
+ -- and reacting appropriately (e.g.: sending HW-generated frames)
+ RT_RECONFIG: tru_reconfig_rt_port_handler
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num=> g_tru_subentry_num
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ read_valid_i => s_valid_d0,
+ read_data_i => tru_tab_entry_i,
+ resp_masks_i => s_resp_masks,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ tru_tab_bank_swap_i=> tru_tab_bank_swap_i,
+ globIngMask_dbg_o => globIngMask_dbg_o,
+ txFrameMask_o => txFrameMask_o
+ );
+
+ CTRL: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+
+ s_self_mask <= (others =>'0');
+ s_patternRep_d0 <= (others =>'0');
+ s_patternAdd_d0 <= (others =>'0');
+ s_patternSub_d0 <= (others =>'0');
+ s_valid_d0 <= '0';
+ s_valid_d1 <= '0';
+ s_reqMask_d0 <= (others =>'0');
+ s_reqMask_d1 <= (others =>'0');
+ s_port_mask <= (others =>'0');
+ s_drop <= '0';
+
+ else
+ -- First stage (remembering/registering input signals)
+ s_patternRep_d0 <= s_patternRep;
+ s_patternAdd_d0 <= s_patternAdd;
+ s_patternSub_d0 <= s_patternSub;
+ s_self_mask <= tru_req_i.reqMask(g_num_ports-1 downto 0);
+ s_valid_d0 <= tru_req_i.valid;
+ s_reqMask_d0 <= tru_req_i.reqMask(g_num_ports-1 downto 0);
+
+ -- Second stage (producing output response)
+ s_reqMask_d1 <= s_reqMask_d0;
+ s_valid_d1 <= s_valid_d0;
+
+ -- provide output mask if TRU is enabled, one clock after receiving request
+ if(config_i.gcr_g_ena = '1' and s_valid_d0 = '1') then
+
+ -- if ingress on the reception is allowed, and the reception port is not meant
+ -- to be down, don't drop
+ if((s_ingress_mask and s_status_mask and s_self_mask) = s_zeros) then
+ s_drop <= '1';
+ s_port_mask <= (others=>'0');-- this is useful in rtu_port_new
+ else
+ s_drop <= '0';
+ -- output mask for forwarding takes into account:
+ -- * status of ports (don't forward to ports which are down)
+ -- * output from the TRU_TAB+patterns interpretation
+ -- * reception port (don't forward to myself)
+ s_port_mask <= s_status_mask and s_egress_mask and
+ (not s_self_mask);-- and (not s_xor_mask); -- TODO (31/07/2013)
+ -- add option somehow!!
+ -- commented: works for LACP
+ -- uncommented: works for RSTP/SPB
+
+ end if;
+
+ -- if there is no new request in the pipe, zero response
+ elsif(config_i.gcr_g_ena = '1' and s_valid_d0 = '0') then
+ s_port_mask <= (others =>'0');
+ s_drop <= '0';
+
+ -- if TRU is disabled, pass all messages to all ports and don't drop
+ -- (this will be ANDed with decision from RTU, of course)
+ else
+ s_port_mask <= (others =>'1');
+ s_drop <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- generating final mask to be used for forwarding based on:
+ -- * generated patterns (replacement and addition)
+ -- * entry read from the TRU TAB from the address equal to the provided (in req) FID
+ s_resp_masks <= f_gen_mask_with_patterns(tru_tab_entry_i,
+ s_patternRep_d0,
+ s_patternAdd_d0,
+ s_patternSub_d0,
+ g_tru_subentry_num);
+ s_backup_masks <= f_gen_mask_with_patterns(tru_tab_entry_i,
+ std_logic_vector(s_self_mask or s_patternRep_d0),
+ std_logic_vector(s_self_mask or s_patternAdd_d0),
+ s_patternSub_d0,
+ g_tru_subentry_num);
+
+ -- just to make the code a bit less messy
+ s_ingress_mask <= s_resp_masks.ingress(g_num_ports-1 downto 0);
+ s_egress_mask <= s_resp_masks.egress(g_num_ports-1 downto 0);
+ s_xor_mask <= s_ingress_mask xor s_backup_masks.ingress(g_num_ports-1 downto 0);
+
+ -- outputs
+ tru_tab_addr_o(g_tru_addr_width-1 downto 0) <= tru_req_i.fid(g_tru_addr_width-1 downto 0);
+ tru_resp_o.port_mask(g_num_ports-1 downto 0) <= s_port_mask;
+ tru_resp_o.respMask(g_num_ports-1 downto 0) <= s_reqMask_d1;
+ tru_resp_o.valid <= s_valid_d1;
+ tru_resp_o.drop <= s_drop;
+ tru_resp_o.respMask(tru_resp_o.respMask'length-1 downto g_num_ports) <= (others => '0');
+ tru_resp_o.port_mask(tru_resp_o.port_mask'length-1 downto g_num_ports) <= (others => '0');
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_port_wrapper.vhd b/modules/wrsw_tru/tru_port_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9a239b1fb7739e74cd62ce649ff469f8eef177c1
--- /dev/null
+++ b/modules/wrsw_tru/tru_port_wrapper.vhd
@@ -0,0 +1,186 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: port wrapper
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_port_wrapper.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-08-28
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-28 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * t_rtu_vlan_tab_entry
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_port_wrapper is
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_width : integer; -- in RTU this is:
+ g_tru_subentry_num : integer;
+ g_endp_entry_width : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer;
+ g_tru_addr_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ------------------------------- I/F with RTU ----------------------------------
+ --t_tru_request
+ tru_req_i : in std_logic_vector(1+48+48+8+1+1+g_num_ports-1 downto 0);
+
+ --rtu_resp_o
+ tru_resp_o : out std_logic_vector(1+2*g_num_ports+1-1 downto 0);
+
+ ------------------------------- I/F with TRU tab -----------------------------------
+ tru_tab_addr_o : out std_logic_vector(g_tru_addr_width-1 downto 0);
+ tru_tab_entry_i : in std_logic_vector(g_tru_subentry_num*g_tru_subentry_width-1 downto 0);
+
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in std_logic_vector(g_num_ports*g_endp_entry_width-1 downto 0);
+
+ -------------------------------global config/variable ----------------------------------
+ gcr_g_ena_i : in std_logic;
+ gcr_tru_bank_i : in std_logic;
+ gcr_rx_frame_reset_i : in std_logic_vector(23 downto 0);
+ -- pattern match config
+ mcr_pattern_mode_rep_i : in std_logic_vector(3 downto 0);
+ mcr_pattern_mode_add_i : in std_logic_vector(3 downto 0);
+ -- linc aggregation config
+ lacr_agg_gr_num_i : in std_logic_vector(3 downto 0);
+ lacr_agg_df_br_id_i : in std_logic_vector(3 downto 0);
+ lacr_agg_df_un_id_i : in std_logic_vector(3 downto 0);
+ lagt_gr_id_mask_i : in std_logic_vector(8*4-1 downto 0);
+ -- transition config
+ tcr_trans_ena_i : in std_logic;
+ tcr_trans_mode_i : in std_logic_vector(2 downto 0);
+ tcr_trans_rx_id_i : in std_logic_vector(2 downto 0);
+ tcr_trans_port_a_id_i : in std_logic_vector(5 downto 0);
+ tcr_trans_port_a_valid_i: in std_logic;
+ tcr_trans_port_b_id_i : in std_logic_vector(5 downto 0);
+ tcr_trans_port_b_valid_i: in std_logic;
+ -- real time reconfiguration config
+ rtrcr_rtr_ena_i : in std_logic;
+ rtrcr_rtr_reset_i : in std_logic;
+ rtrcr_rtr_mode_i : in std_logic_vector(3 downto 0);
+ rtrcr_rtr_rx_i : in std_logic_vector(3 downto 0)
+ );
+end tru_port_wrapper;
+
+architecture rtl of tru_port_wrapper is
+ signal s_tru_req : t_tru_request;
+ signal s_tru_resp : t_tru_response;
+ signal s_tru_tab_entry : t_tru_tab_entry(g_tru_subentry_num-1 downto 0);
+ signal s_endpoints : t_tru_endpoint;
+ signal s_config : t_tru_config;
+ type t_tru_tab_subentry_arr is array(integer range <>) of std_logic_vector(g_tru_subentry_width-1 downto 0);
+
+ signal s_tru_tab_subentry_arr : t_tru_tab_subentry_arr(g_tru_subentry_num-1 downto 0);
+begin
+
+ tru_p: tru_port
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num => g_tru_subentry_num,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_pattern_width,
+ g_tru_addr_width => g_tru_addr_width
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ tru_req_i => s_tru_req,
+ tru_resp_o => s_tru_resp,
+ tru_tab_addr_o => tru_tab_addr_o,
+ tru_tab_entry_i => s_tru_tab_entry,
+ endpoints_i => s_endpoints,
+ config_i => s_config
+ );
+
+ s_tru_req <= f_unpack_tru_request (tru_req_i, g_num_ports);
+ tru_resp_o <= f_pack_tru_response (s_tru_resp, g_num_ports);
+
+ G0: for i in g_num_ports-1 generate
+ s_endpoints(i)<= f_unpack_tru_endpoint(endpoints_i((i+1)*g_endp_entry_width downto i*g_endp_entry_width));
+ end generate G0;
+
+ G1: for i in 0 to g_tru_subentry_num-1 generate
+ s_tru_tab_subentry_arr(i) <= tru_tab_entry_i((i+1)*g_tru_subentry_width-1 downto i*g_tru_subentry_width);
+ s_tru_tab_entry(i) <= f_unpack_tru_subentry(s_tru_tab_subentry_arr(i),g_num_ports);
+ end generate G1;
+
+
+ s_config.gcr_g_ena <= gcr_g_ena_i;
+ s_config.gcr_tru_bank <= gcr_tru_bank_i;
+ s_config.gcr_rx_frame_reset <= gcr_rx_frame_reset_i;
+ s_config.mcr_pattern_mode_rep <= mcr_pattern_mode_rep_i;
+ s_config.mcr_pattern_mode_add <= mcr_pattern_mode_add_i;
+ s_config.lacr_agg_gr_num <= lacr_agg_gr_num_i;
+ s_config.lacr_agg_df_br_id <= lacr_agg_df_br_id_i;
+ s_config.lacr_agg_df_un_id <= lacr_agg_df_un_id_i;
+
+ G2: for i in 0 to 7 generate
+ s_config.lagt_gr_id_mask(i) <= lagt_gr_id_mask_i((i+1)*4 -1 downto i*4);
+ end generate;
+
+ s_config.tcr_trans_ena <= tcr_trans_ena_i;
+ s_config.tcr_trans_mode <= tcr_trans_mode_i;
+ s_config.tcr_trans_rx_id <= tcr_trans_rx_id_i;
+ s_config.tcr_trans_port_a_id <= tcr_trans_port_a_id_i;
+ s_config.tcr_trans_port_a_valid<= tcr_trans_port_a_valid_i;
+ s_config.tcr_trans_port_b_id <= tcr_trans_port_b_id_i;
+ s_config.tcr_trans_port_b_valid<= tcr_trans_port_b_valid_i;
+ s_config.rtrcr_rtr_ena <= rtrcr_rtr_ena_i;
+ s_config.rtrcr_rtr_reset <= rtrcr_rtr_reset_i;
+ s_config.rtrcr_rtr_mode <= rtrcr_rtr_mode_i;
+ s_config.rtrcr_rtr_rx <= rtrcr_rtr_rx_i;
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd b/modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8bf89fb8ae0567288d5d90f8bff4acf2b3ee93c5
--- /dev/null
+++ b/modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd
@@ -0,0 +1,173 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: reconfiguration real-time port handler
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_reconfig_rt_port_handler.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module tracks changes of topology due to boren links and,
+-- if necessary, takes action i.e. sends "quick forward" messages to other
+-- switches to switch port to forwarding state
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-28 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * t_rtu_vlan_tab_entry
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_reconfig_rt_port_handler is
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ read_valid_i : in std_logic;
+ read_data_i : in t_tru_tab_entry(g_tru_subentry_num - 1 downto 0);
+ resp_masks_i : in t_resp_masks;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_swap_i: in std_logic;
+ globIngMask_dbg_o : out std_logic_vector(g_num_ports-1 downto 0);
+ txFrameMask_o : out std_logic_vector(g_num_ports-1 downto 0)
+ );
+end tru_reconfig_rt_port_handler;
+
+architecture rtl of tru_reconfig_rt_port_handler is
+
+ signal s_globIngMask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_globIngMask_d0 : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_globIngMask_or : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_txFrameMask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_globIngMask_xor : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_inject_ready : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_zeros : std_logic_vector(g_num_ports-1 downto 0);
+begin --rtl
+
+ s_zeros <= (others =>'0');
+ -------------------------------------------------------------------------------------------------
+ -- The below code is used to send HW-generated "quick forwrad" frames to request the neighbour
+ -- port to open (for ingress) port connected to the port which has just been made "active" on
+ -- "our switch" (the one the code is run).
+ -- This is used in the case if we've just enabled for ingress "backup" port and we want
+ -- that the neighbour-switch did the same on the same link very quickly.
+ -------------------------------------------------------------------------------------------------
+ -- Here we assume that the first subentry in the TRU TAB (for a given FID) is the default
+ -- entry (read_data_i(0).ports_ingress). Therefore, any ingress decision (resp_masks_i.ingress)
+ -- which is different then the first (number 0) TRU subentry means that there has been some
+ -- change (most probably port was opened as a backup for a port which went down).
+ -- Then we check this changes against the changes in of portIngres mask which we
+ -- have already remembered/detected and stored in the past: s_globIngMask_d0.
+ -- Finally, what we get are (if any) new changes to the port ingress mask.
+ s_globIngMask <= ((read_data_i(0).ports_ingress(g_num_ports-1 downto 0) xor
+ resp_masks_i.ingress(g_num_ports-1 downto 0)) and
+ (resp_masks_i.ingress(g_num_ports-1 downto 0))) and
+ (not s_globIngMask_d0);
+
+ -- to make the code less messy
+ s_globIngMask_or <= s_globIngMask or s_globIngMask_d0;
+ s_globIngMask_xor <= s_globIngMask_d0 xor s_globIngMask_or;
+ s_inject_ready <= endpoints_i.inject_ready(g_num_ports-1 downto 0);
+
+ -- send HW-generated frame
+ txFrameMask_o <= s_txFrameMask;
+
+ -- process which generate requests to send HW-generated frames (rx)
+ RX: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0' or config_i.rtrcr_rtr_ena='0') then
+
+ s_globIngMask_d0 <= (others =>'0');
+ s_txFrameMask <= (others=> '0');
+
+ else
+
+ case config_i.rtrcr_rtr_mode is -- many configs possible, only single available at the moment
+ --------------------------------------------------------------------------------------------
+ when std_logic_vector(to_unsigned(0,4))=> -- default
+ --------------------------------------------------------------------------------------------
+ s_globIngMask_d0 <= (others => '0');
+ s_txFrameMask <= (others=> '0');
+ --------------------------------------------------------------------------------------------
+ when std_logic_vector(to_unsigned(1,4))=> -- eRSTP
+ --------------------------------------------------------------------------------------------
+
+ s_txFrameMask <= (others=> '0');
+
+ -- if we swap the bank of the memory (new configuration) or reset the RT module,
+ -- then we need to clear the remembered chagnes.
+ if(config_i.rtrcr_rtr_reset = '1' or tru_tab_bank_swap_i = '1') then
+ s_globIngMask_d0 <= (others => '0');
+
+ -- Generate signal to send HW-generated frames based on the remembered info and
+ -- newly generated mask
+-- elsif(read_valid_i = '1') then
+-- else
+ elsif((s_inject_ready and s_globIngMask_xor) /= s_zeros) then
+ s_globIngMask_d0 <= s_globIngMask_or;
+ s_txFrameMask <= s_globIngMask_xor;
+ end if;
+ --------------------------------------------------------------------------------------------
+ when others =>
+ --------------------------------------------------------------------------------------------
+ s_globIngMask_d0 <= (others => '0');
+ s_txFrameMask <= (others => '0');
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+ -- debugging
+ globIngMask_dbg_o <= s_globIngMask_d0;
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_sub_vlan_pattern.vhd b/modules/wrsw_tru/tru_sub_vlan_pattern.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c39179a789986eb6c62d36bea16c9dc3882deca1
--- /dev/null
+++ b/modules/wrsw_tru/tru_sub_vlan_pattern.vhd
@@ -0,0 +1,120 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: sub VLAN pattern
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_sub_vlan_pattern.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: A wrapper for different implementations of pattern generation.
+-- Here, based on configuration, proper pattern generator is chosen.
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+-- Pattern is used to decide which information from TRU Table is used to
+-- make the forwarding decision (combination of more info can be used)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-28 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * t_rtu_vlan_tab_entry
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_sub_vlan_pattern is
+ generic(
+ g_num_ports : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer
+
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ portID_i : in std_logic_vector(integer(CEIL(LOG2(real(g_num_ports + 1))))-1 downto 0);
+ patternID_i : in std_logic_vector(g_patternID_width-1 downto 0);
+ ------------------------------- I/F with RTU ----------------------------------
+ tru_req_i : in t_tru_request;
+
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in t_tru_endpoints;
+
+ -------------------------------global config/variable ----------------------------------
+ config_i : in t_tru_config;
+
+ -- thee required response
+ pattern_o : out std_logic_vector(g_pattern_width-1 downto 0)
+
+ );
+end tru_sub_vlan_pattern;
+
+architecture rtl of tru_sub_vlan_pattern is
+
+-- type t_pattern is std_logic_vector(patternID_i'lengt-1 downto 0);
+
+constant c_p_default : std_logic_vector(g_patternID_width-1 downto 0) :=x"0"; -- default
+constant c_p_port_down : std_logic_vector(g_patternID_width-1 downto 0) :=x"1"; -- port down
+constant c_p_quick_fwd : std_logic_vector(g_patternID_width-1 downto 0) :=x"2"; -- quick forward received frames
+constant c_p_quick_blk : std_logic_vector(g_patternID_width-1 downto 0) :=x"3"; -- quick block received frames
+constant c_p_aggr_gr_id : std_logic_vector(g_patternID_width-1 downto 0) :=x"4"; -- aggregation group id
+constant c_p_rx_port : std_logic_vector(g_patternID_width-1 downto 0) :=x"5"; -- received port
+
+
+signal rxFrameNumber : integer range 0 to endpoints_i.rxFrameMaskReg'length-1;
+signal rxPort : integer range 0 to g_num_ports;
+
+begin --rtl
+
+ -----------------------------------------------------------------------------------------------
+ -- Generate different patterns depending on the input configuration
+ -----------------------------------------------------------------------------------------------
+ -- TODO: case and choose functions according to the config
+ -----------------------------------------------------------------------------------------------
+ pattern_o <=
+ (others=>'0') when (patternID_i = c_p_default) else -- 0: defaut
+ f_pattern_port_down (endpoints_i,g_pattern_width) when (patternID_i = c_p_port_down) else -- 1: eRSTP
+ f_pattern_quick_fwd (endpoints_i,config_i,g_pattern_width) when (patternID_i = c_p_quick_fwd) else -- 2: eRSTP:
+ f_pattern_quick_blk (endpoints_i,config_i,g_pattern_width) when (patternID_i = c_p_quick_blk) else -- 3: eRSTP:
+ f_pattern_aggr_gr_id(endpoints_i,tru_req_i, portID_i,config_i,g_pattern_width,g_num_ports) when (patternID_i = c_p_aggr_gr_id) else -- 4: eLACP:
+ f_pattern_rx_port (tru_req_i, g_pattern_width) when (patternID_i = c_p_rx_port) else -- 5: eLACP
+ (others=>'0');
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_trans_lacp_colect.vhd b/modules/wrsw_tru/tru_trans_lacp_colect.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fd6fa368caba3a230a15ab6bd3bdead3560646f0
--- /dev/null
+++ b/modules/wrsw_tru/tru_trans_lacp_colect.vhd
@@ -0,0 +1,109 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: Link Aggregation protocol, marker, distribution
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_trans_lacp_dist.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-09-10
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module supports transition of "message stream" between
+-- links (connections) of "link aggregation" on the switch being a collector.
+--[to be implemented]
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-09-10 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all;
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_trans_lacp_colect is
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in t_tru_endpoints;
+
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+end tru_trans_lacp_colect;
+
+architecture rtl of tru_trans_lacp_colect is
+
+ signal s_ep : t_trans2ep;
+ signal s_sw : t_trans2sw;
+
+begin --rtl
+
+ -- TODO
+
+ statTransActive_o <= '0';
+ statTransFinished_o <= '0';
+ tru_tab_bank_o <= '0';
+ s_ep.pauseSend <= '0';
+ s_ep.pauseTime <= (others => '0');
+ s_ep.pauseSend <= '0';
+ s_ep.pauseTime <= (others => '0');
+ s_sw.blockTime <= (others => '0');
+ s_sw.blockQueuesMask <= (others => '0');
+ s_sw.blockPortsMask <= (others => '0');
+ s_sw.blockReq <= '0';
+
+ EP_OUT: for i in 0 to g_num_ports-1 generate
+ ep_o(i)<= s_ep;
+ end generate EP_OUT;
+
+ sw_o <= s_sw;
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_trans_lacp_dist.vhd b/modules/wrsw_tru/tru_trans_lacp_dist.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a90862c717bd7a9177439c3590a29ac9416fa58a
--- /dev/null
+++ b/modules/wrsw_tru/tru_trans_lacp_dist.vhd
@@ -0,0 +1,270 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: Link Aggregation protocol, marker, distribution
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_trans_lacp_dist.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-09-10
+-- Last update: 2013-08-01
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module supports transition of "message stream" between
+-- links (connections) of "link aggregation" on the switch being a distributor.
+--[to be implemented]
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-09-10 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all;
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_trans_lacp_dist is
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in t_tru_endpoints;
+
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+end tru_trans_lacp_dist;
+
+architecture rtl of tru_trans_lacp_dist is
+
+ type t_tru_trans_state is(S_IDLE,
+ S_WAIT_RESP_MARKER,
+ S_TRANSITIONED);
+
+ signal s_tru_trans_state : t_tru_trans_state;
+ signal s_start_transition : std_logic;
+ signal s_portA_frame_cnt : unsigned(integer(CEIL(LOG2(real(g_mt_trans_max_fr_cnt-1)))) -1 downto 0);
+ signal s_portB_frame_cnt : unsigned(integer(CEIL(LOG2(real(g_mt_trans_max_fr_cnt-1)))) -1 downto 0);
+ signal s_statTransActive : std_logic;
+ signal s_statTransFinished : std_logic;
+ signal s_port_A_mask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_port_B_mask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_port_A_prio : std_logic_vector(g_prio_width-1 downto 0);
+ signal s_port_B_prio : std_logic_vector(g_prio_width-1 downto 0);
+ signal s_port_A_has_prio : std_logic;
+ signal s_port_B_has_prio : std_logic;
+
+ signal s_port_prio_mask : std_logic_vector(2**g_prio_width-1 downto 0);
+
+ signal s_ep_ctr_A : t_trans2ep;
+ signal s_ep_ctr_B : t_trans2ep;
+ signal s_ep_zero : t_trans2ep;
+
+ signal s_sw_ctrl : t_trans2sw;
+
+begin --rtl
+
+ -- to make code less messy - start transition only it is enabled by config and all necessary
+ -- config is valid
+ s_start_transition <= config_i.tcr_trans_ena and
+ config_i.tcr_trans_port_a_valid and
+ config_i.tcr_trans_port_b_valid;
+
+ -- generating mask with 1 at the priority for with we perform transition (configured value)
+ -- TODO: we would need more options here
+ G_PRIO_MASK: for i in 0 to 2**g_prio_width-1 generate
+ s_port_prio_mask(i) <= '1' when(i = to_integer(unsigned(config_i.tcr_trans_prio))) else '0';
+ end generate G_PRIO_MASK;
+
+ -- generating mask with 1 at the port to which we transition ... TODO: we need more then one
+ G_MASK: for i in 0 to g_num_ports-1 generate
+ s_port_A_mask(i) <= '1' when (i = to_integer(unsigned(config_i.tcr_trans_port_a_id)) and config_i.tcr_trans_port_a_valid ='1') else '0';
+ s_port_B_mask(i) <= '1' when (i = to_integer(unsigned(config_i.tcr_trans_port_b_id)) and config_i.tcr_trans_port_b_valid ='1') else '0';
+ end generate G_MASK;
+
+ -- preparing masks
+ s_sw_ctrl.blockPortsMask(g_num_ports-1 downto 0) <= s_port_B_mask;
+ s_sw_ctrl.blockQueuesMask(2**g_prio_width-1 downto 0) <= s_port_prio_mask;
+
+ -- filling in not-used bits
+ s_sw_ctrl.blockPortsMask(s_sw_ctrl.blockPortsMask'length -1 downto g_num_ports) <= (others =>'0');
+ s_sw_ctrl.blockQueuesMask(s_sw_ctrl.blockQueuesMask'length-1 downto 2**g_prio_width) <= (others =>'0');
+
+ -- an empty entry
+ s_ep_zero.pauseSend <= '0';
+ s_ep_zero.pauseTime <= (others => '0');
+ s_ep_zero.outQueueBlockMask <= (others => '0');
+ s_ep_zero.outQueueBlockReq <= '0';
+ s_ep_zero.hwframe_fwd <= '0';
+ s_ep_zero.hwframe_blk <= '0';
+
+ TRANS_FSM: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+
+ s_tru_trans_state <= S_IDLE;
+ s_statTransActive <= '0';
+ s_statTransFinished <= '0';
+ tru_tab_bank_o <= '0';
+
+ s_ep_ctr_A <= s_ep_zero;
+ s_ep_ctr_B <= s_ep_zero;
+
+ s_sw_ctrl.blockTime <= (others => '0');
+ s_sw_ctrl.blockReq <= '0';
+
+ else
+
+ case s_tru_trans_state is
+
+ --====================================================================================
+ when S_IDLE =>
+ --====================================================================================
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_sw_ctrl.blockTime <= (others => '0');
+ s_sw_ctrl.blockReq <= '0';
+
+ -- new transition is not started until the previous has been cleared/finished
+ if(s_start_transition = '1' and s_statTransFinished ='0' and s_statTransActive = '0') then --
+ s_tru_trans_state <= S_WAIT_RESP_MARKER;
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '1'; -- indicate that transition is active (goes to the WBgen
+ -- status reg read by SW)
+ s_statTransFinished <= '0';
+
+ -- block Port_B
+ s_sw_ctrl.blockReq <= '1';
+ s_sw_ctrl.blockTime <= config_i.tcr_trans_block_time;
+
+ -- change distribution
+ tru_tab_bank_o <= '1'; -- request bank swap of TRU TAB
+ end if;
+
+ --====================================================================================
+ when S_WAIT_RESP_MARKER => -- block the output queue of port_B and wait to receive
+ -- Marker Response on port_A
+ --====================================================================================
+
+ tru_tab_bank_o <= '0';
+ s_sw_ctrl.blockReq <= '0';
+ -- Marker Response on port A detected, can unblock the port
+ if((s_port_A_mask and rxFrameMask_i) = s_port_A_mask) then
+ s_tru_trans_state <= S_TRANSITIONED;
+
+ -- stop pause
+ s_sw_ctrl.blockReq <= '1';
+ s_sw_ctrl.blockTime <= (others => '0');
+
+ end if;
+ --====================================================================================
+ when S_TRANSITIONED => -- swap banks (assuming proper config in the TRU TAB)
+ --====================================================================================
+
+ -- transition: done
+ s_tru_trans_state <= S_IDLE;
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_statTransFinished <= '1';
+ tru_tab_bank_o <= '0';
+ s_sw_ctrl.blockReq <= '1';
+
+ --====================================================================================
+ when others =>
+ --====================================================================================
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_statTransFinished <= '0';
+ s_tru_trans_state <= S_IDLE;
+
+ end case;
+
+ -- clearing of finished bit by configuration
+ if(s_statTransFinished = '1' and s_statTransActive ='1' and config_i.tcr_trans_clr = '1') then
+ s_statTransFinished <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+ statTransActive_o <= s_statTransActive;
+ statTransFinished_o <= s_statTransFinished;
+ sw_o <= s_sw_ctrl;
+ -- MUX of Port A/B control (outputs) to appropraite ports
+ EP_OUT: for i in 0 to g_num_ports-1 generate
+ ep_o(i)<= s_ep_ctr_A when (i = to_integer(unsigned(config_i.tcr_trans_port_a_id))) else
+ s_ep_ctr_B when (i = to_integer(unsigned(config_i.tcr_trans_port_b_id))) else
+ s_ep_zero;
+ end generate EP_OUT;
+
+
+
+-- -- TODO
+--
+-- statTransActive_o <= '0';
+-- statTransFinished_o <= '0';
+-- tru_tab_bank_o <= '0';
+-- s_ep.pauseSend <= '0';
+-- s_ep.pauseTime <= (others => '0');
+-- s_sw.blockTime <= (others => '0');
+-- s_sw.blockQueuesMask <= (others => '0');
+-- s_sw.blockPortsMask <= (others => '0');
+-- s_sw.blockReq <= '0';
+--
+-- EP_OUT: for i in 0 to g_num_ports-1 generate
+-- ep_o(i) <= s_ep;
+-- end generate EP_OUT;
+--
+-- sw_o <= s_sw;
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_trans_marker_trig.vhd b/modules/wrsw_tru/tru_trans_marker_trig.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..08426e0e7304472ad8c0f451ce273d82d88834d7
--- /dev/null
+++ b/modules/wrsw_tru/tru_trans_marker_trig.vhd
@@ -0,0 +1,358 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: marker triggered transition
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_trans_marker_trig.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-09-05
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module implements transition (switching) between redundant
+-- links. The transition is triggered by special Ethernet Frames (markers)
+-- sent over WR Network by root switch
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+-- We assume that:
+-- * we switch from port A which is now forwarding (active) to port B which is now blocking
+-- * port A provides "slower" path to our switch
+-- * port B provides "faster" path to our switch
+-- * the time difference between the A-provided "slower" path and B-provided "faster" path
+-- is known (figured out by S/W) and provided to the module
+-- * single transition is done at a time
+
+-- The module uses:
+-- * HW-based detection of frames (e.g. by Endpoint)
+-- * pause mechanism in Endpoint
+-- * information (time diff, from which to which port to switch) provided by S/W
+--
+-- Module needs to be enabled to start working. once it performs the switch-over, it will
+-- not attempt to perform another one until it is reseted by configuration
+--
+-- Works more or less like this:
+-- 1. wait for marker on port B (on faster path, so receives the marker braodcasted from Root
+-- switch faster then port A)
+-- 2. on reception of marker on port B do:
+-- - send HW-generated (in Endpoint) pause with the set pauseTime=diff provided by S/W
+-- - start counting how many messages of the configured priority we receive on this port
+-- (it will take some time for the pause to get to the other side of the link prevent
+-- the other switch from sending stuff)
+-- - blocks output queues of both ports (this is not entirely good solution, working
+-- on better)
+-- 3. wait for marker on port A (on slower path)
+-- 4. on reception of marker on port A:
+-- - start counting frames received on this port
+-- - when the number of frames received on port A is equal the number of frames received on
+-- port B, perform transition
+-- 5. on transition
+-- - swap banks of TRU (we assume that in the new bank a new and proper cnfiguration
+-- is available, in this configuration port A is active and port be is backup)
+-- - set bit finished
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-09-05 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all;
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_trans_marker_trig is
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in t_tru_endpoints;
+
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ ports_req_strobe_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+end tru_trans_marker_trig;
+
+architecture rtl of tru_trans_marker_trig is
+ type t_tru_trans_state is(S_IDLE,
+ S_WAIT_PA_MARKER,
+ S_WAIT_PB_MARKER,
+ S_WAIT_WITH_TRANS,
+ S_TRANSITIONED);
+
+ signal s_tru_trans_state : t_tru_trans_state;
+ signal s_start_transition : std_logic;
+ signal s_portA_frame_cnt : unsigned(integer(CEIL(LOG2(real(g_mt_trans_max_fr_cnt-1)))) -1 downto 0);
+ signal s_portB_frame_cnt : unsigned(integer(CEIL(LOG2(real(g_mt_trans_max_fr_cnt-1)))) -1 downto 0);
+ signal s_statTransActive : std_logic;
+ signal s_statTransFinished : std_logic;
+ signal s_port_A_mask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_port_B_mask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_port_A_prio : std_logic_vector(g_prio_width-1 downto 0);
+ signal s_port_B_prio : std_logic_vector(g_prio_width-1 downto 0);
+ signal s_port_A_has_prio : std_logic;
+ signal s_port_B_has_prio : std_logic;
+
+ signal s_port_prio_mask : std_logic_vector(2**g_prio_width-1 downto 0);
+
+ signal s_port_A_rtu_srobe : std_logic;
+ signal s_port_B_rtu_srobe : std_logic;
+ signal s_ep_ctr_A : t_trans2ep;
+ signal s_ep_ctr_B : t_trans2ep;
+ signal s_ep_zero : t_trans2ep;
+
+ signal s_sw_ctrl : t_trans2sw;
+
+begin --rtl
+
+ -- to make code less messy - start transition only it is enabled by config and all necessary
+ -- config is valid
+ s_start_transition <= config_i.tcr_trans_ena and
+ config_i.tcr_trans_port_a_valid and
+ config_i.tcr_trans_port_b_valid;
+
+ -- generating mask with 1 at the priority for with we perform transition (configured value)
+ G_PRIO_MASK: for i in 0 to 2**g_prio_width-1 generate
+ s_port_prio_mask(i) <= '1' when(i = to_integer(unsigned(config_i.tcr_trans_prio))) else '0';
+ end generate G_PRIO_MASK;
+
+ -- generating mask with 1 at the port for with we perform transition
+ G_MASK: for i in 0 to g_num_ports-1 generate
+ s_port_A_mask(i) <= '1' when (i = to_integer(unsigned(config_i.tcr_trans_port_a_id)) and config_i.tcr_trans_port_a_valid ='1') else '0';
+ s_port_B_mask(i) <= '1' when (i = to_integer(unsigned(config_i.tcr_trans_port_b_id)) and config_i.tcr_trans_port_b_valid ='1') else '0';
+ end generate G_MASK;
+
+ -- preparing masks
+ s_sw_ctrl.blockPortsMask(g_num_ports-1 downto 0) <= s_port_A_mask or s_port_B_mask;
+ s_sw_ctrl.blockQueuesMask(2**g_prio_width-1 downto 0) <= s_port_prio_mask;
+
+ -- filling in not-used bits
+ s_sw_ctrl.blockPortsMask(s_sw_ctrl.blockPortsMask'length -1 downto g_num_ports) <= (others =>'0');
+ s_sw_ctrl.blockQueuesMask(s_sw_ctrl.blockQueuesMask'length-1 downto 2**g_prio_width) <= (others =>'0');
+
+ -- to make the code less messy
+-- s_port_A_prio <= rtu_i.priorities(to_integer(unsigned(config_i.tcr_trans_port_a_id)));
+-- s_port_B_prio <= rtu_i.priorities(to_integer(unsigned(config_i.tcr_trans_port_b_id)));
+
+-- s_port_A_prio <= rtu_i.priorities(to_integer(unsigned(config_i.tcr_trans_port_a_id)));
+-- s_port_A_has_prio <= rtu_i.has_prio(to_integer(unsigned(config_i.tcr_trans_port_a_id)));
+-- s_port_B_prio <= rtu_i.priorities(to_integer(unsigned(config_i.tcr_trans_port_b_id)));
+-- s_port_B_has_prio <= rtu_i.has_prio(to_integer(unsigned(config_i.tcr_trans_port_b_id)));
+
+-- s_port_A_rtu_srobe <= '1' when ((s_port_A_mask and rtu_i.request_valid(g_num_ports-1 downto 0)) = s_port_A_mask and
+-- s_port_A_prio = config_i.tcr_trans_prio and s_port_A_has_prio = '1') else '0';
+-- s_port_B_rtu_srobe <= '1' when ((s_port_B_mask and rtu_i.request_valid(g_num_ports-1 downto 0)) = s_port_B_mask and
+-- s_port_B_prio = config_i.tcr_trans_prio and s_port_B_has_prio = '1') else '0';
+
+ s_port_A_rtu_srobe <= ports_req_strobe_i(to_integer(unsigned(config_i.tcr_trans_port_a_id)));
+ s_port_B_rtu_srobe <= ports_req_strobe_i(to_integer(unsigned(config_i.tcr_trans_port_b_id)));
+
+
+ -- an empty entry
+ s_ep_zero.pauseSend <= '0';
+ s_ep_zero.pauseTime <= (others => '0');
+ s_ep_zero.outQueueBlockMask <= (others => '0');
+ s_ep_zero.outQueueBlockReq <= '0';
+ s_ep_zero.hwframe_fwd <= '0';
+ s_ep_zero.hwframe_blk <= '0';
+
+ -- this FSM tries to switch forwarding from port A to port B without loosing frames on a
+ -- defined priority. It waits for marker broadcasted from the topology root.
+ -- We assume here that the new path (through port B) is "faster/shorter/better". If we
+ -- switched between these paths without special attention, we would loose some frames which
+ -- were in the "longer/slower" path and has been already dropped by port B (on faster/shorter path)
+ -- Once the Marker is received on port B (sooner because it's faster), we send HW-generated
+ -- pause on this port (it takes time for it to take effect) and count how many frames we receive
+ -- (of specified priority).
+ -- We also block output queues on ports A and B (this is for up-traffic nodes->root, but this idea
+ -- needs revision)
+ -- Once the Marker is received on port A, we start counting received frames (of specified priority)
+ -- and as soon as we received the same number as on port B, we request to swap the bank of
+ -- TRU Tab. here we assume that the new configuration is appropraite (port A is not active any
+ -- more, port B is active)
+ TRANS_FSM: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+
+ s_tru_trans_state <= S_IDLE;
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_statTransFinished <= '0';
+ tru_tab_bank_o <= '0';
+
+ s_ep_ctr_A <= s_ep_zero;
+ s_ep_ctr_B <= s_ep_zero;
+
+ s_sw_ctrl.blockTime <= (others => '0');
+ s_sw_ctrl.blockReq <= '0';
+
+ else
+
+ case s_tru_trans_state is
+
+ --====================================================================================
+ when S_IDLE =>
+ --====================================================================================
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_sw_ctrl.blockTime <= (others => '0');
+ s_sw_ctrl.blockReq <= '0';
+
+ -- new transition is not started until the previous has been cleared/finished
+ if(s_start_transition = '1' and s_statTransFinished ='0' and s_statTransActive = '0') then --
+ s_tru_trans_state <= S_WAIT_PB_MARKER;
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '1'; -- indicate that transition is active (goes to the WBgen
+ -- status reg read by SW)
+ s_statTransFinished <= '0';
+ end if;
+
+ --====================================================================================
+ when S_WAIT_PB_MARKER => -- wait for the marker on the "faster" port
+ --====================================================================================
+
+ -- marker frame on port B detected
+ if((s_port_B_mask and rxFrameMask_i) = s_port_B_mask) then
+ s_tru_trans_state <= S_WAIT_PA_MARKER;
+
+ -- send HW-generated paus
+ s_ep_ctr_B.pauseSend <= '1';
+-- s_ep_ctr_B.pauseTime <= config_i.tcr_trans_pause_time;
+
+ -- block output queues (TODO: to be revised)
+ s_sw_ctrl.blockReq <= '1';
+ s_sw_ctrl.blockTime <= config_i.tcr_trans_block_time;
+ end if;
+ --====================================================================================
+ when S_WAIT_PA_MARKER => -- wait for the marker on the "slower" port
+ --====================================================================================
+ s_ep_ctr_B.pauseSend <= '0';
+ s_sw_ctrl.blockReq <= '0';
+
+ -- marker frame on port A deteded
+ if((s_port_A_mask and rxFrameMask_i) = s_port_A_mask) then
+ s_tru_trans_state <= S_WAIT_WITH_TRANS;
+ -- stop pause
+ s_sw_ctrl.blockReq <= '1';
+ s_sw_ctrl.blockTime <= (others => '0');
+ -- send Quick Forward/Block frames
+ s_ep_ctr_A.hwframe_blk <= '1';
+ s_ep_ctr_B.hwframe_fwd <= '1';
+ -- until marker frame on port A is not detected, count rx frames of a defined priority
+ else
+ if(s_port_B_rtu_srobe = '1') then
+ s_portB_frame_cnt <= s_portB_frame_cnt+1;
+ end if;
+ end if;
+ --====================================================================================
+ when S_WAIT_WITH_TRANS => -- wait until the same number of frames is rx-ed on both ports
+ --====================================================================================
+ s_sw_ctrl.blockReq <= '0';
+ s_ep_ctr_A.hwframe_blk <= '0';
+ s_ep_ctr_B.hwframe_fwd <= '0';
+
+ -- as soon as the number of frames received on port A equals the number of frames
+ -- received on port B, transition
+ -- "+ 1" => we change before the next packet - the things is that the strobe
+ -- which increments the counter comes before the request is considered by
+ -- TRU so, instead of making some delay not to make the new TRU TAB configuration
+ -- too fast... we change configuration before the request whic is to be
+ -- handled by new configuration (we have time to change)
+ if(s_portA_frame_cnt = s_portB_frame_cnt) then
+ s_tru_trans_state <= S_TRANSITIONED;
+ tru_tab_bank_o <= '1'; -- request bank swap of TRU TAB
+
+ -- count the number of frames received on port A
+ else
+ if(s_port_A_rtu_srobe = '1') then
+ s_portA_frame_cnt <= s_portA_frame_cnt+1;
+ end if;
+ end if;
+
+ --====================================================================================
+ when S_TRANSITIONED => -- swap banks (assuming proper config in the TRU TAB)
+ --====================================================================================
+
+ -- transition: done
+ s_tru_trans_state <= S_IDLE;
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_statTransFinished <= '1';
+
+ tru_tab_bank_o <= '0';
+
+ --====================================================================================
+ when others =>
+ --====================================================================================
+ s_portA_frame_cnt <= (others => '0');
+ s_portB_frame_cnt <= (others => '0');
+ s_statTransActive <= '0';
+ s_statTransFinished <= '0';
+ s_tru_trans_state <= S_IDLE;
+
+ end case;
+
+ -- clearing of finished bit by configuration
+ if(s_statTransFinished = '1' and s_statTransActive ='1' and config_i.tcr_trans_clr = '1') then
+ s_statTransFinished <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+ statTransActive_o <= s_statTransActive;
+ statTransFinished_o <= s_statTransFinished;
+ sw_o <= s_sw_ctrl;
+ -- MUX of Port A/B control (outputs) to appropraite ports
+ EP_OUT: for i in 0 to g_num_ports-1 generate
+ ep_o(i)<= s_ep_ctr_A when (i = to_integer(unsigned(config_i.tcr_trans_port_a_id))) else
+ s_ep_ctr_B when (i = to_integer(unsigned(config_i.tcr_trans_port_b_id))) else
+ s_ep_zero;
+ end generate EP_OUT;
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_transition.vhd b/modules/wrsw_tru/tru_transition.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f1937a2c1e0f072a60adf947faf3639522091191
--- /dev/null
+++ b/modules/wrsw_tru/tru_transition.vhd
@@ -0,0 +1,188 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: marker triggered transition
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_transition.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-09-10
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: A wrapper for different implementations of transition. Here
+-- we just instantiate modules implementiong different transitions and the
+-- sellection, based on configuration, is done
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-09-05 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+-- use work.wrsw_shared_types_pkg.all; -- need this for:
+-- -- * t_tru_request
+
+-- use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+-- -- * t_rtu_vlan_tab_entry
+
+use work.wrsw_shared_types_pkg.all;
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity tru_transition is
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+
+ ------------------------------- I/F with tru_endpoint ----------------------------------
+ endpoints_i : in t_tru_endpoints;
+
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ ports_req_strobe_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+end tru_transition;
+
+architecture rtl of tru_transition is
+
+ constant c_trans_mode_num_max : integer := 16;
+
+ type t_trans2tru_2array is array (c_trans_mode_num_max-1 downto 0) of t_trans2tru_array(g_num_ports - 1 downto 0);
+ type t_trans2sw_array is array (c_trans_mode_num_max-1 downto 0) of t_trans2sw;
+
+ signal s_tru_tab_bank : std_logic_vector(c_trans_mode_num_max-1 downto 0);
+ signal s_statTransActive : std_logic_vector(c_trans_mode_num_max-1 downto 0);
+ signal s_statTransFinished : std_logic_vector(c_trans_mode_num_max-1 downto 0);
+ signal s_ep_array : t_trans2tru_2array;
+ signal s_rst_n : std_logic_vector(c_trans_mode_num_max-1 downto 0);
+ signal s_sw_array : t_trans2sw_array;
+
+ signal index : integer range c_trans_mode_num_max-1 downto 0;
+begin --rtl
+
+ index <= to_integer(unsigned(config_i.tcr_trans_mode));
+
+ statTransActive_o <= s_statTransActive(index);
+ tru_tab_bank_o <= s_tru_tab_bank(index);
+ statTransFinished_o<= s_statTransFinished(index);
+ ep_o <= s_ep_array(index);
+ sw_o <= s_sw_array(index);
+
+ -- a big and nasty MUX between different modules
+
+ G_RST_N: for i in 0 to c_trans_mode_num_max-1 generate
+ s_rst_n(i) <= rst_n_i when (i = index) else '0';
+ end generate G_RST_N;
+
+ TRANS_MARKER_TRIG: tru_trans_marker_trig
+ generic map(
+ g_num_ports => g_num_ports,
+ g_mt_trans_max_fr_cnt => g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => s_rst_n(0),
+ rxFrameMask_i => rxFrameMask_i,
+ rtu_i => rtu_i,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ tru_tab_bank_i => tru_tab_bank_i,
+ ports_req_strobe_i => ports_req_strobe_i,
+ tru_tab_bank_o => s_tru_tab_bank(0),
+ statTransActive_o => s_statTransActive(0),
+ statTransFinished_o => s_statTransFinished(0),
+ sw_o => s_sw_array(0),
+ ep_o => s_ep_array(0)
+ );
+
+ TRANS_LACP_DIST: tru_trans_lacp_dist
+ generic map(
+ g_num_ports => g_num_ports,
+ g_mt_trans_max_fr_cnt => g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => s_rst_n(1),
+ rxFrameMask_i => rxFrameMask_i,
+ rtu_i => rtu_i,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ tru_tab_bank_i => tru_tab_bank_i,
+
+ tru_tab_bank_o => s_tru_tab_bank(1),
+ statTransActive_o => s_statTransActive(1),
+ statTransFinished_o => s_statTransFinished(1),
+ sw_o => s_sw_array(1),
+ ep_o => s_ep_array(1)
+ );
+
+ TRANS_LACP_CALECT: tru_trans_lacp_colect
+ generic map(
+ g_num_ports => g_num_ports,
+ g_mt_trans_max_fr_cnt => g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => s_rst_n(2),
+ rxFrameMask_i => rxFrameMask_i,
+ rtu_i => rtu_i,
+ endpoints_i => endpoints_i,
+ config_i => config_i,
+ tru_tab_bank_i => tru_tab_bank_i,
+
+ tru_tab_bank_o => s_tru_tab_bank(2),
+ statTransActive_o => s_statTransActive(2),
+ statTransFinished_o => s_statTransFinished(2),
+ sw_o => s_sw_array(2),
+ ep_o => s_ep_array(2)
+ );
+
+end rtl;
diff --git a/modules/wrsw_tru/tru_wbgen2_pkg.vhd b/modules/wrsw_tru/tru_wbgen2_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9f1622f9c3857a459dad6505ea72fd8a25fc86b5
--- /dev/null
+++ b/modules/wrsw_tru/tru_wbgen2_pkg.vhd
@@ -0,0 +1,174 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for Topology Resolution Unit (TRU)
+---------------------------------------------------------------------------------------
+-- File : tru_wbgen2_pkg.vhd
+-- Author : auto-generated by wbgen2 from tru_wishbone_slave.wb
+-- Created : Wed Mar 13 18:49:56 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tru_wishbone_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package tru_wbgen2_pkg is
+
+
+ -- Input registers (user design -> WB slave)
+
+ type t_tru_in_registers is record
+ gsr0_stat_bank_i : std_logic;
+ gsr0_stat_stb_up_i : std_logic_vector(23 downto 0);
+ gsr1_stat_up_i : std_logic_vector(31 downto 0);
+ tsr_trans_stat_active_i : std_logic;
+ tsr_trans_stat_finished_i : std_logic;
+ pidr_iready_i : std_logic;
+ pfdr_class_i : std_logic_vector(7 downto 0);
+ pfdr_cnt_i : std_logic_vector(15 downto 0);
+ ptrdr_ging_mask_i : std_logic_vector(31 downto 0);
+ end record;
+
+ constant c_tru_in_registers_init_value: t_tru_in_registers := (
+ gsr0_stat_bank_i => '0',
+ gsr0_stat_stb_up_i => (others => '0'),
+ gsr1_stat_up_i => (others => '0'),
+ tsr_trans_stat_active_i => '0',
+ tsr_trans_stat_finished_i => '0',
+ pidr_iready_i => '0',
+ pfdr_class_i => (others => '0'),
+ pfdr_cnt_i => (others => '0'),
+ ptrdr_ging_mask_i => (others => '0')
+ );
+
+ -- Output registers (WB slave -> user design)
+
+ type t_tru_out_registers is record
+ gcr_g_ena_o : std_logic;
+ gcr_tru_bank_o : std_logic;
+ gcr_rx_frame_reset_o : std_logic_vector(23 downto 0);
+ mcr_pattern_mode_rep_o : std_logic_vector(3 downto 0);
+ mcr_pattern_mode_add_o : std_logic_vector(3 downto 0);
+ mcr_pattern_mode_sub_o : std_logic_vector(3 downto 0);
+ lacr_agg_df_hp_id_o : std_logic_vector(3 downto 0);
+ lacr_agg_df_br_id_o : std_logic_vector(3 downto 0);
+ lacr_agg_df_un_id_o : std_logic_vector(3 downto 0);
+ tcgr_trans_ena_o : std_logic;
+ tcgr_trans_clear_o : std_logic;
+ tcgr_trans_mode_o : std_logic_vector(2 downto 0);
+ tcgr_trans_rx_id_o : std_logic_vector(2 downto 0);
+ tcgr_trans_prio_o : std_logic_vector(2 downto 0);
+ tcgr_trans_prio_mode_o : std_logic;
+ tcpbr_trans_pause_time_o : std_logic_vector(15 downto 0);
+ tcpbr_trans_block_time_o : std_logic_vector(15 downto 0);
+ tcpr_trans_port_a_id_o : std_logic_vector(5 downto 0);
+ tcpr_trans_port_a_valid_o : std_logic;
+ tcpr_trans_port_b_id_o : std_logic_vector(5 downto 0);
+ tcpr_trans_port_b_valid_o : std_logic;
+ rtrcr_rtr_ena_o : std_logic;
+ rtrcr_rtr_reset_o : std_logic;
+ rtrcr_rtr_mode_o : std_logic_vector(3 downto 0);
+ rtrcr_rtr_rx_o : std_logic_vector(3 downto 0);
+ rtrcr_rtr_tx_o : std_logic_vector(3 downto 0);
+ hwfc_rx_fwd_id_o : std_logic_vector(3 downto 0);
+ hwfc_rx_blk_id_o : std_logic_vector(3 downto 0);
+ hwfc_tx_fwd_id_o : std_logic_vector(3 downto 0);
+ hwfc_tx_blk_id_o : std_logic_vector(3 downto 0);
+ hwfc_tx_fwd_ub_o : std_logic_vector(7 downto 0);
+ hwfc_tx_blk_ub_o : std_logic_vector(7 downto 0);
+ ttr0_fid_o : std_logic_vector(7 downto 0);
+ ttr0_sub_fid_o : std_logic_vector(7 downto 0);
+ ttr0_update_o : std_logic;
+ ttr0_mask_valid_o : std_logic;
+ ttr0_patrn_mode_o : std_logic_vector(3 downto 0);
+ ttr1_ports_ingress_o : std_logic_vector(31 downto 0);
+ ttr2_ports_egress_o : std_logic_vector(31 downto 0);
+ ttr3_ports_mask_o : std_logic_vector(31 downto 0);
+ ttr4_patrn_match_o : std_logic_vector(31 downto 0);
+ ttr5_patrn_mask_o : std_logic_vector(31 downto 0);
+ dps_pid_o : std_logic_vector(7 downto 0);
+ pidr_inject_o : std_logic;
+ pidr_psel_o : std_logic_vector(2 downto 0);
+ pidr_uval_o : std_logic_vector(15 downto 0);
+ pfdr_clr_o : std_logic;
+ end record;
+
+ constant c_tru_out_registers_init_value: t_tru_out_registers := (
+ gcr_g_ena_o => '0',
+ gcr_tru_bank_o => '0',
+ gcr_rx_frame_reset_o => (others => '0'),
+ mcr_pattern_mode_rep_o => (others => '0'),
+ mcr_pattern_mode_add_o => (others => '0'),
+ mcr_pattern_mode_sub_o => (others => '0'),
+ lacr_agg_df_hp_id_o => (others => '0'),
+ lacr_agg_df_br_id_o => (others => '0'),
+ lacr_agg_df_un_id_o => (others => '0'),
+ tcgr_trans_ena_o => '0',
+ tcgr_trans_clear_o => '0',
+ tcgr_trans_mode_o => (others => '0'),
+ tcgr_trans_rx_id_o => (others => '0'),
+ tcgr_trans_prio_o => (others => '0'),
+ tcgr_trans_prio_mode_o => '0',
+ tcpbr_trans_pause_time_o => (others => '0'),
+ tcpbr_trans_block_time_o => (others => '0'),
+ tcpr_trans_port_a_id_o => (others => '0'),
+ tcpr_trans_port_a_valid_o => '0',
+ tcpr_trans_port_b_id_o => (others => '0'),
+ tcpr_trans_port_b_valid_o => '0',
+ rtrcr_rtr_ena_o => '0',
+ rtrcr_rtr_reset_o => '0',
+ rtrcr_rtr_mode_o => (others => '0'),
+ rtrcr_rtr_rx_o => (others => '0'),
+ rtrcr_rtr_tx_o => (others => '0'),
+ hwfc_rx_fwd_id_o => (others => '0'),
+ hwfc_rx_blk_id_o => (others => '0'),
+ hwfc_tx_fwd_id_o => (others => '0'),
+ hwfc_tx_blk_id_o => (others => '0'),
+ hwfc_tx_fwd_ub_o => (others => '0'),
+ hwfc_tx_blk_ub_o => (others => '0'),
+ ttr0_fid_o => (others => '0'),
+ ttr0_sub_fid_o => (others => '0'),
+ ttr0_update_o => '0',
+ ttr0_mask_valid_o => '0',
+ ttr0_patrn_mode_o => (others => '0'),
+ ttr1_ports_ingress_o => (others => '0'),
+ ttr2_ports_egress_o => (others => '0'),
+ ttr3_ports_mask_o => (others => '0'),
+ ttr4_patrn_match_o => (others => '0'),
+ ttr5_patrn_mask_o => (others => '0'),
+ dps_pid_o => (others => '0'),
+ pidr_inject_o => '0',
+ pidr_psel_o => (others => '0'),
+ pidr_uval_o => (others => '0'),
+ pfdr_clr_o => '0'
+ );
+ function "or" (left, right: t_tru_in_registers) return t_tru_in_registers;
+ function f_x_to_zero (x:std_logic) return std_logic;
+end package;
+
+package body tru_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if;
+end function;
+function "or" (left, right: t_tru_in_registers) return t_tru_in_registers is
+variable tmp: t_tru_in_registers;
+begin
+tmp.gsr0_stat_bank_i := left.gsr0_stat_bank_i or right.gsr0_stat_bank_i;
+tmp.gsr0_stat_stb_up_i := left.gsr0_stat_stb_up_i or right.gsr0_stat_stb_up_i;
+tmp.gsr1_stat_up_i := left.gsr1_stat_up_i or right.gsr1_stat_up_i;
+tmp.tsr_trans_stat_active_i := left.tsr_trans_stat_active_i or right.tsr_trans_stat_active_i;
+tmp.tsr_trans_stat_finished_i := left.tsr_trans_stat_finished_i or right.tsr_trans_stat_finished_i;
+tmp.pidr_iready_i := left.pidr_iready_i or right.pidr_iready_i;
+tmp.pfdr_class_i := left.pfdr_class_i or right.pfdr_class_i;
+tmp.pfdr_cnt_i := left.pfdr_cnt_i or right.pfdr_cnt_i;
+tmp.ptrdr_ging_mask_i := left.ptrdr_ging_mask_i or right.ptrdr_ging_mask_i;
+return tmp;
+end function;
+end package body;
diff --git a/modules/wrsw_tru/tru_wishbone_slave.html b/modules/wrsw_tru/tru_wishbone_slave.html
new file mode 100644
index 0000000000000000000000000000000000000000..74ea3f9cf03cc091fc51d9ee406ea0530b37f769
--- /dev/null
+++ b/modules/wrsw_tru/tru_wishbone_slave.html
@@ -0,0 +1,7688 @@
+<HTML>
+<HEAD>
+<TITLE>tru_wishbone_slave</TITLE>
+<STYLE TYPE="text/css" MEDIA="all">
+
+ <!--
+ BODY { background: white; color: black;
+ font-family: Arial,Helvetica; font-size:12; }
+ h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
+ h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
+ h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
+ .td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
+ .td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
+ .td_code { font-family:Courier New,Courier; padding: 3px; }
+ .td_desc { padding: 3px; }
+ .td_sym_center { background: #e0e0f0; padding: 3px; }
+ .td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
+ .td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
+ .td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
+ .td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
+ .td_field { background: #e0e0f0; padding: 3px; text-align:center; }
+ .td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
+ th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
+ .tr_even { background: #f0eff0; }
+ .tr_odd { background: #e0e0f0; }
+ -->
+</STYLE>
+</HEAD>
+<BODY>
+<h1 class="heading">tru_wishbone_slave</h1>
+<h3>Topology Resolution Unit (TRU)</h3>
+<p></p>
+<h3>Contents:</h3>
+<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
+<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
+<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
+<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">TRU Global Control Register</a></span><br/>
+<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">TRU Global Status Register 0</a></span><br/>
+<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">TRU Global Status Register 1</a></span><br/>
+<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Pattern Control Register</a></span><br/>
+<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Link Aggregation Control Register</a></span><br/>
+<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Transition Control General Register</a></span><br/>
+<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Transition Control PAUSE/Block Register</a></span><br/>
+<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Transition Control Port Register</a></span><br/>
+<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Transition Status Register</a></span><br/>
+<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Real Time Reconfiguration Control Register</a></span><br/>
+<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">HW-frame gen/det config</a></span><br/>
+<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">TRU Table Register 0</a></span><br/>
+<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">TRU Table Register 1</a></span><br/>
+<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">TRU Table Register 2</a></span><br/>
+<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">TRU Table Register 3</a></span><br/>
+<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">TRU Table Register 4</a></span><br/>
+<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">TRU Table Register 5</a></span><br/>
+<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Debug port select</a></span><br/>
+<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Packet Injection Debug Register</a></span><br/>
+<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Packet Filter Debug Register</a></span><br/>
+<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">RT Reconfig Debug Register</a></span><br/>
+<h3><a name="sect_1_0">1. Memory map summary</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<th >
+H/W Address
+</th>
+<th >
+Type
+</th>
+<th >
+Name
+</th>
+<th >
+VHDL/Verilog prefix
+</th>
+<th >
+C prefix
+</th>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x0
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#GCR">TRU Global Control Register</a>
+</td>
+<td class="td_code">
+tru_gcr
+</td>
+<td class="td_code">
+GCR
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x1
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#GSR0">TRU Global Status Register 0</a>
+</td>
+<td class="td_code">
+tru_gsr0
+</td>
+<td class="td_code">
+GSR0
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x2
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#GSR1">TRU Global Status Register 1</a>
+</td>
+<td class="td_code">
+tru_gsr1
+</td>
+<td class="td_code">
+GSR1
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x3
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#MCR">Pattern Control Register</a>
+</td>
+<td class="td_code">
+tru_mcr
+</td>
+<td class="td_code">
+MCR
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x4
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#LACR">Link Aggregation Control Register</a>
+</td>
+<td class="td_code">
+tru_lacr
+</td>
+<td class="td_code">
+LACR
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x5
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TCGR">Transition Control General Register</a>
+</td>
+<td class="td_code">
+tru_tcgr
+</td>
+<td class="td_code">
+TCGR
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x6
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TCPBR">Transition Control PAUSE/Block Register</a>
+</td>
+<td class="td_code">
+tru_tcpbr
+</td>
+<td class="td_code">
+TCPBR
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x7
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TCPR">Transition Control Port Register</a>
+</td>
+<td class="td_code">
+tru_tcpr
+</td>
+<td class="td_code">
+TCPR
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x8
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TSR">Transition Status Register</a>
+</td>
+<td class="td_code">
+tru_tsr
+</td>
+<td class="td_code">
+TSR
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x9
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#RTRCR">Real Time Reconfiguration Control Register</a>
+</td>
+<td class="td_code">
+tru_rtrcr
+</td>
+<td class="td_code">
+RTRCR
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0xa
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#HWFC">HW-frame gen/det config</a>
+</td>
+<td class="td_code">
+tru_hwfc
+</td>
+<td class="td_code">
+HWFC
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0xb
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TTR0">TRU Table Register 0</a>
+</td>
+<td class="td_code">
+tru_ttr0
+</td>
+<td class="td_code">
+TTR0
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0xc
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TTR1">TRU Table Register 1</a>
+</td>
+<td class="td_code">
+tru_ttr1
+</td>
+<td class="td_code">
+TTR1
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0xd
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TTR2">TRU Table Register 2</a>
+</td>
+<td class="td_code">
+tru_ttr2
+</td>
+<td class="td_code">
+TTR2
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0xe
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TTR3">TRU Table Register 3</a>
+</td>
+<td class="td_code">
+tru_ttr3
+</td>
+<td class="td_code">
+TTR3
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0xf
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TTR4">TRU Table Register 4</a>
+</td>
+<td class="td_code">
+tru_ttr4
+</td>
+<td class="td_code">
+TTR4
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x10
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#TTR5">TRU Table Register 5</a>
+</td>
+<td class="td_code">
+tru_ttr5
+</td>
+<td class="td_code">
+TTR5
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x11
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#DPS">Debug port select</a>
+</td>
+<td class="td_code">
+tru_dps
+</td>
+<td class="td_code">
+DPS
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x12
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#PIDR">Packet Injection Debug Register</a>
+</td>
+<td class="td_code">
+tru_pidr
+</td>
+<td class="td_code">
+PIDR
+</td>
+</tr>
+<tr class="tr_even">
+<td class="td_code">
+0x13
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#PFDR">Packet Filter Debug Register</a>
+</td>
+<td class="td_code">
+tru_pfdr
+</td>
+<td class="td_code">
+PFDR
+</td>
+</tr>
+<tr class="tr_odd">
+<td class="td_code">
+0x14
+</td>
+<td >
+REG
+</td>
+<td >
+<A href="#PTRDR">RT Reconfig Debug Register</a>
+</td>
+<td class="td_code">
+tru_ptrdr
+</td>
+<td class="td_code">
+PTRDR
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_2_0">2. HDL symbol</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+rst_n_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Global Control Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_clk_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_gcr_g_ena_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇒
+</td>
+<td class="td_pblock_left">
+wb_addr_i[4:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_gcr_tru_bank_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇒
+</td>
+<td class="td_pblock_left">
+wb_data_i[31:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_gcr_rx_frame_reset_o[23:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇐
+</td>
+<td class="td_pblock_left">
+wb_data_o[31:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_cyc_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Global Status Register 0:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+⇒
+</td>
+<td class="td_pblock_left">
+wb_sel_i[3:0]
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_gsr0_stat_bank_i
+</td>
+<td class="td_arrow_right">
+←
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_stb_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_gsr0_stat_stb_up_i[23:0]
+</td>
+<td class="td_arrow_right">
+⇐
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+→
+</td>
+<td class="td_pblock_left">
+wb_we_i
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+←
+</td>
+<td class="td_pblock_left">
+wb_ack_o
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Global Status Register 1:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_gsr1_stat_up_i[31:0]
+</td>
+<td class="td_arrow_right">
+⇐
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Pattern Control Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_mcr_pattern_mode_rep_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_mcr_pattern_mode_add_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_mcr_pattern_mode_sub_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Link Aggregation Control Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_lacr_agg_df_hp_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_lacr_agg_df_br_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_lacr_agg_df_un_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Transition Control General Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcgr_trans_ena_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcgr_trans_clear_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcgr_trans_mode_o[2:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcgr_trans_rx_id_o[2:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcgr_trans_prio_o[2:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcgr_trans_prio_mode_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Transition Control PAUSE/Block Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcpbr_trans_pause_time_o[15:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcpbr_trans_block_time_o[15:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Transition Control Port Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcpr_trans_port_a_id_o[5:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcpr_trans_port_a_valid_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcpr_trans_port_b_id_o[5:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tcpr_trans_port_b_valid_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Transition Status Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tsr_trans_stat_active_i
+</td>
+<td class="td_arrow_right">
+←
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_tsr_trans_stat_finished_i
+</td>
+<td class="td_arrow_right">
+←
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Real Time Reconfiguration Control Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_rtrcr_rtr_ena_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_rtrcr_rtr_reset_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_rtrcr_rtr_mode_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_rtrcr_rtr_rx_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_rtrcr_rtr_tx_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>HW-frame gen/det config:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_hwfc_rx_fwd_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_hwfc_rx_blk_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_hwfc_tx_fwd_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_hwfc_tx_blk_id_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_hwfc_tx_fwd_ub_o[7:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_hwfc_tx_blk_ub_o[7:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Table Register 0:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr0_fid_o[7:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr0_sub_fid_o[7:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr0_update_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr0_mask_valid_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr0_patrn_mode_o[3:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Table Register 1:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr1_ports_ingress_o[31:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Table Register 2:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr2_ports_egress_o[31:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Table Register 3:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr3_ports_mask_o[31:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Table Register 4:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr4_patrn_match_o[31:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>TRU Table Register 5:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ttr5_patrn_mask_o[31:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Debug port select:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_dps_pid_o[7:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Packet Injection Debug Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pidr_inject_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pidr_psel_o[2:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pidr_uval_o[15:0]
+</td>
+<td class="td_arrow_right">
+⇒
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pidr_iready_i
+</td>
+<td class="td_arrow_right">
+←
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>Packet Filter Debug Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pfdr_clr_o
+</td>
+<td class="td_arrow_right">
+→
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pfdr_class_i[7:0]
+</td>
+<td class="td_arrow_right">
+⇐
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_pfdr_cnt_i[15:0]
+</td>
+<td class="td_arrow_right">
+⇐
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+<b>RT Reconfig Debug Register:</b>
+</td>
+<td class="td_arrow_right">
+
+</td>
+</tr>
+<tr>
+<td class="td_arrow_left">
+
+</td>
+<td class="td_pblock_left">
+
+</td>
+<td class="td_sym_center">
+
+</td>
+<td class="td_pblock_right">
+tru_ptrdr_ging_mask_i[31:0]
+</td>
+<td class="td_arrow_right">
+⇐
+</td>
+</tr>
+</table>
+
+<h3><a name="sect_3_0">3. Register description</a></h3>
+<a name="GCR"></a>
+<h3><a name="sect_3_1">3.1. TRU Global Control Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_gcr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x0
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+GCR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x0
+</td>
+</tr>
+</table>
+<p>
+Control register containing global (port-independent) settings of the TRU.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+RX_FRAME_RESET[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+RX_FRAME_RESET[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+RX_FRAME_RESET[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRU_BANK
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+G_ENA
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+G_ENA
+</b>[<i>read/write</i>]: TRU Global Enable
+<br>Global TRU enable bit. Overrides all port settings.<br> 0: RTU is disabled. All packets are dropped.<br> 1: RTU is enabled.
+<li><b>
+TRU_BANK
+</b>[<i>write-only</i>]: Swap TRU TAB bank
+<br>write 1: swaps the active bank of the VLAN TAB (writing to TRU TAB affects<br> inactive bank, only swapping the banks causes the written data to be activated<br> write 0: no effect
+<li><b>
+RX_FRAME_RESET
+</b>[<i>read/write</i>]: Rx Frame Reset
+<br>Resets information about filtered frames received on<br> a port
+</ul>
+<a name="GSR0"></a>
+<h3><a name="sect_3_2">3.2. TRU Global Status Register 0</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_gsr0
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x1
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+GSR0
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x4
+</td>
+</tr>
+</table>
+<p>
+Provides status of TRU actions
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_STB_UP[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_STB_UP[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_STB_UP[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+STAT_BANK
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+STAT_BANK
+</b>[<i>read-only</i>]: Active Bank
+<br>Indicates active bank in the TRU TAB
+<li><b>
+STAT_STB_UP
+</b>[<i>read-only</i>]: Stable Ports UP
+<br>Indicates stable ports which are up (0=down, 1=up)
+</ul>
+<a name="GSR1"></a>
+<h3><a name="sect_3_3">3.3. TRU Global Status Register 1</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_gsr1
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x2
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+GSR1
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x8
+</td>
+</tr>
+</table>
+<p>
+Provides status of TRU actions
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_UP[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_UP[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_UP[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+STAT_UP[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+STAT_UP
+</b>[<i>read-only</i>]: Ports UP
+<br>Indicates ports which are up (0=down, 1=up)
+</ul>
+<a name="MCR"></a>
+<h3><a name="sect_3_4">3.4. Pattern Control Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_mcr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x3
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+MCR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0xc
+</td>
+</tr>
+</table>
+<p>
+Defines matching pattern mode/configuration for quick port reconfiguration
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+PATTERN_MODE_SUB[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+PATTERN_MODE_ADD[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+PATTERN_MODE_REP[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PATTERN_MODE_REP
+</b>[<i>read/write</i>]: Replace Pattern Mode
+<br>Selected Pattern Mode for port config replacement
+<li><b>
+PATTERN_MODE_ADD
+</b>[<i>read/write</i>]: Addition Pattern Mode
+<br>Selected Pattern Mode for port config addition
+<li><b>
+PATTERN_MODE_SUB
+</b>[<i>read/write</i>]: Substraction Pattern Mode
+<br>Selected Pattern Mode for port config substraction
+</ul>
+<a name="LACR"></a>
+<h3><a name="sect_3_5">3.5. Link Aggregation Control Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_lacr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x4
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+LACR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x10
+</td>
+</tr>
+</table>
+<p>
+Enables configuration of Link Aggregation distribution functions for each kind of traffic.<br> Available functions:<br> 0: based on pclass detected by Packet Filter (need proper pFilter config)<br> 1: based on destination MAC address (bits 6 and 7)<br> 2: based on source MAC address (bits 6 and 7)
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+AGG_DF_UN_ID[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+AGG_DF_BR_ID[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+AGG_DF_HP_ID[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+AGG_DF_HP_ID
+</b>[<i>read/write</i>]: HP traffic Distribution Function ID
+<br>ID of Aggregation Distribution Function for HP traffic (value of 0 recommended, requires proper pFilter config)
+<li><b>
+AGG_DF_BR_ID
+</b>[<i>read/write</i>]: Broadcast Distribution Function ID
+<br>ID of Aggregation Distribution Function for broadcast traffic (value of 2 recommended)
+<li><b>
+AGG_DF_UN_ID
+</b>[<i>read/write</i>]: Unicast Distribution Function ID
+<br>ID of Aggregation Distribution Function for unicast traffic
+</ul>
+<a name="TCGR"></a>
+<h3><a name="sect_3_6">3.6. Transition Control General Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_tcgr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x5
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TCGR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x14
+</td>
+</tr>
+</table>
+<p>
+Defines transition mode/configuration for slow port reconfiguration - decides<br> when two swap banks such that HP packets are not lost.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_PRIO_MODE
+</td>
+<td style="border: solid 1px black;" colspan=3 class="td_field">
+TRANS_PRIO[2:0]
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=3 class="td_field">
+TRANS_RX_ID[2:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=3 class="td_field">
+TRANS_MODE[2:0]
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_CLEAR
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_ENA
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+TRANS_ENA
+</b>[<i>read/write</i>]: Transition Enabled
+<br>Enables/disables transition
+<li><b>
+TRANS_CLEAR
+</b>[<i>read/write</i>]: Transition Clear
+<br>Writing 1 clears >Transition Finished< bit so that new transition can be <br> performed. No new transition will be started until >Transition Finished< is cleared
+<li><b>
+TRANS_MODE
+</b>[<i>read/write</i>]: Transition Mode
+<br>Selected Transitin Mode for port re-config
+<li><b>
+TRANS_RX_ID
+</b>[<i>read/write</i>]: Rx Detected Frame ID
+<br>Base transition on detection of the frame which is parsed into provided CLASS ID
+<li><b>
+TRANS_PRIO
+</b>[<i>read/write</i>]: Priority
+<br>Indicates at which traffic priority the transition attempts not to loose <br> frames
+<li><b>
+TRANS_PRIO_MODE
+</b>[<i>read/write</i>]: Priority Mode
+<br>Specifies whether<br> - 0: use indication of HP packet from RTU (fast match)<br> - 1: use the priority specified in TRANS_PRIO register<br> to count packets during transition
+</ul>
+<a name="TCPBR"></a>
+<h3><a name="sect_3_7">3.7. Transition Control PAUSE/Block Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_tcpbr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x6
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TCPBR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x18
+</td>
+</tr>
+</table>
+<p>
+Defines transition mode/configuration for slow port reconfiguration - decides<br> when two swap banks such that HP packets are not lost.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+TRANS_BLOCK_TIME[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+TRANS_BLOCK_TIME[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+TRANS_PAUSE_TIME[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+TRANS_PAUSE_TIME[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+TRANS_PAUSE_TIME
+</b>[<i>read/write</i>]: PAUSE Time
+<br>Time (quanta) send in hw-generated PAUSE message to the link partner (port B) to block the traffic on configured priority
+<li><b>
+TRANS_BLOCK_TIME
+</b>[<i>read/write</i>]: Output Block Time
+<br>Time (quanta) for which output queues of both ports (A and B) are blocked for configured priority
+</ul>
+<a name="TCPR"></a>
+<h3><a name="sect_3_8">3.8. Transition Control Port Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_tcpr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x7
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TCPR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x1c
+</td>
+</tr>
+</table>
+<p>
+Defines transition mode/configuration for slow port reconfiguration - decides<br> when two swap banks such that HP packets are not lost.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_PORT_B_VALID
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=6 class="td_field">
+TRANS_PORT_B_ID[5:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_PORT_A_VALID
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=6 class="td_field">
+TRANS_PORT_A_ID[5:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+TRANS_PORT_A_ID
+</b>[<i>read/write</i>]: Port A ID
+<br>Configuration of port A (PORT ID)
+<li><b>
+TRANS_PORT_A_VALID
+</b>[<i>read/write</i>]: Port A Valid
+<br>Configuration of port A (valid bit)
+<li><b>
+TRANS_PORT_B_ID
+</b>[<i>read/write</i>]: Port B ID
+<br>Configuration of port B (PORT ID)
+<li><b>
+TRANS_PORT_B_VALID
+</b>[<i>read/write</i>]: Port B Valid
+<br>Configuration of port B (valid bit)
+</ul>
+<a name="TSR"></a>
+<h3><a name="sect_3_9">3.9. Transition Status Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_tsr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x8
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TSR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x20
+</td>
+</tr>
+</table>
+<p>
+Provides information about the state of transition (if any).
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_STAT_FINISHED
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+TRANS_STAT_ACTIVE
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+TRANS_STAT_ACTIVE
+</b>[<i>read-only</i>]: Transition Active
+<br>Indicates that transition is active
+<li><b>
+TRANS_STAT_FINISHED
+</b>[<i>read-only</i>]: Transition Finished
+<br>Indicates that transition has been finished
+</ul>
+<a name="RTRCR"></a>
+<h3><a name="sect_3_10">3.10. Real Time Reconfiguration Control Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_rtrcr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x9
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+RTRCR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x24
+</td>
+</tr>
+</table>
+<p>
+Controls Real Time Handler.
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+RTR_TX[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+RTR_RX[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+RTR_MODE[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+RTR_RESET
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+RTR_ENA
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+RTR_ENA
+</b>[<i>read/write</i>]: RTR Enabled
+<br>Enables Real Time Reconfiguration Handler
+<li><b>
+RTR_RESET
+</b>[<i>read/write</i>]: RTR Reset
+<br>Resets Real Time Reconfiguration Handler
+<li><b>
+RTR_MODE
+</b>[<i>read/write</i>]: RTR Handler Mode
+<br>Selected Real Time Reconfig Handler Mode
+<li><b>
+RTR_RX
+</b>[<i>read/write</i>]: RTR Rx Frame ID
+<br> ID (bit number of the rxFrameMask) of the signal from the endpoint which <br> is programmed to indicate reception of Quick Forward Request BPDUe
+<li><b>
+RTR_TX
+</b>[<i>read/write</i>]: RTR Tx Frame ID
+<br> ID (bit number of the txFrameMask) of the HW-sent frame by endpoint<br> (Quick Forward Request BPDUe)
+</ul>
+<a name="HWFC"></a>
+<h3><a name="sect_3_11">3.11. HW-frame gen/det config</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_hwfc
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0xa
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+HWFC
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x28
+</td>
+</tr>
+</table>
+<p>
+Controls HW generation/detection of frames
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+TX_BLK_UB[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+TX_FWD_UB[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+TX_BLK_ID[3:0]
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+TX_FWD_ID[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+RX_BLK_ID[3:0]
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+RX_FWD_ID[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+RX_FWD_ID
+</b>[<i>read/write</i>]: HW Frame Rx Forward ID
+<br> ID (bit number of the rxFrameMask) of the signal from the endpoint which <br> is programmed to indicate reception of Quick Forward Request BPDUe
+<li><b>
+RX_BLK_ID
+</b>[<i>read/write</i>]: HW Frame Rx Block ID
+<br> ID (bit number of the rxFrameMask) of the signal from the endpoint which <br> is programmed to indicate reception of Quick Block Request BPDUe
+<li><b>
+TX_FWD_ID
+</b>[<i>read/write</i>]: HW Frame Tx Forward ID
+<br> ID (bit number of the txFrameMask) of the HW-sent frame by endpoint<br> (Quick Forward Request BPDUe)
+<li><b>
+TX_BLK_ID
+</b>[<i>read/write</i>]: HW Frame Tx Block ID
+<br> ID (bit number of the txFrameMask) of the HW-sent frame by endpoint<br> (Quick Block Request BPDUe)
+<li><b>
+TX_FWD_UB
+</b>[<i>read/write</i>]: HW Frame Tx Forward User Byte
+<br> LOW byte of the 16-bit User Defined Value inserted into tnjected Template
+<li><b>
+TX_BLK_UB
+</b>[<i>read/write</i>]: HW Frame Tx Block User Byte
+<br> LOW byte of the 16-bit User Defined Value inserted into tnjected Template
+</ul>
+<a name="TTR0"></a>
+<h3><a name="sect_3_12">3.12. TRU Table Register 0</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ttr0
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0xb
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TTR0
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x2c
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=4 class="td_field">
+PATRN_MODE[3:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+MASK_VALID
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+UPDATE
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+SUB_FID[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+FID[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+FID
+</b>[<i>read/write</i>]: Filtering Database ID
+<br>Assigns the VID to a particular filtering database
+<li><b>
+SUB_FID
+</b>[<i>read/write</i>]: ID withing Filtering Database Entry
+<br>Identifies entry within FID entry
+<li><b>
+UPDATE
+</b>[<i>write-only</i>]: Force TRU table sub-entry update
+<br>write 1: flush TTR register to inactive bank of TRU table entry at address <br> in FID+SUB_FID
+<li><b>
+MASK_VALID
+</b>[<i>read/write</i>]: Entry Valid
+<li><b>
+PATRN_MODE
+</b>[<i>read/write</i>]: Pattern Mode
+</ul>
+<a name="TTR1"></a>
+<h3><a name="sect_3_13">3.13. TRU Table Register 1</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ttr1
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0xc
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TTR1
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x30
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_INGRESS[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_INGRESS[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_INGRESS[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_INGRESS[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PORTS_INGRESS
+</b>[<i>read/write</i>]: Ingress Mask
+</ul>
+<a name="TTR2"></a>
+<h3><a name="sect_3_14">3.14. TRU Table Register 2</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ttr2
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0xd
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TTR2
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x34
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_EGRESS[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_EGRESS[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_EGRESS[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_EGRESS[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PORTS_EGRESS
+</b>[<i>read/write</i>]: Egress Mask
+</ul>
+<a name="TTR3"></a>
+<h3><a name="sect_3_15">3.15. TRU Table Register 3</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ttr3
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0xe
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TTR3
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x38
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_MASK[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_MASK[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_MASK[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PORTS_MASK[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PORTS_MASK
+</b>[<i>read/write</i>]: Egress Mask
+</ul>
+<a name="TTR4"></a>
+<h3><a name="sect_3_16">3.16. TRU Table Register 4</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ttr4
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0xf
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TTR4
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x3c
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MATCH[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MATCH[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MATCH[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MATCH[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PATRN_MATCH
+</b>[<i>read/write</i>]: Pattern Match
+</ul>
+<a name="TTR5"></a>
+<h3><a name="sect_3_17">3.17. TRU Table Register 5</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ttr5
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x10
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+TTR5
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x40
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MASK[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MASK[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MASK[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PATRN_MASK[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PATRN_MASK
+</b>[<i>read/write</i>]: Patern Mask
+</ul>
+<a name="DPS"></a>
+<h3><a name="sect_3_18">3.18. Debug port select</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_dps
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x11
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+DPS
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x44
+</td>
+</tr>
+</table>
+<p>
+Select port number for applying debugging measures in boht: <br> Packet Injection Debug Register <br> Packet Filter Debug Register
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+PID[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+PID
+</b>[<i>read/write</i>]: Port ID
+<br>ID of the port to be debugged
+</ul>
+<a name="PIDR"></a>
+<h3><a name="sect_3_19">3.19. Packet Injection Debug Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_pidr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x12
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+PIDR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x48
+</td>
+</tr>
+</table>
+<p>
+Used for debugging (ctrl/status) HW packet injection of a selected port
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+IREADY
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+UVAL[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+UVAL[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=3 class="td_field">
+PSEL[2:0]
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+INJECT
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+INJECT
+</b>[<i>write-only</i>]: Injection Request
+<li><b>
+PSEL
+</b>[<i>read/write</i>]: Packet Select
+<br>ID of the packet-template to be sent
+<li><b>
+UVAL
+</b>[<i>read/write</i>]: USER VALUE
+<br>Value to be inserted at predefined place in the injected packet
+<li><b>
+IREADY
+</b>[<i>read-only</i>]: Injection Ready
+</ul>
+<a name="PFDR"></a>
+<h3><a name="sect_3_20">3.20. Packet Filter Debug Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_pfdr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x13
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+PFDR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x4c
+</td>
+</tr>
+</table>
+<p>
+This register stores information about detected packages (class, number)
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+CNT[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+CNT[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+CLASS[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td class="td_unused">
+-
+</td>
+<td style="border: solid 1px black;" colspan=1 class="td_field">
+CLR
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+CLR
+</b>[<i>write-only</i>]: Clear register
+<br>Clears the status regs (count and class)
+<li><b>
+CLASS
+</b>[<i>read-only</i>]: Filtered class
+<br>Shows which class messages has been detected
+<li><b>
+CNT
+</b>[<i>read-only</i>]: CNT
+<br>Counts all detections (regardless of the class)
+</ul>
+<a name="PTRDR"></a>
+<h3><a name="sect_3_21">3.21. RT Reconfig Debug Register</a></h3>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td >
+<b>HW prefix: </b>
+</td>
+<td class="td_code">
+tru_ptrdr
+</td>
+</tr>
+<tr>
+<td >
+<b>HW address: </b>
+</td>
+<td class="td_code">
+0x14
+</td>
+</tr>
+<tr>
+<td >
+<b>C prefix: </b>
+</td>
+<td class="td_code">
+PTRDR
+</td>
+</tr>
+<tr>
+<td >
+<b>C offset: </b>
+</td>
+<td class="td_code">
+0x50
+</td>
+</tr>
+</table>
+<p>
+This register stores information about detected packages (class, number)
+</p>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+31
+</td>
+<td class="td_bit">
+30
+</td>
+<td class="td_bit">
+29
+</td>
+<td class="td_bit">
+28
+</td>
+<td class="td_bit">
+27
+</td>
+<td class="td_bit">
+26
+</td>
+<td class="td_bit">
+25
+</td>
+<td class="td_bit">
+24
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+GING_MASK[31:24]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+23
+</td>
+<td class="td_bit">
+22
+</td>
+<td class="td_bit">
+21
+</td>
+<td class="td_bit">
+20
+</td>
+<td class="td_bit">
+19
+</td>
+<td class="td_bit">
+18
+</td>
+<td class="td_bit">
+17
+</td>
+<td class="td_bit">
+16
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+GING_MASK[23:16]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+15
+</td>
+<td class="td_bit">
+14
+</td>
+<td class="td_bit">
+13
+</td>
+<td class="td_bit">
+12
+</td>
+<td class="td_bit">
+11
+</td>
+<td class="td_bit">
+10
+</td>
+<td class="td_bit">
+9
+</td>
+<td class="td_bit">
+8
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+GING_MASK[15:8]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<table cellpadding=0 cellspacing=0 border=0>
+<tr>
+<td class="td_bit">
+7
+</td>
+<td class="td_bit">
+6
+</td>
+<td class="td_bit">
+5
+</td>
+<td class="td_bit">
+4
+</td>
+<td class="td_bit">
+3
+</td>
+<td class="td_bit">
+2
+</td>
+<td class="td_bit">
+1
+</td>
+<td class="td_bit">
+0
+</td>
+</tr>
+<tr>
+<td style="border: solid 1px black;" colspan=8 class="td_field">
+GING_MASK[7:0]
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+<td >
+
+</td>
+</tr>
+</table>
+<ul>
+<li><b>
+GING_MASK
+</b>[<i>read-only</i>]: globalIngMask
+<br>Global Ingress Mask
+</ul>
+
+
+
+</BODY>
+</HTML>
diff --git a/modules/wrsw_tru/tru_wishbone_slave.v b/modules/wrsw_tru/tru_wishbone_slave.v
new file mode 100644
index 0000000000000000000000000000000000000000..8decbcb887c654b0870bbbd34bbbe119f63d44a3
--- /dev/null
+++ b/modules/wrsw_tru/tru_wishbone_slave.v
@@ -0,0 +1,108 @@
+`define ADDR_TRU_GCR 6'h0
+`define TRU_GCR_G_ENA_OFFSET 0
+`define TRU_GCR_G_ENA 32'h00000001
+`define TRU_GCR_TRU_BANK_OFFSET 1
+`define TRU_GCR_TRU_BANK 32'h00000002
+`define TRU_GCR_RX_FRAME_RESET_OFFSET 8
+`define TRU_GCR_RX_FRAME_RESET 32'hffffff00
+`define ADDR_TRU_GSR0 6'h4
+`define TRU_GSR0_STAT_BANK_OFFSET 0
+`define TRU_GSR0_STAT_BANK 32'h00000001
+`define TRU_GSR0_STAT_STB_UP_OFFSET 8
+`define TRU_GSR0_STAT_STB_UP 32'hffffff00
+`define ADDR_TRU_GSR1 6'h8
+`define TRU_GSR1_STAT_UP_OFFSET 0
+`define TRU_GSR1_STAT_UP 32'hffffffff
+`define ADDR_TRU_MCR 6'hc
+`define TRU_MCR_PATTERN_MODE_REP_OFFSET 0
+`define TRU_MCR_PATTERN_MODE_REP 32'h0000000f
+`define TRU_MCR_PATTERN_MODE_ADD_OFFSET 8
+`define TRU_MCR_PATTERN_MODE_ADD 32'h00000f00
+`define ADDR_TRU_LACR 6'h10
+`define TRU_LACR_AGG_GR_NUM_OFFSET 0
+`define TRU_LACR_AGG_GR_NUM 32'h0000000f
+`define TRU_LACR_AGG_DF_BR_ID_OFFSET 8
+`define TRU_LACR_AGG_DF_BR_ID 32'h00000f00
+`define TRU_LACR_AGG_DF_UN_ID_OFFSET 16
+`define TRU_LACR_AGG_DF_UN_ID 32'h000f0000
+`define ADDR_TRU_LAGT 6'h14
+`define TRU_LAGT_LAGT_GR_ID_MASK_0_OFFSET 0
+`define TRU_LAGT_LAGT_GR_ID_MASK_0 32'h0000000f
+`define TRU_LAGT_LAGT_GR_ID_MASK_1_OFFSET 4
+`define TRU_LAGT_LAGT_GR_ID_MASK_1 32'h000000f0
+`define TRU_LAGT_LAGT_GR_ID_MASK_2_OFFSET 8
+`define TRU_LAGT_LAGT_GR_ID_MASK_2 32'h00000f00
+`define TRU_LAGT_LAGT_GR_ID_MASK_3_OFFSET 12
+`define TRU_LAGT_LAGT_GR_ID_MASK_3 32'h0000f000
+`define TRU_LAGT_LAGT_GR_ID_MASK_4_OFFSET 16
+`define TRU_LAGT_LAGT_GR_ID_MASK_4 32'h000f0000
+`define TRU_LAGT_LAGT_GR_ID_MASK_5_OFFSET 20
+`define TRU_LAGT_LAGT_GR_ID_MASK_5 32'h00f00000
+`define TRU_LAGT_LAGT_GR_ID_MASK_6_OFFSET 24
+`define TRU_LAGT_LAGT_GR_ID_MASK_6 32'h0f000000
+`define TRU_LAGT_LAGT_GR_ID_MASK_7_OFFSET 28
+`define TRU_LAGT_LAGT_GR_ID_MASK_7 32'hf0000000
+`define ADDR_TRU_TCGR 6'h18
+`define TRU_TCGR_TRANS_ENA_OFFSET 0
+`define TRU_TCGR_TRANS_ENA 32'h00000001
+`define TRU_TCGR_TRANS_CLEAR_OFFSET 1
+`define TRU_TCGR_TRANS_CLEAR 32'h00000002
+`define TRU_TCGR_TRANS_MODE_OFFSET 4
+`define TRU_TCGR_TRANS_MODE 32'h00000070
+`define TRU_TCGR_TRANS_RX_ID_OFFSET 8
+`define TRU_TCGR_TRANS_RX_ID 32'h00000700
+`define TRU_TCGR_TRANS_PRIO_OFFSET 12
+`define TRU_TCGR_TRANS_PRIO 32'h00007000
+`define TRU_TCGR_TRANS_TIME_DIFF_OFFSET 16
+`define TRU_TCGR_TRANS_TIME_DIFF 32'hffff0000
+`define ADDR_TRU_TCPR 6'h1c
+`define TRU_TCPR_TRANS_PORT_A_ID_OFFSET 0
+`define TRU_TCPR_TRANS_PORT_A_ID 32'h0000003f
+`define TRU_TCPR_TRANS_PORT_A_VALID_OFFSET 8
+`define TRU_TCPR_TRANS_PORT_A_VALID 32'h00000100
+`define TRU_TCPR_TRANS_PORT_B_ID_OFFSET 16
+`define TRU_TCPR_TRANS_PORT_B_ID 32'h003f0000
+`define TRU_TCPR_TRANS_PORT_B_VALID_OFFSET 24
+`define TRU_TCPR_TRANS_PORT_B_VALID 32'h01000000
+`define ADDR_TRU_TSR 6'h20
+`define TRU_TSR_TRANS_STAT_ACTIVE_OFFSET 0
+`define TRU_TSR_TRANS_STAT_ACTIVE 32'h00000001
+`define TRU_TSR_TRANS_STAT_FINISHED_OFFSET 1
+`define TRU_TSR_TRANS_STAT_FINISHED 32'h00000002
+`define ADDR_TRU_RTRCR 6'h24
+`define TRU_RTRCR_RTR_ENA_OFFSET 0
+`define TRU_RTRCR_RTR_ENA 32'h00000001
+`define TRU_RTRCR_RTR_RESET_OFFSET 1
+`define TRU_RTRCR_RTR_RESET 32'h00000002
+`define TRU_RTRCR_RTR_MODE_OFFSET 8
+`define TRU_RTRCR_RTR_MODE 32'h00000f00
+`define TRU_RTRCR_RTR_RX_OFFSET 16
+`define TRU_RTRCR_RTR_RX 32'h000f0000
+`define TRU_RTRCR_RTR_TX_OFFSET 24
+`define TRU_RTRCR_RTR_TX 32'h0f000000
+`define ADDR_TRU_TTR0 6'h28
+`define TRU_TTR0_FID_OFFSET 0
+`define TRU_TTR0_FID 32'h000000ff
+`define TRU_TTR0_SUB_FID_OFFSET 8
+`define TRU_TTR0_SUB_FID 32'h0000ff00
+`define TRU_TTR0_UPDATE_OFFSET 16
+`define TRU_TTR0_UPDATE 32'h00010000
+`define TRU_TTR0_MASK_VALID_OFFSET 17
+`define TRU_TTR0_MASK_VALID 32'h00020000
+`define TRU_TTR0_PATRN_MODE_OFFSET 24
+`define TRU_TTR0_PATRN_MODE 32'h0f000000
+`define ADDR_TRU_TTR1 6'h2c
+`define TRU_TTR1_PORTS_INGRESS_OFFSET 0
+`define TRU_TTR1_PORTS_INGRESS 32'hffffffff
+`define ADDR_TRU_TTR2 6'h30
+`define TRU_TTR2_PORTS_EGRESS_OFFSET 0
+`define TRU_TTR2_PORTS_EGRESS 32'hffffffff
+`define ADDR_TRU_TTR3 6'h34
+`define TRU_TTR3_PORTS_MASK_OFFSET 0
+`define TRU_TTR3_PORTS_MASK 32'hffffffff
+`define ADDR_TRU_TTR4 6'h38
+`define TRU_TTR4_PATRN_MATCH_OFFSET 0
+`define TRU_TTR4_PATRN_MATCH 32'hffffffff
+`define ADDR_TRU_TTR5 6'h3c
+`define TRU_TTR5_PATRN_MASK_OFFSET 0
+`define TRU_TTR5_PATRN_MASK 32'hffffffff
diff --git a/modules/wrsw_tru/tru_wishbone_slave.vhd b/modules/wrsw_tru/tru_wishbone_slave.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..85a0e814c9b72d92715ab895550e95493834f582
--- /dev/null
+++ b/modules/wrsw_tru/tru_wishbone_slave.vhd
@@ -0,0 +1,782 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for Topology Resolution Unit (TRU)
+---------------------------------------------------------------------------------------
+-- File : tru_wishbone_slave.vhd
+-- Author : auto-generated by wbgen2 from tru_wishbone_slave.wb
+-- Created : Wed Mar 13 18:49:56 2013
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tru_wishbone_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.tru_wbgen2_pkg.all;
+
+
+entity tru_wishbone_slave is
+ port (
+ rst_n_i : in std_logic;
+ wb_clk_i : in std_logic;
+ wb_addr_i : in std_logic_vector(4 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ regs_i : in t_tru_in_registers;
+ regs_o : out t_tru_out_registers
+ );
+end tru_wishbone_slave;
+
+architecture syn of tru_wishbone_slave is
+
+signal tru_gcr_g_ena_int : std_logic ;
+signal tru_gcr_tru_bank_dly0 : std_logic ;
+signal tru_gcr_tru_bank_int : std_logic ;
+signal tru_gcr_rx_frame_reset_int : std_logic_vector(23 downto 0);
+signal tru_mcr_pattern_mode_rep_int : std_logic_vector(3 downto 0);
+signal tru_mcr_pattern_mode_add_int : std_logic_vector(3 downto 0);
+signal tru_mcr_pattern_mode_sub_int : std_logic_vector(3 downto 0);
+signal tru_lacr_agg_df_hp_id_int : std_logic_vector(3 downto 0);
+signal tru_lacr_agg_df_br_id_int : std_logic_vector(3 downto 0);
+signal tru_lacr_agg_df_un_id_int : std_logic_vector(3 downto 0);
+signal tru_tcgr_trans_ena_int : std_logic ;
+signal tru_tcgr_trans_clear_int : std_logic ;
+signal tru_tcgr_trans_mode_int : std_logic_vector(2 downto 0);
+signal tru_tcgr_trans_rx_id_int : std_logic_vector(2 downto 0);
+signal tru_tcgr_trans_prio_int : std_logic_vector(2 downto 0);
+signal tru_tcgr_trans_prio_mode_int : std_logic ;
+signal tru_tcpbr_trans_pause_time_int : std_logic_vector(15 downto 0);
+signal tru_tcpbr_trans_block_time_int : std_logic_vector(15 downto 0);
+signal tru_tcpr_trans_port_a_id_int : std_logic_vector(5 downto 0);
+signal tru_tcpr_trans_port_a_valid_int : std_logic ;
+signal tru_tcpr_trans_port_b_id_int : std_logic_vector(5 downto 0);
+signal tru_tcpr_trans_port_b_valid_int : std_logic ;
+signal tru_rtrcr_rtr_ena_int : std_logic ;
+signal tru_rtrcr_rtr_reset_int : std_logic ;
+signal tru_rtrcr_rtr_mode_int : std_logic_vector(3 downto 0);
+signal tru_rtrcr_rtr_rx_int : std_logic_vector(3 downto 0);
+signal tru_rtrcr_rtr_tx_int : std_logic_vector(3 downto 0);
+signal tru_hwfc_rx_fwd_id_int : std_logic_vector(3 downto 0);
+signal tru_hwfc_rx_blk_id_int : std_logic_vector(3 downto 0);
+signal tru_hwfc_tx_fwd_id_int : std_logic_vector(3 downto 0);
+signal tru_hwfc_tx_blk_id_int : std_logic_vector(3 downto 0);
+signal tru_hwfc_tx_fwd_ub_int : std_logic_vector(7 downto 0);
+signal tru_hwfc_tx_blk_ub_int : std_logic_vector(7 downto 0);
+signal tru_ttr0_fid_int : std_logic_vector(7 downto 0);
+signal tru_ttr0_sub_fid_int : std_logic_vector(7 downto 0);
+signal tru_ttr0_update_dly0 : std_logic ;
+signal tru_ttr0_update_int : std_logic ;
+signal tru_ttr0_mask_valid_int : std_logic ;
+signal tru_ttr0_patrn_mode_int : std_logic_vector(3 downto 0);
+signal tru_ttr1_ports_ingress_int : std_logic_vector(31 downto 0);
+signal tru_ttr2_ports_egress_int : std_logic_vector(31 downto 0);
+signal tru_ttr3_ports_mask_int : std_logic_vector(31 downto 0);
+signal tru_ttr4_patrn_match_int : std_logic_vector(31 downto 0);
+signal tru_ttr5_patrn_mask_int : std_logic_vector(31 downto 0);
+signal tru_dps_pid_int : std_logic_vector(7 downto 0);
+signal tru_pidr_inject_dly0 : std_logic ;
+signal tru_pidr_inject_int : std_logic ;
+signal tru_pidr_psel_int : std_logic_vector(2 downto 0);
+signal tru_pidr_uval_int : std_logic_vector(15 downto 0);
+signal tru_pfdr_clr_dly0 : std_logic ;
+signal tru_pfdr_clr_int : std_logic ;
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(4 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal bus_clock_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_data_i;
+ bwsel_reg <= wb_sel_i;
+ bus_clock_int <= wb_clk_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (bus_clock_int, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ tru_gcr_g_ena_int <= '0';
+ tru_gcr_tru_bank_int <= '0';
+ tru_gcr_rx_frame_reset_int <= "000000000000000000000000";
+ tru_mcr_pattern_mode_rep_int <= "0000";
+ tru_mcr_pattern_mode_add_int <= "0000";
+ tru_mcr_pattern_mode_sub_int <= "0000";
+ tru_lacr_agg_df_hp_id_int <= "0000";
+ tru_lacr_agg_df_br_id_int <= "0000";
+ tru_lacr_agg_df_un_id_int <= "0000";
+ tru_tcgr_trans_ena_int <= '0';
+ tru_tcgr_trans_clear_int <= '0';
+ tru_tcgr_trans_mode_int <= "000";
+ tru_tcgr_trans_rx_id_int <= "000";
+ tru_tcgr_trans_prio_int <= "000";
+ tru_tcgr_trans_prio_mode_int <= '0';
+ tru_tcpbr_trans_pause_time_int <= "0000000000000000";
+ tru_tcpbr_trans_block_time_int <= "0000000000000000";
+ tru_tcpr_trans_port_a_id_int <= "000000";
+ tru_tcpr_trans_port_a_valid_int <= '0';
+ tru_tcpr_trans_port_b_id_int <= "000000";
+ tru_tcpr_trans_port_b_valid_int <= '0';
+ tru_rtrcr_rtr_ena_int <= '0';
+ tru_rtrcr_rtr_reset_int <= '0';
+ tru_rtrcr_rtr_mode_int <= "0000";
+ tru_rtrcr_rtr_rx_int <= "0000";
+ tru_rtrcr_rtr_tx_int <= "0000";
+ tru_hwfc_rx_fwd_id_int <= "0000";
+ tru_hwfc_rx_blk_id_int <= "0000";
+ tru_hwfc_tx_fwd_id_int <= "0000";
+ tru_hwfc_tx_blk_id_int <= "0000";
+ tru_hwfc_tx_fwd_ub_int <= "00000000";
+ tru_hwfc_tx_blk_ub_int <= "00000000";
+ tru_ttr0_fid_int <= "00000000";
+ tru_ttr0_sub_fid_int <= "00000000";
+ tru_ttr0_update_int <= '0';
+ tru_ttr0_mask_valid_int <= '0';
+ tru_ttr0_patrn_mode_int <= "0000";
+ tru_ttr1_ports_ingress_int <= "00000000000000000000000000000000";
+ tru_ttr2_ports_egress_int <= "00000000000000000000000000000000";
+ tru_ttr3_ports_mask_int <= "00000000000000000000000000000000";
+ tru_ttr4_patrn_match_int <= "00000000000000000000000000000000";
+ tru_ttr5_patrn_mask_int <= "00000000000000000000000000000000";
+ tru_dps_pid_int <= "00000000";
+ tru_pidr_inject_int <= '0';
+ tru_pidr_psel_int <= "000";
+ tru_pidr_uval_int <= "0000000000000000";
+ tru_pfdr_clr_int <= '0';
+ elsif rising_edge(bus_clock_int) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ tru_gcr_tru_bank_int <= '0';
+ tru_ttr0_update_int <= '0';
+ tru_pidr_inject_int <= '0';
+ tru_pfdr_clr_int <= '0';
+ ack_in_progress <= '0';
+ else
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(4 downto 0) is
+ when "00000" =>
+ if (wb_we_i = '1') then
+ rddata_reg(0) <= 'X';
+ tru_gcr_g_ena_int <= wrdata_reg(0);
+ tru_gcr_tru_bank_int <= wrdata_reg(1);
+ rddata_reg(1) <= 'X';
+ tru_gcr_rx_frame_reset_int <= wrdata_reg(31 downto 8);
+ else
+ rddata_reg(0) <= tru_gcr_g_ena_int;
+ rddata_reg(1) <= 'X';
+ rddata_reg(31 downto 8) <= tru_gcr_rx_frame_reset_int;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ end if;
+ ack_sreg(2) <= '1';
+ ack_in_progress <= '1';
+ when "00001" =>
+ if (wb_we_i = '1') then
+ rddata_reg(0) <= 'X';
+ else
+ rddata_reg(0) <= regs_i.gsr0_stat_bank_i;
+ rddata_reg(31 downto 8) <= regs_i.gsr0_stat_stb_up_i;
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00010" =>
+ if (wb_we_i = '1') then
+ else
+ rddata_reg(31 downto 0) <= regs_i.gsr1_stat_up_i;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00011" =>
+ if (wb_we_i = '1') then
+ tru_mcr_pattern_mode_rep_int <= wrdata_reg(3 downto 0);
+ tru_mcr_pattern_mode_add_int <= wrdata_reg(11 downto 8);
+ tru_mcr_pattern_mode_sub_int <= wrdata_reg(19 downto 16);
+ else
+ rddata_reg(3 downto 0) <= tru_mcr_pattern_mode_rep_int;
+ rddata_reg(11 downto 8) <= tru_mcr_pattern_mode_add_int;
+ rddata_reg(19 downto 16) <= tru_mcr_pattern_mode_sub_int;
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00100" =>
+ if (wb_we_i = '1') then
+ tru_lacr_agg_df_hp_id_int <= wrdata_reg(3 downto 0);
+ tru_lacr_agg_df_br_id_int <= wrdata_reg(11 downto 8);
+ tru_lacr_agg_df_un_id_int <= wrdata_reg(19 downto 16);
+ else
+ rddata_reg(3 downto 0) <= tru_lacr_agg_df_hp_id_int;
+ rddata_reg(11 downto 8) <= tru_lacr_agg_df_br_id_int;
+ rddata_reg(19 downto 16) <= tru_lacr_agg_df_un_id_int;
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00101" =>
+ if (wb_we_i = '1') then
+ rddata_reg(0) <= 'X';
+ tru_tcgr_trans_ena_int <= wrdata_reg(0);
+ rddata_reg(1) <= 'X';
+ tru_tcgr_trans_clear_int <= wrdata_reg(1);
+ tru_tcgr_trans_mode_int <= wrdata_reg(6 downto 4);
+ tru_tcgr_trans_rx_id_int <= wrdata_reg(10 downto 8);
+ tru_tcgr_trans_prio_int <= wrdata_reg(14 downto 12);
+ rddata_reg(15) <= 'X';
+ tru_tcgr_trans_prio_mode_int <= wrdata_reg(15);
+ else
+ rddata_reg(0) <= tru_tcgr_trans_ena_int;
+ rddata_reg(1) <= tru_tcgr_trans_clear_int;
+ rddata_reg(6 downto 4) <= tru_tcgr_trans_mode_int;
+ rddata_reg(10 downto 8) <= tru_tcgr_trans_rx_id_int;
+ rddata_reg(14 downto 12) <= tru_tcgr_trans_prio_int;
+ rddata_reg(15) <= tru_tcgr_trans_prio_mode_int;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00110" =>
+ if (wb_we_i = '1') then
+ tru_tcpbr_trans_pause_time_int <= wrdata_reg(15 downto 0);
+ tru_tcpbr_trans_block_time_int <= wrdata_reg(31 downto 16);
+ else
+ rddata_reg(15 downto 0) <= tru_tcpbr_trans_pause_time_int;
+ rddata_reg(31 downto 16) <= tru_tcpbr_trans_block_time_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "00111" =>
+ if (wb_we_i = '1') then
+ tru_tcpr_trans_port_a_id_int <= wrdata_reg(5 downto 0);
+ rddata_reg(8) <= 'X';
+ tru_tcpr_trans_port_a_valid_int <= wrdata_reg(8);
+ tru_tcpr_trans_port_b_id_int <= wrdata_reg(21 downto 16);
+ rddata_reg(24) <= 'X';
+ tru_tcpr_trans_port_b_valid_int <= wrdata_reg(24);
+ else
+ rddata_reg(5 downto 0) <= tru_tcpr_trans_port_a_id_int;
+ rddata_reg(8) <= tru_tcpr_trans_port_a_valid_int;
+ rddata_reg(21 downto 16) <= tru_tcpr_trans_port_b_id_int;
+ rddata_reg(24) <= tru_tcpr_trans_port_b_valid_int;
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01000" =>
+ if (wb_we_i = '1') then
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ else
+ rddata_reg(0) <= regs_i.tsr_trans_stat_active_i;
+ rddata_reg(1) <= regs_i.tsr_trans_stat_finished_i;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01001" =>
+ if (wb_we_i = '1') then
+ rddata_reg(0) <= 'X';
+ tru_rtrcr_rtr_ena_int <= wrdata_reg(0);
+ rddata_reg(1) <= 'X';
+ tru_rtrcr_rtr_reset_int <= wrdata_reg(1);
+ tru_rtrcr_rtr_mode_int <= wrdata_reg(11 downto 8);
+ tru_rtrcr_rtr_rx_int <= wrdata_reg(19 downto 16);
+ tru_rtrcr_rtr_tx_int <= wrdata_reg(27 downto 24);
+ else
+ rddata_reg(0) <= tru_rtrcr_rtr_ena_int;
+ rddata_reg(1) <= tru_rtrcr_rtr_reset_int;
+ rddata_reg(11 downto 8) <= tru_rtrcr_rtr_mode_int;
+ rddata_reg(19 downto 16) <= tru_rtrcr_rtr_rx_int;
+ rddata_reg(27 downto 24) <= tru_rtrcr_rtr_tx_int;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01010" =>
+ if (wb_we_i = '1') then
+ tru_hwfc_rx_fwd_id_int <= wrdata_reg(3 downto 0);
+ tru_hwfc_rx_blk_id_int <= wrdata_reg(7 downto 4);
+ tru_hwfc_tx_fwd_id_int <= wrdata_reg(11 downto 8);
+ tru_hwfc_tx_blk_id_int <= wrdata_reg(15 downto 12);
+ tru_hwfc_tx_fwd_ub_int <= wrdata_reg(23 downto 16);
+ tru_hwfc_tx_blk_ub_int <= wrdata_reg(31 downto 24);
+ else
+ rddata_reg(3 downto 0) <= tru_hwfc_rx_fwd_id_int;
+ rddata_reg(7 downto 4) <= tru_hwfc_rx_blk_id_int;
+ rddata_reg(11 downto 8) <= tru_hwfc_tx_fwd_id_int;
+ rddata_reg(15 downto 12) <= tru_hwfc_tx_blk_id_int;
+ rddata_reg(23 downto 16) <= tru_hwfc_tx_fwd_ub_int;
+ rddata_reg(31 downto 24) <= tru_hwfc_tx_blk_ub_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01011" =>
+ if (wb_we_i = '1') then
+ tru_ttr0_fid_int <= wrdata_reg(7 downto 0);
+ tru_ttr0_sub_fid_int <= wrdata_reg(15 downto 8);
+ tru_ttr0_update_int <= wrdata_reg(16);
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ tru_ttr0_mask_valid_int <= wrdata_reg(17);
+ tru_ttr0_patrn_mode_int <= wrdata_reg(27 downto 24);
+ else
+ rddata_reg(7 downto 0) <= tru_ttr0_fid_int;
+ rddata_reg(15 downto 8) <= tru_ttr0_sub_fid_int;
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= tru_ttr0_mask_valid_int;
+ rddata_reg(27 downto 24) <= tru_ttr0_patrn_mode_int;
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(2) <= '1';
+ ack_in_progress <= '1';
+ when "01100" =>
+ if (wb_we_i = '1') then
+ tru_ttr1_ports_ingress_int <= wrdata_reg(31 downto 0);
+ else
+ rddata_reg(31 downto 0) <= tru_ttr1_ports_ingress_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01101" =>
+ if (wb_we_i = '1') then
+ tru_ttr2_ports_egress_int <= wrdata_reg(31 downto 0);
+ else
+ rddata_reg(31 downto 0) <= tru_ttr2_ports_egress_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01110" =>
+ if (wb_we_i = '1') then
+ tru_ttr3_ports_mask_int <= wrdata_reg(31 downto 0);
+ else
+ rddata_reg(31 downto 0) <= tru_ttr3_ports_mask_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "01111" =>
+ if (wb_we_i = '1') then
+ tru_ttr4_patrn_match_int <= wrdata_reg(31 downto 0);
+ else
+ rddata_reg(31 downto 0) <= tru_ttr4_patrn_match_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "10000" =>
+ if (wb_we_i = '1') then
+ tru_ttr5_patrn_mask_int <= wrdata_reg(31 downto 0);
+ else
+ rddata_reg(31 downto 0) <= tru_ttr5_patrn_mask_int;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "10001" =>
+ if (wb_we_i = '1') then
+ tru_dps_pid_int <= wrdata_reg(7 downto 0);
+ else
+ rddata_reg(7 downto 0) <= tru_dps_pid_int;
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "10010" =>
+ if (wb_we_i = '1') then
+ tru_pidr_inject_int <= wrdata_reg(0);
+ rddata_reg(0) <= 'X';
+ tru_pidr_psel_int <= wrdata_reg(3 downto 1);
+ tru_pidr_uval_int <= wrdata_reg(23 downto 8);
+ rddata_reg(24) <= 'X';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(3 downto 1) <= tru_pidr_psel_int;
+ rddata_reg(23 downto 8) <= tru_pidr_uval_int;
+ rddata_reg(24) <= regs_i.pidr_iready_i;
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(2) <= '1';
+ ack_in_progress <= '1';
+ when "10011" =>
+ if (wb_we_i = '1') then
+ tru_pfdr_clr_int <= wrdata_reg(0);
+ rddata_reg(0) <= 'X';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(15 downto 8) <= regs_i.pfdr_class_i;
+ rddata_reg(31 downto 16) <= regs_i.pfdr_cnt_i;
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ end if;
+ ack_sreg(2) <= '1';
+ ack_in_progress <= '1';
+ when "10100" =>
+ if (wb_we_i = '1') then
+ else
+ rddata_reg(31 downto 0) <= regs_i.ptrdr_ging_mask_i;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Drive the data output bus
+ wb_data_o <= rddata_reg;
+-- TRU Global Enable
+ regs_o.gcr_g_ena_o <= tru_gcr_g_ena_int;
+-- Swap TRU TAB bank
+ process (bus_clock_int, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tru_gcr_tru_bank_dly0 <= '0';
+ regs_o.gcr_tru_bank_o <= '0';
+ elsif rising_edge(bus_clock_int) then
+ tru_gcr_tru_bank_dly0 <= tru_gcr_tru_bank_int;
+ regs_o.gcr_tru_bank_o <= tru_gcr_tru_bank_int and (not tru_gcr_tru_bank_dly0);
+ end if;
+ end process;
+
+
+-- Rx Frame Reset
+ regs_o.gcr_rx_frame_reset_o <= tru_gcr_rx_frame_reset_int;
+-- Active Bank
+-- Stable Ports UP
+-- Ports UP
+-- Replace Pattern Mode
+ regs_o.mcr_pattern_mode_rep_o <= tru_mcr_pattern_mode_rep_int;
+-- Addition Pattern Mode
+ regs_o.mcr_pattern_mode_add_o <= tru_mcr_pattern_mode_add_int;
+-- Substraction Pattern Mode
+ regs_o.mcr_pattern_mode_sub_o <= tru_mcr_pattern_mode_sub_int;
+-- HP traffic Distribution Function ID
+ regs_o.lacr_agg_df_hp_id_o <= tru_lacr_agg_df_hp_id_int;
+-- Broadcast Distribution Function ID
+ regs_o.lacr_agg_df_br_id_o <= tru_lacr_agg_df_br_id_int;
+-- Unicast Distribution Function ID
+ regs_o.lacr_agg_df_un_id_o <= tru_lacr_agg_df_un_id_int;
+-- Transition Enabled
+ regs_o.tcgr_trans_ena_o <= tru_tcgr_trans_ena_int;
+-- Transition Clear
+ regs_o.tcgr_trans_clear_o <= tru_tcgr_trans_clear_int;
+-- Transition Mode
+ regs_o.tcgr_trans_mode_o <= tru_tcgr_trans_mode_int;
+-- Rx Detected Frame ID
+ regs_o.tcgr_trans_rx_id_o <= tru_tcgr_trans_rx_id_int;
+-- Priority
+ regs_o.tcgr_trans_prio_o <= tru_tcgr_trans_prio_int;
+-- Priority Mode
+ regs_o.tcgr_trans_prio_mode_o <= tru_tcgr_trans_prio_mode_int;
+-- PAUSE Time
+ regs_o.tcpbr_trans_pause_time_o <= tru_tcpbr_trans_pause_time_int;
+-- Output Block Time
+ regs_o.tcpbr_trans_block_time_o <= tru_tcpbr_trans_block_time_int;
+-- Port A ID
+ regs_o.tcpr_trans_port_a_id_o <= tru_tcpr_trans_port_a_id_int;
+-- Port A Valid
+ regs_o.tcpr_trans_port_a_valid_o <= tru_tcpr_trans_port_a_valid_int;
+-- Port B ID
+ regs_o.tcpr_trans_port_b_id_o <= tru_tcpr_trans_port_b_id_int;
+-- Port B Valid
+ regs_o.tcpr_trans_port_b_valid_o <= tru_tcpr_trans_port_b_valid_int;
+-- Transition Active
+-- Transition Finished
+-- RTR Enabled
+ regs_o.rtrcr_rtr_ena_o <= tru_rtrcr_rtr_ena_int;
+-- RTR Reset
+ regs_o.rtrcr_rtr_reset_o <= tru_rtrcr_rtr_reset_int;
+-- RTR Handler Mode
+ regs_o.rtrcr_rtr_mode_o <= tru_rtrcr_rtr_mode_int;
+-- RTR Rx Frame ID
+ regs_o.rtrcr_rtr_rx_o <= tru_rtrcr_rtr_rx_int;
+-- RTR Tx Frame ID
+ regs_o.rtrcr_rtr_tx_o <= tru_rtrcr_rtr_tx_int;
+-- HW Frame Rx Forward ID
+ regs_o.hwfc_rx_fwd_id_o <= tru_hwfc_rx_fwd_id_int;
+-- HW Frame Rx Block ID
+ regs_o.hwfc_rx_blk_id_o <= tru_hwfc_rx_blk_id_int;
+-- HW Frame Tx Forward ID
+ regs_o.hwfc_tx_fwd_id_o <= tru_hwfc_tx_fwd_id_int;
+-- HW Frame Tx Block ID
+ regs_o.hwfc_tx_blk_id_o <= tru_hwfc_tx_blk_id_int;
+-- HW Frame Tx Forward User Byte
+ regs_o.hwfc_tx_fwd_ub_o <= tru_hwfc_tx_fwd_ub_int;
+-- HW Frame Tx Block User Byte
+ regs_o.hwfc_tx_blk_ub_o <= tru_hwfc_tx_blk_ub_int;
+-- Filtering Database ID
+ regs_o.ttr0_fid_o <= tru_ttr0_fid_int;
+-- ID withing Filtering Database Entry
+ regs_o.ttr0_sub_fid_o <= tru_ttr0_sub_fid_int;
+-- Force TRU table sub-entry update
+ process (bus_clock_int, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tru_ttr0_update_dly0 <= '0';
+ regs_o.ttr0_update_o <= '0';
+ elsif rising_edge(bus_clock_int) then
+ tru_ttr0_update_dly0 <= tru_ttr0_update_int;
+ regs_o.ttr0_update_o <= tru_ttr0_update_int and (not tru_ttr0_update_dly0);
+ end if;
+ end process;
+
+
+-- Entry Valid
+ regs_o.ttr0_mask_valid_o <= tru_ttr0_mask_valid_int;
+-- Pattern Mode
+ regs_o.ttr0_patrn_mode_o <= tru_ttr0_patrn_mode_int;
+-- Ingress Mask
+ regs_o.ttr1_ports_ingress_o <= tru_ttr1_ports_ingress_int;
+-- Egress Mask
+ regs_o.ttr2_ports_egress_o <= tru_ttr2_ports_egress_int;
+-- Egress Mask
+ regs_o.ttr3_ports_mask_o <= tru_ttr3_ports_mask_int;
+-- Pattern Match
+ regs_o.ttr4_patrn_match_o <= tru_ttr4_patrn_match_int;
+-- Patern Mask
+ regs_o.ttr5_patrn_mask_o <= tru_ttr5_patrn_mask_int;
+-- Port ID
+ regs_o.dps_pid_o <= tru_dps_pid_int;
+-- Injection Request
+ process (bus_clock_int, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tru_pidr_inject_dly0 <= '0';
+ regs_o.pidr_inject_o <= '0';
+ elsif rising_edge(bus_clock_int) then
+ tru_pidr_inject_dly0 <= tru_pidr_inject_int;
+ regs_o.pidr_inject_o <= tru_pidr_inject_int and (not tru_pidr_inject_dly0);
+ end if;
+ end process;
+
+
+-- Packet Select
+ regs_o.pidr_psel_o <= tru_pidr_psel_int;
+-- USER VALUE
+ regs_o.pidr_uval_o <= tru_pidr_uval_int;
+-- Injection Ready
+-- Clear register
+ process (bus_clock_int, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tru_pfdr_clr_dly0 <= '0';
+ regs_o.pfdr_clr_o <= '0';
+ elsif rising_edge(bus_clock_int) then
+ tru_pfdr_clr_dly0 <= tru_pfdr_clr_int;
+ regs_o.pfdr_clr_o <= tru_pfdr_clr_int and (not tru_pfdr_clr_dly0);
+ end if;
+ end process;
+
+
+-- Filtered class
+-- CNT
+-- globalIngMask
+ rwaddr_reg <= wb_addr_i;
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/modules/wrsw_tru/tru_wishbone_slave.wb b/modules/wrsw_tru/tru_wishbone_slave.wb
new file mode 100644
index 0000000000000000000000000000000000000000..1719b9b012d14d391832bb958d01dc928fc19d89
--- /dev/null
+++ b/modules/wrsw_tru/tru_wishbone_slave.wb
@@ -0,0 +1,788 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+ name = "Topology Resolution Unit (TRU)";
+ prefix = "tru";
+
+ hdl_entity="tru_wishbone_slave";
+
+-- Port Configuration Register
+ reg {
+ name = "TRU Global Control Register";
+ description = "Control register containing global (port-independent) settings of the TRU.";
+ prefix = "GCR";
+
+ field {
+ name = "TRU Global Enable";
+ description = "Global TRU enable bit. Overrides all port settings.\
+ 0: RTU is disabled. All packets are dropped.\
+ 1: RTU is enabled.";
+ type = BIT;
+ prefix = "G_ENA";
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ };
+
+ field {
+ name = "Swap TRU TAB bank";
+ description = "write 1: swaps the active bank of the VLAN TAB (writing to TRU TAB affects\
+ inactive bank, only swapping the banks causes the written data to be activated\
+ write 0: no effect";
+ prefix = "TRU_BANK";
+ type = MONOSTABLE;
+ };
+
+ field {
+ name = "Rx Frame Reset";
+ description = "Resets information about filtered frames received on\
+ a port";
+ type = SLV;
+ prefix = "RX_FRAME_RESET";
+ size = 24 ;
+ align= 8;
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ };
+ };
+
+ reg {
+ name = "TRU Global Status Register 0";
+ description = "Provides status of TRU actions";
+ prefix = "GSR0";
+
+
+ field {
+ name = "Active Bank";
+ prefix = "STAT_BANK";
+ description = "Indicates active bank in the TRU TAB";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+
+ field {
+ name = "Stable Ports UP";
+ prefix = "STAT_STB_UP";
+ description = "Indicates stable ports which are up (0=down, 1=up)";
+ size = 24;
+ type = SLV;
+ align= 8;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+ };
+ reg {
+ name = "TRU Global Status Register 1";
+ description = "Provides status of TRU actions";
+ prefix = "GSR1";
+
+
+
+ field {
+ name = "Ports UP";
+ prefix = "STAT_UP";
+ description = "Indicates ports which are up (0=down, 1=up)";
+ size = 32;
+ type = SLV;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+ };
+
+ reg {
+ name = "Pattern Control Register";
+ description = "Defines matching pattern mode/configuration for quick port reconfiguration";
+ prefix = "MCR";
+
+ field {
+ name = "Replace Pattern Mode";
+ prefix = "PATTERN_MODE_REP";
+ description = "Selected Pattern Mode for port config replacement";
+ size = 4;
+ align= 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Addition Pattern Mode";
+ prefix = "PATTERN_MODE_ADD";
+ description = "Selected Pattern Mode for port config addition";
+ size = 4;
+ align= 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Substraction Pattern Mode";
+ prefix = "PATTERN_MODE_SUB";
+ description = "Selected Pattern Mode for port config substraction";
+ size = 4;
+ align= 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+ reg {
+ name = "Link Aggregation Control Register";
+ description = "Enables configuration of Link Aggregation distribution functions for each kind of traffic.\
+ Available functions:\
+ 0: based on pclass detected by Packet Filter (need proper pFilter config)\
+ 1: based on destination MAC address (bits 6 and 7)\
+ 2: based on source MAC address (bits 6 and 7)";
+ prefix = "LACR";
+
+ field {
+ name = "HP traffic Distribution Function ID";
+ description = "ID of Aggregation Distribution Function for HP traffic (value of 0 recommended, requires proper pFilter config)";
+ prefix = "AGG_DF_HP_ID";
+
+ type = SLV;
+ size = 4;
+ align= 8;
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ };
+
+ field {
+ name = "Broadcast Distribution Function ID";
+ description = "ID of Aggregation Distribution Function for broadcast traffic (value of 2 recommended)";
+
+ prefix = "AGG_DF_BR_ID";
+ type = SLV;
+ size = 4;
+ align= 8;
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ };
+
+ field {
+ name = "Unicast Distribution Function ID";
+ description = "ID of Aggregation Distribution Function for unicast traffic";
+
+ prefix = "AGG_DF_UN_ID";
+ type = SLV;
+ size = 4;
+ align= 8;
+ access_dev = READ_ONLY;
+ access_bus = READ_WRITE;
+ };
+ };
+-- reg {
+-- name = "Link Aggregation Group ID Mask Table";
+-- description = "Table which Translation between bit number from the endpoint mask and Aggregation Group";
+-- prefix = "LAGT";
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 0";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_0";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 1";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_1";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 2";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_2";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 3";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_3";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 4";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_4";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 5";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_5";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 6";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_6";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+--
+-- field {
+-- name = "Aggregation Group ID Mask Bit Number for group 7";
+-- description = "Translation between bit number from the endpoint mask and Aggregation Group";
+--
+-- prefix = "LAGT_GR_ID_MASK_7";
+-- type = SLV;
+-- size = 4;
+-- access_dev = READ_ONLY;
+-- access_bus = READ_WRITE;
+-- };
+-- };
+
+ reg {
+ name = "Transition Control General Register";
+ description = "Defines transition mode/configuration for slow port reconfiguration - decides\
+ when two swap banks such that HP packets are not lost.";
+ prefix = "TCGR";
+
+ field {
+ name = "Transition Enabled";
+ prefix = "TRANS_ENA";
+ description = "Enables/disables transition";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Transition Clear";
+ prefix = "TRANS_clear";
+ description = "Writing 1 clears >Transition Finished< bit so that new transition can be \
+ performed. No new transition will be started until >Transition Finished< is cleared";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Transition Mode";
+ prefix = "TRANS_MODE";
+ description = "Selected Transitin Mode for port re-config ";
+ size = 3;
+ align = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Rx Detected Frame ID";
+ prefix = "TRANS_RX_ID";
+ description = "Base transition on detection of the frame which is parsed into provided CLASS ID";
+ size = 3;
+ align = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+
+ field {
+ name = "Priority";
+ prefix = "TRANS_PRIO";
+ description = "Indicates at which traffic priority the transition attempts not to loose \
+ frames";
+ size = 3;
+ align = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Priority Mode";
+ prefix = "TRANS_PRIO_MODE";
+ description = "Specifies whether\
+ - 0: use indication of HP packet from RTU (fast match)\
+ - 1: use the priority specified in TRANS_PRIO register\
+ to count packets during transition";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+ reg {
+ name = "Transition Control PAUSE/Block Register";
+ description = "Defines transition mode/configuration for slow port reconfiguration - decides\
+ when two swap banks such that HP packets are not lost.";
+ prefix = "TCPBR";
+
+ field {
+ name = "PAUSE Time";
+ prefix = "TRANS_PAUSE_TIME";
+ description = "Time (quanta) send in hw-generated PAUSE message to the link partner (port B) to block the traffic on configured priority";
+ size = 16;
+ align = 16;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Output Block Time";
+ prefix = "TRANS_BLOCK_TIME";
+ description = "Time (quanta) for which output queues of both ports (A and B) are blocked for configured priority";
+ size = 16;
+ align = 16;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ };
+ reg {
+ name = "Transition Control Port Register";
+ description = "Defines transition mode/configuration for slow port reconfiguration - decides\
+ when two swap banks such that HP packets are not lost.";
+ prefix = "TCPR";
+
+ field {
+ name = "Port A ID";
+ prefix = "TRANS_PORT_A_ID";
+ description = "Configuration of port A (PORT ID)";
+ size = 6;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Port A Valid";
+ prefix = "TRANS_PORT_A_VALID";
+ description = "Configuration of port A (valid bit)";
+ type = BIT;
+ align=8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Port B ID";
+ prefix = "TRANS_PORT_B_ID";
+ description = "Configuration of port B (PORT ID)";
+ size = 6;
+ align=8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Port B Valid";
+ prefix = "TRANS_PORT_B_VALID";
+ description = "Configuration of port B (valid bit)";
+ type = BIT;
+ align=8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ };
+
+ reg {
+ name = "Transition Status Register";
+ description = "Provides information about the state of transition (if any).";
+ prefix = "TSR";
+
+ field {
+ name = "Transition Active";
+ prefix = "TRANS_STAT_ACTIVE";
+ description = "Indicates that transition is active";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+ field {
+ name = "Transition Finished";
+ prefix = "TRANS_STAT_FINISHED";
+ description = "Indicates that transition has been finished";
+ type = BIT;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+
+ reg {
+ name = "Real Time Reconfiguration Control Register";
+ description = "Controls Real Time Handler.";
+ prefix = "RTRCR";
+
+ field {
+ name = "RTR Enabled";
+ prefix = "RTR_ENA";
+ description = "Enables Real Time Reconfiguration Handler";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "RTR Reset";
+ prefix = "RTR_RESET";
+ description = "Resets Real Time Reconfiguration Handler";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "RTR Handler Mode";
+ prefix = "RTR_MODE";
+ description = "Selected Real Time Reconfig Handler Mode";
+ size = 4;
+ align= 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "RTR Rx Frame ID";
+ prefix = "RTR_RX";
+ description = " ID (bit number of the rxFrameMask) of the signal from the endpoint which \
+ is programmed to indicate reception of Quick Forward Request BPDUe";
+ size = 4;
+ align= 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "RTR Tx Frame ID";
+ prefix = "RTR_TX";
+ description = " ID (bit number of the txFrameMask) of the HW-sent frame by endpoint\
+ (Quick Forward Request BPDUe)";
+ size = 4;
+ align= 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+ reg {
+ name = "HW-frame gen/det config";
+ description = "Controls HW generation/detection of frames";
+ prefix = "HWFC";
+
+ field {
+ name = "HW Frame Rx Forward ID";
+ prefix = "RX_FWD_ID";
+ description = " ID (bit number of the rxFrameMask) of the signal from the endpoint which \
+ is programmed to indicate reception of Quick Forward Request BPDUe";
+ size = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "HW Frame Rx Block ID";
+ prefix = "RX_BLK_ID";
+ description = " ID (bit number of the rxFrameMask) of the signal from the endpoint which \
+ is programmed to indicate reception of Quick Block Request BPDUe";
+ size = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "HW Frame Tx Forward ID";
+ prefix = "TX_FWD_ID";
+ description = " ID (bit number of the txFrameMask) of the HW-sent frame by endpoint\
+ (Quick Forward Request BPDUe)";
+ size = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "HW Frame Tx Block ID";
+ prefix = "TX_BLK_ID";
+ description = " ID (bit number of the txFrameMask) of the HW-sent frame by endpoint\
+ (Quick Block Request BPDUe)";
+ size = 4;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "HW Frame Tx Forward User Byte";
+ prefix = "TX_FWD_UB";
+ description = " LOW byte of the 16-bit User Defined Value inserted into tnjected Template";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "HW Frame Tx Block User Byte";
+ prefix = "TX_BLK_UB";
+ description = " LOW byte of the 16-bit User Defined Value inserted into tnjected Template";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+ reg {
+ name = "TRU Table Register 0";
+ prefix = "TTR0";
+
+ field {
+ prefix = "FID";
+ name = "Filtering Database ID";
+ description = "Assigns the VID to a particular filtering database";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "SUB_FID";
+ name = "ID withing Filtering Database Entry";
+ description = "Identifies entry within FID entry";
+ size = 8;
+ type = SLV;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ prefix = "UPDATE";
+ name = "Force TRU table sub-entry update";
+ description = "write 1: flush TTR register to inactive bank of TRU table entry at address \
+ in FID+SUB_FID";
+ type = MONOSTABLE;
+ };
+ field {
+ name = "Entry Valid";
+ prefix = "MASK_VALID";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "Pattern Mode";
+ prefix = "PATRN_MODE";
+ type = SLV;
+ size = 4;
+ align = 8;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TRU Table Register 1";
+ prefix = "TTR1";
+
+ field {
+ name = "Ingress Mask";
+ prefix = "PORTS_INGRESS";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ };
+ reg {
+ name = "TRU Table Register 2";
+ prefix = "TTR2";
+
+ field {
+ name = "Egress Mask";
+ prefix = "PORTS_EGRESS";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TRU Table Register 3";
+ prefix = "TTR3";
+
+ field {
+ name = "Egress Mask";
+ prefix = "PORTS_MASK";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TRU Table Register 4";
+ prefix = "TTR4";
+
+ field {
+ name = "Pattern Match";
+ prefix = "PATRN_MATCH";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg {
+ name = "TRU Table Register 5";
+ prefix = "TTR5";
+
+ field {
+ name = "Patern Mask";
+ prefix = "PATRN_MASK";
+ type = SLV;
+ size = 32;
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
+ reg { -- added by ML
+ name = "Debug port select";
+ description = "Select port number for applying debugging measures in boht: \
+ Packet Injection Debug Register \
+ Packet Filter Debug Register";
+ prefix = "DPS";
+ field {
+ name = "Port ID";
+ description = "ID of the port to be debugged";
+ type = SLV;
+ size = 8;
+ prefix = "PID";
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+ reg { -- added by ML
+ name = "Packet Injection Debug Register";
+ description = "Used for debugging (ctrl/status) HW packet injection of a selected port";
+ prefix = "PIDR";
+ field {
+ name = "Injection Request";
+ prefix = "INJECT";
+ type = MONOSTABLE;
+ };
+ field {
+ name = "Packet Select";
+ description = "ID of the packet-template to be sent";
+ type = SLV;
+ size = 3;
+ prefix = "PSEL";
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+
+ field {
+ name = "USER VALUE";
+ description = "Value to be inserted at predefined place in the injected packet";
+ type = SLV;
+ size = 16;
+ align = 8;
+ prefix = "UVAL";
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ field {
+ name = "Injection Ready";
+ prefix = "IREADY";
+ type = BIT;
+ align = 8;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+
+ };
+
+ reg {
+ name = "Packet Filter Debug Register";
+ description = "This register stores information about detected packages (class, number)";
+ prefix = "PFDR";
+ field {
+ name = "Clear register";
+ description = "Clears the status regs (count and class)";
+ type = MONOSTABLE;
+ prefix = "CLR";
+ };
+
+ field {
+ name = "Filtered class";
+ description = "Shows which class messages has been detected";
+ prefix = "CLASS";
+ type = SLV;
+ size = 8;
+ align = 8;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ field {
+ name = "CNT";
+ description = "Counts all detections (regardless of the class)";
+ prefix = "CNT";
+ type = SLV;
+ size = 16;
+ align = 16;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+ reg {
+ name = "RT Reconfig Debug Register";
+ description = "This register stores information about detected packages (class, number)";
+ prefix = "PTRDR";
+ field {
+ name = "globalIngMask";
+ description = "Global Ingress Mask";
+ prefix = "GING_MASK";
+ type = SLV;
+ size = 32;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+};
+
+
+
diff --git a/modules/wrsw_tru/wrsw_tru.vhd b/modules/wrsw_tru/wrsw_tru.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..33921f0041f2a65a26c9bd5dfc1d7801036101cb
--- /dev/null
+++ b/modules/wrsw_tru/wrsw_tru.vhd
@@ -0,0 +1,222 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit (wrapper)
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_port_wrapper.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: wrapper of xwrsw_tru module to be used with simulation
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+-- This wrapper does not need WB interface to access configuration/TRU Tab
+-- (currently not supported but can be useful)
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-31 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * t_rtu_vlan_tab_entry
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity wrsw_tru is
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer;
+ g_tru_subentry_width : integer;
+ g_pattern_mode_width : integer;
+ g_patternID_width : integer;
+ g_stableUP_treshold : integer;
+ g_tru_addr_width : integer;
+ g_pclass_number : integer;
+ g_tru2ep_record_width : integer;
+ g_ep2tru_record_width : integer;
+ g_rtu2tru_record_width: integer;
+ g_tru_req_record_width: integer;
+ g_tru_resp_record_width:integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer;
+ g_tru_entry_num : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ------------------------------- I/F with RTU ----------------------------------
+ --t_tru_request
+ tru_req_i : in std_logic_vector(g_tru_req_record_width-1 downto 0);
+
+ --rtu_resp_o
+ tru_resp_o : out std_logic_vector(g_tru_resp_record_width-1 downto 0);
+
+ rtu_i : in std_logic_vector(g_rtu2tru_record_width-1 downto 0);
+
+ ep_i : in std_logic_vector(g_num_ports*g_ep2tru_record_width-1 downto 0);
+ ep_o : out std_logic_vector(g_num_ports*g_tru2ep_record_width-1 downto 0);
+
+ swc_o : out std_logic_vector(g_num_ports-1 downto 0); -- for pausing
+ ------------------------------- I/F with TRU tab -----------------------------------
+ tru_tab_addr_o : out std_logic_vector(g_tru_addr_width-1 downto 0);
+ tru_tab_entry_i : in std_logic_vector(g_tru_subentry_num*g_tru_subentry_width-1 downto 0);
+
+ -------------------------------global config/variable ----------------------------------
+ gcr_g_ena_i : in std_logic;
+ gcr_tru_bank_i : in std_logic;
+ gcr_rx_frame_reset_i : in std_logic_vector(23 downto 0);
+ -- pattern match config
+ mcr_pattern_mode_rep_i : in std_logic_vector(3 downto 0);
+ mcr_pattern_mode_add_i : in std_logic_vector(3 downto 0);
+ -- linc aggregation config
+ lacr_agg_gr_num_i : in std_logic_vector(3 downto 0);
+ lacr_agg_df_br_id_i : in std_logic_vector(3 downto 0);
+ lacr_agg_df_un_id_i : in std_logic_vector(3 downto 0);
+ lagt_gr_id_mask_i : in std_logic_vector(8*4-1 downto 0);
+ -- transition config
+ tcr_trans_ena_i : in std_logic;
+ tcr_trans_clr_i : in std_logic;
+ tcr_trans_mode_i : in std_logic_vector(2 downto 0);
+ tcr_trans_rx_id_i : in std_logic_vector(2 downto 0);
+ tcr_trans_prio_i : in std_logic_vector(2 downto 0);
+ tcr_trans_port_a_id_i : in std_logic_vector(5 downto 0);
+ tcr_trans_port_a_pause_i: in std_logic_vector(15 downto 0);
+ tcr_trans_port_a_valid_i: in std_logic;
+ tcr_trans_port_b_id_i : in std_logic_vector(5 downto 0);
+ tcr_trans_port_b_pause_i: in std_logic_vector(15 downto 0);
+ tcr_trans_port_b_valid_i: in std_logic;
+ -- real time reconfiguration config
+ rtrcr_rtr_ena_i : in std_logic;
+ rtrcr_rtr_reset_i : in std_logic;
+ rtrcr_rtr_mode_i : in std_logic_vector(3 downto 0);
+ rtrcr_rtr_rx_i : in std_logic_vector(3 downto 0)
+ );
+end wrsw_tru;
+
+architecture rtl of wrsw_tru is
+ type t_tru_tab_subentry_array is array(integer range <>) of
+ std_logic_vector(g_tru_subentry_width-1 downto 0);
+ type t_ep_array is array(integer range <>) of std_logic_vector(g_ep2tru_record_width-1 downto 0);
+
+ signal s_tru_req : t_tru_request;
+ signal s_tru_resp : t_tru_response;
+ signal s_tru_tab_entry : t_tru_tab_entry(g_tru_subentry_num-1 downto 0);
+ signal s_config : t_tru_config;
+ signal s_tru_tab_subentry_arr : t_tru_tab_subentry_array(g_tru_subentry_num-1 downto 0);
+ signal s_rtu : t_rtu2tru;
+ signal s_ep_in : t_ep2tru_array(g_num_ports-1 downto 0);
+ signal s_ep_out : t_tru2ep_array(g_num_ports-1 downto 0);
+ signal s_ep_arr : t_ep_array(g_num_ports-1 downto 0);
+begin
+
+ X_TRU: xwrsw_tru
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num => g_tru_subentry_num,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_num_ports,
+ g_stableUP_treshold=> g_stableUP_treshold,
+ g_tru_addr_width => g_tru_addr_width,
+ g_pclass_number => g_pclass_number,
+ g_mt_trans_max_fr_cnt=> g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width,
+ g_pattern_mode_width => g_pattern_mode_width,
+ g_tru_entry_num => g_tru_entry_num
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ req_i => s_tru_req,
+ resp_o => s_tru_resp,
+ rtu_i => s_rtu,
+ ep_i => s_ep_in,
+ ep_o => s_ep_out,
+ swc_o => swc_o,
+ ------------------------------------------
+ tmp_tru_tab_addr_o => tru_tab_addr_o,
+ tmp_tru_tab_entry_i => s_tru_tab_entry,
+ tmp_config_i => s_config
+ );
+
+ s_tru_req <= f_unpack_tru_request (tru_req_i, g_num_ports);
+ tru_resp_o <= f_pack_tru_response (s_tru_resp, g_num_ports);
+ s_rtu <= f_unpack_rtu (rtu_i, g_num_ports);
+
+ G1: for i in 0 to g_tru_subentry_num-1 generate
+ s_tru_tab_subentry_arr(i) <= tru_tab_entry_i((i+1)*g_tru_subentry_width-1 downto
+ i *g_tru_subentry_width);
+ s_tru_tab_entry(i) <= f_unpack_tru_subentry(s_tru_tab_subentry_arr(i),g_num_ports);
+ end generate G1;
+
+ s_config.gcr_g_ena <= gcr_g_ena_i;
+ s_config.gcr_tru_bank <= gcr_tru_bank_i;
+ s_config.gcr_rx_frame_reset <= gcr_rx_frame_reset_i;
+ s_config.mcr_pattern_mode_rep <= mcr_pattern_mode_rep_i;
+ s_config.mcr_pattern_mode_add <= mcr_pattern_mode_add_i;
+ s_config.lacr_agg_gr_num <= lacr_agg_gr_num_i;
+ s_config.lacr_agg_df_br_id <= lacr_agg_df_br_id_i;
+ s_config.lacr_agg_df_un_id <= lacr_agg_df_un_id_i;
+
+ G2: for i in 0 to 7 generate
+ s_config.lagt_gr_id_mask(i) <= lagt_gr_id_mask_i((i+1)*4 -1 downto i*4);
+ end generate;
+
+ s_config.tcr_trans_ena <= tcr_trans_ena_i;
+ s_config.tcr_trans_clr <= tcr_trans_clr_i;
+ s_config.tcr_trans_mode <= tcr_trans_mode_i;
+ s_config.tcr_trans_rx_id <= tcr_trans_rx_id_i;
+ s_config.tcr_trans_prio <= tcr_trans_prio_i;
+ s_config.tcr_trans_port_a_id <= tcr_trans_port_a_id_i;
+ s_config.tcr_trans_port_a_valid<= tcr_trans_port_a_valid_i;
+ s_config.tcr_trans_port_a_pause<= tcr_trans_port_a_pause_i;
+ s_config.tcr_trans_port_b_id <= tcr_trans_port_b_id_i;
+ s_config.tcr_trans_port_b_valid<= tcr_trans_port_b_valid_i;
+ s_config.tcr_trans_port_b_pause<= tcr_trans_port_b_pause_i;
+ s_config.rtrcr_rtr_ena <= rtrcr_rtr_ena_i;
+ s_config.rtrcr_rtr_reset <= rtrcr_rtr_reset_i;
+ s_config.rtrcr_rtr_mode <= rtrcr_rtr_mode_i;
+ s_config.rtrcr_rtr_rx <= rtrcr_rtr_rx_i;
+
+ G3: for i in 0 to g_num_ports-1 generate
+ s_ep_arr(i) <= ep_i((i+1)*g_ep2tru_record_width-1 downto i*g_ep2tru_record_width);
+ s_ep_in(i) <= f_unpack_ep2tru(s_ep_arr(i));
+ ep_o((i+1)*g_tru2ep_record_width-1 downto i*g_tru2ep_record_width) <= f_pack_tru2ep(s_ep_out(i));
+ end generate G3;
+
+end rtl;
diff --git a/modules/wrsw_tru/wrsw_tru_pkg.vhd b/modules/wrsw_tru/wrsw_tru_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..14e71f4dd3c614875b8c0075dc699c29d5fefbb3
--- /dev/null
+++ b/modules/wrsw_tru/wrsw_tru_pkg.vhd
@@ -0,0 +1,984 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit: package
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : wrsw_tru_pkg.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Package with records, function, constants and components
+-- declarations for TRU module
+--
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+--
+--
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-28 1.0 mlipinsk Created
+-- 2012-09-03 1.0 mlipinsk changed pattern stuff
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+library work;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * c_RTU_MAX_PORTS
+ -- * c_wrsw_fid_width
+use work.tru_wbgen2_pkg.all; -- for wbgen-erated records
+use work.wishbone_pkg.all; -- wishbone_{interface_mode,address_granularity}
+package wrsw_tru_pkg is
+
+ -- constant c_RTU_MAX_PORTS : integer := 24;
+ -- constant c_wrsw_fid_width : integer := 8;
+ constant c_wrsw_pclass_number : integer :=8;
+ constant c_wrsw_pause_delay_width : integer :=16;
+ constant c_wrsw_max_queue_number : integer :=8;
+ constant c_tru_pattern_mode_width : integer :=4;
+ -------------------------- main input/output data ----------------------------------------
+
+ type t_trans2ep is record
+ pauseSend : std_logic;
+ pauseTime : std_logic_vector(c_wrsw_pause_delay_width-1 downto 0);
+ outQueueBlockMask : std_logic_vector(c_wrsw_max_queue_number-1 downto 0);
+ outQueueBlockReq : std_logic;
+ hwframe_fwd : std_logic;
+ hwframe_blk : std_logic;
+ end record;
+
+ type t_trans2sw is record
+ blockTime : std_logic_vector(c_wrsw_pause_delay_width-1 downto 0);
+ blockQueuesMask : std_logic_vector(c_wrsw_max_queue_number -1 downto 0);
+ blockPortsMask : std_logic_vector(c_SWC_MAX_PORTS -1 downto 0);
+ blockReq : std_logic;
+ end record;
+
+
+ type t_tru2ep is record
+-- ctrlWr : std_logic;
+ --frmae generation
+-- tx_pck : std_logic; -- to be changed
+-- tx_pck_class : std_logic_vector(7 downto 0); -- to be changed
+ -- pause generation
+-- pauseSend : std_logic;
+-- pauseTime : std_logic_vector(15 downto 0);
+-- outQueueBlockMask : std_logic_vector(7 downto 0);
+ -- new stuff
+ link_kill : std_logic; --ok
+ fc_pause_req : std_logic; -- not really used, we use inject for PAUSE
+ fc_pause_delay : std_logic_vector(15 downto 0); -- not really used, we use inject for PAUSE
+ inject_req : std_logic;
+ inject_packet_sel : std_logic_vector(2 downto 0) ;
+ inject_user_value : std_logic_vector(15 downto 0) ;
+ end record;
+
+ constant c_tru2ep_zero : t_tru2ep := (
+ link_kill => '0',
+ fc_pause_req => '0',
+ fc_pause_delay => (others => '0'),
+ inject_req => '0',
+ inject_packet_sel => (others => '0'),
+ inject_user_value => (others => '0'));
+
+ type t_ep2tru is record
+ status : std_logic;
+-- ctrlRd : std_logic;
+ -- frame detectin
+-- rx_pck : std_logic; -- in Endpoint this is : pfilter_done_i
+-- rx_pck_class : std_logic_vector(7 downto 0); -- in Endpoint this is :pfilter_pclass_i
+ -- new stuff
+ fc_pause_ready : std_logic;
+ inject_ready : std_logic;
+ pfilter_pclass : std_logic_vector(7 downto 0);
+ pfilter_drop : std_logic;
+ pfilter_done : std_logic;
+ end record;
+
+ type t_tru2ep_array is array(integer range <>) of t_tru2ep;
+ type t_ep2tru_array is array(integer range <>) of t_ep2tru;
+
+ type t_tru_tab_subentry is record
+ valid : std_logic;
+ ports_ingress : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ ports_egress : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ ports_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ pattern_match : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ pattern_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ pattern_mode : std_logic_vector(c_tru_pattern_mode_width-1 downto 0);
+ end record;
+
+
+ type t_tru_endpoint is record
+ status : std_logic; -- port up/down
+ rxFrameMask : std_logic_vector(c_wrsw_pclass_number-1 downto 0); -- frame received (current)
+ rxFrameMaskReg : std_logic_vector(c_wrsw_pclass_number-1 downto 0); -- frame received (registered)
+ stableUp : std_logic;
+ inject_ready : std_logic;
+ end record;
+
+ type t_xFrameMask is array(c_wrsw_pclass_number-1 downto 0) of std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ type t_xFramePerPortMask is array(c_RTU_MAX_PORTS-1 downto 0) of std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+
+ type t_tru_endpoints is record
+ status : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0); -- port up/down
+ rxFrameMask : t_xFrameMask; -- frame received (current)
+ rxFrameMaskReg : t_xFrameMask; -- frame received (registered)
+ rxFramePerPortMask : t_xFramePerPortMask; -- for LACP
+ stableUp : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ inject_ready : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ end record;
+
+ type t_lagt_gr_id_mask_array is array(integer range <>) of std_logic_vector(3 downto 0);
+
+ type t_tru_config is record
+ --general config
+ gcr_g_ena : std_logic;
+ gcr_rx_frame_reset : std_logic_vector(23 downto 0);
+ -- pattern match config
+ mcr_pattern_mode_rep : std_logic_vector(3 downto 0);
+ mcr_pattern_mode_add : std_logic_vector(3 downto 0);
+ mcr_pattern_mode_sub : std_logic_vector(3 downto 0);
+ -- linc aggregation config
+ lacr_agg_df_hp_id : std_logic_vector(3 downto 0);
+ lacr_agg_df_br_id : std_logic_vector(3 downto 0);
+ lacr_agg_df_un_id : std_logic_vector(3 downto 0);
+ lagt_gr_id_mask : t_lagt_gr_id_mask_array(7 downto 0);
+ -- transition config
+ tcr_trans_ena : std_logic;
+ tcr_trans_clr : std_logic; -- added
+ tcr_trans_mode : std_logic_vector(2 downto 0);
+ tcr_trans_rx_id : std_logic_vector(2 downto 0);
+ tcr_trans_prio : std_logic_vector(2 downto 0); -- added
+ tcr_trans_prio_mode : std_logic;
+ tcr_trans_port_a_id : std_logic_vector(5 downto 0);
+-- tcr_trans_port_a_pause: std_logic_vector(15 downto 0); -- added
+ tcr_trans_port_a_valid: std_logic;
+ tcr_trans_port_b_id : std_logic_vector(5 downto 0);
+-- tcr_trans_port_b_pause: std_logic_vector(15 downto 0); -- added
+ tcr_trans_port_b_valid: std_logic;
+ tcr_trans_pause_time : std_logic_vector(15 downto 0); -- added
+ tcr_trans_block_time : std_logic_vector(15 downto 0); -- added
+ -- real time reconfiguration config
+ rtrcr_rtr_ena : std_logic;
+ rtrcr_rtr_reset : std_logic;
+ rtrcr_rtr_mode : std_logic_vector(3 downto 0);
+
+ hwframe_rx_fwd : std_logic_vector(3 downto 0);
+ hwframe_tx_fwd : std_logic_vector(3 downto 0);
+
+ hwframe_rx_blk : std_logic_vector(3 downto 0);
+ hwframe_tx_blk : std_logic_vector(3 downto 0);
+
+ rtrcr_rtr_rx : std_logic_vector(3 downto 0);
+ rtrcr_rtr_tx : std_logic_vector(3 downto 0);
+ end record;
+
+
+ type t_resp_masks is record
+ egress : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ ingress : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ end record;
+
+ type t_inject_sel is record
+ dbg : std_logic;
+ fwd : std_logic;
+ blk : std_logic;
+ pause : std_logic;
+ end record;
+
+ type t_inject_sel_array is array(integer range <>) of t_inject_sel;
+
+ type t_tru_status is record
+ transitionActive : std_logic;
+ transitionFinished : std_logic;
+ truTabBank : std_logic;
+ end record;
+ --------------------------------- arrays ----------------------------------------------
+-- type t_tru2ep_array is array(integer range <>) of t_tru2ep;
+-- type t_ep2tru_array is array(integer range <>) of t_ep2tru;
+ type t_trans2tru_array is array(integer range <>) of t_trans2ep;
+
+ type t_tru_tab_entry is array(integer range <>) of t_tru_tab_subentry;
+ type t_tru_tab_entries is array(integer range <>,integer range <>) of t_tru_tab_subentry;
+ type t_tru_endpoint_array is array(integer range<>) of t_tru_endpoint;
+-- type t_tru_tab_subentry_array is array(integer range <>) of std_logic_vector(g_tru_subentry_width-1 downto 0);
+-- type t_ep_array is array(integer range <>) of std_logic_vector(g_ep2tru_record_width-1 downto 0);
+
+ type t_pinject_ctr is record
+ inject_packet_sel : std_logic_vector(2 downto 0) ;
+ inject_user_value : std_logic_vector(15 downto 0) ;
+ end record;
+
+ type t_pinject_ctr_array is array(integer range<>) of t_pinject_ctr;
+--------------------------------- dubigging ----------------------------------------------
+ type t_debug_stuff is record
+ pfdr_class : std_logic_vector(7 downto 0);
+ pfdr_cnt : std_logic_vector(15 downto 0);
+ end record;
+
+ type t_debug_stuff_array is array(integer range <>) of t_debug_stuff;
+-------------------------------------------------------------------------------------------
+
+
+ function f_one_hot_to_binary (One_Hot : std_logic_vector)
+ return integer;
+ function f_unpack_tru_subentry (input_data: std_logic_vector; port_number: integer)
+ return t_tru_tab_subentry;
+ function f_pack_tru_subentry (input_data: t_tru_tab_subentry; port_number: integer)
+ return std_logic_vector;
+ function f_gen_mask_with_patterns(entry: t_tru_tab_entry; pattern_rep : std_logic_vector;
+ pattern_add : std_logic_vector; pattern_sub : std_logic_vector;
+ subentry_num : integer)
+ return t_resp_masks;
+-- function f_pack_tru_endpoint (input_data: t_tru_endpoint; port_number: integer )
+-- return std_logic_vector;
+ function f_unpack_tru_endpoint (input_data: std_logic_vector )
+ return t_tru_endpoint;
+ function f_pack_tru_request (input_data: t_tru_request;port_number: integer )
+ return std_logic_vector;
+ function f_unpack_tru_request (input_data: std_logic_vector; port_number: integer )
+ return t_tru_request;
+ function f_pack_tru_response (input_data: t_tru_response; port_number: integer )
+ return std_logic_vector;
+ function f_unpack_tru_response (input_data: std_logic_vector; port_number: integer )
+ return t_tru_response;
+ function f_unpack_ep2tru (input_data: std_logic_vector )
+ return t_ep2tru;
+ function f_pack_tru2ep (input_data: t_tru2ep)
+ return std_logic_vector;
+ function f_unpack_rtu (input_data: std_logic_vector;port_number: integer)
+ return t_rtu2tru;
+
+ function f_rxFrameMaskInv(input_data: t_tru_endpoint_array;rx_class_id: integer;port_number: integer)
+ return std_logic_vector;
+ function f_rxFrameMaskRegInv(input_data: t_tru_endpoint_array;rx_class_id: integer;port_number: integer)
+ return std_logic_vector;
+ function f_pattern_port_down(endpoints_i: t_tru_endpoints;pattern_width_i: integer)
+ return std_logic_vector;
+ function f_pattern_quick_fwd (endpoints_i: t_tru_endpoints; config_i: t_tru_config;pattern_width_i: integer)
+ return std_logic_vector;
+ function f_pattern_quick_blk (endpoints_i: t_tru_endpoints; config_i: t_tru_config;pattern_width_i: integer)
+ return std_logic_vector;
+ function f_pattern_aggr_gr_id(endpoints_i: t_tru_endpoints;tru_req_i : t_tru_request;portID_i: std_logic_vector;config_i: t_tru_config;pattern_width_i: integer; port_number_i : integer)
+ return std_logic_vector;
+ function f_pattern_rx_port (tru_req_i: t_tru_request; pattern_width_i : integer)
+ return std_logic_vector;
+ function f_aggr_dist_fun (endpoints_i : t_tru_endpoints;tru_req_i : t_tru_request;portID_i : std_logic_vector; aggr_df_id_i : std_logic_vector; pattern_width_i: integer; port_number_i: integer)
+ return std_logic_vector ;
+ component tru_wishbone_slave
+ port (
+ rst_n_i : in std_logic;
+ wb_clk_i : in std_logic;
+-- wb_addr_i : in std_logic_vector(3 downto 0);
+ wb_addr_i : in std_logic_vector(4 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ regs_i : in t_tru_in_registers;
+ regs_o : out t_tru_out_registers
+ );
+ end component;
+
+ component tru_sub_vlan_pattern
+ generic(
+ g_num_ports : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ portID_i : in std_logic_vector(integer(CEIL(LOG2(real(g_num_ports + 1))))-1 downto 0);
+ patternID_i : in std_logic_vector(g_patternID_width-1 downto 0);
+ tru_req_i : in t_tru_request;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ pattern_o : out std_logic_vector(g_pattern_width-1 downto 0)
+ );
+ end component;
+
+ component tru_reconfig_rt_port_handler
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ read_valid_i : in std_logic;
+ read_data_i : in t_tru_tab_entry(g_tru_subentry_num - 1 downto 0);
+ resp_masks_i : in t_resp_masks;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_swap_i: in std_logic;
+ globIngMask_dbg_o : out std_logic_vector(g_num_ports-1 downto 0);
+ txFrameMask_o : out std_logic_vector(g_num_ports-1 downto 0)
+ );
+ end component;
+
+ component tru_port
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer;
+ g_tru_addr_width : integer -- fid
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ tru_req_i : in t_tru_request;
+ tru_resp_o : out t_tru_response;
+ tru_tab_addr_o : out std_logic_vector(g_tru_addr_width-1 downto 0);
+ tru_tab_entry_i : in t_tru_tab_entry(g_tru_subentry_num - 1 downto 0);
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_swap_i: in std_logic;
+ globIngMask_dbg_o : out std_logic_vector(g_num_ports-1 downto 0);
+ txFrameMask_o : out std_logic_vector(g_num_ports - 1 downto 0)
+ );
+ end component;
+
+ component tru_endpoint is
+ generic(
+ g_num_ports : integer;
+ g_pclass_number : integer;
+ g_tru_subentry_num : integer;
+ g_patternID_width : integer;
+ g_pattern_width : integer;
+ g_stableUP_treshold: integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ port_if_i : in t_ep2tru;
+ port_if_ctrl_o : out std_logic;
+ rtu_pass_all_i : in std_logic;
+ endpoint_o : out t_tru_endpoint;
+ reset_rxFlag_i : in std_logic
+ );
+ end component;
+
+ component xwrsw_tru is
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer;
+ g_pattern_width : integer;
+ g_patternID_width : integer;
+ g_stableUP_treshold : integer;
+-- g_tru_addr_width : integer;
+ g_pclass_number : integer;
+ g_mt_trans_max_fr_cnt: integer;
+ g_prio_width : integer;
+ g_pattern_mode_width : integer;
+ g_tru_entry_num : integer;
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity: t_wishbone_address_granularity := BYTE
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ req_i : in t_tru_request;
+ resp_o : out t_tru_response;
+ rtu_i : in t_rtu2tru;
+ ep_i : in t_ep2tru_array(g_num_ports-1 downto 0);
+ ep_o : out t_tru2ep_array(g_num_ports-1 downto 0);
+ swc_block_oq_req_o : out t_global_pause_request;
+ enabled_o : out std_logic;
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+ );
+ end component;
+
+ component tru_transition
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ ports_req_strobe_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+ end component;
+
+ component tru_trans_marker_trig
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ ports_req_strobe_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+ end component;
+
+ component tru_trans_lacp_colect
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+ end component;
+
+ component tru_trans_lacp_dist
+ generic(
+ g_num_ports : integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ endpoints_i : in t_tru_endpoints;
+ config_i : in t_tru_config;
+ tru_tab_bank_i : in std_logic;
+ tru_tab_bank_o : out std_logic;
+ statTransActive_o : out std_logic;
+ statTransFinished_o: out std_logic;
+ rxFrameMask_i : in std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_i : in t_rtu2tru;
+ sw_o : out t_trans2sw;
+ ep_o : out t_trans2tru_array(g_num_ports - 1 downto 0)
+ );
+ end component;
+
+
+end wrsw_tru_pkg;
+
+package body wrsw_tru_pkg is
+
+ ----------------- translate one hot to binary --------------------------
+ function f_one_hot_to_binary (
+ One_Hot : std_logic_vector
+ ) return integer is
+ variable Bin_Vec_Var : integer range 0 to One_Hot'length -1;
+ begin
+ Bin_Vec_Var := 0;
+
+ for I in 0 to (One_Hot'length - 1) loop
+ if One_Hot(I) = '1' then
+ Bin_Vec_Var := I;
+ end if;
+ end loop;
+ return Bin_Vec_Var;
+ end function;
+ -----------------------------------------------------------------------
+ function f_unpack_tru_subentry (
+ input_data: std_logic_vector;
+ port_number: integer
+ ) return t_tru_tab_subentry is
+ variable entry: t_tru_tab_subentry;
+ begin
+
+ entry.valid := input_data(0);
+ entry.ports_ingress(port_number-1 downto 0) := input_data(1+1*port_number -1 downto 1+0*port_number);
+ entry.ports_egress (port_number-1 downto 0) := input_data(1+2*port_number -1 downto 1+1*port_number);
+ entry.ports_mask (port_number-1 downto 0) := input_data(1+3*port_number -1 downto 1+2*port_number);
+ entry.pattern_match(port_number-1 downto 0) := input_data(1+4*port_number -1 downto 1+3*port_number);
+ entry.pattern_mask (port_number-1 downto 0) := input_data(1+5*port_number -1 downto 1+4*port_number);
+ entry.pattern_mode (c_tru_pattern_mode_width-1 downto 0) := input_data(1+5*port_number+c_tru_pattern_mode_width-1 downto 1+5*port_number);
+
+ entry.ports_ingress(c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+ entry.ports_egress (c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+ entry.ports_mask (c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+ entry.pattern_match(c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+ entry.pattern_mask (c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+
+ return(entry);
+
+ end function;
+ -----------------------------------------------------------------------
+ function f_pack_tru_subentry (
+ input_data: t_tru_tab_subentry ;
+ port_number: integer
+ ) return std_logic_vector is
+ variable entry: std_logic_vector((3*port_number)+(3*8)+1-1 downto 0);
+ begin
+
+ entry(0) := input_data.valid;
+ entry(1+1*port_number -1 downto 1+0*port_number) := input_data.ports_ingress(port_number-1 downto 0);
+ entry(1+2*port_number -1 downto 1+1*port_number) := input_data.ports_egress (port_number-1 downto 0);
+ entry(1+3*port_number -1 downto 1+2*port_number) := input_data.ports_mask (port_number-1 downto 0);
+ entry(1+4*port_number -1 downto 1+3*port_number) := input_data.pattern_match(port_number-1 downto 0);
+ entry(1+5*port_number -1 downto 1+4*port_number) := input_data.pattern_mask (port_number-1 downto 0);
+ entry(1+6*port_number+c_tru_pattern_mode_width-1 downto 1+5*port_number) := input_data.pattern_mode(c_tru_pattern_mode_width-1 downto 0);
+ return(entry);
+ end function;
+
+-- function f_pack_tru_endpoint (
+-- input_data: t_tru_endpoint ;
+-- port_number: integer
+-- ) return std_logic_vector is
+-- variable entry: std_logic_vector(3*port_number-1 downto 0);
+-- begin
+--
+-- entry(1*port_number -1 downto 0*port_number) := input_data.status (port_number-1 downto 0);
+-- entry(2*port_number -1 downto 1*port_number) := input_data.rxFrameMask (port_number-1 downto 0);
+-- entry(3*port_number -1 downto 2*port_number) := input_data.rxFrameMaskReg (port_number-1 downto 0);
+-- return(entry);
+-- end function;
+
+ function f_unpack_tru_endpoint (
+ input_data: std_logic_vector
+ ) return t_tru_endpoint is
+ variable entry: t_tru_endpoint;
+ begin
+
+ entry.status := input_data(0);
+ entry.rxFrameMask := input_data(1+1*c_wrsw_pclass_number -1 downto 1+0*c_wrsw_pclass_number);
+ entry.rxFrameMaskReg:= input_data(1+2*c_wrsw_pclass_number -1 downto 1+1*c_wrsw_pclass_number);
+
+ return(entry);
+
+ end function;
+
+ function f_pack_tru_request (
+ input_data: t_tru_request;
+ port_number : integer
+ ) return std_logic_vector is
+ variable entry: std_logic_vector(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1+1+c_RTU_MAX_PORTS-1 downto 0);
+ begin
+ entry(0) := input_data.valid;
+ entry(1+c_wrsw_mac_addr_width-1 downto 1) := input_data.smac;
+ entry(1+2*c_wrsw_mac_addr_width-1 downto
+ 1+c_wrsw_mac_addr_width) := input_data.dmac;
+ entry(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width-1 downto
+ 1+2*c_wrsw_mac_addr_width) := input_data.fid;
+ entry(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width) := input_data.isHP;
+ entry(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1) := input_data.isBR;
+ entry(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1+1+port_number-1 downto
+ 1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1+1) := input_data.reqMask(port_number-1 downto 0);
+ return(entry);
+ end function;
+
+
+ function f_unpack_tru_request (
+ input_data : std_logic_vector;
+ port_number : integer
+ ) return t_tru_request is
+ variable entry: t_tru_request;
+ begin
+ entry.valid := input_data(0);
+ entry.smac := input_data(1+1*c_wrsw_mac_addr_width-1 downto 1);
+ entry.dmac := input_data(1+2*c_wrsw_mac_addr_width-1 downto 1+1*c_wrsw_mac_addr_width);
+ entry.fid := input_data(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width-1 downto 1+2*c_wrsw_mac_addr_width);
+ entry.isHP := input_data(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width);
+ entry.isBR := input_data(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1);
+ entry.reqMask(port_number-1 downto 0) := input_data(1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1+1+port_number-1 downto 1+2*c_wrsw_mac_addr_width+c_wrsw_fid_width+1+1) ;
+ entry.reqMask(c_RTU_MAX_PORTS-1 downto port_number) := (others =>'0');
+ return(entry);
+ end function;
+
+ function f_pack_tru_response (
+ input_data: t_tru_response;
+ port_number: integer
+ ) return std_logic_vector is
+ variable entry: std_logic_vector(1+2*port_number+1-1 downto 0);
+ begin
+ entry(0) := input_data.valid;
+ entry(1+port_number-1 downto 1) := input_data.port_mask(port_number-1 downto 0);
+ entry(1+port_number) := input_data.drop;
+ entry(1+2*port_number+1-1 downto 1+port_number+1) := input_data.respMask(port_number-1 downto 0);
+ return(entry);
+ end function;
+
+
+ function f_unpack_tru_response (
+ input_data: std_logic_vector;
+ port_number: integer
+ ) return t_tru_response is
+ variable entry: t_tru_response;
+ begin
+ entry.valid := input_data(0);
+ entry.port_mask(port_number-1 downto 0) := input_data(1+port_number-1 downto 1);
+ entry.port_mask(c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+ entry.drop := input_data(1+port_number);
+ entry.respMask(port_number-1 downto 0) := input_data(1+2*port_number-1 downto 1+port_number);
+ entry.respMask(c_RTU_MAX_PORTS-1 downto port_number) := (others => '0');
+ return(entry);
+ end function;
+
+
+ function f_gen_mask_with_patterns(
+ entry : t_tru_tab_entry;
+ pattern_rep : std_logic_vector;
+ pattern_add : std_logic_vector;
+ pattern_sub : std_logic_vector;
+ subentry_num : integer
+ ) return t_resp_masks is
+ variable resp_masks : t_resp_masks;
+ variable resp_masks_tmp : t_resp_masks;
+ variable pattern_replacement : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ variable pattern_addition : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ variable pattern_substraction: std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ variable zeros : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ begin
+ resp_masks.egress := (others=>'0');
+ resp_masks.ingress := (others=>'0');
+ zeros := (others=>'0');
+
+ pattern_replacement (pattern_rep'length-1 downto 0) := pattern_rep;
+ pattern_addition (pattern_add'length-1 downto 0) := pattern_add;
+ pattern_substraction(pattern_add'length-1 downto 0) := pattern_add;
+ pattern_replacement (c_RTU_MAX_PORTS-1 downto pattern_rep'length) := (others=>'0');
+ pattern_addition (c_RTU_MAX_PORTS-1 downto pattern_add'length) := (others=>'0');
+ pattern_substraction(c_RTU_MAX_PORTS-1 downto pattern_add'length) := (others=>'0');
+
+ for i in 0 to subentry_num-1 loop
+ if(entry(i).valid = '1') then
+ case entry(i).pattern_mode is
+ when "0000" => -- replace TRU-defined masked bits with the bits defined in the TRU
+ if((pattern_replacement and entry(i).pattern_mask) = entry(i).pattern_match) then
+ resp_masks.egress := (resp_masks.egress and (not entry(i).ports_mask)) or (entry(i).ports_egress and entry(i).ports_mask);
+ resp_masks.ingress := (resp_masks.ingress and (not entry(i).ports_mask)) or (entry(i).ports_ingress and entry(i).ports_mask);
+ end if;
+ when "0001" => -- add bits defined in TRU for the TRU-defined masked bits
+ if ((pattern_addition and entry(i).pattern_mask) = entry(i).pattern_match) then
+ resp_masks.egress := resp_masks.egress or (entry(i).ports_egress and entry(i).ports_mask);
+ resp_masks.ingress := resp_masks.ingress or (entry(i).ports_ingress and entry(i).ports_mask);
+ end if;
+ when "0010" => -- add pattern for the bits defined in the TRU
+ if ((pattern_addition and entry(i).pattern_mask and entry(i).pattern_match) /= zeros) then
+ resp_masks.egress := resp_masks.egress or (entry(i).ports_egress and entry(i).ports_mask and pattern_addition);
+ resp_masks.ingress := resp_masks.ingress or (entry(i).ports_ingress and entry(i).ports_mask and pattern_addition);
+ end if;
+ when "0011" => -- substract pattern for the bits defined in TRU
+ if ((pattern_substraction and entry(i).pattern_mask and entry(i).pattern_match) /= zeros) then
+ resp_masks.egress := resp_masks.egress and not (entry(i).ports_egress and entry(i).ports_mask and pattern_substraction);
+ resp_masks.ingress := resp_masks.ingress and not (entry(i).ports_ingress and entry(i).ports_mask and pattern_substraction);
+ end if;
+ when "0100" => -- explicitely LACP stuff
+ if ((pattern_replacement and entry(i).pattern_mask and entry(i).pattern_match) /= zeros and
+ (pattern_substraction and entry(i).ports_ingress and entry(i).ports_mask) = zeros) then
+ resp_masks.egress := (resp_masks.egress and (not entry(i).ports_mask)) or (entry(i).ports_egress and entry(i).ports_mask);
+ resp_masks.ingress := (resp_masks.ingress and (not entry(i).ports_mask)) or (entry(i).ports_ingress and entry(i).ports_mask);
+ end if;
+ when "0101" => -- substract mask for the bits defined in TRU -> does not seem to work
+ if ((pattern_substraction and entry(i).pattern_mask and entry(i).pattern_match) /= zeros) then
+ resp_masks.egress := resp_masks.egress and not (entry(i).ports_egress and entry(i).ports_mask);
+ resp_masks.ingress := resp_masks.ingress and not (entry(i).ports_ingress and entry(i).ports_mask);
+ end if;
+ when others =>
+ resp_masks.egress := resp_masks.egress;
+ resp_masks.ingress := resp_masks.ingress ;
+ end case;
+ else
+ resp_masks.egress := resp_masks.egress;
+ resp_masks.ingress := resp_masks.ingress ;
+ end if;
+
+ end loop;
+
+ return(resp_masks);
+ end function;
+
+ function f_rxFrameMaskInv(
+ input_data: t_tru_endpoint_array;
+ rx_class_id: integer ;
+ port_number: integer
+ ) return std_logic_vector is
+ variable rxs_for_allPorts: std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ begin
+ for i in 0 to c_RTU_MAX_PORTS-1 loop
+ if(i<port_number) then
+ rxs_for_allPorts(i) := input_data(i).rxFrameMask(rx_class_id);
+ else
+ rxs_for_allPorts(i) := '0';
+ end if;
+ end loop;
+ return(rxs_for_allPorts);
+ end function;
+
+ function f_rxFrameMaskRegInv(
+ input_data: t_tru_endpoint_array;
+ rx_class_id: integer ;
+ port_number: integer
+ ) return std_logic_vector is
+ variable rxs_for_allPorts: std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);
+ begin
+ for i in 0 to c_RTU_MAX_PORTS-1 loop
+ if(i<port_number) then
+ rxs_for_allPorts(i) := input_data(i).rxFrameMaskReg(rx_class_id);
+ else
+ rxs_for_allPorts(i) := '0';
+ end if;
+ end loop;
+ return(rxs_for_allPorts);
+ end function;
+
+
+ function f_unpack_ep2tru ( -- this function needs to be changed for tru testbench to work
+ input_data: std_logic_vector
+ ) return t_ep2tru is
+ variable entry: t_ep2tru;
+ begin
+ entry.status := input_data(0);
+-- entry.ctrlRd := input_data(1);
+-- entry.rx_pck := input_data(2);
+-- entry.rx_pck_class := input_data(3+c_wrsw_pclass_number-1 downto 3);
+ return(entry);
+ end function;
+
+ function f_pack_tru2ep ( -- this function needs to be changed for tru testbench to work
+ input_data: t_tru2ep
+ ) return std_logic_vector is
+ variable entry: std_logic_vector(3+c_wrsw_pclass_number+
+ c_wrsw_pause_delay_width+
+ c_wrsw_max_queue_number-1 downto 0);
+ begin
+-- entry(0) := input_data.ctrlWr;
+-- entry(1) := input_data.tx_pck;
+-- entry(2+ c_wrsw_pclass_number-1 downto 2) := input_data.tx_pck_class;
+-- entry(2+ c_wrsw_pclass_number) := input_data.pauseSend;
+-- entry(2+ c_wrsw_pclass_number+1+c_wrsw_pause_delay_width-1 downto
+-- 2+ c_wrsw_pclass_number+1) := input_data.pauseTime;
+-- entry(2+ c_wrsw_pclass_number+1+c_wrsw_pause_delay_width+
+-- c_wrsw_max_queue_number-1 downto
+-- 2+ c_wrsw_pclass_number+1+c_wrsw_pause_delay_width) := input_data.outQueueBlockMask;
+ return(entry);
+ end function;
+
+ function f_unpack_rtu (
+ input_data: std_logic_vector;
+ port_number: integer
+ ) return t_rtu2tru is
+ variable entry: t_rtu2tru;
+ variable i : integer;
+ begin
+ entry.pass_all(port_number-1 downto 0) := input_data(1*port_number-1 downto 0*port_number);
+ entry.forward_bpdu_only(port_number-1 downto 0) := input_data(2*port_number-1 downto 1*port_number);
+ entry.request_valid(port_number-1 downto 0) := input_data(3*port_number-1 downto 2*port_number);
+-- for i in 0 to port_number-1 loop
+-- entry.priorities(i) := input_data(3*port_number+(i+1)*c_wrsw_prio_width-1 downto 3*port_number+i*c_wrsw_prio_width);
+-- end loop;
+ entry.pass_all(c_RTU_MAX_PORTS-1 downto port_number) := (others =>'0');
+ entry.forward_bpdu_only(c_RTU_MAX_PORTS-1 downto port_number) := (others =>'0');
+ entry.request_valid(c_RTU_MAX_PORTS-1 downto port_number) := (others =>'0');
+
+ return(entry);
+ end function;
+
+ -------------------------------------- pattern -------------------------------------------------
+ function f_pattern_port_down (
+ endpoints_i : t_tru_endpoints;
+ pattern_width_i : integer
+ ) return std_logic_vector is
+ variable pattern_o : std_logic_vector(pattern_width_i-1 downto 0);
+ begin
+ pattern_o := not (endpoints_i.status(pattern_width_i-1 downto 0));
+ return(pattern_o);
+ end function;
+
+ function f_pattern_quick_fwd (
+ endpoints_i : t_tru_endpoints;
+ config_i : t_tru_config;
+ pattern_width_i : integer
+ ) return std_logic_vector is
+ variable pattern_o : std_logic_vector(pattern_width_i-1 downto 0);
+ variable rxFrameNumber : integer range 0 to endpoints_i.rxFrameMaskReg'length-1;
+ begin
+ rxFrameNumber := to_integer(unsigned(config_i.hwframe_rx_fwd));
+ pattern_o := endpoints_i.rxFrameMaskReg(rxFrameNumber)(pattern_width_i-1 downto 0);
+ return(pattern_o);
+ end function;
+
+ function f_pattern_quick_blk (
+ endpoints_i : t_tru_endpoints;
+ config_i : t_tru_config;
+ pattern_width_i : integer
+ ) return std_logic_vector is
+ variable pattern_o : std_logic_vector(pattern_width_i-1 downto 0);
+ variable rxFrameNumber : integer range 0 to endpoints_i.rxFrameMaskReg'length-1;
+ begin
+ rxFrameNumber := to_integer(unsigned(config_i.hwframe_rx_blk));
+ pattern_o := endpoints_i.rxFrameMaskReg(rxFrameNumber)(pattern_width_i-1 downto 0);
+ return(pattern_o);
+ end function;
+
+ function f_pattern_aggr_gr_id (
+ endpoints_i : t_tru_endpoints;
+ tru_req_i : t_tru_request;
+ portID_i : std_logic_vector;
+ config_i : t_tru_config;
+ pattern_width_i : integer;
+ port_number_i : integer
+ ) return std_logic_vector is
+ variable pattern_o : std_logic_vector(pattern_width_i-1 downto 0);
+ variable rxPort : integer range 0 to port_number_i-1;
+ variable zeros : std_logic_vector(3 downto 0) := "0000";
+ begin
+ rxPort := to_integer(unsigned(portID_i));
+ if(tru_req_i.isHP = '1') then
+ pattern_o := f_aggr_dist_fun(endpoints_i,
+ tru_req_i,
+ portID_i,
+ config_i.lacr_agg_df_hp_id, -- aggregation group ID
+ pattern_width_i,
+ port_number_i);
+ elsif(tru_req_i.isBR = '1') then
+ pattern_o := f_aggr_dist_fun(endpoints_i,
+ tru_req_i,
+ portID_i,
+ config_i.lacr_agg_df_br_id,
+ pattern_width_i,
+ port_number_i);
+ else
+ pattern_o := f_aggr_dist_fun(endpoints_i,
+ tru_req_i,
+ portID_i,
+ config_i.lacr_agg_df_un_id,
+ pattern_width_i,
+ port_number_i);
+ end if;
+
+ return(pattern_o);
+ end function;
+
+ function f_pattern_rx_port (
+ tru_req_i : t_tru_request;
+ pattern_width_i : integer
+ ) return std_logic_vector is
+ variable pattern_o : std_logic_vector(pattern_width_i-1 downto 0);
+ begin
+ pattern_o := tru_req_i.reqMask(pattern_width_i-1 downto 0);
+ return(pattern_o);
+ end function;
+
+ function f_aggr_dist_fun (
+ endpoints_i : t_tru_endpoints;
+ tru_req_i : t_tru_request;
+ portID_i : std_logic_vector;
+ aggr_df_id_i : std_logic_vector;
+ pattern_width_i : integer;
+ port_number_i : integer
+ ) return std_logic_vector is
+ variable pattern_o : std_logic_vector(pattern_width_i-1 downto 0);
+ variable dmac : std_logic_vector(1 downto 0);
+ variable smac : std_logic_vector(1 downto 0);
+ variable aggr_df_id : std_logic_vector(3 downto 0);
+ variable rxPort : integer range 0 to port_number_i-1;
+ begin
+
+ aggr_df_id := aggr_df_id_i(3 downto 0);
+ dmac := tru_req_i.dmac(9) & tru_req_i.dmac(8);
+ smac := tru_req_i.smac(9) & tru_req_i.smac(8);
+ rxPort := to_integer(unsigned(portID_i));
+
+ case aggr_df_id is
+ when "0000" => -- filtered pclass
+ pattern_o := endpoints_i.rxFramePerPortMask(rxPort)(pattern_width_i-1 downto 0) ;
+ when "0001" => -- dmac
+ case (dmac) is
+ when "00" =>
+ pattern_o(3 downto 0) := "0001";
+ when "01" =>
+ pattern_o(3 downto 0) := "0010";
+ when "10" =>
+ pattern_o(3 downto 0) := "0100";
+ when "11" =>
+ pattern_o(3 downto 0) := "1000";
+ when others =>
+ pattern_o(3 downto 0) := "0001";--??
+ end case;
+ pattern_o(pattern_width_i-1 downto 4) := (others =>'0');
+ when "0010" => -- sac
+ case (smac) is
+ when "00" =>
+ pattern_o(3 downto 0) := "0001";
+ when "01" =>
+ pattern_o(3 downto 0) := "0010";
+ when "10" =>
+ pattern_o(3 downto 0) := "0100";
+ when "11" =>
+ pattern_o(3 downto 0) := "1000";
+ when others =>
+ pattern_o(3 downto 0) := "0001";--??
+ end case;
+ pattern_o(pattern_width_i-1 downto 4) := (others =>'0');
+ when others => -- Default
+ pattern_o := endpoints_i.rxFramePerPortMask(rxPort)(pattern_width_i-1 downto 0) ;
+ end case;
+
+ return(pattern_o);
+
+ end function;
+
+
+end wrsw_tru_pkg;
+
+-- wbgen2 --lang=vhdl --hstyle=record --vo=tru_wishbone_slave.vhd --vpo=tru_wbgen2_pkg.vhd --doco=rtu_wishbone_slave.html tru_wishbone_slave.wb
diff --git a/modules/wrsw_tru/wrsw_tru_wb.vhd b/modules/wrsw_tru/wrsw_tru_wb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0d65f1c8a1764b7c60236c87219ba234195a2c03
--- /dev/null
+++ b/modules/wrsw_tru/wrsw_tru_wb.vhd
@@ -0,0 +1,178 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit (wrapper with WB I/F)
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_port_wrapper.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Wrapper of the xwrsw_tru top entity to be used for simulation.
+-- "_wb" because it has wishbone interface for configuration.
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-31 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * t_rtu_vlan_tab_entry
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+use work.wishbone_pkg.all; -- wishbone_{interface_mode,address_granularity}
+
+entity wrsw_tru_wb is
+ generic(
+ g_num_ports : integer := 8;
+ g_tru_subentry_num : integer := 8;
+ g_tru_subentry_width : integer := 45; -- 1+5*8+4 = (1+5*`c_num_ports+`c_pattern_mode_width)
+ g_pattern_mode_width : integer := 4;
+ g_patternID_width : integer := 4;
+ g_stableUP_treshold : integer := 100;
+ g_pclass_number : integer := 8;
+ g_tru2ep_record_width : integer := 35; -- 3+8+16+8 = (3+`c_pclass_number+`c_pause_delay_width+`c_swc_max_queue_number)
+ g_ep2tru_record_width : integer := 11; -- 3+8 = (3+`c_pclass_number)
+ g_rtu2tru_record_width: integer := 48; -- 3*8+8*3 = (3*`c_num_ports+`c_num_ports*`c_prio_width)
+ g_tru_req_record_width: integer := 115;-- 1+2*48+8+2+8 = (1+2*`c_mac_addr_width+`c_fid_width+2+`c_num_ports)
+ g_tru_resp_record_width:integer := 18; -- 1+8+1+8 = (1+`c_num_ports+1+`c_num_ports)
+ g_mt_trans_max_fr_cnt : integer := 1000;
+ g_prio_width : integer := 3;
+ g_tru_entry_num : integer := 256
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ------------------------------- I/F with RTU ----------------------------------
+ --t_tru_request
+ tru_req_i : in std_logic_vector(g_tru_req_record_width-1 downto 0);
+
+ --rtu_resp_o
+ tru_resp_o : out std_logic_vector(g_tru_resp_record_width-1 downto 0);
+
+ rtu_i : in std_logic_vector(g_rtu2tru_record_width-1 downto 0);
+
+ ep_i : in std_logic_vector(g_num_ports*g_ep2tru_record_width-1 downto 0);
+ ep_o : out std_logic_vector(g_num_ports*g_tru2ep_record_width-1 downto 0);
+
+ swc_o : out std_logic_vector(g_num_ports-1 downto 0); -- for pausing
+
+ wb_addr_i : in std_logic_vector(5 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic
+ );
+end wrsw_tru_wb;
+
+architecture rtl of wrsw_tru_wb is
+
+ constant c_tru_subentry_width : integer := (1+5*g_num_ports+g_pattern_mode_width);
+
+ type t_tru_tab_subentry_array is array(integer range <>) of
+ std_logic_vector(g_tru_subentry_width-1 downto 0);
+ type t_ep_array is array(integer range <>) of std_logic_vector(g_ep2tru_record_width-1 downto 0);
+
+ signal s_tru_req : t_tru_request;
+ signal s_tru_resp : t_tru_response;
+ signal s_tru_tab_entry : t_tru_tab_entry(g_tru_subentry_num-1 downto 0);
+ signal s_config : t_tru_config;
+ signal s_tru_tab_subentry_arr : t_tru_tab_subentry_array(g_tru_subentry_num-1 downto 0);
+ signal s_rtu : t_rtu2tru;
+ signal s_ep_in : t_ep2tru_array(g_num_ports-1 downto 0);
+ signal s_ep_out : t_tru2ep_array(g_num_ports-1 downto 0);
+ signal s_ep_arr : t_ep_array(g_num_ports-1 downto 0);
+
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+begin
+
+ X_TRU: xwrsw_tru
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num => g_tru_subentry_num,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_num_ports,
+ g_stableUP_treshold => g_stableUP_treshold,
+ g_pclass_number => g_pclass_number,
+ g_mt_trans_max_fr_cnt => g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width,
+ g_pattern_mode_width => g_pattern_mode_width,
+ g_tru_entry_num => g_tru_entry_num,
+ g_interface_mode => PIPELINED, --CLASSIC, -- PIPELINED,
+ g_address_granularity => BYTE --WORD --BYTE
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ req_i => s_tru_req,
+ resp_o => s_tru_resp,
+ rtu_i => s_rtu,
+ ep_i => s_ep_in,
+ ep_o => s_ep_out,
+-- swc_o => swc_o,
+
+ wb_i => wb_in,
+ wb_o => wb_out
+ );
+
+ s_tru_req <= f_unpack_tru_request (tru_req_i, g_num_ports);
+ tru_resp_o <= f_pack_tru_response (s_tru_resp, g_num_ports);
+ s_rtu <= f_unpack_rtu (rtu_i, g_num_ports);
+
+ G3: for i in 0 to g_num_ports-1 generate
+ s_ep_arr(i) <= ep_i((i+1)*g_ep2tru_record_width-1 downto i*g_ep2tru_record_width);
+ s_ep_in(i) <= f_unpack_ep2tru(s_ep_arr(i));
+ ep_o((i+1)*g_tru2ep_record_width-1 downto i*g_tru2ep_record_width) <= f_pack_tru2ep(s_ep_out(i));
+ end generate G3;
+
+ wb_in.adr(5 downto 0) <= wb_addr_i;
+ wb_in.dat <= wb_data_i;
+ wb_in.cyc <= wb_cyc_i;
+ wb_in.sel <= wb_sel_i;
+ wb_in.stb <= wb_stb_i;
+ wb_in.we <= wb_we_i;
+
+ wb_ack_o <= wb_out.ack;
+ wb_data_o <= wb_out.dat;
+
+end rtl;
diff --git a/modules/wrsw_tru/xwrsw_tru.vhd b/modules/wrsw_tru/xwrsw_tru.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cf401f37720bb9d2827876e0f9ef26e7ade9f93
--- /dev/null
+++ b/modules/wrsw_tru/xwrsw_tru.vhd
@@ -0,0 +1,555 @@
+-------------------------------------------------------------------------------
+-- Title : (Extended) Topology Resolution Unit
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : xwrsw_tru.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-20
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Top level of the Topology Resolution Unit (TRU) with
+-- record input/output (Extended) to make it easier connecting with other
+-- modules in the switch
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+-- THis unit takes care of hardware side of the topology resolutions - in
+-- other words, in a WR network we need to avoid network loops. A special
+-- protocol is used to make sure there are not loops. THe hardware side of
+-- this protocol is a TRU module. TRU module is as universal as possible to
+-- enable support of many different S/W protocols (e.g. RSTP, LACP).
+-- There is part of the Topology Resolution Protocol implementation in HW
+-- to make the stuff work really fast to minimize the number of frame lost
+-- while we switch-over between redundant paths
+--
+--
+-- It does the following:
+-- 1. accepts request
+-- 2. reads TRU TABLE
+-- 3. checks Patterns to be used and ports state
+-- 4. based on patterns/state/TRU_tab prepares forwarding decision.
+--
+-- Assumptions/requrements/etc:
+-- - there is a single request in single cycle - RoundRobin access to this module by
+-- all ports of RTU is assumed in the RTU
+-- - every cycle a new request can be handled
+-- - FID needs to be provided (VLAN table read by RTU
+--
+-- Pipelined response is available in 2 cycles.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-20 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all;
+use work.wrsw_tru_pkg.all;
+use work.genram_pkg.all;
+use work.tru_wbgen2_pkg.all; -- for wbgen-erated records
+use work.wishbone_pkg.all; -- wishbone_{interface_mode,address_granularity}
+
+entity xwrsw_tru is
+ generic(
+ g_num_ports : integer := 6;
+ g_tru_subentry_num : integer := 8;
+ g_pattern_width : integer := 4;
+ g_patternID_width : integer := 4;
+ g_stableUP_treshold : integer := 100;
+ g_pclass_number : integer := 8;
+ g_mt_trans_max_fr_cnt: integer := 1000;
+ g_prio_width : integer := 3;
+ g_pattern_mode_width : integer := 4;
+ g_tru_entry_num : integer := 256;
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity: t_wishbone_address_granularity := BYTE
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ -------------------------- request/rosponse (from/to RTU) ------------------------------
+ req_i : in t_tru_request;
+ resp_o : out t_tru_response;
+
+ --------------------------- I/F with RTU -----------------------------------
+ -- info from within RTU (i.e. config) necessary for TRU
+ rtu_i : in t_rtu2tru;
+
+ ----------------------- I/F with Endpoint------------------------------------
+ -- multi-port access
+ ep_i : in t_ep2tru_array(g_num_ports-1 downto 0);
+ ep_o : out t_tru2ep_array(g_num_ports-1 downto 0);
+
+ ----------------------- I/F with SW core ------------------------------------
+ -- multi-port access (bit per port)
+ swc_block_oq_req_o : out t_global_pause_request;
+
+ -- info to other moduels that TRU is enabled
+ enabled_o : out std_logic;
+ ---------------------------- WB I/F -----------------------------------------
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+
+ );
+end xwrsw_tru;
+
+architecture rtl of xwrsw_tru is
+
+ constant c_tru_subentry_width : integer := (1+5*g_num_ports+g_pattern_mode_width);
+ constant c_tru_entry_width : integer := c_tru_subentry_width*g_tru_subentry_num;
+ constant c_tru_addr_width : integer := integer(CEIL(LOG2(real(g_tru_entry_num))));
+
+ type t_tru_tab_subentry_array is array(integer range <>) of
+ std_logic_vector(c_tru_subentry_width-1 downto 0);
+ type t_wr_sub_entry_array is array(g_tru_subentry_num - 1 downto 0) of
+ std_logic_vector(c_tru_subentry_width-1 downto 0);
+
+ signal s_endpoint_array : t_tru_endpoint_array(g_num_ports-1 downto 0);
+ signal s_endpoints : t_tru_endpoints;
+ signal s_tru_tab_addr : std_logic_vector(c_tru_addr_width-1 downto 0);
+ signal s_tru_tab_entry : t_tru_tab_entry(g_tru_subentry_num - 1 downto 0);
+ signal s_config : t_tru_config;
+ signal s_tx_rt_reconf_FRM : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_trans_ep_ctr : t_trans2tru_array(g_num_ports-1 downto 0);
+ signal s_trans_rxFrameMask : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_tru_tab_rd_subentry_arr : t_tru_tab_subentry_array(g_tru_subentry_num-1 downto 0);
+ signal s_tru_rd_addr : std_logic_vector(c_tru_addr_width+1-1 downto 0);
+ signal s_tru_tab_bank : std_logic;
+ signal s_tru_tab_wr_subentry_arr : t_wr_sub_entry_array;
+ signal s_tru_wr_ena : std_logic_vector(g_tru_subentry_num-1 downto 0);
+ signal s_tru_tab_wr_index : integer range 0 to g_tru_subentry_num-1;
+ signal s_tru_wr_addr : std_logic_vector(c_tru_addr_width+1-1 downto 0);
+ signal s_tru_wr_data : std_logic_vector(c_tru_subentry_width-1 downto 0);
+ signal s_transitionFinished : std_logic;
+ signal s_transitionActive : std_logic;
+ signal s_bank_swap_on_trans : std_logic;
+ signal s_regs_towb : t_tru_in_registers;
+ signal s_regs_fromwb : t_tru_out_registers;
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+ signal s_bank_swap : std_logic;
+ signal s_port_if_ctrl : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_pinject_ctr : t_pinject_ctr_array(g_num_ports-1 downto 0);
+ -- debugging pfilter + pinjection
+ signal s_debug_port_sel : integer range 0 to 2**8-1;
+ signal s_pidr_inject : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_debug_filter : t_debug_stuff_array(g_num_ports-1 downto 0);
+ signal s_ports_req_strobe : std_logic_vector(g_num_ports-1 downto 0);
+ signal s_req_s_hp : std_logic;
+ signal s_req_s_prio : std_logic;
+ signal s_tru_ena : std_logic;
+ signal s_swc_ctrl : t_trans2sw;
+ signal s_inject_sel : t_inject_sel_array(g_num_ports-1 downto 0);
+ signal s_ep : t_tru2ep_array(g_num_ports-1 downto 0);
+ signal s_inject_ready_d : std_logic_vector(g_num_ports-1 downto 0);
+begin --rtl
+
+ U_T_PORT: tru_port
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num => g_tru_subentry_num,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_pattern_width,
+ g_tru_addr_width => c_tru_addr_width
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ tru_req_i => req_i,
+ tru_resp_o => resp_o,
+ tru_tab_addr_o => s_tru_tab_addr,
+ tru_tab_entry_i => s_tru_tab_entry,
+ endpoints_i => s_endpoints,
+ config_i => s_config,
+ tru_tab_bank_swap_i=> s_bank_swap,
+ globIngMask_dbg_o => s_regs_towb.ptrdr_ging_mask_i(g_num_ports-1 downto 0),
+ txFrameMask_o => s_tx_rt_reconf_FRM
+ );
+ s_regs_towb.ptrdr_ging_mask_i(31 downto g_num_ports) <= (others => '0');
+
+ G_ENDP: for i in 0 to g_num_ports-1 generate
+ U_T_ENDPOINT: tru_endpoint
+ generic map(
+ g_num_ports => g_num_ports,
+ g_pclass_number => g_pclass_number,
+ g_tru_subentry_num => g_tru_subentry_num,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_pattern_width,
+ g_stableUP_treshold=> g_stableUP_treshold
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ port_if_i => ep_i(i),
+ port_if_ctrl_o => s_port_if_ctrl(i), --ep_o(i).ctrlWr,
+ rtu_pass_all_i => rtu_i.pass_all(i),
+ endpoint_o => s_endpoint_array(i),
+ reset_rxFlag_i => s_config.gcr_rx_frame_reset(i)
+ );
+ ep_o(i).link_kill <= not s_port_if_ctrl(i) when (s_tru_ena = '1') else '0';
+ end generate G_ENDP;
+
+ -- generating strobe to count packets which enter switch after receiving MARKER/sending PAUSE
+ -- * if transition priority (trans_prio) configured to 0, then we use indication of HP frames
+ -- from fast match
+ s_req_s_hp <= req_i.valid and req_i.isHP when (s_config.tcr_trans_prio_mode = '0') else
+ '0';
+ -- * if trans_prio is set, we take packets with indicated priority (more for testing)
+ s_req_s_prio <= req_i.valid when (s_config.tcr_trans_prio_mode = '1' and
+ s_config.tcr_trans_prio = req_i.prio ) else
+ '0';
+
+ -- generating the strobe
+ s_ports_req_strobe <= req_i.reqMask(g_num_ports-1 downto 0) when (s_req_s_hp = '1' or
+ s_req_s_prio = '1') else
+ (others => '0');
+
+ U_TRANSITION: tru_transition
+ generic map(
+ g_num_ports => g_num_ports,
+ g_mt_trans_max_fr_cnt => g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ endpoints_i => s_endpoints,
+ config_i => s_config,
+ tru_tab_bank_i => s_tru_tab_bank,
+ tru_tab_bank_o => s_bank_swap_on_trans,
+ statTransActive_o => s_transitionActive,
+ statTransFinished_o => s_transitionFinished,
+ rxFrameMask_i => s_trans_rxFrameMask,
+ rtu_i => rtu_i,
+ ports_req_strobe_i => s_ports_req_strobe, -- new shit
+ sw_o => s_swc_ctrl,
+ ep_o => s_trans_ep_ctr
+ );
+ s_trans_rxFrameMask <= s_endpoints.rxFrameMask(to_integer(unsigned(s_config.tcr_trans_rx_id)))(g_num_ports-1 downto 0);
+
+ G_ENDP_CONX: for i in 0 to g_num_ports-1 generate
+ s_endpoints.status(i) <= s_endpoint_array(i).status ;
+ s_endpoints.stableUp(i) <= s_endpoint_array(i).stableUp;
+ s_endpoints.rxFramePerPortMask(i)(c_wrsw_pclass_number-1 downto 0) <= s_endpoint_array(i).rxFrameMask;
+ s_endpoints.inject_ready(i) <= s_endpoint_array(i).inject_ready;
+ end generate G_ENDP_CONX;
+
+ s_endpoints.status(s_endpoints.status'length-1 downto g_num_ports) <= (others =>'0');
+ s_endpoints.stableUp(s_endpoints.stableUp'length-1 downto g_num_ports) <= (others =>'0');
+ s_endpoints.inject_ready(s_endpoints.inject_ready'length-1 downto g_num_ports) <= (others =>'0');
+
+ G_FRAME_MASK: for i in 0 to g_pclass_number-1 generate
+ s_endpoints.rxFrameMask(i) <= f_rxFrameMaskInv(s_endpoint_array,i,g_num_ports);
+ s_endpoints.rxFrameMaskReg(i) <= f_rxFrameMaskRegInv(s_endpoint_array,i,g_num_ports);
+ end generate G_FRAME_MASK;
+
+ CTRL_PINJECT: process(clk_i, rst_n_i) -- this is not really optimal for resources... shit
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ CLEAR: for i in 0 to g_num_ports-1 loop
+ s_inject_sel(i).dbg <= '0';
+ s_inject_sel(i).fwd <= '0';
+ s_inject_sel(i).blk <= '0';
+ s_inject_sel(i).pause <= '0';
+ s_inject_ready_d(i) <= '0';
+ end loop;
+ else
+
+ -- below we register the info from different modules about hw-injection of frames.
+ -- This is needed as one injection can be done at a time and many injection request
+ -- can (theoretically) happen at the same time.
+ -- We remember each request and hw-inject framess with the following priority:
+ -- 1) dbg msg - from WB
+ -- 2) quick forward - from R-T Re-config module or transition (if a request is
+ -- is made when other is being handled ... we don't care, since
+ -- the effect is achieved with the handled one
+ -- 3) quick block - from transition
+ -- 4) pause - from transition (it can be delayed since we count the received
+ -- frames after we requested the PAUSE -- this is to accommodate
+ -- the delay between requesting the PAUSE frame and the pause
+ -- stopping the traffic
+ -- The stored values of s_inject_sel are used to select the values of
+ -- *inject_packet_sel* and *inject_user_value* to be fed into the module
+
+ REMEMBER: for i in 0 to g_num_ports-1 loop
+ if(s_pidr_inject(i) ='1' and s_inject_sel(i).dbg = '0') then
+ s_inject_sel(i).dbg <= '1';
+ elsif(s_inject_ready_d(i) = '0' and ep_i(i).inject_ready = '1' and -- finished injection
+ s_inject_sel(i).dbg = '1') then
+ s_inject_sel(i).dbg <= '0';
+ end if;
+
+ if((s_tx_rt_reconf_FRM(i) ='1' or s_trans_ep_ctr(i).hwframe_fwd = '1') and s_inject_sel(i).fwd = '0') then -- quick forward
+ s_inject_sel(i).fwd <= '1';
+ elsif(s_inject_ready_d(i) = '0' and ep_i(i).inject_ready = '1' and -- finished injection
+ s_inject_sel(i).dbg = '0' and s_inject_sel(i).fwd = '1') then
+ s_inject_sel(i).fwd <= '0';
+ end if;
+
+ if(s_trans_ep_ctr(i).hwframe_blk ='1' and s_inject_sel(i).blk = '0') then -- quick block
+ s_inject_sel(i).blk <='1';
+ elsif(s_inject_ready_d(i) = '0' and ep_i(i).inject_ready = '1' and -- finished injection
+ s_inject_sel(i).dbg = '0' and s_inject_sel(i).fwd = '0' and s_inject_sel(i).blk ='1') then
+ s_inject_sel(i).blk <='0';
+ end if;
+
+ if(s_trans_ep_ctr(i).pauseSend = '1' and s_inject_sel(i).pause ='0') then
+ s_inject_sel(i).pause <='1';
+ elsif(s_inject_ready_d(i) = '0' and ep_i(i).inject_ready = '1' and -- finished injection
+ s_inject_sel(i).dbg = '0' and s_inject_sel(i).fwd = '0' and s_inject_sel(i).blk = '0' and
+ s_inject_sel(i).pause = '1') then
+ s_inject_sel(i).pause <='0';
+ end if;
+
+ s_inject_ready_d(i) <= ep_i(i).inject_ready; -- detect end of injection
+ end loop;
+ end if;
+ end if;
+ end process;
+
+ -- the proper mux to feed into injection control of Endpoints
+ G_EP_O: for i in 0 to g_num_ports-1 generate
+
+ s_ep(i).inject_packet_sel <= s_regs_fromwb.pidr_psel_o when (s_inject_sel(i).dbg ='1') else
+ s_config.hwframe_tx_fwd(2 downto 0) when (s_inject_sel(i).fwd ='1') else
+ s_config.hwframe_tx_blk(2 downto 0) when (s_inject_sel(i).blk ='1') else
+ "000" when (s_inject_sel(i).pause ='1') else
+ "000";
+
+ s_ep(i).inject_user_value <= s_regs_fromwb.pidr_uval_o when (s_inject_sel(i).dbg ='1') else
+ x"00" & s_regs_fromwb.hwfc_tx_fwd_ub_o when (s_inject_sel(i).fwd ='1') else
+ x"00" & s_regs_fromwb.hwfc_tx_blk_ub_o when (s_inject_sel(i).blk ='1') else
+ s_regs_fromwb.tcpbr_trans_pause_time_o when (s_inject_sel(i).pause ='1') else
+ x"0000";
+
+ s_ep(i).inject_req <= '1' when (s_inject_sel(i).dbg = '1' and ep_i(i).inject_ready = '1' and s_inject_ready_d(i) = '1') else
+ '1' when (s_inject_sel(i).fwd = '1' and ep_i(i).inject_ready = '1' and s_inject_ready_d(i) = '1') else
+ '1' when (s_inject_sel(i).blk = '1' and ep_i(i).inject_ready = '1' and s_inject_ready_d(i) = '1') else
+ '1' when (s_inject_sel(i).pause = '1' and ep_i(i).inject_ready = '1' and s_inject_ready_d(i) = '1') else
+ '0';
+
+ ep_o(i).inject_packet_sel <= s_ep(i).inject_packet_sel when (s_tru_ena = '1') else (others => '0');
+ ep_o(i).inject_user_value <= s_ep(i).inject_user_value when (s_tru_ena = '1') else (others => '0');
+ ep_o(i).inject_req <= s_ep(i).inject_req when (s_tru_ena = '1') else '0';
+ ep_o(i).fc_pause_req <= '0'; --s_trans_ep_ctr(i).pauseSend;
+ ep_o(i).fc_pause_delay <= (others => '0'); --s_trans_ep_ctr(i).pauseTime;
+
+ end generate G_EP_O;
+
+ G_TRU_TAB: for i in 0 to g_tru_subentry_num-1 generate
+ U_TRU_TAB : generic_dpram
+ generic map (
+ g_data_width => c_tru_subentry_width,
+ g_size => 2*g_tru_entry_num,
+ g_with_byte_enable => false,
+ g_dual_clock => false)
+ port map (
+ rst_n_i => rst_n_i,
+ clka_i => clk_i,
+ clkb_i => '0',
+ bwea_i => (others => '1'),
+ wea_i => s_tru_wr_ena(i),
+ aa_i => s_tru_wr_addr,
+ da_i => s_tru_wr_data,
+ ab_i => s_tru_rd_addr,
+ qb_o => s_tru_tab_rd_subentry_arr(i));
+ end generate G_TRU_TAB;
+
+ s_tru_rd_addr <= s_tru_tab_bank & s_tru_tab_addr;
+
+ G1: for i in 0 to g_tru_subentry_num-1 generate
+ s_tru_tab_entry(i) <= f_unpack_tru_subentry(s_tru_tab_rd_subentry_arr(i),g_num_ports);
+ s_tru_wr_ena(i) <= s_regs_fromwb.ttr0_update_o when (i = s_tru_tab_wr_index) else '0';
+ end generate G1;
+
+ U_WB_ADAPTER : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => true,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_i,
+ rst_n_i => rst_n_i,
+ slave_i => wb_i,
+ slave_o => wb_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ U_WISHBONE_IF: tru_wishbone_slave
+ port map(
+ rst_n_i => rst_n_i,
+ wb_clk_i => clk_i,
+-- wb_addr_i => wb_in.adr(3 downto 0),
+ wb_addr_i => wb_in.adr(4 downto 0),
+ wb_data_i => wb_in.dat,
+ wb_data_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
+ regs_i => s_regs_towb,
+ regs_o => s_regs_fromwb
+ );
+
+ s_bank_swap <= s_regs_fromwb.gcr_tru_bank_o or s_bank_swap_on_trans ;
+
+ CTRL_BANK: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ s_tru_tab_bank<= '0';
+ else
+ if(s_bank_swap = '1') then
+ s_tru_tab_bank<= not s_tru_tab_bank;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ s_regs_towb.gsr0_stat_bank_i <= s_tru_tab_bank;
+ s_regs_towb.gsr0_stat_stb_up_i <= s_endpoints.stableUp(s_regs_towb.gsr0_stat_stb_up_i'length-1 downto 0);
+ s_regs_towb.gsr1_stat_up_i <= s_endpoints.status(s_regs_towb.gsr1_stat_up_i'length-1 downto 0);
+ s_regs_towb.tsr_trans_stat_active_i <= s_transitionActive;
+ s_regs_towb.tsr_trans_stat_finished_i <= s_transitionFinished;
+
+ s_config.gcr_g_ena <= s_regs_fromwb.gcr_g_ena_o ;
+ s_config.gcr_rx_frame_reset <= s_regs_fromwb.gcr_rx_frame_reset_o ;
+ s_config.mcr_pattern_mode_rep <= s_regs_fromwb.mcr_pattern_mode_rep_o ;
+ s_config.mcr_pattern_mode_add <= s_regs_fromwb.mcr_pattern_mode_add_o ;
+ s_config.mcr_pattern_mode_sub <= s_regs_fromwb.mcr_pattern_mode_sub_o ;
+ s_config.lacr_agg_df_hp_id <= s_regs_fromwb.lacr_agg_df_hp_id_o ;
+ s_config.lacr_agg_df_br_id <= s_regs_fromwb.lacr_agg_df_br_id_o ;
+ s_config.lacr_agg_df_un_id <= s_regs_fromwb.lacr_agg_df_un_id_o ;
+-- s_config.lagt_gr_id_mask(0) <= s_regs_fromwb.lagt_lagt_gr_id_mask_0_o ;
+-- s_config.lagt_gr_id_mask(1) <= s_regs_fromwb.lagt_lagt_gr_id_mask_1_o ;
+-- s_config.lagt_gr_id_mask(2) <= s_regs_fromwb.lagt_lagt_gr_id_mask_2_o ;
+-- s_config.lagt_gr_id_mask(3) <= s_regs_fromwb.lagt_lagt_gr_id_mask_3_o ;
+-- s_config.lagt_gr_id_mask(4) <= s_regs_fromwb.lagt_lagt_gr_id_mask_4_o ;
+-- s_config.lagt_gr_id_mask(5) <= s_regs_fromwb.lagt_lagt_gr_id_mask_5_o ;
+-- s_config.lagt_gr_id_mask(6) <= s_regs_fromwb.lagt_lagt_gr_id_mask_6_o ;
+-- s_config.lagt_gr_id_mask(7) <= s_regs_fromwb.lagt_lagt_gr_id_mask_7_o ;
+ s_config.tcr_trans_ena <= s_regs_fromwb.tcgr_trans_ena_o ;
+ s_config.tcr_trans_clr <= s_regs_fromwb.tcgr_trans_clear_o ;
+ s_config.tcr_trans_mode <= s_regs_fromwb.tcgr_trans_mode_o ;
+ s_config.tcr_trans_rx_id <= s_regs_fromwb.tcgr_trans_rx_id_o ;
+ s_config.tcr_trans_prio <= s_regs_fromwb.tcgr_trans_prio_o ;
+ s_config.tcr_trans_prio_mode <= s_regs_fromwb.tcgr_trans_prio_mode_o ;
+ s_config.tcr_trans_port_a_id <= s_regs_fromwb.tcpr_trans_port_a_id_o ;
+ s_config.tcr_trans_port_a_valid <= s_regs_fromwb.tcpr_trans_port_a_valid_o ;
+ s_config.tcr_trans_port_b_id <= s_regs_fromwb.tcpr_trans_port_b_id_o ;
+ s_config.tcr_trans_port_b_valid <= s_regs_fromwb.tcpr_trans_port_b_valid_o ;
+ s_config.tcr_trans_pause_time <= s_regs_fromwb.tcpbr_trans_pause_time_o ;
+ s_config.tcr_trans_block_time <= s_regs_fromwb.tcpbr_trans_block_time_o ;
+ s_config.rtrcr_rtr_ena <= s_regs_fromwb.rtrcr_rtr_ena_o ;
+ s_config.rtrcr_rtr_reset <= s_regs_fromwb.rtrcr_rtr_reset_o ;
+ s_config.rtrcr_rtr_mode <= s_regs_fromwb.rtrcr_rtr_mode_o ;
+ s_config.rtrcr_rtr_rx <= s_regs_fromwb.rtrcr_rtr_rx_o ;
+ s_config.rtrcr_rtr_tx <= s_regs_fromwb.rtrcr_rtr_tx_o ;
+
+ s_config.hwframe_rx_fwd <= s_regs_fromwb.hwfc_rx_fwd_id_o ;
+ s_config.hwframe_tx_fwd <= s_regs_fromwb.hwfc_tx_fwd_id_o ;
+ s_config.hwframe_rx_blk <= s_regs_fromwb.hwfc_rx_blk_id_o ;
+ s_config.hwframe_tx_blk <= s_regs_fromwb.hwfc_tx_blk_id_o ;
+
+ s_tru_tab_wr_index <= to_integer(unsigned(s_regs_fromwb.ttr0_sub_fid_o));
+ s_tru_wr_addr <= (not s_tru_tab_bank) & s_regs_fromwb.ttr0_fid_o;
+ s_tru_wr_data <= s_regs_fromwb.ttr0_patrn_mode_o &
+ s_regs_fromwb.ttr5_patrn_mask_o (g_num_ports-1 downto 0) &
+ s_regs_fromwb.ttr4_patrn_match_o (g_num_ports-1 downto 0) &
+ s_regs_fromwb.ttr3_ports_mask_o (g_num_ports-1 downto 0) &
+ s_regs_fromwb.ttr2_ports_egress_o (g_num_ports-1 downto 0) &
+ s_regs_fromwb.ttr1_ports_ingress_o(g_num_ports-1 downto 0) &
+ s_regs_fromwb.ttr0_mask_valid_o ;
+ -- TODO:
+ swc_block_oq_req_o.ports <= s_swc_ctrl.blockPortsMask when (s_tru_ena = '1') else (others => '0');
+ swc_block_oq_req_o.req <= s_swc_ctrl.blockReq when (s_tru_ena = '1') else '0';
+ swc_block_oq_req_o.quanta <= s_swc_ctrl.blockTime when (s_tru_ena = '1') else (others => '0');
+ swc_block_oq_req_o.classes <= s_swc_ctrl.blockQueuesMask when (s_tru_ena = '1') else (others => '0');
+
+ enabled_o <= s_regs_fromwb.gcr_g_ena_o ;
+ s_tru_ena <= s_regs_fromwb.gcr_g_ena_o ;
+ --------------
+ s_debug_port_sel <= to_integer(unsigned(s_regs_fromwb.dps_pid_o));
+
+ DEBUG_CTRL_GEN: for i in 0 to g_num_ports-1 generate
+ s_pidr_inject(i) <= s_regs_fromwb.pidr_inject_o when (i = s_debug_port_sel) else
+ '0';
+ end generate;
+
+ DEBUG: process(clk_i, rst_n_i)
+ begin
+ if rising_edge(clk_i) then
+ if(rst_n_i = '0') then
+ CLEAR: for i in 0 to g_num_ports-1 loop
+ s_debug_filter(i).pfdr_class <= (others =>'0');
+ s_debug_filter(i).pfdr_cnt <= (others =>'0');
+ end loop;
+ s_regs_towb.pidr_iready_i <= '0';
+ s_regs_towb.pfdr_class_i <= (others =>'0');
+ s_regs_towb.pfdr_cnt_i <= (others =>'0');
+ else
+ REMEMBER: for i in 0 to g_num_ports-1 loop
+ if(ep_i(i).pfilter_done ='1' and ep_i(i).pfilter_pclass /= x"00") then -- something filtered
+ if(s_debug_port_sel = i and s_regs_fromwb.pfdr_clr_o = '1') then
+ s_debug_filter(i).pfdr_class <= ep_i(i).pfilter_pclass;
+ s_debug_filter(i).pfdr_cnt(7 downto 0) <= x"01"; -- filtered
+ s_debug_filter(i).pfdr_cnt(15 downto 8) <= x"01";
+ else
+ s_debug_filter(i).pfdr_class <= ep_i(i).pfilter_pclass or s_debug_filter(i).pfdr_class;
+ s_debug_filter(i).pfdr_cnt(7 downto 0) <= std_logic_vector(unsigned(s_debug_filter(i).pfdr_cnt(7 downto 0))+1);
+ s_debug_filter(i).pfdr_cnt(15 downto 8) <= std_logic_vector(unsigned(s_debug_filter(i).pfdr_cnt(15 downto 8))+1);
+ end if;
+ elsif(ep_i(i).pfilter_done ='1' and ep_i(i).pfilter_pclass = x"00") then -- non-recognzied pck
+ if(s_debug_port_sel = i and s_regs_fromwb.pfdr_clr_o = '1') then
+ s_debug_filter(i).pfdr_cnt(15 downto 8) <= x"01";
+ else
+ s_debug_filter(i).pfdr_cnt(15 downto 8) <= std_logic_vector(unsigned(s_debug_filter(i).pfdr_cnt(15 downto 8))+1);
+ end if;
+ elsif(s_debug_port_sel = i and s_regs_fromwb.pfdr_clr_o = '1') then
+ s_debug_filter(i).pfdr_class <= (others =>'0');
+ s_debug_filter(i).pfdr_cnt <= (others =>'0');
+ end if;
+ end loop;
+
+ s_regs_towb.pidr_iready_i <= ep_i(s_debug_port_sel).inject_ready;
+ s_regs_towb.pfdr_class_i <= s_debug_filter(s_debug_port_sel).pfdr_class;
+ s_regs_towb.pfdr_cnt_i <= s_debug_filter(s_debug_port_sel).pfdr_cnt;
+
+ end if;
+ end if;
+ end process;
+
+end rtl;
diff --git a/sim/pstats_gen.sv b/sim/pstats_gen.sv
new file mode 100644
index 0000000000000000000000000000000000000000..27046de2cf1aa92eee4f8758af2262efed6abceb
--- /dev/null
+++ b/sim/pstats_gen.sv
@@ -0,0 +1,59 @@
+module pstats_gen (rst_n_i, clk_i, trig_o);
+
+ parameter g_trig_width = 10;
+ parameter g_time = 25;
+
+ input rst_n_i;
+ input clk_i;
+ output [g_trig_width-1:0]trig_o;
+
+ integer num[g_trig_width-1:0], rnd[g_trig_width-1:0];
+ reg [g_trig_width-1:0]trig_o;
+
+ reg stop;
+
+ initial
+ begin
+ fork
+ begin
+ stop = 1'b1;
+ #21496us
+// #236us
+ stop = 1'b0;
+ end
+ join_none
+ end
+
+ genvar n;
+ generate
+ for(n=0; n<g_trig_width; n=n+1) begin
+ //initial
+ //begin
+ // for(rnd[n]=$urandom()%10; rnd[n]>0; rnd[n]=rnd[n]-1)
+ // #20ns;
+ //end
+ initial
+ begin
+ #(n*10ns);
+ end
+ always //@(posedge clk_i)
+ begin
+ trig_o[n] = 1'b0;
+ //#100ns;
+ //rnd[n] = $urandom() %100;
+ //num[n] = $urandom() %100;
+ //if(num[n]<rnd[n])
+ begin
+ trig_o[n] = 1'b1 & stop;
+ #10ns;
+ trig_o[n] = 1'b0;
+ #310ns; //310 + 10 = 320 -> minimum frame size
+ end
+ //for(rnd[n]=$urandom()%10; rnd[n]>0; rnd[n]=rnd[n]-1)
+ // #20ns;
+ end
+ end
+ endgenerate
+
+
+endmodule
diff --git a/sim/regs/hwdu_regs.v b/sim/regs/hwdu_regs.v
new file mode 100644
index 0000000000000000000000000000000000000000..befc6392c0d0f17a50437cba7182ca50225cb060
--- /dev/null
+++ b/sim/regs/hwdu_regs.v
@@ -0,0 +1,8 @@
+`define ADDR_HWDU_CR 3'h0
+`define HWDU_CR_ADR_OFFSET 0
+`define HWDU_CR_ADR 32'h0000ffff
+`define HWDU_CR_RD_ERR_OFFSET 30
+`define HWDU_CR_RD_ERR 32'h40000000
+`define HWDU_CR_RD_EN_OFFSET 31
+`define HWDU_CR_RD_EN 32'h80000000
+`define ADDR_HWDU_REG_VAL 3'h4
diff --git a/sim/regs/rtu_regs.vh b/sim/regs/rtu_regs.vh
index 99bd51a7b9fdef2c98d0715b96e8273688e29115..c47c3b5d4879e83b5532b56d6adf3d06de6e7c75 100644
--- a/sim/regs/rtu_regs.vh
+++ b/sim/regs/rtu_regs.vh
@@ -5,6 +5,8 @@
`define RTU_GCR_MFIFOTRIG 32'h00000002
`define RTU_GCR_POLY_VAL_OFFSET 8
`define RTU_GCR_POLY_VAL 32'h00ffff00
+`define RTU_GCR_RTU_VERSION_OFFSET 24
+`define RTU_GCR_RTU_VERSION 32'h0f000000
`define ADDR_RTU_PSR 11'h4
`define RTU_PSR_PORT_SEL_OFFSET 0
`define RTU_PSR_PORT_SEL 32'h000000ff
@@ -41,31 +43,83 @@
`define ADDR_RTU_VTR2 11'h10
`define RTU_VTR2_PORT_MASK_OFFSET 0
`define RTU_VTR2_PORT_MASK 32'hffffffff
-`define ADDR_RTU_EIC_IDR 11'h20
+`define ADDR_RTU_RX_CTR 11'h14
+`define RTU_RX_CTR_FF_MAC_BR_OFFSET 0
+`define RTU_RX_CTR_FF_MAC_BR 32'h00000001
+`define RTU_RX_CTR_FF_MAC_RANGE_OFFSET 1
+`define RTU_RX_CTR_FF_MAC_RANGE 32'h00000002
+`define RTU_RX_CTR_FF_MAC_SINGLE_OFFSET 2
+`define RTU_RX_CTR_FF_MAC_SINGLE 32'h00000004
+`define RTU_RX_CTR_FF_MAC_LL_OFFSET 3
+`define RTU_RX_CTR_FF_MAC_LL 32'h00000008
+`define RTU_RX_CTR_FF_MAC_PTP_OFFSET 4
+`define RTU_RX_CTR_FF_MAC_PTP 32'h00000010
+`define RTU_RX_CTR_MR_ENA_OFFSET 5
+`define RTU_RX_CTR_MR_ENA 32'h00000020
+`define RTU_RX_CTR_AT_FMATCH_TOO_SLOW_OFFSET 6
+`define RTU_RX_CTR_AT_FMATCH_TOO_SLOW 32'h00000040
+`define RTU_RX_CTR_PRIO_MASK_OFFSET 8
+`define RTU_RX_CTR_PRIO_MASK 32'h0000ff00
+`define RTU_RX_CTR_HP_FW_CPU_ENA_OFFSET 16
+`define RTU_RX_CTR_HP_FW_CPU_ENA 32'h00010000
+`define RTU_RX_CTR_UREC_FW_CPU_ENA_OFFSET 17
+`define RTU_RX_CTR_UREC_FW_CPU_ENA 32'h00020000
+`define RTU_RX_CTR_LEARN_DST_ENA_OFFSET 18
+`define RTU_RX_CTR_LEARN_DST_ENA 32'h00040000
+`define RTU_RX_CTR_FORCE_FAST_MATCH_ENA_OFFSET 24
+`define RTU_RX_CTR_FORCE_FAST_MATCH_ENA 32'h01000000
+`define RTU_RX_CTR_FORCE_FULL_MATCH_ENA_OFFSET 25
+`define RTU_RX_CTR_FORCE_FULL_MATCH_ENA 32'h02000000
+`define ADDR_RTU_RX_FF_MAC_R0 11'h18
+`define RTU_RX_FF_MAC_R0_LO_OFFSET 0
+`define RTU_RX_FF_MAC_R0_LO 32'hffffffff
+`define ADDR_RTU_RX_FF_MAC_R1 11'h1c
+`define RTU_RX_FF_MAC_R1_HI_ID_OFFSET 0
+`define RTU_RX_FF_MAC_R1_HI_ID 32'h0000ffff
+`define RTU_RX_FF_MAC_R1_ID_OFFSET 16
+`define RTU_RX_FF_MAC_R1_ID 32'h00ff0000
+`define RTU_RX_FF_MAC_R1_TYPE_OFFSET 24
+`define RTU_RX_FF_MAC_R1_TYPE 32'h01000000
+`define RTU_RX_FF_MAC_R1_VALID_OFFSET 25
+`define RTU_RX_FF_MAC_R1_VALID 32'h02000000
+`define ADDR_RTU_CPU_PORT 11'h20
+`define RTU_CPU_PORT_MASK_OFFSET 0
+`define RTU_CPU_PORT_MASK 32'hffffffff
+`define ADDR_RTU_RX_MP_R0 11'h24
+`define RTU_RX_MP_R0_DST_SRC_OFFSET 0
+`define RTU_RX_MP_R0_DST_SRC 32'h00000001
+`define RTU_RX_MP_R0_RX_TX_OFFSET 1
+`define RTU_RX_MP_R0_RX_TX 32'h00000002
+`define RTU_RX_MP_R0_MASK_ID_OFFSET 16
+`define RTU_RX_MP_R0_MASK_ID 32'hffff0000
+`define ADDR_RTU_RX_MP_R1 11'h28
+`define RTU_RX_MP_R1_MASK_OFFSET 0
+`define RTU_RX_MP_R1_MASK 32'hffffffff
+`define ADDR_RTU_EIC_IDR 11'h40
`define RTU_EIC_IDR_NEMPTY_OFFSET 0
`define RTU_EIC_IDR_NEMPTY 32'h00000001
-`define ADDR_RTU_EIC_IER 11'h24
+`define ADDR_RTU_EIC_IER 11'h44
`define RTU_EIC_IER_NEMPTY_OFFSET 0
`define RTU_EIC_IER_NEMPTY 32'h00000001
-`define ADDR_RTU_EIC_IMR 11'h28
+`define ADDR_RTU_EIC_IMR 11'h48
`define RTU_EIC_IMR_NEMPTY_OFFSET 0
`define RTU_EIC_IMR_NEMPTY 32'h00000001
-`define ADDR_RTU_EIC_ISR 11'h2c
+`define ADDR_RTU_EIC_ISR 11'h4c
`define RTU_EIC_ISR_NEMPTY_OFFSET 0
`define RTU_EIC_ISR_NEMPTY 32'h00000001
-`define ADDR_RTU_UFIFO_R0 11'h30
+`define ADDR_RTU_UFIFO_R0 11'h50
`define RTU_UFIFO_R0_DMAC_LO_OFFSET 0
`define RTU_UFIFO_R0_DMAC_LO 32'hffffffff
-`define ADDR_RTU_UFIFO_R1 11'h34
+`define ADDR_RTU_UFIFO_R1 11'h54
`define RTU_UFIFO_R1_DMAC_HI_OFFSET 0
`define RTU_UFIFO_R1_DMAC_HI 32'h0000ffff
-`define ADDR_RTU_UFIFO_R2 11'h38
+`define ADDR_RTU_UFIFO_R2 11'h58
`define RTU_UFIFO_R2_SMAC_LO_OFFSET 0
`define RTU_UFIFO_R2_SMAC_LO 32'hffffffff
-`define ADDR_RTU_UFIFO_R3 11'h3c
+`define ADDR_RTU_UFIFO_R3 11'h5c
`define RTU_UFIFO_R3_SMAC_HI_OFFSET 0
`define RTU_UFIFO_R3_SMAC_HI 32'h0000ffff
-`define ADDR_RTU_UFIFO_R4 11'h40
+`define ADDR_RTU_UFIFO_R4 11'h60
`define RTU_UFIFO_R4_VID_OFFSET 0
`define RTU_UFIFO_R4_VID 32'h00000fff
`define RTU_UFIFO_R4_PRIO_OFFSET 12
@@ -76,18 +130,18 @@
`define RTU_UFIFO_R4_HAS_VID 32'h01000000
`define RTU_UFIFO_R4_HAS_PRIO_OFFSET 25
`define RTU_UFIFO_R4_HAS_PRIO 32'h02000000
-`define ADDR_RTU_UFIFO_CSR 11'h44
+`define ADDR_RTU_UFIFO_CSR 11'h64
`define RTU_UFIFO_CSR_EMPTY_OFFSET 17
`define RTU_UFIFO_CSR_EMPTY 32'h00020000
`define RTU_UFIFO_CSR_USEDW_OFFSET 0
`define RTU_UFIFO_CSR_USEDW 32'h0000007f
-`define ADDR_RTU_MFIFO_R0 11'h48
+`define ADDR_RTU_MFIFO_R0 11'h68
`define RTU_MFIFO_R0_AD_SEL_OFFSET 0
`define RTU_MFIFO_R0_AD_SEL 32'h00000001
-`define ADDR_RTU_MFIFO_R1 11'h4c
+`define ADDR_RTU_MFIFO_R1 11'h6c
`define RTU_MFIFO_R1_AD_VAL_OFFSET 0
`define RTU_MFIFO_R1_AD_VAL 32'hffffffff
-`define ADDR_RTU_MFIFO_CSR 11'h50
+`define ADDR_RTU_MFIFO_CSR 11'h70
`define RTU_MFIFO_CSR_FULL_OFFSET 16
`define RTU_MFIFO_CSR_FULL 32'h00010000
`define RTU_MFIFO_CSR_EMPTY_OFFSET 17
diff --git a/sim/regs/tatsu_regs.v b/sim/regs/tatsu_regs.v
new file mode 100644
index 0000000000000000000000000000000000000000..7a613459a9b0a1192c92361b641a372b52e3b588
--- /dev/null
+++ b/sim/regs/tatsu_regs.v
@@ -0,0 +1,44 @@
+`define ADDR_TATSU_TCR 5'h0
+`define TATSU_TCR_VALIDATE_OFFSET 0
+`define TATSU_TCR_VALIDATE 32'h00000001
+`define TATSU_TCR_DISABLE_OFFSET 1
+`define TATSU_TCR_DISABLE 32'h00000002
+`define TATSU_TCR_DROP_ENA_OFFSET 8
+`define TATSU_TCR_DROP_ENA 32'h00000100
+`define TATSU_TCR_MIN_RPT_OFFSET 16
+`define TATSU_TCR_MIN_RPT 32'h00ff0000
+`define TATSU_TCR_STARTED_OFFSET 24
+`define TATSU_TCR_STARTED 32'h01000000
+`define TATSU_TCR_DELAYED_OFFSET 25
+`define TATSU_TCR_DELAYED 32'h02000000
+`define TATSU_TCR_STG_OK_OFFSET 26
+`define TATSU_TCR_STG_OK 32'h04000000
+`define TATSU_TCR_STG_ERR_OFFSET 27
+`define TATSU_TCR_STG_ERR 32'h08000000
+`define TATSU_TCR_STG_ERR_TAI_OFFSET 28
+`define TATSU_TCR_STG_ERR_TAI 32'h10000000
+`define TATSU_TCR_STG_ERR_CYC_OFFSET 29
+`define TATSU_TCR_STG_ERR_CYC 32'h20000000
+`define TATSU_TCR_STG_ERR_RPT_OFFSET 30
+`define TATSU_TCR_STG_ERR_RPT 32'h40000000
+`define TATSU_TCR_STG_ERR_SNC_OFFSET 31
+`define TATSU_TCR_STG_ERR_SNC 32'h80000000
+`define ADDR_TATSU_TSR0 5'h4
+`define TATSU_TSR0_QNT_OFFSET 0
+`define TATSU_TSR0_QNT 32'h0000ffff
+`define TATSU_TSR0_PRIO_OFFSET 16
+`define TATSU_TSR0_PRIO 32'h00ff0000
+`define TATSU_TSR0_HTAI_OFFSET 24
+`define TATSU_TSR0_HTAI 32'hff000000
+`define ADDR_TATSU_TSR1 5'h8
+`define TATSU_TSR1_LTAI_OFFSET 0
+`define TATSU_TSR1_LTAI 32'hffffffff
+`define ADDR_TATSU_TSR2 5'hc
+`define TATSU_TSR2_CYC_OFFSET 0
+`define TATSU_TSR2_CYC 32'h0fffffff
+`define ADDR_TATSU_TSR3 5'h10
+`define TATSU_TSR3_CYC_OFFSET 0
+`define TATSU_TSR3_CYC 32'h0fffffff
+`define ADDR_TATSU_TSR4 5'h14
+`define TATSU_TSR4_PORTS_OFFSET 0
+`define TATSU_TSR4_PORTS 32'hffffffff
diff --git a/sim/regs/tru_wb_regs.v b/sim/regs/tru_wb_regs.v
new file mode 100644
index 0000000000000000000000000000000000000000..f20d96a145960e647d4c2656b9bb582d2620606f
--- /dev/null
+++ b/sim/regs/tru_wb_regs.v
@@ -0,0 +1,133 @@
+`define ADDR_TRU_GCR 7'h0
+`define TRU_GCR_G_ENA_OFFSET 0
+`define TRU_GCR_G_ENA 32'h00000001
+`define TRU_GCR_TRU_BANK_OFFSET 1
+`define TRU_GCR_TRU_BANK 32'h00000002
+`define TRU_GCR_RX_FRAME_RESET_OFFSET 8
+`define TRU_GCR_RX_FRAME_RESET 32'hffffff00
+`define ADDR_TRU_GSR0 7'h4
+`define TRU_GSR0_STAT_BANK_OFFSET 0
+`define TRU_GSR0_STAT_BANK 32'h00000001
+`define TRU_GSR0_STAT_STB_UP_OFFSET 8
+`define TRU_GSR0_STAT_STB_UP 32'hffffff00
+`define ADDR_TRU_GSR1 7'h8
+`define TRU_GSR1_STAT_UP_OFFSET 0
+`define TRU_GSR1_STAT_UP 32'hffffffff
+`define ADDR_TRU_MCR 7'hc
+`define TRU_MCR_PATTERN_MODE_REP_OFFSET 0
+`define TRU_MCR_PATTERN_MODE_REP 32'h0000000f
+`define TRU_MCR_PATTERN_MODE_ADD_OFFSET 8
+`define TRU_MCR_PATTERN_MODE_ADD 32'h00000f00
+`define TRU_MCR_PATTERN_MODE_SUB_OFFSET 16
+`define TRU_MCR_PATTERN_MODE_SUB 32'h000f0000
+`define ADDR_TRU_LACR 7'h10
+`define TRU_LACR_AGG_DF_HP_ID_OFFSET 0
+`define TRU_LACR_AGG_DF_HP_ID 32'h0000000f
+`define TRU_LACR_AGG_DF_BR_ID_OFFSET 8
+`define TRU_LACR_AGG_DF_BR_ID 32'h00000f00
+`define TRU_LACR_AGG_DF_UN_ID_OFFSET 16
+`define TRU_LACR_AGG_DF_UN_ID 32'h000f0000
+`define ADDR_TRU_TCGR 7'h14
+`define TRU_TCGR_TRANS_ENA_OFFSET 0
+`define TRU_TCGR_TRANS_ENA 32'h00000001
+`define TRU_TCGR_TRANS_CLEAR_OFFSET 1
+`define TRU_TCGR_TRANS_CLEAR 32'h00000002
+`define TRU_TCGR_TRANS_MODE_OFFSET 4
+`define TRU_TCGR_TRANS_MODE 32'h00000070
+`define TRU_TCGR_TRANS_RX_ID_OFFSET 8
+`define TRU_TCGR_TRANS_RX_ID 32'h00000700
+`define TRU_TCGR_TRANS_PRIO_OFFSET 12
+`define TRU_TCGR_TRANS_PRIO 32'h00007000
+`define TRU_TCGR_TRANS_PRIO_MODE_OFFSET 15
+`define TRU_TCGR_TRANS_PRIO_MODE 32'h00008000
+`define ADDR_TRU_TCPBR 7'h18
+`define TRU_TCPBR_TRANS_PAUSE_TIME_OFFSET 0
+`define TRU_TCPBR_TRANS_PAUSE_TIME 32'h0000ffff
+`define TRU_TCPBR_TRANS_BLOCK_TIME_OFFSET 16
+`define TRU_TCPBR_TRANS_BLOCK_TIME 32'hffff0000
+`define ADDR_TRU_TCPR 7'h1c
+`define TRU_TCPR_TRANS_PORT_A_ID_OFFSET 0
+`define TRU_TCPR_TRANS_PORT_A_ID 32'h0000003f
+`define TRU_TCPR_TRANS_PORT_A_VALID_OFFSET 8
+`define TRU_TCPR_TRANS_PORT_A_VALID 32'h00000100
+`define TRU_TCPR_TRANS_PORT_B_ID_OFFSET 16
+`define TRU_TCPR_TRANS_PORT_B_ID 32'h003f0000
+`define TRU_TCPR_TRANS_PORT_B_VALID_OFFSET 24
+`define TRU_TCPR_TRANS_PORT_B_VALID 32'h01000000
+`define ADDR_TRU_TSR 7'h20
+`define TRU_TSR_TRANS_STAT_ACTIVE_OFFSET 0
+`define TRU_TSR_TRANS_STAT_ACTIVE 32'h00000001
+`define TRU_TSR_TRANS_STAT_FINISHED_OFFSET 1
+`define TRU_TSR_TRANS_STAT_FINISHED 32'h00000002
+`define ADDR_TRU_RTRCR 7'h24
+`define TRU_RTRCR_RTR_ENA_OFFSET 0
+`define TRU_RTRCR_RTR_ENA 32'h00000001
+`define TRU_RTRCR_RTR_RESET_OFFSET 1
+`define TRU_RTRCR_RTR_RESET 32'h00000002
+`define TRU_RTRCR_RTR_MODE_OFFSET 8
+`define TRU_RTRCR_RTR_MODE 32'h00000f00
+`define TRU_RTRCR_RTR_RX_OFFSET 16
+`define TRU_RTRCR_RTR_RX 32'h000f0000
+`define TRU_RTRCR_RTR_TX_OFFSET 24
+`define TRU_RTRCR_RTR_TX 32'h0f000000
+`define ADDR_TRU_HWFC 7'h28
+`define TRU_HWFC_RX_FWD_ID_OFFSET 0
+`define TRU_HWFC_RX_FWD_ID 32'h0000000f
+`define TRU_HWFC_RX_BLK_ID_OFFSET 4
+`define TRU_HWFC_RX_BLK_ID 32'h000000f0
+`define TRU_HWFC_TX_FWD_ID_OFFSET 8
+`define TRU_HWFC_TX_FWD_ID 32'h00000f00
+`define TRU_HWFC_TX_BLK_ID_OFFSET 12
+`define TRU_HWFC_TX_BLK_ID 32'h0000f000
+`define TRU_HWFC_TX_FWD_UB_OFFSET 16
+`define TRU_HWFC_TX_FWD_UB 32'h00ff0000
+`define TRU_HWFC_TX_BLK_UB_OFFSET 24
+`define TRU_HWFC_TX_BLK_UB 32'hff000000
+`define ADDR_TRU_TTR0 7'h2c
+`define TRU_TTR0_FID_OFFSET 0
+`define TRU_TTR0_FID 32'h000000ff
+`define TRU_TTR0_SUB_FID_OFFSET 8
+`define TRU_TTR0_SUB_FID 32'h0000ff00
+`define TRU_TTR0_UPDATE_OFFSET 16
+`define TRU_TTR0_UPDATE 32'h00010000
+`define TRU_TTR0_MASK_VALID_OFFSET 17
+`define TRU_TTR0_MASK_VALID 32'h00020000
+`define TRU_TTR0_PATRN_MODE_OFFSET 24
+`define TRU_TTR0_PATRN_MODE 32'h0f000000
+`define ADDR_TRU_TTR1 7'h30
+`define TRU_TTR1_PORTS_INGRESS_OFFSET 0
+`define TRU_TTR1_PORTS_INGRESS 32'hffffffff
+`define ADDR_TRU_TTR2 7'h34
+`define TRU_TTR2_PORTS_EGRESS_OFFSET 0
+`define TRU_TTR2_PORTS_EGRESS 32'hffffffff
+`define ADDR_TRU_TTR3 7'h38
+`define TRU_TTR3_PORTS_MASK_OFFSET 0
+`define TRU_TTR3_PORTS_MASK 32'hffffffff
+`define ADDR_TRU_TTR4 7'h3c
+`define TRU_TTR4_PATRN_MATCH_OFFSET 0
+`define TRU_TTR4_PATRN_MATCH 32'hffffffff
+`define ADDR_TRU_TTR5 7'h40
+`define TRU_TTR5_PATRN_MASK_OFFSET 0
+`define TRU_TTR5_PATRN_MASK 32'hffffffff
+`define ADDR_TRU_DPS 7'h44
+`define TRU_DPS_PID_OFFSET 0
+`define TRU_DPS_PID 32'h000000ff
+`define ADDR_TRU_PIDR 7'h48
+`define TRU_PIDR_INJECT_OFFSET 0
+`define TRU_PIDR_INJECT 32'h00000001
+`define TRU_PIDR_PSEL_OFFSET 1
+`define TRU_PIDR_PSEL 32'h0000000e
+`define TRU_PIDR_UVAL_OFFSET 8
+`define TRU_PIDR_UVAL 32'h00ffff00
+`define TRU_PIDR_IREADY_OFFSET 24
+`define TRU_PIDR_IREADY 32'h01000000
+`define ADDR_TRU_PFDR 7'h4c
+`define TRU_PFDR_CLR_OFFSET 0
+`define TRU_PFDR_CLR 32'h00000001
+`define TRU_PFDR_CLASS_OFFSET 8
+`define TRU_PFDR_CLASS 32'h0000ff00
+`define TRU_PFDR_CNT_OFFSET 16
+`define TRU_PFDR_CNT 32'hffff0000
+`define ADDR_TRU_PTRDR 7'h50
+`define TRU_PTRDR_GING_MASK_OFFSET 0
+`define TRU_PTRDR_GING_MASK 32'hffffffff
diff --git a/sim/simdrv_hwdu.svh b/sim/simdrv_hwdu.svh
new file mode 100644
index 0000000000000000000000000000000000000000..005e3c38e8a7265a43e313b0c01d1678f8efae4e
--- /dev/null
+++ b/sim/simdrv_hwdu.svh
@@ -0,0 +1,35 @@
+`ifndef __SIMDRV_WR_HWDU
+`define __SIMDRV_WR_HWDU 1
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "regs/hwdu_regs.v"
+
+
+
+class CSimDrv_HWDU;
+
+ protected CBusAccessor m_acc;
+ protected uint64_t m_base;
+
+ function new(CBusAccessor acc, uint64_t base, bit dbg=0);
+ m_acc = acc;
+ m_base = base;
+ endfunction // new
+
+ task dump_mpm_page_utilization(bit[15:0] addr);
+
+ uint64_t tmp;
+ m_acc.write(m_base + `ADDR_HWDU_CR,
+ `HWDU_CR_RD_EN | (`HWDU_CR_ADR & (addr << `HWDU_CR_ADR_OFFSET)) );
+ m_acc.read(m_base + `ADDR_HWDU_REG_VAL, tmp, 4);
+ $display("HWDU: raw_val: 0x%x, addr: 0%d",tmp, addr);
+ $display("HWDU: unused res: %d",'h3FF & tmp);
+ $display("HWDU: hp res: %d",'h3FF & (tmp >> 10));
+ $display("HWDU: normal res: %d",'h3FF & (tmp >> 20));
+
+ endtask;
+
+endclass // CSimDrv_TATSU
+
+`endif // `ifndef __SIMDRV_TATSU_SVH
diff --git a/sim/simdrv_rtu.sv b/sim/simdrv_rtu.sv
index 4a9cd679836c728b5e56046b9db67581d516ea64..66ef0fa2c34a5f905e3ef79d08f226444dc49ecd 100644
--- a/sim/simdrv_rtu.sv
+++ b/sim/simdrv_rtu.sv
@@ -1,5 +1,6 @@
`include "regs/rtu_regs.vh"
+// `include "regs/rtu_regs_old.vh"
`include "eth_packet.svh"
`include "simdrv_defs.svh"
@@ -52,14 +53,22 @@ class CRTUSimDriver;
extern task set_bus(CBusAccessor _bus, int _base_addr);
extern task add_hash_entry(rtu_filtering_entry_t ent);
- extern task set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en);
-
- extern task add_static_rule(bit[7:0] dmac[], bit[31:0] dpm);
+ extern task set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en, bit dbg = 0);
+ extern task add_static_rule(bit[7:0] dmac[], bit[31:0] dpm, bit[7:0] fid=0);
extern task add_vlan_entry(int vlan_id, rtu_vlan_entry_t ent);
extern task poll_ufifo();
-
-
+ // RTU extension functions
+ extern task rx_add_ff_mac_single(int mac_id, bit valid, bit[47:0] mac);
+ extern task rx_add_ff_mac_range(int mac_id, bit valid, bit[47:0] mac_lower, bit[47:0] mac_upper);
+ extern task rx_set_port_mirror(bit[31:0] mirror_src_mask, bit[31:0] mirror_dst_mask, bit rx, bit tx);
+ extern task rx_set_hp_prio_mask(bit[7:0] hp_prio_mask);
+ extern task rx_read_cpu_port();
+ extern task rx_forward_on_fmatch_full();
+ extern task rx_drop_on_fmatch_full();
+ extern task rx_feature_ctrl(bit mr, bit mac_ptp, bit mac_ll, bit mac_single, bit mac_range, bit mac_br);
+ extern task rx_feature_dbg(bit f_fast_match, bit f_full_match);
+ extern task rx_fw_to_CPU(bit hp, bit unrec);
// extern task run();
extern protected task htab_write(int hash, int bucket, rtu_filtering_entry_t ent);
extern protected task mfifo_write(int addr, int size, bit[31:0] data[]);
@@ -279,18 +288,18 @@ task CRTUSimDriver::add_hash_entry(rtu_filtering_entry_t ent);
endtask // CRTUSimDriver
-task CRTUSimDriver::set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en);
+task CRTUSimDriver::set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en, bit dbg = 0);
uint64_t rv, tmp;
bus.read(base_addr + `ADDR_RTU_PSR, rv);
- $display("PSel: %d supported ports, configuration for port %d:", (rv>>8) & 'hff, port);
+ if(dbg) $display("PSel: %d supported ports, configuration for port %d:", (rv>>8) & 'hff, port);
- if(learn_en == 1) begin tmp = tmp | `RTU_PCR_LEARN_EN; $display("learn"); end;
- if(pass_all == 1) begin tmp = tmp | `RTU_PCR_PASS_ALL; $display("pass all"); end;
- if(pass_bpdu == 1) begin tmp = tmp | `RTU_PCR_PASS_BPDU; $display("pass bpdu"); end;
+ if(learn_en == 1) begin tmp = tmp | `RTU_PCR_LEARN_EN; if(dbg) $display("learn"); end;
+ if(pass_all == 1) begin tmp = tmp | `RTU_PCR_PASS_ALL; if(dbg) $display("pass all"); end;
+ if(pass_bpdu == 1) begin tmp = tmp | `RTU_PCR_PASS_BPDU;if(dbg) $display("pass bpdu"); end;
- tmp = `RTU_PCR_B_UNREC | tmp; $display("broadcast unrecognized");
+ tmp = `RTU_PCR_B_UNREC | tmp; if(dbg) $display("broadcast unrecognized");
bus.write(base_addr + `ADDR_RTU_PSR, port);
bus.write(base_addr + `ADDR_RTU_PCR, tmp);
@@ -329,14 +338,14 @@ function bit[15:0] CRTUSimDriver::mac_hash(bit[7:0] mac[], bit[7:0] fid);
endfunction // mac_hash
-task CRTUSimDriver::add_static_rule(bit[7:0] dmac[], bit[31:0] dpm);
+task CRTUSimDriver::add_static_rule(bit[7:0] dmac[], bit[31:0] dpm, bit[7:0] fid=0);
rtu_filtering_entry_t ent;
ent.mac = dmac;
ent.valid = 1'b1;
// ent.end_of_bucket = 1;
ent.is_bpdu = 0;
- ent.fid = 0;
+ ent.fid = fid;
ent.port_mask_dst = dpm;
ent.port_mask_src = 32'hffffffff;
ent.drop_when_source=0;
@@ -363,11 +372,209 @@ task CRTUSimDriver::add_vlan_entry(int vlan_id, rtu_vlan_entry_t ent);
| (ent.prio_override ? `RTU_VTR1_PRIO_OVERRIDE : 0)
| (ent.has_prio ? `RTU_VTR1_HAS_PRIO : 0)
| ((ent.prio & 'h7) << `RTU_VTR1_PRIO_OFFSET)
- | ((ent.fid & 'hff) << `RTU_VTR1_FID_OFFSET);
+ | ((ent.fid & 'hff) << `RTU_VTR1_FID_OFFSET)
+ | (vlan_id & `RTU_VTR1_VID) ;
bus.write(base_addr + `ADDR_RTU_VTR2, vtr2);
bus.write(base_addr + `ADDR_RTU_VTR1, vtr1);
+ $display("[CRTUSimDriver::add_vlan_entry] drop=%1d, has_prio=%1d, prio=%1d,\
+prio_override=%1d, fid=%1d, vlan_id=%1d", ent.drop, ent.has_prio, ent.prio,
+ ent.prio_override, ent.fid, vlan_id);
+
+endtask // CRTUSimDriver
+
+task CRTUSimDriver::rx_add_ff_mac_single(int mac_id, bit valid, bit[47:0] mac);
+ uint64_t mac_hi, mac_lo;
+
+
+ mac_lo = `RTU_RX_FF_MAC_R0_LO & (mac[31:0] << `RTU_RX_FF_MAC_R0_LO_OFFSET);
+ mac_hi = `RTU_RX_FF_MAC_R1_HI_ID & (mac[47:32] << `RTU_RX_FF_MAC_R1_HI_ID_OFFSET) |
+ `RTU_RX_FF_MAC_R1_ID & (mac_id << `RTU_RX_FF_MAC_R1_ID_OFFSET) |
+ `RTU_RX_FF_MAC_R1_TYPE & (0 << `RTU_RX_FF_MAC_R1_TYPE_OFFSET) |
+ `RTU_RX_FF_MAC_R1_VALID & (valid << `RTU_RX_FF_MAC_R1_VALID_OFFSET);
+
+ bus.write(base_addr + `ADDR_RTU_RX_FF_MAC_R0, mac_lo);
+ bus.write(base_addr + `ADDR_RTU_RX_FF_MAC_R1, mac_hi);
+
+ $display("RTU eXtension: set fast forward single mac (id=%d, valid=%d) of 0xd",mac_id, valid,mac);
+
+endtask // CRTUSimDriver
+
+task CRTUSimDriver::rx_add_ff_mac_range(int mac_id, bit valid, bit[47:0] mac_lower, bit[47:0] mac_upper);
+ uint64_t mac_hi, mac_lo;
+ int m_mac_id; // modified mac id
+
+ // writting lower boundary of the mac range
+ m_mac_id = (~(1 << 7) ) & mac_id; // lower range (highest bit is low)
+
+ mac_lo = `RTU_RX_FF_MAC_R0_LO & (mac_lower[31:0] << `RTU_RX_FF_MAC_R0_LO_OFFSET);
+ mac_hi = `RTU_RX_FF_MAC_R1_HI_ID & (mac_lower[47:32] << `RTU_RX_FF_MAC_R1_HI_ID_OFFSET) |
+ `RTU_RX_FF_MAC_R1_ID & (m_mac_id << `RTU_RX_FF_MAC_R1_ID_OFFSET) |
+ `RTU_RX_FF_MAC_R1_TYPE & (1 << `RTU_RX_FF_MAC_R1_TYPE_OFFSET) |
+ `RTU_RX_FF_MAC_R1_VALID & (valid << `RTU_RX_FF_MAC_R1_VALID_OFFSET);
+
+ bus.write(base_addr + `ADDR_RTU_RX_FF_MAC_R0, mac_lo);
+ bus.write(base_addr + `ADDR_RTU_RX_FF_MAC_R1, mac_hi);
+ // writting upper boundary of the mac range
+ m_mac_id = (1 << 7) | mac_id; // upper range high (highest bit is low)
+
+ mac_lo = `RTU_RX_FF_MAC_R0_LO & (mac_upper[31:0] << `RTU_RX_FF_MAC_R0_LO_OFFSET);
+ mac_hi = `RTU_RX_FF_MAC_R1_HI_ID & (mac_upper[47:32] << `RTU_RX_FF_MAC_R1_HI_ID_OFFSET) |
+ `RTU_RX_FF_MAC_R1_ID & (m_mac_id << `RTU_RX_FF_MAC_R1_ID_OFFSET) |
+ `RTU_RX_FF_MAC_R1_TYPE & (1 << `RTU_RX_FF_MAC_R1_TYPE_OFFSET) |
+ `RTU_RX_FF_MAC_R1_VALID & (valid << `RTU_RX_FF_MAC_R1_VALID_OFFSET) ;
+
+ bus.write(base_addr + `ADDR_RTU_RX_FF_MAC_R0, mac_lo);
+ bus.write(base_addr + `ADDR_RTU_RX_FF_MAC_R1, mac_hi);
+ $display("RTU eXtension: set fast forward mac range: (id=%d, valid=%d):", mac_id, valid);
+ $display("\t lower_mac = 0x%x",mac_lower);
+ $display("\t upper_mac = 0x%x",mac_upper);
+
endtask // CRTUSimDriver
+task CRTUSimDriver::rx_set_port_mirror(bit[31:0] mirror_src_mask, bit[31:0] mirror_dst_mask, bit rx, bit tx);
+ uint64_t mp_src_rx, mp_src_tx, mp_dst, mp_sel;
+
+ $display("RTU eXtension: set port mirroring:" );
+
+ mp_dst = `RTU_RX_MP_R1_MASK & (mirror_dst_mask<< `RTU_RX_MP_R1_MASK_OFFSET);
+ mp_src_tx = 0;
+ mp_src_rx = 0;
+
+ mp_sel = (0 << `RTU_RX_MP_R0_DST_SRC_OFFSET); // destinatioon
+ bus.write(base_addr + `ADDR_RTU_RX_MP_R0, mp_sel);
+ bus.write(base_addr + `ADDR_RTU_RX_MP_R1, mp_dst);
+
+ if(rx) begin
+ mp_src_rx = `RTU_RX_MP_R1_MASK & (mirror_src_mask<< `RTU_RX_MP_R1_MASK_OFFSET);
+ mp_sel = 0;
+ mp_sel =(1 << `RTU_RX_MP_R0_DST_SRC_OFFSET) | (0 << `RTU_RX_MP_R0_RX_TX_OFFSET);
+ bus.write(base_addr + `ADDR_RTU_RX_MP_R0, mp_sel);
+ bus.write(base_addr + `ADDR_RTU_RX_MP_R1, mp_src_rx);
+
+ end;
+
+ if(tx) begin
+ mp_src_tx = `RTU_RX_MP_R1_MASK & (mirror_src_mask<< `RTU_RX_MP_R1_MASK_OFFSET);
+ mp_sel = 0;
+ mp_sel =(1 << `RTU_RX_MP_R0_DST_SRC_OFFSET) | (1 << `RTU_RX_MP_R0_RX_TX_OFFSET);
+ bus.write(base_addr + `ADDR_RTU_RX_MP_R0, mp_sel);
+ bus.write(base_addr + `ADDR_RTU_RX_MP_R1, mp_src_tx);
+ end;
+
+ $display("\t mirror output port(s) mask (dst) = 0x%x",mp_dst);
+ $display("\t ingress traffic mirror source port(s) mask (src_rx) = 0x%x",mp_src_rx);
+ $display("\t egress traffic mirror source port(s) mask (src_tx) = 0x%x",mp_src_tx);
+
+
+endtask // CRTUSimDriver
+
+task CRTUSimDriver::rx_set_hp_prio_mask(bit[7:0] hp_prio_mask);
+ uint64_t mask;
+
+ mask = `RTU_RX_CTR_PRIO_MASK & (hp_prio_mask << `RTU_RX_CTR_PRIO_MASK_OFFSET);
+
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
+ $display("RTU eXtension: set hp priorities (for which priorities traffic is considered HP), mask=0x%x",hp_prio_mask );
+endtask // CRTUSimDriver
+
+task CRTUSimDriver::rx_read_cpu_port();
+ uint64_t mask;
+
+ bus.read(base_addr + `ADDR_RTU_CPU_PORT, mask);
+ $display("RTU eXtension: CPU port (to which link-limited traffic is forwarded) mask=0x%x",mask );
+endtask // CRTUSimDriver
+
+task CRTUSimDriver::rx_forward_on_fmatch_full();
+ uint64_t rd_mask, wr_mask;
+ bus.read(base_addr + `ADDR_RTU_RX_CTR, rd_mask);
+ $display("RTU eXtension: forward (broadcast) on full_match full");
+ wr_mask = `RTU_RX_CTR_AT_FMATCH_TOO_SLOW | rd_mask;
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, wr_mask);
+endtask // CRTUSimDriver
+task CRTUSimDriver::rx_drop_on_fmatch_full();
+ uint64_t mask;
+ bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
+ mask = (~`RTU_RX_CTR_AT_FMATCH_TOO_SLOW) & mask;
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
+ $display("RTU eXtension: drop on full_match full");
+endtask // CRTUSimDriver
+
+
+task CRTUSimDriver::rx_feature_ctrl(bit mr, bit mac_ptp, bit mac_ll, bit mac_single, bit mac_range, bit mac_br);
+ uint64_t mask;
+ bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
+
+ mask = 'hFFFFFFC0 & mask;
+ mask =(((mr << `RTU_RX_CTR_MR_ENA_OFFSET) & `RTU_RX_CTR_MR_ENA) |
+ ((mac_ptp << `RTU_RX_CTR_FF_MAC_PTP_OFFSET) & `RTU_RX_CTR_FF_MAC_PTP) |
+ ((mac_ll << `RTU_RX_CTR_FF_MAC_LL_OFFSET) & `RTU_RX_CTR_FF_MAC_LL) |
+ ((mac_single << `RTU_RX_CTR_FF_MAC_SINGLE_OFFSET) & `RTU_RX_CTR_FF_MAC_SINGLE) |
+ ((mac_range << `RTU_RX_CTR_FF_MAC_RANGE_OFFSET) & `RTU_RX_CTR_FF_MAC_RANGE) |
+ ((mac_br << `RTU_RX_CTR_FF_MAC_BR_OFFSET) & `RTU_RX_CTR_FF_MAC_BR) ) |
+ mask;
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
+ $display("RTU eXtension features:");
+ if(mr ) $display("\t Port Mirroring - enabled");
+ else $display("\t Port Mirroring - disabled");
+ if(mac_ptp ) $display("\t PTP fast forward - enabled");
+ else $display("\t PTP fast forward - disabled");
+ if(mac_br ) $display("\t Broadcast fast forward - enabled");
+ else $display("\t Broadcast fast forward - disabled");
+ if(mac_ll ) $display("\t Link-limited traffic (BPDU) fast forward - enabled");
+ else $display("\t Link-limited traffic (BPDU) fast forward - disabled");
+ if(mac_single) $display("\t Single configured MACs fast forward - enabled");
+ else $display("\t Single configured MACs fast forward - disabled");
+ if(mac_range ) $display("\t Range of configured MACs fast forward - enabled");
+ else $display("\t Range of configured MACs fast forward - disabled");
+
+endtask // CRTUSimDriver
+
+task CRTUSimDriver::rx_feature_dbg(bit f_fast_match, bit f_full_match);
+ uint64_t mask = 0;
+ bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
+
+ if(f_fast_match & f_full_match)
+ begin
+ $display("RTU eXtension debugging features: FAILED (you want to sent all, cannot do that, use one feature at at time)");
+ return;
+ end
+ if(f_fast_match)
+ begin
+ mask = `RTU_RX_CTR_FORCE_FAST_MATCH_ENA | mask;
+ $display("RTU eXtension debugging features: set fast match only");
+ end
+ else if(f_full_match)
+ begin
+ mask = `RTU_RX_CTR_FORCE_FULL_MATCH_ENA | mask;
+ $display("RTU eXtension debugging features: set full match only");
+ end
+ else
+ begin
+ $display("RTU eXtension debugging features: FAILED (nothing to set)");
+ return;
+ end
+
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
+
+endtask
+
+task CRTUSimDriver::rx_fw_to_CPU(bit hp, bit unrec);
+ uint64_t mask;
+ bus.read(base_addr + `ADDR_RTU_RX_CTR, mask);
+ mask = 'hFFF0FFFF & mask;
+ /*$display("RTU eXtension features debugging: 2: cleared mask: 0x%x",mask);*/
+ mask =(((hp << `RTU_RX_CTR_HP_FW_CPU_ENA_OFFSET) & `RTU_RX_CTR_HP_FW_CPU_ENA) |
+ ((unrec << `RTU_RX_CTR_UREC_FW_CPU_ENA_OFFSET) & `RTU_RX_CTR_UREC_FW_CPU_ENA))|
+ mask;
+// $display("RTU eXtension features debugging: 1: written mask: 0x%x",mask);
+ bus.write(base_addr + `ADDR_RTU_RX_CTR, mask);
+ $display("RTU eXtension features [forward to CPU]:");
+ if(hp ) $display("\t Forward HP to CPU - enabled");
+ else $display("\t Forward HP to CPU - disabled");
+ if(unrec ) $display("\t Forward unrecognized broadcast to CPU - enabled");
+ else $display("\t Forward unrecognized broadcast to CPU - disabled");
+
+endtask // CRTUSimDriver
\ No newline at end of file
diff --git a/sim/simdrv_tatsu.svh b/sim/simdrv_tatsu.svh
new file mode 100644
index 0000000000000000000000000000000000000000..63c8dc877dd22ce57ceeb287fa21bb3c3bb9a289
--- /dev/null
+++ b/sim/simdrv_tatsu.svh
@@ -0,0 +1,78 @@
+`ifndef __SIMDRV_WR_TATSU
+`define __SIMDRV_WR_TATSU 1
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "regs/tatsu_regs.v"
+
+
+
+class CSimDrv_TATSU;
+
+ protected CBusAccessor m_acc;
+ protected uint64_t m_base;
+
+ function new(CBusAccessor acc, uint64_t base, bit dbg=0);
+ m_acc = acc;
+ m_base = base;
+ endfunction // new
+
+ task set_tatsu(bit[15:0] quanta, bit[39:0] tm_tai, bit[27:0] tm_cycles,
+ bit[ 7:0] prio_mask, bit[31:0] port_mask, bit[27:0] repeat_cycles);
+
+ m_acc.write(m_base + `ADDR_TATSU_TSR0,
+ (tm_tai[39:32] << `TATSU_TSR0_HTAI_OFFSET) & `TATSU_TSR0_HTAI |
+ (prio_mask << `TATSU_TSR0_PRIO_OFFSET) & `TATSU_TSR0_PRIO |
+ (quanta << `TATSU_TSR0_QNT_OFFSET) & `TATSU_TSR0_QNT );
+ m_acc.write(m_base + `ADDR_TATSU_TSR1, tm_tai[31:0]);
+ m_acc.write(m_base + `ADDR_TATSU_TSR2, tm_cycles);
+ m_acc.write(m_base + `ADDR_TATSU_TSR3, repeat_cycles & `TATSU_TSR3_CYC );
+ m_acc.write(m_base + `ADDR_TATSU_TSR4, port_mask);
+
+ m_acc.write(m_base + `ADDR_TATSU_TCR, `TATSU_TCR_VALIDATE);
+
+ endtask;
+
+ task drop_at_HP_enable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
+ m_acc.write(m_base + `ADDR_TATSU_TCR, tmp | `TATSU_TCR_DROP_ENA);
+ $display("TATSU: enable drop at HP");
+ endtask;
+
+ task drop_at_HP_disable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
+ m_acc.write(m_base + `ADDR_TATSU_TCR, tmp & ~(`TATSU_TCR_DROP_ENA));
+ $display("TATSU: disable drop at HP");
+ endtask;
+
+
+// task get_status(output int OK, output int error);
+// uint64_t tmp;
+//
+// m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
+// OK = (tmp & `TATSU_TCR_OK) >> `TATSU_TCR_OK_OFFSET;
+// error = (tmp & `TATSU_TCR_ERROR) >> `TATSU_TCR_ERROR_OFFSET;
+// $display("TATSU status: OK=%1d Error=%1d", OK, error);
+//
+// endtask;
+
+ task print_status();
+ uint64_t tmp;
+ int OK, error;
+ m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
+ $display("TATSU status: [raw=x%x]",tmp);
+ if(tmp & `TATSU_TCR_STARTED) $display("\t TATSU started");
+ if(tmp & `TATSU_TCR_DELAYED) $display("\t TATSU starte delayed");
+ if(tmp & `TATSU_TCR_STG_ERR) $display("\t ERROR");
+ if(tmp & `TATSU_TCR_STG_OK) $display("\t Settings OK");
+ if(tmp & `TATSU_TCR_STG_ERR_TAI) $display("\t Settings ERROR: TAI value");
+ if(tmp & `TATSU_TCR_STG_ERR_CYC) $display("\t Settings ERROR: cycle value");
+ if(tmp & `TATSU_TCR_STG_ERR_RPT) $display("\t Settings ERROR: repeat value");
+ if(tmp & `TATSU_TCR_STG_ERR_SNC) $display("\t Sync ERROR");
+ endtask;
+
+endclass // CSimDrv_TATSU
+
+`endif // `ifndef __SIMDRV_TATSU_SVH
diff --git a/sim/simdrv_wr_tru.svh b/sim/simdrv_wr_tru.svh
new file mode 100644
index 0000000000000000000000000000000000000000..0333907945c47717e18052c724db30c67b2b84ae
--- /dev/null
+++ b/sim/simdrv_wr_tru.svh
@@ -0,0 +1,397 @@
+`ifndef __SIMDRV_WR_TRU_SVH
+`define __SIMDRV_WR_TRU_SVH 1
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "regs/tru_wb_regs.v"
+
+`define c_RTU_MAX_PORTS 32
+`define c_tru_pattern_mode_width 4
+`define c_tru_subentry_num 8
+`define c_tru_entry_num 256
+typedef struct {
+ bit valid;
+ bit[`c_RTU_MAX_PORTS-1:0] ports_ingress;
+ bit[`c_RTU_MAX_PORTS-1:0] ports_egress;
+ bit[`c_RTU_MAX_PORTS-1:0] ports_mask;
+ bit[`c_RTU_MAX_PORTS-1:0] pattern_match;
+ bit[`c_RTU_MAX_PORTS-1:0] pattern_mask;
+ bit[`c_RTU_MAX_PORTS-1:0] pattern_mode;
+} vlan_tab_entry_p_s;
+
+
+
+class CSimDrv_WR_TRU;
+
+ protected CBusAccessor m_acc;
+ protected uint64_t m_base;
+ protected bit m_dbg;
+ protected int m_port_number;
+ protected vlan_tab_entry_p_s m_tru_tab[`c_tru_entry_num][`c_tru_subentry_num];
+
+ function new(CBusAccessor acc, uint64_t base, port_number, bit dbg=0);
+ m_acc = acc;
+ m_base = base;
+ m_dbg = dbg;
+ m_port_number = port_number;
+ endfunction // new
+
+ task write_tru_tab(int valid, int fid, int subfid,
+ int patrn_mask, int patrn_match, int patrn_mode,
+ int ports_mask, int ports_egress, int ports_ingress);
+
+ m_acc.write(m_base + `ADDR_TRU_TTR1, ports_ingress);
+ m_acc.write(m_base + `ADDR_TRU_TTR2, ports_egress);
+ m_acc.write(m_base + `ADDR_TRU_TTR3, ports_mask);
+ m_acc.write(m_base + `ADDR_TRU_TTR4, patrn_match);
+ m_acc.write(m_base + `ADDR_TRU_TTR5, patrn_mask);
+ // write
+ m_acc.write(m_base + `ADDR_TRU_TTR0, fid << `TRU_TTR0_FID_OFFSET |
+ subfid << `TRU_TTR0_SUB_FID_OFFSET |
+ valid << `TRU_TTR0_MASK_VALID_OFFSET |
+ patrn_mode << `TRU_TTR0_PATRN_MODE_OFFSET |
+ 1 << `TRU_TTR0_UPDATE_OFFSET );
+ m_tru_tab[fid][subfid].valid = valid;
+ m_tru_tab[fid][subfid].ports_ingress = ports_ingress;
+ m_tru_tab[fid][subfid].ports_egress = ports_egress;
+ m_tru_tab[fid][subfid].ports_mask = ports_mask;
+ m_tru_tab[fid][subfid].pattern_match = patrn_match;
+ m_tru_tab[fid][subfid].pattern_mask = patrn_mask;
+ m_tru_tab[fid][subfid].pattern_mode = patrn_mode;
+
+ if(m_dbg & valid)
+ begin
+ $display("TRU: TAB entry write [fid = %2d, subfid = %2d, pattern mode = %2d]:", fid, subfid, patrn_mode);
+ if(patrn_mode==0)
+ $display("\t Pattern Mode : replace masked bits of the port mask");
+ if(patrn_mode==1)
+ $display("\t Pattern Mode : add masked bits of the port mask");
+ if(patrn_mode==2)
+ $display("\t Pattern Mode : add port status based masked bits");
+ if(patrn_mode > 2)
+ $display("\t Pattern Mode : error, unrecognized mode");
+ $display("\t Ingress config : port = 0x%x , mask = 0x%x",ports_ingress,ports_mask);
+ $display("\t Egress config : port = 0x%x , mask = 0x%x",ports_egress, ports_mask);
+ $display("\t Pattern config : match = 0x%x , mask = 0x%x",patrn_match, patrn_mask);
+ end
+ endtask;
+
+ task transition_config(int mode, int rx_id, int prio_mode , int prio, int time_diff,
+ int port_a_id, int port_b_id);
+
+ m_acc.write(m_base +`ADDR_TRU_TCGR,
+ (mode << `TRU_TCGR_TRANS_MODE_OFFSET ) & `TRU_TCGR_TRANS_MODE |
+ (rx_id << `TRU_TCGR_TRANS_RX_ID_OFFSET ) & `TRU_TCGR_TRANS_RX_ID |
+ (prio << `TRU_TCGR_TRANS_PRIO_OFFSET ) & `TRU_TCGR_TRANS_PRIO |
+ (prio_mode << `TRU_TCGR_TRANS_PRIO_MODE_OFFSET) & `TRU_TCGR_TRANS_PRIO_MODE );
+
+
+ m_acc.write(m_base +`ADDR_TRU_TCPBR,
+ (time_diff << `TRU_TCPBR_TRANS_PAUSE_TIME_OFFSET) & `TRU_TCPBR_TRANS_PAUSE_TIME |
+ (time_diff << `TRU_TCPBR_TRANS_BLOCK_TIME_OFFSET) & `TRU_TCPBR_TRANS_BLOCK_TIME );
+
+ m_acc.write(m_base +`ADDR_TRU_TCPR,
+ (port_a_id << `TRU_TCPR_TRANS_PORT_A_ID_OFFSET ) & `TRU_TCPR_TRANS_PORT_A_ID |
+ (1 << `TRU_TCPR_TRANS_PORT_A_VALID_OFFSET) & `TRU_TCPR_TRANS_PORT_A_VALID |
+ (port_b_id << `TRU_TCPR_TRANS_PORT_B_ID_OFFSET ) & `TRU_TCPR_TRANS_PORT_B_ID |
+ (1 << `TRU_TCPR_TRANS_PORT_B_VALID_OFFSET) & `TRU_TCPR_TRANS_PORT_B_VALID );
+ if(m_dbg)
+ begin
+ $display("TRU: transition configuration [mode id = %2d]:",mode);
+ if(mode == 0)
+ $display("\tMode : marker triggered");
+ if(mode == 1)
+ $display("\tMode : LACP distributor");
+ if(mode == 1)
+ $display("\tMode : LACP collector");
+ $display("\tPorts : A_ID = %2d (before tran), B_ID = %d2 (after trans)",port_a_id,
+ port_b_id);
+ $display("\tParams : Rx Frame ID = %2d, PrioMode = %s, Priority = %2d, Time diff = %3d",
+ rx_id, prio_mode, prio, time_diff);
+ end
+ endtask;
+
+ task transition_enable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_TCGR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_TCGR, tmp | 1 << `TRU_TCGR_TRANS_ENA_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: enable transition");
+ end
+ endtask;
+
+ task transition_disable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_TCGR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_TCGR, tmp & ! (1 << `TRU_TCGR_TRANS_ENA_OFFSET));
+ if(m_dbg)
+ begin
+ $display("TRU: disable transition");
+ end
+ endtask;
+
+ task transition_clear();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_TCGR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_TCGR, tmp & 1 << `TRU_TCGR_TRANS_CLEAR_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: clear transition");
+ end
+ endtask;
+
+ task pattern_config(int replacement, int addition, int subtraction);
+ m_acc.write(m_base +`ADDR_TRU_MCR,
+ (subtraction << `TRU_MCR_PATTERN_MODE_SUB_OFFSET) & `TRU_MCR_PATTERN_MODE_SUB |
+ (addition << `TRU_MCR_PATTERN_MODE_ADD_OFFSET) & `TRU_MCR_PATTERN_MODE_ADD |
+ (replacement << `TRU_MCR_PATTERN_MODE_REP_OFFSET) & `TRU_MCR_PATTERN_MODE_REP);
+
+ if(m_dbg)
+ begin
+ $display("TRU: Real Time transition source of patterns config:");
+ $display("\tReplacement pattern ID = %d:",replacement);
+ $display("\tAddition pattern ID = %d:",addition);
+ $display("\tChoice info:");
+ $display("\t\t0: non: zeros");
+ $display("\t\t1: ports status (bit HIGH when port down");
+ $display("\t\t2: received special frames - filtered by endpoints according to configuration (pfliter in endpoint + RTR_RX class ID in Real Time Reconfiguration Control Register)");
+ $display("\t\t3: according to aggregation ID (the source of the ID depends on the traffic kind: HP/Broadcast/Uniast, set in Link Aggregation Control Register)");
+ $display("\t\t4: received port");
+ $display("\t\tx: non: zero");
+ end
+ endtask;
+
+ task tru_enable();
+ m_acc.write(m_base + `ADDR_TRU_GCR, 1 << `TRU_GCR_G_ENA_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: enable");
+ end
+ endtask;
+
+ task tru_swap_bank();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_GCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_GCR, tmp | 1 << `TRU_GCR_TRU_BANK_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: swap TABLE banks");
+ end
+ endtask;
+
+ task tru_rx_frame_reset(int reset_rx);
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_GCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_GCR, tmp | reset_rx << `TRU_GCR_RX_FRAME_RESET_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: reset rx frame register (foget received frames)");
+ end
+ endtask;
+
+ task ep_debug_read_pfilter(int port);
+ uint64_t tmp,cnt, cnt1, cnt2;
+ m_acc.write(m_base +`ADDR_TRU_DPS, `TRU_DPS_PID & port);
+ m_acc.read(m_base + `ADDR_TRU_PFDR, tmp, 4);
+ cnt = (`TRU_PFDR_CNT & tmp)>>`TRU_PFDR_CNT_OFFSET;
+ cnt1 = 'hFF & cnt;
+ cnt2 = 'hFF & (cnt>>8);
+ if(m_dbg)
+ begin
+ $display("DBG [pFILTER-port_%2d]: filtered packet classes 0x%x [cnt_filtered=%4d, cnt_all=%4d]",port,
+ (`TRU_PFDR_CLASS & tmp)>>`TRU_PFDR_CLASS_OFFSET, cnt1,cnt2);
+ end
+ endtask;
+
+ task ep_debug_clear_pfilter(int port);
+ uint64_t tmp;
+ m_acc.write(m_base +`ADDR_TRU_DPS, `TRU_DPS_PID & port);
+ m_acc.write(m_base +`ADDR_TRU_PFDR, `TRU_PFDR_CLR);
+ if(m_dbg)
+ begin
+ $display("DBG [pFILTER-port_%2d]: filtered packet classes & cnt cleared",port);
+ end
+ endtask;
+
+ task ep_debug_inject_packet(int port, int user_val, int pck_sel);
+ uint64_t tmp, tmp2;
+ m_acc.write(m_base +`ADDR_TRU_DPS, `TRU_DPS_PID & port);
+ tmp = `TRU_PIDR_INJECT |
+ (pck_sel << `TRU_PIDR_PSEL_OFFSET) & `TRU_PIDR_PSEL |
+ (user_val<< `TRU_PIDR_UVAL_OFFSET) & `TRU_PIDR_UVAL;
+ m_acc.write(m_base +`ADDR_TRU_PIDR, tmp, 4);
+ if(m_dbg)
+ begin
+ $display("DBG [pINJECT-port_%2d]: inject packet: pck_sel=%2d, user_val=0x%x",port,pck_sel, user_val);
+ end
+ endtask;
+
+ task ep_debug_read_pinject(int port);
+ uint64_t tmp;
+ m_acc.write(m_base +`ADDR_TRU_DPS, `TRU_DPS_PID & port);
+ m_acc.read(m_base + `ADDR_TRU_PIDR, tmp, 4);
+ if(m_dbg)
+ begin
+ $display("DBG [pINJECT-port_%2d]: inject ready = %1d ",port,
+ (`TRU_PIDR_IREADY & tmp)>>`TRU_PIDR_IREADY_OFFSET);
+ end
+ endtask;
+
+
+ task rt_reconf_config(int tx_frame_id, int rx_frame_id, int mode);
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp & 'h000F |
+ mode << `TRU_RTRCR_RTR_MODE_OFFSET |
+ rx_frame_id << `TRU_RTRCR_RTR_RX_OFFSET |
+ tx_frame_id << `TRU_RTRCR_RTR_TX_OFFSET );
+ if(m_dbg)
+ begin
+ $display("TRU: Real Time re-configuration Mode [%2d]:",mode);
+ $display("\tFrames: rx_id = %2d, tx_id = %2d", rx_frame_id, tx_frame_id);
+ if(mode == 0)
+ $display("\tMode : default (do nothing)");
+ if(mode == 1)
+ $display("\tMode : eRSTP (send HW-generated frames on port down, etc...)");
+ if(mode > 1)
+ $display("\tMode : undefined");
+ end
+ endtask;
+
+ task hw_frame_config(int tx_fwd_id, int rx_fwd_id, int tx_blk_id, int rx_blk_id);
+ uint64_t tmp;
+
+ m_acc.write(m_base +`ADDR_TRU_HWFC,
+ ('h96 << `TRU_HWFC_TX_BLK_UB_OFFSET) & `TRU_HWFC_TX_BLK_UB |
+ ('h69 << `TRU_HWFC_TX_FWD_UB_OFFSET) & `TRU_HWFC_TX_FWD_UB |
+ (tx_blk_id << `TRU_HWFC_TX_BLK_ID_OFFSET) & `TRU_HWFC_TX_BLK_ID |
+ (tx_fwd_id << `TRU_HWFC_TX_FWD_ID_OFFSET) & `TRU_HWFC_TX_FWD_ID |
+ (rx_blk_id << `TRU_HWFC_RX_BLK_ID_OFFSET) & `TRU_HWFC_RX_BLK_ID |
+ (rx_fwd_id << `TRU_HWFC_RX_FWD_ID_OFFSET) & `TRU_HWFC_RX_FWD_ID );
+ if(m_dbg)
+ begin
+ $display("TRU: HW-generated/detected frame config]:");
+ $display("\tFrame forward: tx_fwd_id = %2d, rx_fwd_id = %2d tx_fwd_ub = x%2x",
+ tx_fwd_id, rx_fwd_id, 'h69);
+ $display("\tFrame block : tx_blk_id = %2d, rx_blk_id = %2d tx_blk_ub = x%2x",
+ tx_blk_id, rx_blk_id, 'h96);
+
+ end
+ endtask;
+
+ task lacp_config(int df_hp_id, int df_br_id, int df_un_id);
+ uint64_t tmp;
+ tmp = (`TRU_LACR_AGG_DF_HP_ID & (df_hp_id << `TRU_LACR_AGG_DF_HP_ID_OFFSET)) |
+ (`TRU_LACR_AGG_DF_BR_ID & (df_br_id << `TRU_LACR_AGG_DF_BR_ID_OFFSET)) |
+ (`TRU_LACR_AGG_DF_UN_ID & (df_un_id << `TRU_LACR_AGG_DF_UN_ID_OFFSET));
+ m_acc.write(m_base +`ADDR_TRU_LACR, tmp );
+ if(m_dbg)
+ begin
+ $display("TRU: Link Aggregation config:");
+ $display("\tDistribution Function for High Priority traffic: id = %2d",df_hp_id);
+ $display("\tDistribution Function for Broadcast traffic: id = %2d",df_br_id);
+ $display("\tDistribution Function for Unicast traffic: id = %2d",df_un_id);
+ end
+ endtask;
+
+ task rt_reconf_enable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp | 1 << `TRU_RTRCR_RTR_ENA_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: Real Time re-configuration enable");
+ end
+ endtask;
+
+ task rt_reconf_disable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp | !(1 << `TRU_RTRCR_RTR_ENA_OFFSET));
+ if(m_dbg)
+ begin
+ $display("TRU: Real Time re-configuration disable");
+ end
+ endtask;
+
+ task rt_reconf_reset();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp | 1 << `TRU_RTRCR_RTR_RESET_OFFSET);
+ if(m_dbg)
+ begin
+ $display("TRU: Real Time re-configuration reset (memory)");
+ end
+ endtask;
+
+ task read_status(output int bank, output int ports_up, output int ports_stb_up);
+ uint64_t tmp;
+
+ m_acc.read(m_base + `ADDR_TRU_GSR0, tmp, 4);
+ bank = (tmp & `TRU_GSR0_STAT_BANK) >> `TRU_GSR0_STAT_BANK_OFFSET;
+ ports_stb_up = (tmp & `TRU_GSR0_STAT_STB_UP) >> `TRU_GSR0_STAT_STB_UP_OFFSET;
+
+ m_acc.read(m_base + `ADDR_TRU_GSR1, tmp, 4);
+ ports_up = (tmp & `TRU_GSR1_STAT_UP) >> `TRU_GSR1_STAT_UP_OFFSET;
+ if(m_dbg)
+ begin
+ $display("TRU: status read:");
+ $display("\tactive TABLE bank : %2d", bank);
+ $display("\tports status (1:up, 0: down): 0x%x", ports_up);
+ $display("\tports stabily UP (1:up : 0x%x", ports_stb_up);
+ end
+ endtask;
+
+ task tru_port_config(int fid);
+ int backup = 0;
+
+
+ $display("====== Ports settings for FID = %2d ===========",fid);
+ for(int i=0;i<m_port_number; i++)
+ begin
+ if(m_tru_tab[fid][0].ports_ingress[i] &
+ m_tru_tab[fid][0].ports_egress[i] &
+ m_tru_tab[fid][0].ports_mask[i])
+ $display("Port %2d - active", i);
+ if(~m_tru_tab[fid][0].ports_ingress[i] &
+ m_tru_tab[fid][0].ports_egress[i] &
+ m_tru_tab[fid][0].ports_mask[i])
+ $display("Port %2d - egress-only", i);
+ if(m_tru_tab[fid][0].ports_ingress[i] &
+ ~m_tru_tab[fid][0].ports_egress[i] &
+ m_tru_tab[fid][0].ports_mask[i])
+ $display("Port %2d - egress-only", i);
+ if((~m_tru_tab[fid][0].ports_ingress[i] &
+ ~m_tru_tab[fid][0].ports_egress[i]) |
+ ~m_tru_tab[fid][0].ports_mask[i])
+ $display("Port %2d - blocking", i);
+ for(int j=1;j<`c_tru_subentry_num; j++)
+ begin
+ if(m_tru_tab[fid][j].valid &
+ m_tru_tab[fid][j].ports_ingress[i] &
+ m_tru_tab[fid][j].ports_egress[i] &
+ m_tru_tab[fid][j].ports_mask[i])
+ begin
+ for(int g=0;g<m_port_number;g++)
+ begin
+ backup = 0;
+ if(m_tru_tab[fid][j].pattern_match[g] &
+ m_tru_tab[fid][j].pattern_mask[g])
+ begin
+ if(backup == 0)
+ begin
+ $display(" backup for port %2d",g);
+ backup = 1;
+ end
+ end
+ end
+ end
+ end
+ end
+ $display("===============================================");
+ endtask;
+
+endclass // CSimDrv_WR_TRU
+
+`endif // `ifndef __SIMDRV_WR_TRU_SVH
diff --git a/sim/simdrv_wrsw_nic.svh b/sim/simdrv_wrsw_nic.svh
index 1bd5e14d8f81df1eaf14c290de2ba8eec1d371c6..3b4690ba7189ace25ff2789f52b809fd9c3df9c5 100644
--- a/sim/simdrv_wrsw_nic.svh
+++ b/sim/simdrv_wrsw_nic.svh
@@ -508,7 +508,18 @@ class NICPacketSink extends EthPacketSink;
function int poll();
return (nic.rx_queue.size() > 0) ? 1 :0;
endfunction // poll
-
+
+ //ML stuff
+ function int permanent_stall_enable();
+ //empty
+ return 0;
+ endfunction
+ //ML stuff
+ function int permanent_stall_disable();
+ // empty
+ return 0;
+ endfunction
+
task recv(ref EthPacket pkt, ref int result = _null);
while(!nic.rx_queue.size()) #1ns;
pkt = nic.rx_queue.pop_front();
diff --git a/syn/scb_15ports/Manifest.py b/syn/scb_15ports/Manifest.py
index 1a42e2cb8a2b13222da01c2cc25140bd88791f3a..45f282c3170baa0c9e6f9c0cbeb6d4036ce8b828 100644
--- a/syn/scb_15ports/Manifest.py
+++ b/syn/scb_15ports/Manifest.py
@@ -3,7 +3,7 @@ action = "synthesis"
fetchto = "../../ip_cores"
-syn_device = "xc6vlx130t"
+syn_device = "xc6vlx240t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
diff --git a/syn/scb_18ports/Manifest.py b/syn/scb_18ports/Manifest.py
index 06ec2f903a05c6b0f9df372de61eda2d782ec4cc..914405427b81db9cb741af36546392d0ccba98ab 100644
--- a/syn/scb_18ports/Manifest.py
+++ b/syn/scb_18ports/Manifest.py
@@ -3,10 +3,12 @@ action = "synthesis"
fetchto = "../../ip_cores"
-syn_device = "xc6vlx130t"
+syn_device = "xc6vlx240t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
syn_project = "test_scb.xise"
-modules = { "local" : [ "../../top/scb_18ports" ] }
+modules = { "local" : [ "../../top/scb_18ports",
+ "../../ip_cores/general-cores",
+ "../../ip_cores/wr-cores" ] }
diff --git a/syn/scb_18ports/test_scb.xise b/syn/scb_18ports/test_scb.xise
index 41ff81fc4b6cca74eab7f48c35672e9f697f2e40..6e289fb87b3abfa39d3b2573673eefef56397130 100644
--- a/syn/scb_18ports/test_scb.xise
+++ b/syn/scb_18ports/test_scb.xise
@@ -79,7 +79,7 @@
<property xil_pn:name="DCI Update Mode" xil_pn:value="Quiet(Off)" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx240t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -123,7 +123,7 @@
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -134,7 +134,7 @@
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
@@ -158,8 +158,8 @@
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Map" xil_pn:value="Area" xil_pn:valueState="non-default"/>
- <property xil_pn:name="LUT Combining Xst" xil_pn:value="Area" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Minimum Runtime" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Runtime Reduction with Multi-Threading;/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
@@ -202,7 +202,7 @@
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="scb_top_synthesis" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -211,14 +211,14 @@
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="scb_top_synthesis_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="scb_top_synthesis_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="scb_top_synthesis_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="scb_top_synthesis_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Extra Effort" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@@ -233,7 +233,7 @@
<property xil_pn:name="Read Cores" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
@@ -309,7 +309,7 @@
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -351,756 +351,933 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../modules/wrsw_swcore/ram_bug/buggy_ram.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
- <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+ <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
- <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_descriptors_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_descriptor_manager.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_descriptors_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_descriptor_manager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_tx_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/wrsw_nic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
- <file xil_pn:name="../../modules/wrsw_shared_types_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/xwrsw_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
- <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/wrsw_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
- <file xil_pn:name="../../top/bare_top/wrsw_top_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_swcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_shared_types_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_linked_list.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../top/bare_top/wrsw_top_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_swcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_linked_list.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_ob_prio_queue.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_alloc_resource_manager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_input.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_output.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_ob_prio_queue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_input.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_elastic_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_output.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/xswc_input_block.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
- <file xil_pn:name="../../top/bare_top/scb_top_bare.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_output_queue_scheduler.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_ll_read_data_validation.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_core.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_elastic_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/PCK_CRC16_D16.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_output_block_new.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_ll_read_data_validation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/pack_unpack_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_lookup_engine.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_components_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_output_traffic_shaper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/PCK_CRC16_D16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_port.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/xwrsw_rtu.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/pack_unpack_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/wrsw_rtu.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_fast_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_match.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_lookup_engine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
- <file xil_pn:name="../../platform/xilinx/pll200MhZ.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_components_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_port_new.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/xwrsw_rtu_new.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_top.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/wrsw_tru_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_write_path.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_read_path.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/xwrsw_tru.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/wrsw_tru_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/xswc_core.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_sub_vlan_pattern.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
- <file xil_pn:name="../../top/scb_18ports/scb_top_synthesis.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_transition.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_trans_marker_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_trans_lacp_dist.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tru/tru_trans_lacp_colect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
- <file xil_pn:name="../../top/bare_top/scb_top_sim.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../top/bare_top/wb_cpu_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../top/scb_18ports/scb_top_synthesis.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../top/bare_top/scb_top_bare.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tatsu/xwrsw_tatsu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_tatsu/tatsu_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/pstats_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/port_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/irq_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/pstats_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_pstats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/xwrsw_pstats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_rx_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_hwdu/hwdu_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_hwdu/wrsw_hwdu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_hwdu/xwrsw_hwdu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../platform/xilinx/pll200MhZ.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_write_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_read_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_rx_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../top/bare_top/scb_top_sim.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
- <file xil_pn:name="../../modules/wrsw_swcore/xswc_output_block.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
- <file xil_pn:name="../../modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/xwr_eca.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/xwr_eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_tx_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wbp_mux.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
- <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
- <file xil_pn:name="../../top/bare_top/wb_cpu_bridge.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/xwrsw_nic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_fifo_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../modules/wrsw_nic/nic_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_fifo_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
</file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
</file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="250"/>
</file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="251"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="252"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="253"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="254"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="255"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="256"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="257"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="258"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="259"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="260"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="261"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="262"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="263"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="264"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="265"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="266"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="267"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="268"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="269"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="270"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="271"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="272"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="273"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="274"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="275"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="276"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="277"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="278"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="279"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="280"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="281"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="282"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="283"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="284"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="285"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="286"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="287"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="288"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="289"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="290"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="291"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="292"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="293"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="294"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="295"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="296"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="297"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="298"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="299"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="300"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="301"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="302"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="303"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="304"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="305"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="306"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="307"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="308"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="309"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="310"/>
+ </file>
</files>
<bindings/>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
</project>
diff --git a/syn/scb_8ports/Manifest.py b/syn/scb_8ports/Manifest.py
index 3d413bcba9cb373276e2284af13c7f9a1fb6df35..bb646b23293a73304f3364c10ff18680b765dc9b 100644
--- a/syn/scb_8ports/Manifest.py
+++ b/syn/scb_8ports/Manifest.py
@@ -3,10 +3,13 @@ action = "synthesis"
fetchto = "../../ip_cores"
-syn_device = "xc6vlx130t"
+#syn_device = "xc6vlx130t"
+syn_device = "xc6vlx240t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
syn_project = "test_scb.xise"
-modules = { "local" : [ "../../top/scb_8ports" ] }
+modules = { "local" : [ "../../top/scb_8ports",
+ "../../ip_cores/general-cores",
+ "../../ip_cores/wr-cores" ] }
diff --git a/syn/scb_8ports/test_scb.xise b/syn/scb_8ports/test_scb.xise
index 480c773d2752116322bd6fc20b0e85e0a94eebf9..49518f75d75cc532c7ee662d24b02a45c92058e1 100644
--- a/syn/scb_8ports/test_scb.xise
+++ b/syn/scb_8ports/test_scb.xise
@@ -1,1112 +1,993 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<?xml version="1.0" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
- <properties>
- <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="50" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="Quiet(Off)" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
- <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="2" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
- <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|scb_top_synthesis|Behavioral" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/scb_test/scb_top_synthesis.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/scb_top_synthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Map" xil_pn:value="Area" xil_pn:valueState="non-default"/>
- <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Applied Goal" xil_pn:value="Minimum Runtime" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Last Applied Strategy" xil_pn:value="Runtime Reduction with Multi-Threading;/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
- <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="scb_top_synthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="scb_top_synthesis_map.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="scb_top_synthesis_timesim.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="scb_top_synthesis_synthesis.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="scb_top_synthesis_translate.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Read Cores" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="test_scb" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-11T16:12:13" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1A4D4649CF666ED7BAA8C2DBABE3B6A0" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <libraries/>
-
- <files>
- <file xil_pn:name="../../top/scb_8ports/scb_top_synthesis.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/ram_bug/buggy_ram.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_descriptors_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_descriptor_manager.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_tx_fsm.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/wrsw_nic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_shared_types_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
- </file>
- <file xil_pn:name="../../top/bare_top/wrsw_top_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_swcore_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_linked_list.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_ob_prio_queue.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_input.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_output.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_elastic_buffer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/xswc_input_block.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
- </file>
- <file xil_pn:name="../../top/bare_top/scb_top_bare.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_ll_read_data_validation.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/swc_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/PCK_CRC16_D16.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_private_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/pack_unpack_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_lookup_engine.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_components_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_port.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/xwrsw_rtu.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/wrsw_rtu.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_rtu/rtu_match.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
- </file>
- <file xil_pn:name="../../platform/xilinx/pll200MhZ.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_private_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_top.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_write_path.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_read_path.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/xswc_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
- </file>
- <file xil_pn:name="../../top/scb_8ports/scb_top_synthesis.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
- </file>
- <file xil_pn:name="../../top/bare_top/scb_top_sim.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_rx_fsm.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_swcore/xswc_output_block.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_eca/xwr_eca.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_eca/xwr_eca_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wbp_mux.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
- </file>
- <file xil_pn:name="../../../wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
- </file>
- <file xil_pn:name="../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
- </file>
- <file xil_pn:name="../../top/bare_top/wb_cpu_bridge.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_buffer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="179"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/xwrsw_nic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/virtex6/v6_fifo_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="224"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="225"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="226"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="227"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="228"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="229"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="230"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="231"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="232"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="233"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="234"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="235"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="Implementation" xil_pn:seqID="236"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="237"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="238"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="239"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="240"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="241"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="242"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="243"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="244"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="245"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="246"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="247"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="248"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="249"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="250"/>
- </file>
- <file xil_pn:name="../../../general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="251"/>
- </file>
- <file xil_pn:name="../../modules/wrsw_nic/nic_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="252"/>
- </file>
- </files>
-
- <bindings/>
-
- <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
-
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+</header>
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+</autoManagedFiles>
+ <properties>
+ <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+ <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="50" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="Quiet(Off)" xil_pn:valueState="default"/>
+ <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx240t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="2" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|scb_top_synthesis|Behavioral" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/scb_test/scb_top_synthesis.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/scb_top_synthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Area" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Goal" xil_pn:value="Minimum Runtime" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Last Applied Strategy" xil_pn:value="Runtime Reduction with Multi-Threading;/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="scb_top_synthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="scb_top_synthesis_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="scb_top_synthesis_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="scb_top_synthesis_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="scb_top_synthesis_translate.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.3/ISE_DS/ISE/virtex6/data/virtex6_runtime_multithreading.xds" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="test_scb" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-11T16:12:13" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1A4D4649CF666ED7BAA8C2DBABE3B6A0" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+</properties>
+ <libraries/>
+ <files>
+ <file xil_pn:name="../../top/scb_8ports/scb_top_synthesis.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/ram_bug/buggy_ram.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+</file>
+ <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+</file>
+ <file xil_pn:name="../../platform/virtex6/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+</file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+</file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_constants_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_descriptors_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+</file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_descriptor_manager.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/xwrsw_nic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/wrsw_nic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_shared_types_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_txtsu/wrsw_txtsu_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+</file>
+ <file xil_pn:name="../../top/bare_top/wrsw_top_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_swcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_linked_list.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/optimized_new_allocator/swc_multiport_page_allocator.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_alloc_resource_manager.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_ob_prio_queue.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_pg_free_module.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_input.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_pck_transfer_output.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_output_queue_scheduler.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_elastic_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_output_block_new.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_input_block.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_ll_read_data_validation.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/swc_output_traffic_shaper.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/PCK_CRC16_D16.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/pack_unpack_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_fast_match.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_lookup_engine.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_components_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_crc.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_port_new.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/xwrsw_rtu_new.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_rtu/rtu_match.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/wrsw_tru_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/xwrsw_tru.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/wrsw_tru_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_port.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_sub_vlan_pattern.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_transition.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_trans_marker_trig.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_trans_lacp_dist.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tru/tru_trans_lacp_colect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+</file>
+ <file xil_pn:name="../../top/bare_top/wb_cpu_bridge.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
+</file>
+ <file xil_pn:name="../../top/scb_8ports/scb_top_synthesis.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+</file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
+</file>
+ <file xil_pn:name="../../top/bare_top/scb_top_bare.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tatsu/xwrsw_tatsu.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_tatsu/tatsu_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/pstats_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/port_cntr.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/irq_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/pstats_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_pstats.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/xwrsw_pstats.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_dummy/dummy_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_dummy/dummy_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_pstats/wrsw_dummy/dummy_rmon.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_hwdu/hwdu_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_hwdu/wrsw_hwdu.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_hwdu/xwrsw_hwdu.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
+</file>
+ <file xil_pn:name="../../platform/xilinx/pll200MhZ.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_fifo_mem_cell.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_shrink_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_pipelined_mux.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_top.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_write_path.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_read_path.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/mpm/mpm_rpath_core_block.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_rx_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+</file>
+ <file xil_pn:name="../../top/bare_top/scb_top_sim.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_nic/nic_tx_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_swcore/xswc_output_block.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
+</file>
+ <file xil_pn:name="../../modules/wrsw_txtsu/xwrsw_txtsu.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="179"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
+</file>
+</files>
+ <bindings/>
+ <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
</project>
diff --git a/syn/test_tru/test_tru.xise b/syn/test_tru/test_tru.xise
new file mode 100644
index 0000000000000000000000000000000000000000..6559647aade893c2ebba8b2d59b4131ac39cd6c6
--- /dev/null
+++ b/syn/test_tru/test_tru.xise
@@ -0,0 +1,545 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_port.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_reconfig_rt_port_handler.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_sub_vlan_pattern.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_trans_lacp_colect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_trans_lacp_dist.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_trans_marker_trig.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_transition.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_wishbone_slave.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/tru_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/wrsw_tru_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_tru/xwrsw_tru.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_fifo_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_shared_types_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_rtu/rtu_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/modules/wrsw_rtu/rtu_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../../../stupid_ise/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+ <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+ <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+ <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="Quiet(Off)" xil_pn:valueState="default"/>
+ <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+ <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx240t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Evaluation Development Board" xil_pn:value="Virtex 6 ML605 Evaluation Platform" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+ <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|xwrsw_tru|rtl" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="../../modules/wrsw_tru/xwrsw_tru.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/xwrsw_tru" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+ <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+ <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="xwrsw_tru" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="xwrsw_tru_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="xwrsw_tru_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="xwrsw_tru_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="xwrsw_tru_translate.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="../../../../stupid_ise/syn/test_tru" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="test_tru" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-09-13T14:56:11" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3B4820FBE00AEC0E8C508B227688D5A5" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="OutSideAbove" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/testbench/scb_network_top/Manifest.py b/testbench/scb_network_top/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..09db7a266d1648085e526ab29698607be5c7e9ce
--- /dev/null
+++ b/testbench/scb_network_top/Manifest.py
@@ -0,0 +1,12 @@
+target = "xilinx"
+action = "simulation"
+syn_device = "XC6VLX130T"
+fetchto = "../../ip_cores"
+vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
+
+files = [ "main.sv" ]
+
+modules = { "local" : ["../../", "../../top/bare_top"] }
+
+
+
diff --git a/testbench/scb_network_top/main.sv b/testbench/scb_network_top/main.sv
new file mode 100644
index 0000000000000000000000000000000000000000..e28cb9b773f33968820339373816de4d3040c293
--- /dev/null
+++ b/testbench/scb_network_top/main.sv
@@ -0,0 +1,416 @@
+`timescale 1ns/1ps
+
+`include "tbi_utils.sv"
+`include "simdrv_wrsw_nic.svh"
+`include "simdrv_rtu.sv"
+`include "simdrv_wr_tru.svh"
+`include "simdrv_txtsu.svh"
+`include "endpoint_regs.v"
+`include "endpoint_mdio.v"
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+`include "wb_packet_source.svh"
+`include "wb_packet_sink.svh"
+
+`include "scb_top_sim_svwrap.svh"
+
+
+
+module main;
+
+ reg clk_ref=0;
+ reg clk_sys=0;
+ reg clk_swc_mpm_core=0;
+ reg rst_n=0;
+
+ parameter g_num_ports = 18;
+ parameter g_scb_number = 3; // dont' try to change :)
+ parameter g_port_bunch_number = 6; // dont' try to change :)
+ reg [g_num_ports-1:0] ep_ctrl;
+
+ // prameters to create some gaps between pks (not work really well)
+ parameter g_enable_pck_gaps = 1; //1=TRUE, 0=FALSE
+ parameter g_min_pck_gap = 100; // cycles
+ parameter g_max_pck_gap = 500; // cycles
+
+ reg [18:0] portUnderTest = 18'b000000000000001111; // unicast
+
+ integer repeat_number = 10;
+ integer tries_number = 3;
+
+ always #2.5ns clk_swc_mpm_core <=~clk_swc_mpm_core;
+ always #8ns clk_sys <= ~clk_sys;
+ always #8ns clk_ref <= ~clk_ref;
+
+ initial begin
+ repeat(100) @(posedge clk_sys);
+ rst_n <= 1;
+ end
+/*
+ * wait ncycles
+ */
+ task automatic wait_cycles;
+ input [31:0] ncycles;
+ begin : wait_body
+ integer i;
+
+ for(i=0;i<ncycles;i=i+1) @(posedge clk_sys);
+
+ end
+ endtask // wait_cycles
+
+// assign clk_ref = clk_sys;
+
+ task automatic tx_test(ref int seed, input int n_tries, input int is_q,input int unvid, ref EthPacketSource src, ref EthPacketSink sink, input int srcPort, input int dstPort, input int opt=0);
+ EthPacketGenerator gen = new;
+ EthPacket pkt, tmpl, pkt2;
+ EthPacket arr[];
+ //int i,j;
+
+ arr = new[n_tries](arr);
+ if(opt !=3 && opt != 4)
+ gen.set_seed(seed);
+
+ tmpl = new;
+
+ if(opt==3 || opt==4)
+ tmpl.src = '{0, 2,3,4,5,6};
+ else
+ tmpl.src = '{srcPort, 2,3,4,5,6};
+
+ if(opt==0)
+ tmpl.dst = '{dstPort, 'h50, 'hca, 'hfe, 'hba, 'hbe};
+ else if(opt==1)
+ tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF};
+ else if(opt==2)
+ tmpl.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h00};
+ else if(opt==3)
+ tmpl.dst = '{17, 'h50, 'hca, 'hfe, 'hba, 'hbe};
+ else if(opt==4)
+ tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF};
+
+ tmpl.has_smac = 1;
+ tmpl.is_q = is_q;
+ tmpl.vid = 100;
+ tmpl.ethertype = 'h88f7;
+ //
+ gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::SEQ_ID);
+ gen.set_template(tmpl);
+ gen.set_size(63, 257);
+
+ fork
+ begin
+ for(int i=0;i<n_tries;i++)
+ begin
+ pkt = gen.gen();
+ pkt.oob = TX_FID;
+
+ $display("[port %d] tx %d", srcPort, i);
+
+ src.send(pkt);
+ arr[i] = pkt;
+ //pkt.dump();
+ // repeat(3000) @(posedge clk_sys);
+
+ // $display("Send: %d [dsize %d]", i+1,pkt.payload.size() + 14);
+
+ end
+ end
+ begin
+ for(int j=0;j<n_tries;j++)
+ begin
+ sink.recv(pkt2);
+ $display("rx %d at port %d", j,dstPort);
+ //pkt2.dump();
+ if(unvid)
+ arr[j].is_q = 0;
+
+ if(!arr[j].equal(pkt2))
+ begin
+ $display("Fault at %d", j);
+ $display("Should be: ");
+ arr[j].dump();
+ $display("Is: ");
+ pkt2.dump();
+ //$fatal("dupa"); //ML
+ //sfp $stop;
+ end
+ end // for (i=0;i<n_tries;i++)
+ end
+ join
+ seed = gen.get_seed();
+
+ if(g_enable_pck_gaps == 1)
+ wait_cycles($dist_uniform(seed,g_min_pck_gap,g_max_pck_gap));
+
+ endtask // tx_test
+
+ scb_top_sim_svwrap
+ #(
+ .g_num_ports(g_num_ports)
+ ) DUT (
+ .clk_sys_i(clk_sys),
+ .clk_ref_i(clk_ref),
+ .rst_n_i(rst_n),
+ .cpu_irq(),
+ .clk_swc_mpm_core_i(clk_swc_mpm_core),
+ .ep_ctrl_i(ep_ctrl)
+ );
+
+ typedef struct {
+ CSimDrv_WR_Endpoint ep;
+ EthPacketSource send;
+ EthPacketSink recv;
+ } port_t;
+
+ /// simulation endpoints
+ port_t ports[$];
+ CSimDrv_NIC nic[3];
+
+ /// Switches
+ CRTUSimDriver rtu[3];
+ CSimDrv_WR_TRU tru[3];
+ CSimDrv_TXTSU txtsu[3];
+
+ task automatic init_ports(ref port_t p[$], ref CWishboneAccessor wb, int scp_nr);
+ int i;
+
+// for(i=0;i<g_port_bunch_number;i++)
+ for(i=0;i<g_num_ports;i++)
+ begin
+ port_t tmp;
+ CSimDrv_WR_Endpoint ep;
+ ep = new(wb, 'h30000 + i * 'h400);
+ ep.init(i);
+ if(i<g_port_bunch_number) begin
+ tmp.ep = ep;
+ tmp.send = EthPacketSource'(DUT.to_port[i+g_port_bunch_number*scp_nr]);
+ tmp.recv = EthPacketSink'(DUT.from_port[i+g_port_bunch_number*scp_nr]);
+ p.push_back(tmp);
+ end
+ end
+ endtask // init_endpoints
+
+ task automatic init_nic(ref port_t p[$],ref CWishboneAccessor wb, int scp_nr);
+ NICPacketSource nic_src;
+ NICPacketSink nic_snk;
+ port_t tmp;
+
+ nic[scp_nr] = new(wb, 'h20000);
+ $display("NICInit");
+ nic[scp_nr].init();
+ $display("Done");
+
+ nic_src = new (nic[scp_nr]);
+ nic_snk = new (nic[scp_nr]);
+ $display("Src: %x\n",nic_src);
+
+ tmp.send = EthPacketSource'(nic_src);
+ tmp.recv = EthPacketSink'(nic_snk);
+ p.push_back(tmp);
+
+ endtask // init_nic
+
+ task automatic init_tru(input CSimDrv_WR_TRU tru_drv);
+
+ $display(">>>>>>>>>>>>>>>>>>> TRU initialization <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tru_drv.pattern_config(1 /*replacement*/ ,2 /*addition*/);
+ tru_drv.rt_reconf_config(4 /*tx_frame_id*/, 4/*rx_frame_id*/, 1 /*mode*/);
+ tru_drv.rt_reconf_enable();
+
+ /*
+ * transition
+ **/
+ tru_drv.transition_config(0 /*mode */, 4 /*rx_id*/, 0 /*prio*/, 20 /*time_diff*/,
+ 3 /*port_a_id*/, 4 /*port_b_id*/);
+
+ /*
+ * | port | ingress | egress |
+ * |--------------------------|
+ * | 0 | 1 | 1 |
+ * | 1 | 0 | 1 |
+ * | 2 | 1 | 1 |
+ * | 3 | 1 | 1 |
+ * | 4 | 1 | 1 |
+ * | 5 | 0 | 1 |
+ * |--------------------------|
+ *
+ * 5 -> 1 -> 0
+ * ----------------
+ * port 1 is backup for 0
+ * port 5 is backup ofr 1
+ *
+ **/
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h000 /* pattern_mode */,
+ 32'h3FFFF /*ports_mask */, 32'b111000000010100001 /* ports_egress */,32'b111000000010100001 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000011 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h0 /* pattern_mode */,
+ 32'b00000011 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'b00000011 /*pattern_mask*/, 32'b00000011 /* pattern_match*/,'h0 /* pattern_mode */,
+ 32'b00000111 /*ports_mask */, 32'b00000100 /* ports_egress */,32'b00000100 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.tru_swap_bank();
+ tru_drv.tru_enable();
+ tru_drv.tru_port_config(0);
+ $display("TRU configured and enabled");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ endtask; //init_tru
+ task automatic init_rtu(input CRTUSimDriver rtu, bit[31:0] vlanMask, bit[17:0] staticEntries = 0, bit RTUeX=0);
+ rtu_vlan_entry_t def_vlan;
+ $display(">>>>>>>>>>>>>>>>>>> RTU initialization <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ for (int dd=0;dd<g_num_ports;dd++)
+ begin
+ rtu.set_port_config(dd, 1, 0, 1);
+ end
+
+ rtu.set_port_config(g_num_ports, 1, 0, 0); // for NIC
+
+ if(staticEntries[0]) rtu.add_static_rule('{17, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<17));
+ if(staticEntries[1]) rtu.add_static_rule('{16, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<16));
+ if(staticEntries[2]) rtu.add_static_rule('{15, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<15));
+ if(staticEntries[3]) rtu.add_static_rule('{14, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<14));
+ if(staticEntries[4]) rtu.add_static_rule('{13, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<13));
+ if(staticEntries[5]) rtu.add_static_rule('{12, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<12));
+ if(staticEntries[6]) rtu.add_static_rule('{11, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<11));
+ if(staticEntries[7]) rtu.add_static_rule('{10, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<10));
+ if(staticEntries[8]) rtu.add_static_rule('{ 9, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<9 ));
+ if(staticEntries[9]) rtu.add_static_rule('{ 8, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<8 ));
+ if(staticEntries[10]) rtu.add_static_rule('{ 7, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<7 ));
+ if(staticEntries[11]) rtu.add_static_rule('{ 6, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<6 ));
+ if(staticEntries[12]) rtu.add_static_rule('{ 5, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<5 ));
+ if(staticEntries[13]) rtu.add_static_rule('{ 4, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<4 ));
+ if(staticEntries[14]) rtu.add_static_rule('{ 3, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<3 ));
+ if(staticEntries[15]) rtu.add_static_rule('{ 2, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<2 ));
+ if(staticEntries[16]) rtu.add_static_rule('{ 1, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<1 ));
+ if(staticEntries[17]) rtu.add_static_rule('{ 0, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<0 ));
+
+ def_vlan.port_mask = vlanMask;
+ def_vlan.fid = 0;
+ def_vlan.drop = 0;
+ def_vlan.prio = 0;
+ def_vlan.has_prio = 0;
+ def_vlan.prio_override = 0;
+
+ rtu.add_vlan_entry(0, def_vlan);
+ if(RTUeX) begin
+// rtu.rx_add_ff_mac_single(0/*ID*/,1/*valid*/,'h1150cafebabe /*MAC*/);
+// rtu.rx_add_ff_mac_single(1/*ID*/,1/*valid*/,'h111111111111/*MAC*/);
+// rtu.rx_add_ff_mac_range (0/*ID*/,1/*valid*/,'h0050cafebabe/*MAC_lower*/,'h0850cafebabe/*MAC_upper*/);
+// rtu.rx_set_port_mirror ('h00020000 /*mirror_src_mask*/,'h00000008 /*mirror_dst_mask*/,0/*rx*/,1/*tx*/);
+// rtu.rx_set_hp_prio_mask ('b10000001 /*hp prio mask*/); //HP traffic set to 7th priority
+// rtu.rx_set_cpu_port ((1<<g_num_ports)/*mask: virtual port of CPU*/);
+// // rtu.rx_forward_on_fmatch_full();
+// rtu.rx_drop_on_fmatch_full();
+ rtu.rx_feature_ctrl(0 /*mr*/, 0 /*mac_ptp*/, 0/*mac_ll*/, 0/*mac_single*/, 0/*mac_range*/, 1/*mac_br*/);
+ end
+ ////////////////////////////////////////////////////////////////////////////////////////
+
+ rtu.enable();
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ endtask; //init_tru
+ /// ========================================= main stuff =================================//
+ initial begin
+ uint64_t msr;
+ int seed;
+ bit [31:0] vlanMasks[3];
+
+ CWishboneAccessor cpu_acc[3]; //= DUT.cpu.get_accessor();
+ cpu_acc[0] = DUT.cpu_0.get_accessor();
+ cpu_acc[1] = DUT.cpu_1.get_accessor();
+ cpu_acc[2] = DUT.cpu_2.get_accessor();
+
+ for(int gg=0;gg<g_num_ports;gg++)
+ begin
+ ep_ctrl[gg] = 'b1;
+ end
+ repeat(200) @(posedge clk_sys);
+
+ $display("Startup!");
+
+ for(int i=0;i<g_scb_number;i++) begin
+ cpu_acc[i].set_mode(PIPELINED);
+ cpu_acc[i].write('h10304, (1<<3));
+ init_ports(ports, cpu_acc[i],i);
+ end
+
+ vlanMasks[0] = 32'h00011F1;
+ vlanMasks[1] = 32'h0001111;
+ vlanMasks[2] = 32'h0001011;
+
+ for(int i=0;i<g_scb_number;i++) begin
+
+ $display("Switch_%1d: InitNIC",i);
+ init_nic(ports, cpu_acc[i],i);
+
+ $display("Switch_%1d: InitTXTS",i);
+
+ txtsu[i] = new (cpu_acc[i], 'h51000);
+ txtsu[i].init();
+
+ $display("Switch_%1d: Initialization done",i);
+
+ rtu[i] = new;
+ rtu[i].set_bus(cpu_acc[i], 'h60000);
+
+ init_rtu(rtu[i], vlanMasks[i] /* VLAN */, 32'h00000000 /* static entries */, 1 /* RTUeX*/);
+ end
+ fork
+// begin
+// wait_cycles(500);
+// ep_ctrl[0] = 'b0;
+// wait_cycles(500);
+// ep_ctrl[1] = 'b0;
+// end
+ begin
+ if(portUnderTest[0])
+ begin
+ for(int g=0;g<tries_number;g++)
+ begin
+ $display("Try port_0:%d", g);
+ tx_test(seed /* seed */, repeat_number /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[0].send /* src */, ports[12].recv /* sink */, 0 /* srcPort */ , 12 /* dstPort */, 4 /*option*/);
+ end
+ end
+ end // fork begin
+
+ /// Switch 0
+ forever begin
+ nic[0].update(DUT.U_SW_0.U_Wrapped_SCBCore.vic_irqs[0]);
+ @(posedge clk_sys);
+ end
+ forever begin
+ txtsu[0].update(DUT.U_SW_0.U_Wrapped_SCBCore.vic_irqs[1]);
+ @(posedge clk_sys);
+ end
+ /// Switch 1
+ forever begin
+ nic[0].update(DUT.U_SW_1.U_Wrapped_SCBCore.vic_irqs[0]);
+ @(posedge clk_sys);
+ end
+ forever begin
+ txtsu[0].update(DUT.U_SW_1.U_Wrapped_SCBCore.vic_irqs[1]);
+ @(posedge clk_sys);
+ end
+ /// Switch 2
+ forever begin
+ nic[0].update(DUT.U_SW_2.U_Wrapped_SCBCore.vic_irqs[0]);
+ @(posedge clk_sys);
+ end
+ forever begin
+ txtsu[0].update(DUT.U_SW_2.U_Wrapped_SCBCore.vic_irqs[1]);
+ @(posedge clk_sys);
+ end
+ join_none
+
+ end // initial begin
+
+endmodule // main
+
diff --git a/testbench/scb_network_top/run.do b/testbench/scb_network_top/run.do
new file mode 100644
index 0000000000000000000000000000000000000000..10b1d768e9ba393b8b9b59b349857e7b93e332cf
--- /dev/null
+++ b/testbench/scb_network_top/run.do
@@ -0,0 +1,13 @@
+make -f Makefile
+#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
+vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+# do wave_new.do
+#do wave-master.do
+#do wave-allports.do
+radix -hexadecimal
+run 4000us
+wave zoomfull
+radix -hexadecimal
diff --git a/testbench/scb_network_top/scb_top_sim_svwrap.svh b/testbench/scb_network_top/scb_top_sim_svwrap.svh
new file mode 100644
index 0000000000000000000000000000000000000000..bd09521d394bf3df75582feaf89a6537dbf7948e
--- /dev/null
+++ b/testbench/scb_network_top/scb_top_sim_svwrap.svh
@@ -0,0 +1,402 @@
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "simdrv_wr_endpoint.svh"
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+
+`define c_max_pipe_len 100
+
+
+function automatic bit f_next_8b10b_disparity8(bit cur_disp, bit k, bit [7:0] data);
+ const bit[0:31] c_disPar_6b = 32'b11101000100000011000000110010111;
+ const bit [0:7] c_disPar_4b = 8'b10001001;
+ bit dp4bit, dp6bit, new_disp;
+
+ dp4bit = c_disPar_4b[data[7:5]];
+ dp6bit = c_disPar_6b[data[4:0]];
+ new_disp = cur_disp;
+
+
+ case (cur_disp)
+ 1'b0: if (k ^ dp6bit ^ dp4bit)
+ new_disp = 1;
+ 1'b1: if (k ^ dp6bit ^ dp4bit)
+ new_disp = 0;
+ endcase // case (cur_disp)
+
+ if ( data[1:0] != 2'b0 && k)
+ new_disp = cur_disp;
+
+ return new_disp;
+endfunction // f_next_8b10b_disparity8
+
+function automatic bit f_next_8b10b_disparity16(bit cur_disp,bit[1:0] k, bit[15:0] data);
+ bit tmp;
+ bit [7:0] msb;
+
+ msb = data[15:0];
+ tmp = f_next_8b10b_disparity8(cur_disp, k[1], msb);
+ tmp = f_next_8b10b_disparity8(tmp, k[0], data[7:0]);
+ return tmp;
+endfunction // f_next_8b10b_disparity16
+
+ bit[17:0] pipeline[2][`c_max_pipe_len];
+
+function automatic bit[17:0] f_link_simulation(bit[17:0] int_data, int delay, int nbr);
+
+ for(int i=`c_max_pipe_len-1;i>0;i--)
+ begin
+ pipeline[nbr][i] = pipeline[nbr][i-1];
+ end
+ pipeline[nbr][0] = int_data;
+ return pipeline[nbr][delay];
+
+endfunction;
+
+module scb_top_sim_svwrap
+ (
+ clk_sys_i,
+ clk_ref_i,
+ rst_n_i,
+ cpu_irq,
+ clk_swc_mpm_core_i,
+ ep_ctrl_i
+// links_ctrl_i
+ );
+
+ parameter g_num_ports = 18; // default
+ parameter g_port_bunch_number = 6;
+
+ input clk_sys_i, clk_ref_i,rst_n_i,clk_swc_mpm_core_i;
+ input bit[g_num_ports-1:0] ep_ctrl_i; // control (up/down) of "simulation endpoints"
+ //input bit[g_num_ports-1:0] links_ctrl_i; // control (up/down) of links connecting switches
+ //input int links_delay_i[g_num_ports-1:0] ; // delay on links connecting switches
+ output bit[2:0] cpu_irq;
+
+ wire [g_num_ports-1:0] rbclk;
+
+ wire [18 * g_num_ports - 1:0] td, rd;
+ reg [18 * g_num_ports - 1:0] sw_td[3], sw_rd[3];
+
+
+ typedef struct {
+ logic rst;
+ logic loopen;
+ logic enable;
+ logic syncen;
+ logic [15:0] tx_data;
+ logic [1:0] tx_k;
+ } t_phyif_output;
+
+
+ typedef struct {
+ logic ref_clk;
+ logic tx_disparity;
+ logic tx_enc_err ;
+ logic [15:0] rx_data ;
+ logic rx_clk ;
+ logic [1:0] rx_k ;
+ logic rx_enc_err ;
+ logic rx_bitslide ;
+ } t_phyif_input;
+
+ t_phyif_output phys_out[g_num_ports];
+ t_phyif_input phys_in[g_num_ports];
+
+ WBPacketSource to_port[g_num_ports];
+ WBPacketSink from_port[g_num_ports];
+ int seed2;
+
+ IWishboneMaster #(32, 32) cpu_0(clk_sys_i, rst_n_i);
+ IWishboneMaster #(32, 32) cpu_1(clk_sys_i, rst_n_i);
+ IWishboneMaster #(32, 32) cpu_2(clk_sys_i, rst_n_i);
+
+ initial
+ begin
+ cpu_0.settings.cyc_on_stall = 1;
+ cpu_0.settings.addr_gran = BYTE;
+ cpu_1.settings.cyc_on_stall = 1;
+ cpu_1.settings.addr_gran = BYTE;
+ cpu_2.settings.cyc_on_stall = 1;
+ cpu_2.settings.addr_gran = BYTE;
+ end
+
+ reg [g_num_ports-1:0] clk_ref_phys = 0;
+ time periods[g_num_ports];
+
+
+
+
+
+ /// generate simulation endpints
+ generate
+ genvar i;
+ for(i=0; i<g_num_ports; i++) begin
+ initial forever #(periods[i]) clk_ref_phys[i] <= ~clk_ref_phys[i];
+ initial periods[i] = 8ns;
+ IWishboneMaster U_ep_wb (clk_sys_i, rst_n_i) ;
+ IWishboneMaster #(2,16) U_ep_src (clk_sys_i, rst_n_i) ;
+ IWishboneSlave #(2,16) U_ep_snk (clk_sys_i, rst_n_i) ;
+
+ wr_endpoint
+ #(
+ .g_simulation (1),
+ .g_pcs_16bit(1),
+ .g_rx_buffer_size (1024),
+ .g_with_rx_buffer (0),
+ .g_with_timestamper (1),
+ .g_with_dpi_classifier (1),
+ .g_with_vlans (0),
+ .g_with_rtu (0)
+ ) DUT (
+ .clk_ref_i (clk_ref_phys[i]),
+ .clk_sys_i (clk_sys_i),
+ .clk_dmtd_i (clk_ref_i),
+ .rst_n_i (rst_n_i),
+ .pps_csync_p1_i (1'b0),
+
+ .phy_rst_o (phys_out[i].rst),
+ .phy_loopen_o (),
+ .phy_enable_o (),
+ .phy_syncen_o (),
+
+ .phy_ref_clk_i (phys_in[i].ref_clk),
+ .phy_tx_data_o (phys_out[i].tx_data),
+ .phy_tx_k_o (phys_out[i].tx_k),
+ .phy_tx_disparity_i (phys_in[i].tx_disparity),
+ .phy_tx_enc_err_i (phys_in[i].tx_enc_err),
+
+ .phy_rx_data_i (phys_in[i].rx_data),
+ .phy_rx_clk_i (phys_in[i].rx_clk),
+ .phy_rx_k_i (phys_in[i].rx_k),
+ .phy_rx_enc_err_i (phys_in[i].rx_enc_err),
+ .phy_rx_bitslide_i (5'b0),
+
+ .src_dat_o (U_ep_snk.slave.dat_i),
+ .src_adr_o (U_ep_snk.slave.adr),
+ .src_sel_o (U_ep_snk.slave.sel),
+ .src_cyc_o (U_ep_snk.slave.cyc),
+ .src_stb_o (U_ep_snk.slave.stb),
+ .src_we_o (U_ep_snk.slave.we),
+ .src_stall_i (U_ep_snk.slave.stall),
+ .src_ack_i (U_ep_snk.slave.ack),
+ .src_err_i(1'b0),
+
+ .snk_dat_i (U_ep_src.master.dat_o[15:0]),
+ .snk_adr_i (U_ep_src.master.adr[1:0]),
+ .snk_sel_i (U_ep_src.master.sel[1:0]),
+ .snk_cyc_i (U_ep_src.master.cyc),
+ .snk_stb_i (U_ep_src.master.stb),
+ .snk_we_i (U_ep_src.master.we),
+ .snk_stall_o (U_ep_src.master.stall),
+ .snk_ack_o (U_ep_src.master.ack),
+ .snk_err_o (U_ep_src.master.err),
+ .snk_rty_o (U_ep_src.master.rty),
+
+ .txtsu_ack_i (1'b1),
+
+ .rtu_full_i (1'b0),
+
+ .wb_cyc_i(U_ep_wb.master.cyc),
+ .wb_stb_i(U_ep_wb.master.stb),
+ .wb_we_i (U_ep_wb.master.we),
+ .wb_sel_i(U_ep_wb.master.sel),
+ .wb_adr_i(U_ep_wb.master.adr[7:0]),
+ .wb_dat_i(U_ep_wb.master.dat_o),
+ .wb_dat_o(U_ep_wb.master.dat_i),
+ .wb_ack_o (U_ep_wb.master.ack),
+
+ // new stuff
+ .tru_status_o(),
+ .tru_ctrlRd_o(),
+ .tru_rx_pck_o(),
+ .tru_rx_pck_class_o(),
+
+ .tru_ctrlWr_i(ep_ctrl_i[i]),
+ .tru_tx_pck_i(1'b0),
+ .tru_tx_pck_class_i(8'b0),
+ .tru_pauseSend_i(1'b0),
+ .tru_pauseTime_i(16'b0),
+ .tru_outQueueBlockMask_i(8'b0)
+ );
+ /// initialize the simulation endpints
+ initial begin
+ CWishboneAccessor ep_acc;
+ CSimDrv_WR_Endpoint ep_drv;
+
+ U_ep_src.settings.gen_random_throttling = 0;
+ U_ep_snk.settings.gen_random_stalls = 0;
+
+ @(posedge rst_n_i);
+ repeat(100) @(posedge clk_sys_i);
+
+ ep_acc = U_ep_wb.get_accessor();
+ ep_drv = new (ep_acc, 0);
+ ep_drv.init(0);
+
+ from_port[i] = new (U_ep_snk.get_accessor());
+ to_port[i] = new (U_ep_src.get_accessor());
+
+ end
+ end // for (i=0; i<g_num_ports; i++)
+ endgenerate
+
+ /// connections: ALL endpints/switches
+
+ generate
+ genvar g;
+ for(g=0;g<g_num_ports;g++) begin
+
+ /// ALL switches
+ assign rbclk[g] = clk_ref_phys[g];
+
+ /// ALL endpints
+ assign phys_in[g].tx_enc_err = ~ep_ctrl_i[g];
+ assign phys_in[g].ref_clk = clk_ref_phys[g];
+ assign phys_in[g].rx_clk = clk_ref_i;
+ assign phys_in[g].rx_enc_err = 0;
+ always@(posedge clk_ref_i) begin : gen_disparity
+ if(phys_out[g].rst)
+ phys_in[g].tx_disparity = 0;
+ else
+ phys_in[g].tx_disparity = f_next_8b10b_disparity16
+ (
+ phys_in[g].tx_disparity,
+ phys_out[g].tx_k,
+ phys_out[g].tx_data);
+ end
+ end
+ endgenerate
+
+
+// always@(posedge clk_ref_i) begin : gen_link_delay
+// sw_td[0][18 * (g_port_bunch_number)+ 17 : 18 * (g_port_bunch_number)] = f_link_simulation(sw_rd[1][18 * (g_port_bunch_number)+ 17 : 18 * (g_port_bunch_number)],90,0);
+// sw_td[1][18 * (g_port_bunch_number)+ 17 : 18 * (g_port_bunch_number)] = f_link_simulation(sw_rd[0][18 * (g_port_bunch_number)+ 17 : 18 * (g_port_bunch_number)],90,1);
+// end
+ generate
+ genvar j;
+ for(j=0;j<g_port_bunch_number;j++) begin
+
+ /// connections: Endpints to Switch 0
+ assign sw_td[0][18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : 'h00BC;
+ assign sw_td[0][18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : 2'b01;
+ assign phys_in[j].rx_data = sw_rd[0][18 * j + 15 : 18 * j];
+ assign phys_in[j].rx_k = sw_rd[0][18 * j + 17 : 18 * j + 16];
+
+ /// connections: Endpints to Switch 1
+ assign sw_td[1][18 * j + 15 : 18 * j] = ep_ctrl_i[1*g_port_bunch_number + j] ? phys_out[1*g_port_bunch_number + j].tx_data : 'h00BC;
+ assign sw_td[1][18 * j + 17 : 18 * j + 16] = ep_ctrl_i[1*g_port_bunch_number + j] ? phys_out[1*g_port_bunch_number + j].tx_k : 2'b01;
+ assign phys_in[1*g_port_bunch_number + j].rx_data = sw_rd[1][18 * j + 15 : 18 * j];
+ assign phys_in[1*g_port_bunch_number + j].rx_k = sw_rd[1][18 * j + 17 : 18 * j + 16];
+
+ /// connections: Endpints to Switch 2
+ assign sw_td[2][18 * j + 15 : 18 * j] = ep_ctrl_i[2*g_port_bunch_number + j] ? phys_out[2*g_port_bunch_number + j].tx_data : 'h00BC;
+ assign sw_td[2][18 * j + 17 : 18 * j + 16] = ep_ctrl_i[2*g_port_bunch_number + j] ? phys_out[2*g_port_bunch_number + j].tx_k : 2'b01;
+ assign phys_in[2*g_port_bunch_number + j].rx_data = sw_rd[2][18 * j + 15 : 18 * j];
+ assign phys_in[2*g_port_bunch_number + j].rx_k = sw_rd[2][18 * j + 17 : 18 * j + 16];
+
+ /// connections: Switch 0 <=> Switch 1
+// if(j != 0)begin
+ assign sw_td[0][18 * (g_port_bunch_number+j)+ 17 : 18 * (j+g_port_bunch_number)] = sw_rd[1][18 * (g_port_bunch_number+j)+ 17 : 18 * (g_port_bunch_number+j)];
+ assign sw_td[1][18 * (g_port_bunch_number+j)+ 17 : 18 * (j+g_port_bunch_number)] = sw_rd[0][18 * (g_port_bunch_number+j)+ 17 : 18 * (g_port_bunch_number+j)];
+// end
+
+ /// connections: Switch 0 <=> Switch 2
+ assign sw_td[2][18 * ( g_port_bunch_number+j) + 17 : 18 * ( g_port_bunch_number+j)] = sw_rd[0][18 * (2*g_port_bunch_number+j)+ 17 : 18 * (2*g_port_bunch_number+j)];
+ assign sw_td[0][18 * (2*g_port_bunch_number+j) + 17 : 18 * (2*g_port_bunch_number+j)] = sw_rd[2][18 * ( g_port_bunch_number+j)+ 17 : 18 * ( g_port_bunch_number+j)];
+
+ /// connections: Switch 1 <=> Switch 2
+ assign sw_td[2][18 * (2*g_port_bunch_number+j) + 17 : 18 * (2*g_port_bunch_number+j)] = sw_rd[1][18 * (2*g_port_bunch_number+j) + 17 : 18 * (2*g_port_bunch_number+j)];
+ assign sw_td[1][18 * (2*g_port_bunch_number+j) + 17 : 18 * (2*g_port_bunch_number+j)] = sw_rd[2][18 * (2*g_port_bunch_number+j) + 17 : 18 * (2*g_port_bunch_number+j)];
+ end
+ endgenerate
+ /// ======================= Devices Under Test (3 WR switches) ========================//
+
+ /// WR Switch 0
+ scb_top_sim
+ #(
+ .g_num_ports(g_num_ports)
+ )
+ U_SW_0
+ (
+ .sys_rst_n_i ( rst_n_i),
+ .clk_startup_i ( clk_sys_i),
+ .clk_ref_i ( clk_ref_i),
+ .clk_dmtd_i ( clk_ref_i),
+ .clk_aux_i ( clk_swc_mpm_core_i),
+ .wb_adr_i ( cpu_0.master.adr),
+ .wb_dat_i ( cpu_0.master.dat_o),
+ .wb_dat_o ( cpu_0.master.dat_i),
+ .wb_cyc_i ( cpu_0.master.cyc),
+ .wb_sel_i ( cpu_0.master.sel),
+ .wb_stb_i ( cpu_0.master.stb),
+ .wb_we_i ( cpu_0.master.we),
+ .wb_ack_o ( cpu_0.master.ack),
+ .wb_stall_o ( cpu_0.master.stall),
+ .wb_irq_o ( cpu_irq[0] ),
+ .pps_i ( 1'b0 ),
+ .td_o ( sw_rd[0]),
+ .rd_i ( sw_td[0]),
+ .rbclk_i ( rbclk)
+ );
+
+ /// WR Switch 1
+ scb_top_sim
+ #(
+ .g_num_ports(g_num_ports)
+ )
+ U_SW_1
+ (
+ .sys_rst_n_i ( rst_n_i),
+ .clk_startup_i ( clk_sys_i),
+ .clk_ref_i ( clk_ref_i),
+ .clk_dmtd_i ( clk_ref_i),
+ .clk_aux_i ( clk_swc_mpm_core_i),
+ .wb_adr_i ( cpu_1.master.adr),
+ .wb_dat_i ( cpu_1.master.dat_o),
+ .wb_dat_o ( cpu_1.master.dat_i),
+ .wb_cyc_i ( cpu_1.master.cyc),
+ .wb_sel_i ( cpu_1.master.sel),
+ .wb_stb_i ( cpu_1.master.stb),
+ .wb_we_i ( cpu_1.master.we),
+ .wb_ack_o ( cpu_1.master.ack),
+ .wb_stall_o ( cpu_1.master.stall),
+ .wb_irq_o ( cpu_irq[1] ),
+ .pps_i ( 1'b0 ),
+ .td_o ( sw_rd[1]),
+ .rd_i ( sw_td[1]),
+ .rbclk_i ( rbclk)
+ );
+
+ /// WR Switch 2
+ scb_top_sim
+ #(
+ .g_num_ports(g_num_ports)
+ )
+ U_SW_2
+ (
+ .sys_rst_n_i ( rst_n_i),
+ .clk_startup_i ( clk_sys_i),
+ .clk_ref_i ( clk_ref_i),
+ .clk_dmtd_i ( clk_ref_i),
+ .clk_aux_i ( clk_swc_mpm_core_i),
+ .wb_adr_i ( cpu_2.master.adr),
+ .wb_dat_i ( cpu_2.master.dat_o),
+ .wb_dat_o ( cpu_2.master.dat_i),
+ .wb_cyc_i ( cpu_2.master.cyc),
+ .wb_sel_i ( cpu_2.master.sel),
+ .wb_stb_i ( cpu_2.master.stb),
+ .wb_we_i ( cpu_2.master.we),
+ .wb_ack_o ( cpu_2.master.ack),
+ .wb_stall_o ( cpu_2.master.stall),
+ .wb_irq_o ( cpu_irq[2] ),
+ .pps_i ( 1'b0 ),
+ .td_o ( sw_rd[2]),
+ .rd_i ( sw_td[2]),
+ .rbclk_i ( rbclk)
+ );
+
+
+endmodule // scb_top_sim_svwrap
+
diff --git a/testbench/scb_network_top/simdrv_wr_endpoint.svh b/testbench/scb_network_top/simdrv_wr_endpoint.svh
new file mode 100644
index 0000000000000000000000000000000000000000..0804da7e27af3aeaa34f6d01a0309c8c9e24afe3
--- /dev/null
+++ b/testbench/scb_network_top/simdrv_wr_endpoint.svh
@@ -0,0 +1,84 @@
+`ifndef __SIMDRV_WR_ENDPOINT_SVH
+`define __SIMDRV_WR_ENDPOINT_SVH 1
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "endpoint_regs.v"
+
+class CSimDrv_WR_Endpoint;
+
+ protected CBusAccessor m_acc;
+ protected uint64_t m_base;
+
+ function new(CBusAccessor acc, uint64_t base);
+ m_acc = acc;
+ m_base = base;
+ endfunction // new
+
+ task vlan_egress_untag(int vid, int untag);
+ m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
+ endtask // vlan_egress_untag
+
+ task pfilter_load_microcode(uint64_t mcode[]);
+ int i;
+
+ for(i=0;i<mcode.size();i++)
+ begin
+ m_acc.write(m_base + `ADDR_EP_PFCR1, (mcode[i] & 'hfff) << `EP_PFCR1_MM_DATA_LSB_OFFSET);
+
+ m_acc.write(m_base + `ADDR_EP_PFCR0,
+ (i << `EP_PFCR0_MM_ADDR_OFFSET) |
+ (((mcode[i] >> 12) & 'hffffff) << `EP_PFCR0_MM_DATA_MSB_OFFSET) |
+ `EP_PFCR0_MM_WRITE);
+ end
+ endtask // pfilter_load_microcde
+
+ task pfilter_enable(int enable);
+ m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0);
+ endtask // pfilter_enable
+
+`define EP_QMODE_VLAN_DISABLED 2
+
+ task init(int port_id);
+ m_acc.write(m_base + `ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN | (port_id << `EP_ECR_PORTID_OFFSET)) ;
+ m_acc.write(m_base + `ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
+ m_acc.write(m_base + `ADDR_EP_VCR0, `EP_QMODE_VLAN_DISABLED << `EP_VCR0_QMODE_OFFSET);
+ m_acc.write(m_base + `ADDR_EP_TSCR, `EP_TSCR_EN_RXTS | `EP_TSCR_EN_TXTS);
+ endtask // init
+
+ task automatic mdio_read(int addr, output int val);
+ uint64_t rval;
+
+ m_acc.write(m_base + `ADDR_EP_MDIO_CR, (addr>>2) << 16, 4);
+ while(1)begin
+ m_acc.read(m_base + `ADDR_EP_MDIO_ASR, rval, 4);
+ if(rval & 'h80000000) begin
+ val = rval & 'hffff;
+ return;
+ end
+
+ end
+ endtask // mdio_read
+
+ task automatic mdio_write(int addr,int val);
+ uint64_t rval;
+
+ m_acc.write(m_base+`ADDR_EP_MDIO_CR, ((addr>>2) << 16) | `EP_MDIO_CR_RW | val);
+ while(1)begin
+ #8ns;
+ m_acc.read(m_base+`ADDR_EP_MDIO_ASR, rval);
+ if(rval & 'h80000000)
+ return;
+ end
+ endtask // automatic
+
+ task automatic check_link(ref int up);
+ reg[31:0] rval;
+ mdio_read(m_base + `ADDR_MDIO_MSR, rval);
+ up= (rval & `MDIO_MSR_LSTATUS) ? 1 : 0;
+ endtask // check_link
+
+
+endclass // CSimDrv_WR_Endpoint
+
+`endif // `ifndef __SIMDRV_WR_ENDPOINT_SVH
diff --git a/testbench/scb_top/alloc.svh b/testbench/scb_top/alloc.svh
new file mode 100644
index 0000000000000000000000000000000000000000..2758051f05b539d40074e67b8aa189c7356c9d49
--- /dev/null
+++ b/testbench/scb_top/alloc.svh
@@ -0,0 +1,317 @@
+
+typedef enum
+ {
+ ALLOC,
+ FREE,
+ FORCE_FREE,
+ SET_USECOUNT
+ } alloc_req_type_t ;
+
+typedef struct {
+ int is_allocated;
+ int last_page_freed;
+ int usecnt;
+ int free_cnt; //for 3 resoruces
+ int force_free_cnt; // 3 resoruces
+ int alloc_port_vec;
+ int free_port_vec;
+ int f_free_port_vec;
+} alloc_page_instance_t;
+
+
+
+`define g_alloc_pages 1024
+`define g_usecnt_width 5
+`define g_pg_addr_width 10
+`define g_num_ports 19
+`define g_res_num_width 2
+`define g_alloc_inst_num 100
+
+typedef struct {
+ int alloc_cnt; // number of allocations of that page
+ alloc_page_instance_t alloc_inst[`g_alloc_inst_num];
+} alloc_page_t;
+
+
+alloc_page_t alloc_tab[`g_alloc_pages];
+int pre_s_alloc_tab[`g_alloc_pages]; // pre-allocated start page
+int pre_i_alloc_tab[`g_alloc_pages]; // pre-allocated inter page
+
+function init_alloc_tab();
+ int i;
+ for(i=0;i<`g_alloc_pages;i++) begin
+ alloc_tab[i].alloc_cnt = -1;
+ pre_s_alloc_tab[i] = 0;
+ pre_i_alloc_tab[i] = 0;
+ end
+endfunction;
+
+function automatic alloc_check(
+ input bit alloc_done,
+ input bit set_usecnt,
+ input bit free,
+ input bit force_free,
+ input bit [`g_usecnt_width -1:0] usecnt_alloc,
+ input bit [`g_usecnt_width -1:0] usecnt_set,
+ input bit [`g_pg_addr_width-1:0] pga_f, //page address freed
+ input bit [`g_pg_addr_width-1:0] pga_u, //page address usecnt
+ input bit [`g_pg_addr_width-1:0] pga_a, //page address allocated
+ input bit [`g_num_ports -1:0] req_vec
+ );
+ int cnt=0;
+ if(alloc_done) begin
+ cnt = ++alloc_tab[pga_a].alloc_cnt;
+ if(cnt >= `g_alloc_inst_num) $fatal("not enough alloc instances [see define g_alloc_inst_num in alloc.svh]");
+ alloc_tab[pga_a].alloc_inst[cnt].is_allocated = 1;
+ alloc_tab[pga_a].alloc_inst[cnt].usecnt = usecnt_alloc;
+ alloc_tab[pga_a].alloc_inst[cnt].free_cnt = 0;
+ alloc_tab[pga_a].alloc_inst[cnt].force_free_cnt = 0;
+ alloc_tab[pga_a].alloc_inst[cnt].alloc_port_vec = req_vec;
+ alloc_tab[pga_a].alloc_inst[cnt].free_port_vec = 0;
+ alloc_tab[pga_a].alloc_inst[cnt].f_free_port_vec= 0;
+ end
+ if(set_usecnt) begin
+ cnt = alloc_tab[pga_u].alloc_cnt;
+ alloc_tab[pga_u].alloc_inst[cnt].usecnt = usecnt_set;
+ end
+ if(free) begin
+ cnt = alloc_tab[pga_f].alloc_cnt;
+ alloc_tab[pga_f].alloc_inst[cnt].free_cnt++;
+ alloc_tab[pga_f].alloc_inst[cnt].free_port_vec = req_vec | alloc_tab[pga_f].alloc_inst[cnt].free_port_vec;
+ end
+
+ if(force_free) begin
+ cnt = alloc_tab[pga_f].alloc_cnt;
+ alloc_tab[pga_f].alloc_inst[cnt].force_free_cnt++;
+ alloc_tab[pga_f].alloc_inst[cnt].f_free_port_vec = req_vec | alloc_tab[pga_f].alloc_inst[cnt].f_free_port_vec;
+ end
+endfunction // first_free
+
+
+function automatic int check_if_prealloc(
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckstart_pageaddr,
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckinter_pageaddr,
+ input int pageaddr);
+ int i;
+ int tab_s[19];
+ int tab_i[19];
+
+ tab_s[ 0] = pckstart_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)];
+ tab_s[ 1] = pckstart_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)];
+ tab_s[ 2] = pckstart_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)];
+ tab_s[ 3] = pckstart_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)];
+ tab_s[ 4] = pckstart_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)];
+ tab_s[ 5] = pckstart_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)];
+ tab_s[ 6] = pckstart_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)];
+ tab_s[ 7] = pckstart_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)];
+ tab_s[ 8] = pckstart_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)];
+ tab_s[ 9] = pckstart_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)];
+ tab_s[10] = pckstart_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)];
+ tab_s[11] = pckstart_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)];
+ tab_s[12] = pckstart_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)];
+ tab_s[13] = pckstart_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)];
+ tab_s[14] = pckstart_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)];
+ tab_s[15] = pckstart_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)];
+ tab_s[16] = pckstart_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)];
+ tab_s[17] = pckstart_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)];
+ tab_s[18] = pckstart_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)];
+
+ tab_i[ 0] = pckinter_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)];
+ tab_i[ 1] = pckinter_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)];
+ tab_i[ 2] = pckinter_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)];
+ tab_i[ 3] = pckinter_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)];
+ tab_i[ 4] = pckinter_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)];
+ tab_i[ 5] = pckinter_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)];
+ tab_i[ 6] = pckinter_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)];
+ tab_i[ 7] = pckinter_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)];
+ tab_i[ 8] = pckinter_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)];
+ tab_i[ 9] = pckinter_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)];
+ tab_i[10] = pckinter_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)];
+ tab_i[11] = pckinter_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)];
+ tab_i[12] = pckinter_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)];
+ tab_i[13] = pckinter_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)];
+ tab_i[14] = pckinter_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)];
+ tab_i[15] = pckinter_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)];
+ tab_i[16] = pckinter_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)];
+ tab_i[17] = pckinter_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)];
+ tab_i[18] = pckinter_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)];
+
+ for(i=0;i<19;i++) begin
+ if(tab_s[i] == pageaddr) begin
+ pre_s_alloc_tab[i]++;
+// $display("start pck pre-alloc page: pageaddr=%3d | %3d [port=%2d | vector: %p]", pageaddr,tab_s[i],i, pckstart_pageaddr);
+ return i;
+ end
+ if(tab_i[i] == pageaddr) begin
+ pre_i_alloc_tab[i]++;
+// $display("inter pck pre-alloc page: pageaddr=%3d | %3d [port=%2d | vector: %p]", pageaddr,tab_i[i],i, pckstart_pageaddr);
+ return i;
+ end
+ end
+
+// if(pckstart_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)] == pageaddr) return 0;
+// if(pckstart_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)] == pageaddr) return 1;
+// if(pckstart_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)] == pageaddr) return 2;
+// if(pckstart_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)] == pageaddr) return 3;
+// if(pckstart_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)] == pageaddr) return 4;
+// if(pckstart_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)] == pageaddr) return 5;
+// if(pckstart_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)] == pageaddr) return 6;
+// if(pckstart_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)] == pageaddr) return 7;
+// if(pckstart_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)] == pageaddr) return 8;
+// if(pckstart_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)] == pageaddr) return 9;
+// if(pckstart_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)] == pageaddr) return 0;
+// if(pckstart_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)] == pageaddr) return 11;
+// if(pckstart_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)] == pageaddr) return 12;
+// if(pckstart_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)] == pageaddr) return 13;
+// if(pckstart_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)] == pageaddr) return 14;
+// if(pckstart_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)] == pageaddr) return 15;
+// if(pckstart_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)] == pageaddr) return 16;
+// if(pckstart_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)] == pageaddr) return 17;
+// if(pckstart_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)] == pageaddr) return 18;
+//
+// if(pckinter_pageaddr[(( 0+1)*`g_pg_addr_width-1):( 0*`g_pg_addr_width)] == pageaddr) return 0;
+// if(pckinter_pageaddr[(( 1+1)*`g_pg_addr_width-1):( 1*`g_pg_addr_width)] == pageaddr) return 1;
+// if(pckinter_pageaddr[(( 2+1)*`g_pg_addr_width-1):( 2*`g_pg_addr_width)] == pageaddr) return 2;
+// if(pckinter_pageaddr[(( 3+1)*`g_pg_addr_width-1):( 3*`g_pg_addr_width)] == pageaddr) return 3;
+// if(pckinter_pageaddr[(( 4+1)*`g_pg_addr_width-1):( 4*`g_pg_addr_width)] == pageaddr) return 4;
+// if(pckinter_pageaddr[(( 5+1)*`g_pg_addr_width-1):( 5*`g_pg_addr_width)] == pageaddr) return 5;
+// if(pckinter_pageaddr[(( 6+1)*`g_pg_addr_width-1):( 6*`g_pg_addr_width)] == pageaddr) return 6;
+// if(pckinter_pageaddr[(( 7+1)*`g_pg_addr_width-1):( 7*`g_pg_addr_width)] == pageaddr) return 7;
+// if(pckinter_pageaddr[(( 8+1)*`g_pg_addr_width-1):( 8*`g_pg_addr_width)] == pageaddr) return 8;
+// if(pckinter_pageaddr[(( 9+1)*`g_pg_addr_width-1):( 9*`g_pg_addr_width)] == pageaddr) return 9;
+// if(pckinter_pageaddr[((10+1)*`g_pg_addr_width-1):(10*`g_pg_addr_width)] == pageaddr) return 10;
+// if(pckinter_pageaddr[((11+1)*`g_pg_addr_width-1):(11*`g_pg_addr_width)] == pageaddr) return 11;
+// if(pckinter_pageaddr[((12+1)*`g_pg_addr_width-1):(12*`g_pg_addr_width)] == pageaddr) return 12;
+// if(pckinter_pageaddr[((13+1)*`g_pg_addr_width-1):(13*`g_pg_addr_width)] == pageaddr) return 13;
+// if(pckinter_pageaddr[((14+1)*`g_pg_addr_width-1):(14*`g_pg_addr_width)] == pageaddr) return 14;
+// if(pckinter_pageaddr[((15+1)*`g_pg_addr_width-1):(15*`g_pg_addr_width)] == pageaddr) return 15;
+// if(pckinter_pageaddr[((16+1)*`g_pg_addr_width-1):(16*`g_pg_addr_width)] == pageaddr) return 16;
+// if(pckinter_pageaddr[((17+1)*`g_pg_addr_width-1):(17*`g_pg_addr_width)] == pageaddr) return 17;
+// if(pckinter_pageaddr[((18+1)*`g_pg_addr_width-1):(18*`g_pg_addr_width)] == pageaddr) return 18;
+
+// for(i=0;i<`g_num_ports;i++) begin
+// pg_s = pckstart_pageaddr[((i+1)*`g_pg_addr_width):(i*`g_pg_addr_width)];
+// pg_i = pckinter_pageaddr[((i+1)*`g_pg_addr_width):(i*`g_pg_addr_width)];
+// $display("checking pre-alloc: pg_s =0x%4x | pg_s =0x%4x | pg =0x%4x",pg_s,pg_i, pageaddr);
+// if(pg_s == pageaddr && pg_i == pageaddr ) return 1;
+// end
+ return -1;
+endfunction
+
+function automatic dump_results(
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckstart_pageaddr,
+ input bit [`g_pg_addr_width*`g_num_ports-1:0] pckinter_pageaddr
+ );
+
+
+ int i = 0;
+ int j = 0;
+ int chk = 0;
+ int per_alloc_cnt =0;
+ int pg_pre_alloc = 0;
+ $display("--------------------------------- dumping resutls -------------------------------------");
+ while(alloc_tab[i].alloc_cnt >=0)
+ begin
+ for(j=0;j<=alloc_tab[i].alloc_cnt;j++)
+ begin
+ chk = alloc_tab[i].alloc_inst[j].usecnt - alloc_tab[i].alloc_inst[j].free_cnt;
+ if((chk != 0 || alloc_tab[i].alloc_inst[j].usecnt == 0) &&
+ alloc_tab[i].alloc_inst[j].is_allocated == 1 && // allocated and
+ alloc_tab[i].alloc_cnt == j) // last usage and
+ pg_pre_alloc = check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i);
+ else
+ pg_pre_alloc = -1;
+
+ if(chk == 0 && alloc_tab[i].alloc_inst[j].usecnt != 0)
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | OK",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec);
+ else if(pg_pre_alloc > -1) // one of pre-allocated
+ begin
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | pre-alloc-ed page for port %2d",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec,
+ pg_pre_alloc);
+ per_alloc_cnt++;
+ end
+// else if(chk == 1 && //possible candidate for pre-allocated page
+// alloc_tab[i].alloc_cnt == j && // needs to be the last usage
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i) > -1) // needs to be preallocated in one of ports
+// begin
+// $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | pre-alloc-ed page %2d",
+// i, j,
+// alloc_tab[i].alloc_inst[j].is_allocated,
+// alloc_tab[i].alloc_inst[j].usecnt,
+// alloc_tab[i].alloc_inst[j].free_cnt,
+// alloc_tab[i].alloc_inst[j].force_free_cnt,
+// alloc_tab[i].alloc_inst[j].alloc_port_vec,
+// alloc_tab[i].alloc_inst[j].free_port_vec,
+// alloc_tab[i].alloc_inst[j].f_free_port_vec,
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i));
+// per_alloc_cnt++;
+// end
+// else if(alloc_tab[i].alloc_inst[j].is_allocated == 1 && //allocated but...
+// alloc_tab[i].alloc_inst[j].usecnt == 0 && // no usecnt set and
+// alloc_tab[i].alloc_inst[j].free_cnt == 0 && // neither freed ...
+// alloc_tab[i].alloc_inst[j].force_free_cnt == 0 && // nor force-freed and
+// alloc_tab[i].alloc_cnt == j && // needs to be the last usage
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i) >-1) // needs to be preallocated in one of ports
+// begin
+// $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | pre-alloc-ed page %2d",
+// i, j,
+// alloc_tab[i].alloc_inst[j].is_allocated,
+// alloc_tab[i].alloc_inst[j].usecnt,
+// alloc_tab[i].alloc_inst[j].free_cnt,
+// alloc_tab[i].alloc_inst[j].force_free_cnt,
+// alloc_tab[i].alloc_inst[j].alloc_port_vec,
+// alloc_tab[i].alloc_inst[j].free_port_vec,
+// alloc_tab[i].alloc_inst[j].f_free_port_vec,
+// check_if_prealloc(pckstart_pageaddr,pckinter_pageaddr,i));
+// per_alloc_cnt++;
+// end
+ else if(alloc_tab[i].alloc_inst[j].force_free_cnt)
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | Force Free",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec);
+ else
+ $display("[p=%4d|u=%2d] alloc=%1d | usecnt=%2d | f_cnt=%2d | ff_cnt=%2d | a_v=0x%20x | f_v=0x%20x | ff_v=0x%20x | check this one",
+ i, j,
+ alloc_tab[i].alloc_inst[j].is_allocated,
+ alloc_tab[i].alloc_inst[j].usecnt,
+ alloc_tab[i].alloc_inst[j].free_cnt,
+ alloc_tab[i].alloc_inst[j].force_free_cnt,
+ alloc_tab[i].alloc_inst[j].alloc_port_vec,
+ alloc_tab[i].alloc_inst[j].free_port_vec,
+ alloc_tab[i].alloc_inst[j].f_free_port_vec);
+ end //for
+ i++;
+ end //while
+ $display("--------------------------------- --------------- -------------------------------------");
+ $display("pre-alloc pages: %3d",per_alloc_cnt);
+ for(i=0;i<`g_num_ports;i++) begin
+ if(pre_s_alloc_tab[i] != 1 || pre_i_alloc_tab[i] != 1)
+ $display("something wrong....: port %2d pre-allocation skrewed: start cnt=%2d | inter cnt = %2d",i, pre_s_alloc_tab[i], pre_i_alloc_tab[i]);
+ end
+
+endfunction
+
+
+
diff --git a/testbench/scb_top/main.sv b/testbench/scb_top/main.sv
index 2bd94bafc613e0d447568f97f308975ee94be6ba..c482e7884601b99676b4a25a8bc53d413ae7085b 100644
--- a/testbench/scb_top/main.sv
+++ b/testbench/scb_top/main.sv
@@ -3,16 +3,21 @@
`include "tbi_utils.sv"
`include "simdrv_wrsw_nic.svh"
`include "simdrv_rtu.sv"
+`include "simdrv_wr_tru.svh"
`include "simdrv_txtsu.svh"
+`include "simdrv_tatsu.svh"
+`include "simdrv_hwdu.svh"
`include "endpoint_regs.v"
`include "endpoint_mdio.v"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
-
-
`include "scb_top_sim_svwrap.svh"
+`include "scb_snake_sim_svwrap.svh"
+`include "pfilter.svh"
+`include "alloc.svh"
+// `define snake_test 1
module main;
@@ -20,159 +25,3180 @@ module main;
reg clk_sys=0;
reg clk_swc_mpm_core=0;
reg rst_n=0;
-
+ parameter g_max_ports = 18;
parameter g_num_ports = 18;
+ parameter g_mvlan = 19; //max simulation vlans
+ parameter g_max_dist_port_number = 4;
+ parameter g_snake_test = 0;
+ typedef enum {
+ PAUSE=0,
+ BPDU_0,
+ MARKER
+ } tx_special_pck_t;
+
+ typedef struct {
+ integer tx;
+ integer rx;
+ integer op;
+ } t_trans_path;
+
+ typedef struct{
+ rtu_vlan_entry_t vlan_entry;
+ integer vlan_id;
+ bit valid;
+ } t_sim_vlan_entry;
+
+ typedef struct{
+ int distPortN; //number of entries in the distribution
+ int srcPort;
+ int distr[g_max_dist_port_number];
+ } t_sim_port_distr;
+
+ typedef struct {
+ CSimDrv_WR_Endpoint ep;
+ EthPacketSource send;
+ EthPacketSink recv;
+ } port_t;
+
+ typedef struct{
+ int qmode;
+ int fix_prio;
+ int prio_val;
+ int pvid;
+ } t_vlan_port_config;
+
+ int mmu_alloc_cnt[g_num_ports+1];
+ int mmu_usecnt_cnt[g_num_ports+1];
+ int mmu_free_cnt[g_num_ports+1];
+ int mmu_f_free_cnt[g_num_ports+1];
+ int tx_done = 0;
+ int rx_done = 0;
+ reg [g_num_ports-1:0] txrx_done = 0;
+
+ port_t ports[$];
+ CSimDrv_NIC nic;
+ CRTUSimDriver rtu;
+ CSimDrv_WR_TRU tru;
+ CSimDrv_TXTSU txtsu;
+ CSimDrv_TATSU tatsu;
+ CSimDrv_HWDU hwdu;
+
+ reg [g_num_ports-1:0] ep_ctrl;
+ reg [15:0] ep_failure_type = 'h00;
// prameters to create some gaps between pks (not work really well)
- parameter g_enable_pck_gaps = 0; //1=TRUE, 0=FALSE
- parameter g_min_pck_gap = 100; // cycles
- parameter g_max_pck_gap = 500; // cycles
+ // default settings
+
+ /** *************************** basic conf ************************************* **/
+ integer g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ integer g_min_pck_gap = 300; // cycles
+ integer g_max_pck_gap = 300; // cycles
+ integer g_force_payload_size = 0; // if 0, then opt is used
+ integer g_payload_range_min = 63;
+ integer g_payload_range_max = 257;
+ integer g_failure_scenario = 0; // no link failure
+ integer g_active_port = 0;
+ integer g_backup_port = 1;
+ integer g_tru_enable = 0; //TRU disabled
+ integer g_is_qvlan = 1; // has vlan header
+ integer g_pfilter_enabled = 0;
+ integer g_limit_config_to_port_num = g_num_ports;
+ integer g_pause_mode = 0; //config of endpoints' PAUSE stuff
+ //0:disabled | 1: standard PAUSE | 2: prio-based PAUSE
+ // tx ,rx ,opt (send from port tx to rx with option opt
+ t_trans_path trans_paths[g_max_ports] ='{'{0 ,17 , 0 }, // port 0:
+ '{1 ,16 , 0 }, // port 1
+ '{2 ,15 , 0 }, // port 2
+ '{3 ,14 , 0 }, // port 3
+ '{4 ,13 , 0 }, // port 4
+ '{5 ,12 , 0 }, // port 5
+ '{6 ,11 , 0 }, // port 6
+ '{7 ,10 , 0 }, // port 7
+ '{8 ,9 , 0 }, // port 8
+ '{9 ,8 , 0 }, // port 9
+ '{10 ,7 , 0 }, // port 10
+ '{11 ,6 , 0 }, // port 11
+ '{12 ,5 , 0 }, // port 12
+ '{13 ,4 , 0 }, // port 13
+ '{14 ,3 , 0 }, // port 14
+ '{15 ,2 , 0 }, // port 15
+ '{16 ,1 , 0 }, // port 16
+ '{17 ,0 , 0 }};// port 17
+ //index: 1,2,3,4,5,6,7,8,9, ....
+ integer start_send_init_delay[g_max_ports] = '{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+ //mask with ports we want to use, port number: 18 ...............0
+ reg [g_max_ports-1:0] portUnderTest = 18'b111111111111111111; //
+ reg [g_max_ports-1:0] portRtuEnabled = 18'b111111111111111111; //
+ integer repeat_number = 20;
+ integer tries_number = 3;
+ integer vid_init_for_inc = 0; // with opt 666 and 668
+// reg [31:0] vlan_port_mask = 32'hFFFFFFFF;
+ reg [31:0] mirror_src_mask = 'h00000002;
+ reg [31:0] mirror_dst_mask = 'h00000080;
+ reg [7 :0] hp_prio_mask ='b10000001;
+ bit mr_rx = 1;
+ bit mr_tx = 1;
+ bit mr = 0;
+ bit mac_ptp = 0;
+ bit mac_ll = 0;
+ bit mac_single = 0;
+ bit mac_range = 0;
+ bit mac_br = 0;
+ bit hp_fw_cpu = 0;
+ bit rx_forward_on_fmatch_full = 0;
+ bit unrec_fw_cpu = 0;
+ bit rtu_dbg_f_fast_match = 0;
+ bit rtu_dbg_f_full_match = 0;
+ bit g_ignore_rx_test_check = 0;
+
+ // vlans
+// int prio_map[8] = '{7, // Class of Service masked into prioTag 0
+// 6, // Class of Service masked into prioTag 1
+// 5, // Class of Service masked into prioTag 2
+// 4, // Class of Service masked into prioTag 3
+// 3, // Class of Service masked into prioTag 4
+// 2, // Class of Service masked into prioTag 5
+// 1, // Class of Service masked into prioTag 6
+// 0};// Class of Service masked into prioTag 7
+ int prio_map[8] = '{0, // Class of Service masked into prioTag 0
+ 1, // Class of Service masked into prioTag 1
+ 2, // Class of Service masked into prioTag 2
+ 3, // Class of Service masked into prioTag 3
+ 4, // Class of Service masked into prioTag 4
+ 5, // Class of Service masked into prioTag 5
+ 6, // Class of Service masked into prioTag 6
+ 7};// Class of Service masked into prioTag 7
+ int qmode = 2; //VLAN tagging/untagging disabled- pass as is
+ //0: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN
+ //1: TRUNK port - passes only tagged VLAN packets. Drops all untagged packets.
+ //3: unqualified port - passes all traffic regardless of VLAN configuration
+
+ int fix_prio = 0;
+ int prio_val = 0;
+ int pvid = 0;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ t_sim_vlan_entry sim_vlan_tab[g_mvlan] = '{'{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 10, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 11, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 12, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 13, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 14, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 15, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 16, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 17, 1'b0 },
+ '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 18, 1'b0 }};
+ integer tru_config_opt = 0;
+ PFilterMicrocode mc = new;
+ byte BPDU_templ[] ='{'h01,'h80,'hC2,'h00,'h00,'h00, //0 - 5: dst addr
+ 'h00,'h00,'h00,'h00,'h00,'h00, //6 -11: src addr (to be filled in ?)
+ 'h26,'h07,'h42,'h42,'h03, //12-16: rest of the Eth Header
+ 'h00,'h00, //17-18: protocol ID
+ 'h00, //19 : protocol Version
+ 'h00, //20 : BPDU type =>: repleacable
+ 'h00, //21 : flags =>: repleacable
+ 'h00,'h00,'h00,'h00,'h00,'h00, //22-27: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //28-33: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //34-39: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //40-45: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //46-51: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //52-57: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00}; //58-63: padding
+
+ byte PAUSE_templ[] ='{'h01,'h80,'hC2,'h00,'h00,'h01, //0 - 5: dst addr
+ 'h00,'h00,'h00,'h00,'h00,'h00, //6 -11: src addr (to be filled in ?)
+ 'h88,'h08, //12-13: Type Field = MAC control Frame
+ 'h00,'h01, //14-15: MAC Control Opcode = PAUSE
+ 'h00,'h00, //16-17: param: pause time: repleacable
+ 'h00,'h00,'h00,'h00,'h00,'h00, //18-23: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //24-29: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //30-35: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //36-41: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //42-47: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //48-53: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //54-59: padding
+ 'h00,'h00,'h00,'h00}; //60-63: padding
+
+ byte MARKER_templ[] ='{'h01,'h80,'hC2,'h00,'h00,'h02, //0 - 5: dst addr
+ 'h00,'h00,'h00,'h00,'h00,'h00, //6 -11: src addr (to be filled in ?)
+ 'h88,'h09, //12-13: Type Field = Marker
+ 'h02, //14 : Subtype: Marker Protocol
+ 'h01, //15 : Version
+ 'h00, //16 : Marker response
+ 'h10, //17 : length
+ //////// there should be more here, but not needed for simulation and I'm too lazy
+ 'h00,'h00,'h00,'h00,'h00,'h00, //18-23: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //24-29: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //30-35: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //36-41: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //42-47: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //48-53: padding
+ 'h00,'h00,'h00,'h00,'h00,'h00, //54-59: padding
+ 'h00,'h00,'h00,'h00}; //60-63: padding
+ byte TEST_GEN_templ[] ='{'h01,'h80,'hC2,'h00,'h00,'h01, //0 - 5: dst addr
+ 'h00,'h00,'h00,'h00,'h00,'h00, //6 -11: src addr (to be filled in ?)
+ 'hDE,'hED}; //12-13: EtherType
+
+ integer inj_gen_frame_size = 225;
+ integer inj_gen_if_gap_size = 10;
+ integer inj_gen_mode = 0; //0:default | 1: corrupted | 2,3: undefined (yet)
+ integer g_test_inj_gen = 0;
+ //qmode, fix_prio, prio_val, pvid
+ t_vlan_port_config ep_vlan_conf[] ='{'{ 0, 0, 0, 1 }, //port = 0
+ '{ 0, 0, 0, 1 }, //port = 1
+ '{ 0, 0, 0, 2 }, //port = 2
+ '{ 0, 0, 0, 2 }, //port = 3
+ '{ 0, 0, 0, 3 }, //port = 4
+ '{ 0, 0, 0, 3 }, //port = 5
+ '{ 0, 0, 0, 4 }, //port = 6
+ '{ 0, 0, 0, 4 }, //port = 7
+ '{ 0, 0, 0, 5 }, //port = 8
+ '{ 0, 0, 0, 5 }, //port = 9
+ '{ 0, 0, 0, 6 }, //port = 10
+ '{ 0, 0, 0, 6 }, //port = 11
+ '{ 0, 0, 0, 7 }, //port = 12
+ '{ 0, 0, 0, 7 }, //port = 13
+ '{ 0, 0, 0, 8 }, //port = 14
+ '{ 0, 0, 0, 8 }, //port = 15
+ '{ 0, 0, 0, 9 }, //port = 16
+ '{ 0, 0, 0, 9 }};//port = 17
+
+ integer g_injection_templates_programmed = 0;
+ integer g_transition_scenario = 0;
+ integer g_do_vlan_config = 1;
+// int vlan_port_mask[] ='{32'h00000000,
+// 32'h00000001,
+// 32'h00000000,
+// 32'h00000000,
+// }
+ t_sim_port_distr LACPdistro = '{ 4, // distribution port nubmer
+ 0, // source port (we send on this
+ { 4, // every 4th frame send to port 1
+ 5, // every 4th frame send to port 2
+ 6, // every 4th frame send to port 3
+ 7} // every 4th frame send to port 4
+ };
+ integer g_LACP_scenario = 0;
+ integer g_traffic_shaper_scenario = 0;
+ integer g_enable_WRtime = 0;
+ integer g_tatsu_config = 0;
+ integer g_fw_to_cpu_scenario = 0;
+ integer g_set_untagging = 0;
+ int lacp_df_hp_id = 0;
+ int lacp_df_br_id = 2;
+ int lacp_df_un_id = 1;
+ int g_simple_allocator_unicast_check = 0;
+ /** *************************** test scenario 1 ************************************* **/
+ /*
+ * testing switch over between ports 0,1,2
+ * we broadcast on ports 0,1 and 2. One of them is only active.
+ * after some time port 0 failes (failure_scenario 1) and we switch to the othter
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_failure_scenario = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 2 ************************************* **/
+ /*
+ * testing Fast forward of single mac entry
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_failure_scenario = 1;
+ mac_single = 1; // enable single mac entry for fast forward
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 5 };
+ trans_paths[1] = '{1 ,16 , 5 };
+ trans_paths[2] = '{2 ,15 , 5 };
+ end
+ */
+ /** *************************** te scenario 3 ************************************* **/
+ /*
+ * test mirroring: simple case: mirroring rx/tx of port 1 into port 7
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000010000010;
+ vlan_port_mask = 32'h00000006;
+ g_tru_enable = 0;
+ mac_br = 1; // enable fast forward for broadcast
+ mr = 1; // enable mirror
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,2 , 5 };
+ trans_paths[7] = '{7 ,7 , 5 }; // this is the mirror port
+
+ end
+*/
+ /** *************************** te scenario 4 ************************************* **/
+ /*
+ * test mirroring: simple case: mirroring rx/tx of port 1 into port 7
+ * when we broadcast traffic on port 1 and we want only egress traffic on this port, we should
+ * not receive the sent traffic
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000010000110;
+ vlan_port_mask = 32'h00000006;
+ g_tru_enable = 0;
+ mac_br = 1; // enable fast forward for broadcast
+ mr = 1; // enable mirror
+ mr_rx = 0; // mirror only traffic sent on port 1 (egress)
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,2 , 4 };
+ trans_paths[2] = '{2 ,1 , 4 };
+ trans_paths[7] = '{7 ,7 , 4 }; // this is the mirror port
+
+ end
+*/
+ /** *************************** te scenario 5 ************************************* **/
+ /*
+ * test mirroring: mirroring received traffic on port 1 - sending from 1 , so should
+ * go to mirror port
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000010000010;
+ vlan_port_mask = 32'h00000086;
+ g_tru_enable = 0;
+ mac_br = 1; // enable fast forward for broadcast
+ mr = 1; // enable mirror
+ mr_tx = 0; // mirror only traffic received on port
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,2 , 4 };
+ trans_paths[7] = '{7 ,7 , 4 }; // this is the mirror port
+
+ end
+ */
+ /** *************************** te scenario 6 ************************************* **/
+ /*
+ * test mirroring: mirroring received traffic on port 1 - sending on 2, so it should not go
+ * to mirror port
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000010000100;
+ vlan_port_mask = 32'h00000086;
+ g_tru_enable = 0;
+ mac_br = 1; // enable fast forward for broadcast
+ mr = 1; // enable mirror
+ mr_tx = 0; // mirror only traffic received on port
+ // tx ,rx ,opt
+ trans_paths[2] = '{2 ,1 , 4 };
+ trans_paths[7] = '{7 ,7 , 4 }; // this is the mirror port
+
+ end
+ */
+ /** *************************** te scenario 7 ************************************* **/
+ /*
+ * test mirroring: simple case: mirroring rx/tx of port 1 into port 7
+ * when we broadcast traffic on port 1 and we want only egress traffic on this port, we should
+ * not receive the sent traffic
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000010000110;
+ vlan_port_mask = 32'h00000086;
+ g_tru_enable = 0;
+ mac_br = 1; // enable fast forward for broadcast
+ mr = 1; // enable mirror
+ mr_rx = 0; // mirror only traffic sent on port 1 (egress)
+ // tx ,rx ,opt
+ trans_paths[2] = '{1 ,2 , 4 };
+ trans_paths[7] = '{7 ,7 , 4 }; // this is the mirror port
+
+ end
+*/
+ /** *************************** te scenario 8 ************************************* **/
+ /*
+ * checking single MAC : checking if fast forward works for singe entries
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000010;
+ vlan_port_mask = 32'h000000FF;
+ g_tru_enable = 0;
+ mac_br = 1; // enable fast forward for broadcast
+ mac_single = 1;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,2 , 6 };
+ trans_paths[7] = '{7 ,7 , 6 };
+
+ end
+*/
+ /** *************************** te scenario 9 ************************************* **/
+ /*
+ * checking range MAC :
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000010;
+ vlan_port_mask = 32'h000000FF;
+ g_tru_enable = 0;
+ mac_range = 1;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,2 , 7 };
+ trans_paths[7] = '{7 ,7 , 7 };
+
+ end
+*/
+
+ /** *************************** test scenario 10 ************************************* **/
+ /*
+ * testing no-mirroring: verifying bug which makes the dst_mirror port disabled even if
+ * mirroring is not enabled (but the dst_mirror mask is set)
+ **/
+/*
+ initial begin
+ mirror_src_mask = 'h00000002;
+ mirror_dst_mask = 'h00000080;
+ mr_rx = 1;
+ mr_tx = 1;
+ mr = 0;
+ end
+*/
+ /** *************************** test scenario 11 ************************************* **/
+ /** *************************** (problematic) ************************************* **/
+ /*
+ * testing switch over for TRU->eRSTP
+ * 1) we put port 1 (backup) down and up again (nothing should happen and nothing happens)
+ * 2) we put port 0 (active) down and the switch over works, we take packets from port 1
+ * (so far this port was dropping ingress packets)
+ *
+ * here, the switchover takes place during pck reception
+ *
+ * PROBLEM: we receive the previous packet (somehow)
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 2;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 12 ************************************* **/
+ /** *************************** (problematic) ************************************* **/
+ /*
+ * testing switch over for TRU->eRSTP
+ * 1) we put port 1 (backup) down and up again (nothing should happen and nothing happens)
+ * 2) we put port 0 (active) down and the switch over works, we take packets from port 1
+ * (so far this port was dropping ingress packets)
+ *
+ * here, the switchover takes place between pck receptions
+ *
+ * PROBLEM: we receive the previous packet (somehow)
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 3;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 13 ************************************* **/
+ /*
+ * testing switch over for TRU->eRSTP
+ * we kill port 0, works
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 1;
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 14 ************************************* **/
+ /*
+ * testing switch over for TRU->eRSTP
+ * we kill port 1 (backup) (DOWN) and then revivie it (UP) and then kill port 0 (active)
+ * the killing of port 1 happens between frames being sent... OK
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 4;
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 15 ************************************* **/
+ /** *************************** (problematic) ************************************* **/
+ /*
+ * testing switch over for TRU->eRSTP
+ * we kill port 1 (backup) (DOWN) and then revivie it (UP) and then kill port 0 (active)
+ * the killing of port 1 happens during reception of frame... problem
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 2;
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 16 ************************************* **/
+ /*
+ * simple VLAN tests: sending pckts on VLAN =100, we have no entries in hashTable for these,
+ * so unrecongizes entries are broadcast
+ **/
+/*
+ initial begin
+ sim_vlan_tab[0] = '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 200, 1'b1 };
+ sim_vlan_tab[2] = '{'{32'hFFFFFFFF, 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 100, 1'b1 };
+
+ end
+*/
+ /** *************************** test scenario 17 ************************************* **/
+ /*
+ * test of TRU+VLANs:
+ * we have two VLANs with different active/backup ports
+ * VLAN_0: 0-3 ports: 0-active, 1-backup, 2 & 3 - receive broadcast from 0 & 1
+ * VLAN_1: 4-7 ports: 4-active, 5-backup, 6 & 7 - receive broadcast from 4 & 5
+ *
+ * at some point we kill both active ports -> change to backup ports
+ **/
+/*
+ initial begin
+ sim_vlan_tab[0] = '{'{32'h0000000F, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'h000000F0, 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b0 };
+
+ portUnderTest = 18'b000000000000110011;
+ g_tru_enable = 1;
+ g_failure_scenario = 5;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,2 , 4 };
+ trans_paths[1] = '{1 ,3 , 4 };
+ trans_paths[4] = '{4 ,6 , 10};
+ trans_paths[5] = '{5 ,7 , 10};
+ repeat_number = 30;
+ tries_number = 1;
+ g_is_qvlan = 1;
+ tru_config_opt = 1;
+
+ end
+*/
+ /** *************************** test scenario 18 ************************************* **/
+ /*
+ * simle VLAN tagging test:
+ * we send untagged frame and it should (acccording to the table with which I don't agree)
+ * tagged (simulation errors appear)
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ g_tru_enable = 0;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,2 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ g_is_qvlan = 0;
+ qmode = 3;
+
+ end
+*/
+ /** *************************** test scenario 19 ************************************* **/
+ /*
+ * simle VLAN test
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000010001;
+ g_tru_enable = 0;
+ sim_vlan_tab[0] = '{'{32'h0000000F, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'h000000F0, 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b0 };
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,1 , 4 };
+ trans_paths[4] = '{4 ,5 , 10 };
+ repeat_number = 30;
+ tries_number = 1;
+ g_is_qvlan = 1;
+
+ end
+*/
+ /** *************************** test scenario 19 ************************************* **/
+ /*
+ * simple pfilter test: sets class=1 for each packet sent
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ g_tru_enable = 0;
+ sim_vlan_tab[0] = '{'{32'h0000000F, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'h000000F0, 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b0 };
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,1 , 4 };
+ trans_paths[5] = '{5 ,6 , 10 };
+ repeat_number = 30;
+ tries_number = 1;
+ g_is_qvlan = 1;
+ g_pfilter_enabled = 1;
+
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(6, 'h8100, 'hffff, PFilterMicrocode::MOV, 1);
+ mc.nop();
+ mc.cmp(8, 'h88f7, 'hffff, PFilterMicrocode::AND, 1);
+ mc.logic2(24, 1, PFilterMicrocode::MOV, 0);
+
+ end
+*/
+ /** *************************** test scenario 20 ************************************* **/
+ /*
+ * Testing pFilter:
+ * detecting different classes of incoming packets using pFilter
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000010001;
+ g_tru_enable = 0;
+ sim_vlan_tab[0] = '{'{32'h0000000F, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'h000000F0, 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'hFFFFFFFF, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b0 };
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,1 , 100 };
+ trans_paths[4] = '{4 ,5 , 10 };
+ repeat_number = 30;
+ tries_number = 1;
+ g_is_qvlan = 1;
+ g_pfilter_enabled = 1;
+
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(6, 'h8100, 'hffff, PFilterMicrocode::MOV, 1);
+ mc.nop();
+ mc.cmp(8, 'hbabe, 'hffff, PFilterMicrocode::AND, 1);
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(16, 'h0001, 'hffff, PFilterMicrocode::MOV, 2);
+ mc.cmp(16, 'h0010, 'hffff, PFilterMicrocode::MOV, 3);
+ mc.cmp(16, 'h0100, 'hffff, PFilterMicrocode::MOV, 4);
+ mc.cmp(16, 'h1000, 'hffff, PFilterMicrocode::MOV, 5);
+
+ mc.logic2(24, 1, PFilterMicrocode::AND, 2);
+ mc.logic2(25, 1, PFilterMicrocode::AND, 3);
+ mc.logic2(26, 1, PFilterMicrocode::AND, 4);
+ mc.logic2(27, 1, PFilterMicrocode::AND, 5);
+
+ end
+*/
+ /** *************************** test scenario 21 ********************** **/
+ /** *************************** (IMPORTANT) ********************** **/
+ /*
+ * injection/filtering test => transition test
+ * we imitate transition when new (and better) link is added and we change the configuraiton
+ * with pausing taffic not to loose anything, so we have
+ * ports 0 & 7 - normal = active
+ * ports 1 & 2 - 1 is active and 2 is backup (ingress blocking, egress forwarding)
+ *
+ * what we do:
+ * 1. send frame to 0,1,2 ports just for test
+ * 2. send special "marker" on port 2 to start transition
+ * 3. send few frames to port 2 which are counted
+ * 4. send "marker" to port 1 to indicate that ports can be changed
+ * 5. send few frames to port 1 (the are counted, as soon as the same number as on port 2 is counted
+ * the configuration is swapped and the frames start to be blocked)
+ * 6. saend frames to port 2 which now works as active
+ */
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000000; // we send pcks (Markers) in other place
+ g_tru_enable = 1;
+ // tx ,rx ,opt
+ repeat_number = 1;
+ tries_number = 1;
+ g_injection_templates_programmed = 1;
+ tru_config_opt = 3;
+ g_pfilter_enabled = 1;
+ g_transition_scenario= 1;
+ g_limit_config_to_port_num = 8; //to speed up the config, don't configure VLANS and stuff
+ // in ports above nubmer 7
+
+ mc.nop();
+ mc.cmp(0, 'h0180, 'hffff, PFilterMicrocode::MOV, 1);
+ mc.cmp(1, 'hc200, 'hffff, PFilterMicrocode::AND, 1);
+ mc.cmp(2, 'h0000, 'hffff, PFilterMicrocode::AND, 1);
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(6, 'hbabe, 'hffff, PFilterMicrocode::AND, 1);
+ mc.logic2(25, 1, PFilterMicrocode::MOV, 0);
+
+ end
+*/
+ /** *************************** test scenario 22 ************************************* **/
+ /*
+ * Sending Pause the switch: a problem is that switch does not react to PAUSEs -- no
+ * flow control impolemented -- to be FIXED
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000011;
+ g_tru_enable = 1;
+// g_injection_templates_programmed = 1;
+ g_transition_scenario= 2;
+ tru_config_opt = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,2 , 4 };
+ trans_paths[1] = '{1 ,3 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 23 ************************************* **/
+ /*
+ * simple LACP test:
+ * - sending frames to port 0
+ * - two link aggregations
+ * * ports 3 - 7
+ * * ports 12 & 15
+ * - sending frames on port 5 (from aggregated links)
+ * - we don't recongize HP traffic, all the kinds of traffic have the same distribbution
+ * source...
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000100; // no frames this way
+ g_tru_enable = 1;
+ tru_config_opt = 2;
+ hp_prio_mask = 'b10000000;
+ // tx ,rx ,opt
+ trans_paths[2] = '{5 ,0 , 444 };// not FEC traffic cause etherType is not 0xbabe (the rest is)
+ repeat_number = 30;
+ tries_number = 1;
+ g_LACP_scenario = 1;
+ mac_br = 1;
+ g_pfilter_enabled = 1;
+ g_do_vlan_config = 0; //to make simulation faster, we don't need VLAN config, default is OK
+ // limiting with VLAN
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0000F0F1, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+
+ mc.nop();
+ mc.cmp(0, 'hFFFF, 'hffff, PFilterMicrocode::MOV, 1); //setting bit 1 to HIGH if it
+ mc.cmp(1, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // is righ kind of frame, i.e:
+ mc.cmp(2, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // 1. broadcast
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(8, 'hbabe, 'hffff, PFilterMicrocode::AND, 1); // 2. EtherType
+ mc.cmp(9, 'h0000, 'hffff, PFilterMicrocode::MOV, 2); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0001, 'hffff, PFilterMicrocode::MOV, 3); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0002, 'hffff, PFilterMicrocode::MOV, 4); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0003, 'hffff, PFilterMicrocode::MOV, 5); // veryfing info in the frame for aggregation ID
+ mc.logic2(24, 2, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(25, 3, PFilterMicrocode::AND, 1); // recognizing class 1 in correct frame
+ mc.logic2(26, 4, PFilterMicrocode::AND, 1); // recognizing class 2 in correct frame
+ mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 3 in correct frame
+ end
+ */
+ /** *************************** test scenario 23 ************************************* **/
+ /*
+ * LACP test:
+ * - hp/broadcast/unicast distribution functions
+ * - sending traffic to two port aggregations groups (4-7 and 13&15 ports)
+ * - sending traffic from port on aggregation group
+ * - the simulation is a bit simple, so the distribution looks the same for
+ * hp/broarcast/unicast but each of them is derived differently:
+ * - hp - from plcass detected using packet filter
+ * - br - from source MAC, bits 8 & 9
+ * - un - from destination MAC, bits 8 & 9
+ **/
+ /*
+ initial begin
+ g_min_pck_gap = 50; // cycles
+ g_max_pck_gap = 50; // cycles
+ portUnderTest = 18'b000000000000000100; // no frames this way
+ g_tru_enable = 1;
+ tru_config_opt = 2;
+ // tx ,rx ,opt
+ trans_paths[2] = '{5 ,0 , 4 };//
+ repeat_number = 30;
+ tries_number = 1;
+ g_LACP_scenario = 2;
+ mac_br = 1;
+ g_pfilter_enabled = 1;
+ repeat_number = 20;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0000F0F1, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+
+ mc.nop();
+ mc.cmp(0, 'hFFFF, 'hffff, PFilterMicrocode::MOV, 1); //setting bit 1 to HIGH if it
+ mc.cmp(1, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // is righ kind of frame, i.e:
+ mc.cmp(2, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // 1. broadcast
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(8, 'hbabe, 'hffff, PFilterMicrocode::AND, 1); // 2. EtherType
+ mc.cmp(9, 'h0000, 'hffff, PFilterMicrocode::MOV, 2); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0001, 'hffff, PFilterMicrocode::MOV, 3); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0002, 'hffff, PFilterMicrocode::MOV, 4); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0003, 'hffff, PFilterMicrocode::MOV, 5); // veryfing info in the frame for aggregation ID
+ mc.logic2(24, 2, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(25, 3, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(26, 4, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ end
+ */
+ /*****************************************************************************************/
+
+// defining which ports send pcks -> forwarding is one-to-one
+// (port_1 to port_14, port_2 to port_13, etc)
+// reg [18:0] portUnderTest = 18'b000000000000000011; // unicast -- port 0 disabled by VLAN config
+// reg [18:0] portUnderTest = 18'b111000000000000111; // unicast
+// reg [18:0] portUnderTest = 18'b000000000000001111; // unicast - switch over
+// reg [18:0] portUnderTest = 18'b100000000000000001; // unicast
+// reg [18:0] portUnderTest = 18'b000000000000001000; // broadcast
+// reg [18:0] portUnderTest = 18'b100000000000000101;
+// reg [18:0] portUnderTest = 18'b111111111111111111;
+// integer tx_option[18] = {4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+// integer repeat_number = 10;
+// integer tries_number = 3;
+
+ /** *************************** test scenario 24 ************************************* **/
+ /** *************************** (PROBLEMATIC) ************************************* **/
+ /*
+ * problematic, packets get merged
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ tru_config_opt = 4;
+ g_failure_scenario = 1;
+ g_injection_templates_programmed = 1;
+ mac_single = 1; // enable single mac entry for fast forward
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 5 };
+ trans_paths[1] = '{1 ,16 , 5 };
+ trans_paths[2] = '{2 ,15 , 5 };
+ end
+ */
+
+ /** *************************** test scenario 25 ************************************* **/
+ /*
+ *
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000011;
+ g_tru_enable = 1;
+ tru_config_opt = 4;
+ g_failure_scenario = 1;
+ g_active_port = 0;
+ g_injection_templates_programmed = 1;
+ mac_single = 1; // enable single mac entry for fast forward
+ // tx ,rx ,opt
+ // trans_paths[0] = '{0 ,17 , 5 };
+ trans_paths[0] = '{0 ,2 , 5 };
+ trans_paths[1] = '{1 ,2 , 5 };
+ end
+*/
+
+
+ /** *************************** test scenario 26 ************************************* **/
+ /*
+ * problem with small frames and min InterFrame Gap: Linked-list is too slow
+ **/
+ /*
+ initial begin
+
+ portUnderTest = 18'b000000000000000001;
+ g_active_port = 0;
+ g_enable_pck_gaps = 0;
+ repeat_number = 2000;
+ tries_number = 1;
+ g_force_payload_size = 64;
+
+// mac_br = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 203 };
+ start_send_init_delay = '{0,20,40,60,80,100,120,140,160,180,200,220,240,260,280,300,320,340};
+
+// mac_br = 1;
+ end
+ */
+
+ /** *************************** test scenario 27 ************************************* **/
+ /*
+ * Sending heavily broadcast (stress-tests)
+ **/
+ /*
+ initial begin
+// portUnderTest = 18'b000000011111111111;
+ portUnderTest = 18'b000000000000000001;
+ g_active_port = 0;
+ g_enable_pck_gaps = 0;
+ repeat_number = 2000;
+ tries_number = 1;
+ g_force_payload_size = 500;
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 204 };
+
+ start_send_init_delay = '{0,20,40,60,80,100,120,140,160,180,200,220,240,260,280,300,320,340};
+
+ end
+ */
+ /** *************************** test scenario 28 ************************************* **/
+ /*
+ * PAUSE test - simple test of Time Aware Traffic Shaper (TATSU) and output queues
+ * - sending PAUSE frames
+ * - making some strange configuration of TATSU
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_active_port = 0;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 0;
+ g_min_pck_gap = 800; // cycles
+ g_max_pck_gap = 800; // cycles
+ g_pause_mode = 2;
+ g_enable_WRtime = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 900 };
+ trans_paths[1] = '{1 ,16 , 901 };
+ trans_paths[2] = '{2 ,15 , 1 };
+
+ g_traffic_shaper_scenario = 1;
+ end
+ */
+ /** *************************** test scenario 29 ************************************* **/
+ /*
+ *
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_active_port = 0;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 0;
+ g_min_pck_gap = 1000; // cycles
+ g_max_pck_gap = 1000; // cycles
+ g_pause_mode = 2;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 900 };
+ trans_paths[1] = '{1 ,16 , 901 };
+ trans_paths[2] = '{2 ,15 , 205 };
+
+ g_traffic_shaper_scenario = 2;
+ g_enable_WRtime = 1;
+
+ end
+ */
+ /** *************************** test scenario 30 ************************************* **/
+ /*
+ * testing simple RTU forwarding and stuff
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b010101010101010101;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 700;
+ g_min_pck_gap = 100; // cycles
+ g_max_pck_gap = 100; // cycles
+ // tx ,rx ,opt
+
+ end
+ */
+ /** *************************** test scenario 31 ************************************* **/
+ /*
+ * output drop at HP - testing
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_enable_pck_gaps = 0;
+ repeat_number = 20;
+ tries_number = 1;
+ g_force_payload_size = 300;
+ g_tatsu_config = 1;
+ mac_br = 1;
+// g_min_pck_gap = 100; // cycles
+// g_max_pck_gap = 100; // cycles
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 206 };
+ trans_paths[1] = '{1 ,16 , 206 };
+ trans_paths[2] = '{2 ,15 , 206 };
+
+ end
+*/
+ /** *************************** test scenario 32 ************************************* **/
+ /*
+ * testing switch over for TRU->eRSTP
+ * we port 0 (active) in the middle of frame reception - the rx error should be handled
+ * properly
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 6;
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ end
+*/
+ /** *************************** test scenario 33 ************************************* **/
+ /*
+ * test WR Marker (HP+CPU forward)
+ * - forwarding of HP traffic to NIC is disabled, but marker is recognized as link-limited (nf)
+ * so it is forwarded to CPU anyway (not as HP but as NF)
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 6;
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 11 };
+ trans_paths[1] = '{1 ,16 , 11 };
+ trans_paths[2] = '{2 ,15 , 11 };
+ repeat_number = 30;
+ tries_number = 1;
+
+ mac_ll = 1;
+ mac_single = 1;
+ hp_fw_cpu = 0; //
+ end
+ */
+ /** *************************** test scenario 34 ************************************* **/
+ /*
+ * HP traffic forwarding to NIC:
+ * - by default should not be forwarded: nic_fw =0
+ * - should be forwarded if nic_fw=1
+ *
+ * we change the config of nic_fw in failure sceonario 7 (out of laziness here)
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 7; // changes hp_fw_cpu to 1
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+
+ mac_ll = 1;
+ mac_single = 1;
+ mac_br = 1;
+ hp_fw_cpu = 0; //
+ end
+ /*/
+ /** *************************** test scenario 35 ************************************* **/
+ /*
+ * Learning - enable/disble forwarding of unrecognized broadcast to CPU
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 12 };
+ repeat_number = 30;
+ tries_number = 1;
+
+ mac_ll = 1;
+ mac_single = 1;
+ mac_br = 1;
+ hp_fw_cpu = 0; //
+ unrec_fw_cpu = 0;
+ g_fw_to_cpu_scenario = 1;
+ end
+ */
+ /** *************************** test scenario 36 ************************************* **/
+ /*
+ * testing switch over with HW-frame generation
+ *
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1;
+ g_enable_pck_gaps = 1; // 1=TRUE, 0=FALSE
+ g_min_pck_gap = 300; // cycles
+ g_max_pck_gap = 300; // cycles
+ g_failure_scenario = 6;
+ g_active_port = 0;
+ g_backup_port = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 4 };
+ trans_paths[1] = '{1 ,16 , 4 };
+ trans_paths[2] = '{2 ,15 , 4 };
+ repeat_number = 30;
+ tries_number = 1;
+ tru_config_opt = 5;
+// g_injection_templates_programmed = 1;
+ end
+*/
+ /** *************************** test scenario 37 ************************************* **/
+ /*
+ * quick forward/block massage detection and action
+ *
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000000;
+ g_tru_enable = 1;
+ g_transition_scenario= 3;
+ g_active_port = 0;
+ g_backup_port = 1;
+ tru_config_opt = 6;
+ g_pfilter_enabled = 1;
+ g_injection_templates_programmed = 1;
+
+ mc.nop();
+ mc.cmp(0, 'h0180, 'hffff, PFilterMicrocode::MOV, 1);
+ mc.cmp(1, 'hc200, 'hffff, PFilterMicrocode::AND, 1);
+ mc.cmp(2, 'h0000, 'hffff, PFilterMicrocode::AND, 1);
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(6, 'h2607, 'hffff, PFilterMicrocode::AND, 1);
+ mc.logic2(25, 1, PFilterMicrocode::MOV, 0);
+ mc.logic2(26, 1, PFilterMicrocode::MOV, 0);
+
+ end
+*/
+ /** *************************** test scenario 38 ************************************* **/
+ /*
+ * simple tagging/untagging test:
+ * 1) send untaggged frames
+ * 2) they get tagged at ingress port
+ * 3) they get forwarded for pvid VLAN id
+ * 4) they get untagged on egress
+ **/
+ /*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+
+ qmode = 0;//access
+ pvid = 1;//tagging vlan
+ g_is_qvlan = 0; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ g_set_untagging = 1; // set pre-defined untagging config (untag VIDs:0 - 10)
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 0 };
+ trans_paths[1] = '{1 ,16 , 0 };
+ trans_paths[2] = '{2 ,15 , 0 };
+
+ end
+/*/
+ /** *************************** test scenario 39 ************************************* **/
+ /*
+ * tagging+untaggint + HP
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+
+ qmode = 0;//access
+ pvid = 1;//tagging vlan
+ prio_val = 7;//tag with prio 7 (7 is for HP)
+ g_is_qvlan = 0; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ g_set_untagging = 1; // set pre-defined untagging config (untag VIDs:0 - 10)
+
+ mac_br = 1; // fast forward broadcast
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 1 };
+// trans_paths[1] = '{1 ,16 , 0 };
+// trans_paths[2] = '{2 ,15 , 0 };
+
+ end
+*/
+ /** *************************** test scenario 40 ************************************* **/
+ /*
+ * Transparent TRU confgi
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000111;
+ g_tru_enable = 1; //enable TRU
+ tru_config_opt = 7; //TRUE transparent
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 , 0 };
+ trans_paths[1] = '{1 ,16 , 0 };
+ trans_paths[2] = '{2 ,15 , 0 };
+
+ end
+*/
+ /** *************************** test scenario 41 ************************************* **/
+ /*
+ * testing switch over between ports 1,2
+ * we broadcast on ports 1 and 2. One of them is only active.
+ * after some time port 0 failes (failure_scenario 7) and we switch to the othter
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000110;
+ g_tru_enable = 1;
+ g_failure_scenario = 8;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,6 , 4 };
+ trans_paths[2] = '{2 ,7 , 4 };
+ repeat_number = 30;
+ g_active_port = 1;
+ g_backup_port = 2;
+ tries_number = 1;
+ tru_config_opt = 3;
+ end
+*/
+ /** *************************** test scenario 42 ************************************* **/
+ /*
+ * testing switch over between ports 1,2
+ * we broadcast on ports 1 and 2. One of them is only active.
+ * after some time port 0 failes (failure_scenario 7) and we switch to the othter
+ *
+ * with much higher laod
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000110;
+ g_tru_enable = 1;
+ g_failure_scenario = 9;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,6 , 4 };
+ trans_paths[2] = '{2 ,7 , 4 };
+ repeat_number = 30;
+ g_active_port = 1;
+ g_backup_port = 2;
+ tries_number = 1;
+ tru_config_opt = 3;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+
+ /** *************************** test scenario 43 ************************************* **/
+ /** *************************** (PROBLEMATIC) ************************************* **/
+ /*
+ * stress test: 18 ports with packets, no gap - page-allocation too slow...
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b111111111111111111;
+ repeat_number = 30;
+ tries_number = 1;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+ /** *************************** test scenario 44 ************************************* **/
+ /** *************************** (PROBLEMATIC) ************************************* **/
+ /*
+ * stress test: 18 ports with packets, no gap - page-allocation too slow...
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b111111111111111111;
+ repeat_number = 30;
+ tries_number = 1;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+ /** *************************** test scenario 45 ************************************* **/
+ /*
+ * test HP detection by prio - works
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ trans_paths[0] = '{0 ,1 , 207 }; //prio 3, broadcast
+ repeat_number = 30;
+ tries_number = 1;
+ mac_br = 1;
+ hp_prio_mask ='b01000010;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 64;
+ end
+*/
+ /** *************************** test scenario 46 ************************************* **/
+ /** *************************** (FIXED BUG) ************************************* **/
+ /*
+ * trying to simulate test setup in the lab to check whether 8 ports binary 09_05_13_00/5
+ * does not show RTUful events -
+ *
+ * found and fixed :)
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ trans_paths[0] = '{0 ,1 ,7}; //fast forward with single entry 11...11
+ repeat_number = 30;
+ tries_number = 1;
+ mac_single = 1;
+ mac_br = 0;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ hp_prio_mask = 'b00000000;
+ end
+*/
+ /** *************************** test scenario 47 ************************************* **/
+ /*
+ * testing switch over between ports 1,2
+ * simulating thrashing of lost physic signal....
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000110;
+ g_tru_enable = 1;
+ g_failure_scenario = 10;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,6 , 4 };
+ trans_paths[2] = '{2 ,7 , 4 };
+ repeat_number = 30;
+ g_active_port = 1;
+ g_backup_port = 2;
+ tries_number = 1;
+ tru_config_opt = 3;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+ /** *************************** test scenario 48 ************************************* **/
+ /** *************************** (FIXED BUG) ************************************* **/
+ /*
+ * testing switch over between ports 1,2
+ * trying to simulate situation which happens in hw: stuck at S_WAIT_RTU_VALID,-> simulated and fixed
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000110;
+ g_tru_enable = 1;
+ g_failure_scenario = 11;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,6 , 7 };
+ trans_paths[2] = '{2 ,7 , 7 };
+ repeat_number = 30;
+ g_active_port = 1;
+ g_backup_port = 2;
+ tries_number = 1;
+ tru_config_opt = 3;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+ /** *************************** test scenario 49 ************************************* **/
+ /** *************************** (FIXED BUG) ************************************* **/
+ /*
+ * testing switch over between ports 1,2 on the "upper switch" -> the one which is sending
+ * onto two ports
+ * trying to simulate situation which happens in hw: the switch starts to drop frames forward
+ * to the rendundant link aggregation
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b0000000000010000000;
+ portRtuEnabled = 18'b0000000000010000110;
+ g_tru_enable = 1;
+ g_failure_scenario = 11;
+ // tx ,rx ,opt
+ trans_paths[7] = '{7 ,2 , 7 };
+ repeat_number = 30;
+ g_active_port = 1;
+ g_backup_port = 2;
+ tries_number = 1;
+ tru_config_opt = 3;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+ /** *************************** test scenario 50 ************************************* **/
+ /*
+ * testing switch over between ports 1,2
+ * simulating ungraceful loss of physic signal....
+ *
+ **/
+/*
+
+ initial begin
+ portUnderTest = 18'b000000000000000110;
+ g_tru_enable = 1;
+ g_failure_scenario = 11;
+ // tx ,rx ,opt
+ trans_paths[1] = '{1 ,6 , 4 };
+ trans_paths[2] = '{2 ,7 , 4 };
+ repeat_number = 30;
+ g_active_port = 1;
+ g_backup_port = 2;
+ ep_failure_type = 'h01;
+ tries_number = 1;
+ tru_config_opt = 3;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 512;
+ end
+*/
+ /** *************************** test scenario 51 ************************************* **/
+ /*
+ * VLAN + FF bug
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000010000001;
+
+ g_is_qvlan = 1; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ qmode = 2;
+ mac_br = 1; // fast forward broadcast
+ hp_prio_mask = 8'b0;
+ sim_vlan_tab[1] = '{'{32'b11 , 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'b110 , 8'h2, 3'h0, 1'b0, 1'b0, 1'b0}, 2 , 1'b1 };
+ sim_vlan_tab[3] = '{'{32'b1100 , 8'h3, 3'h0, 1'b0, 1'b0, 1'b0}, 3 , 1'b1 };
+ sim_vlan_tab[4] = '{'{32'b11000 , 8'h4, 3'h0, 1'b0, 1'b0, 1'b0}, 4 , 1'b1 };
+ sim_vlan_tab[5] = '{'{32'b110000 , 8'h5, 3'h0, 1'b0, 1'b0, 1'b0}, 5 , 1'b1 };
+ sim_vlan_tab[6] = '{'{32'b1100000 , 8'h6, 3'h0, 1'b0, 1'b0, 1'b0}, 6 , 1'b1 };
+ sim_vlan_tab[7] = '{'{32'b11000000 , 8'h7, 3'h0, 1'b0, 1'b0, 1'b0}, 7 , 1'b1 };
+ sim_vlan_tab[8] = '{'{32'b110000000 , 8'h8, 3'h0, 1'b0, 1'b0, 1'b0}, 8 , 1'b1 };
+ sim_vlan_tab[9] = '{'{32'b1100000000, 8'h9, 3'h0, 1'b0, 1'b0, 1'b0}, 9 , 1'b1 };
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,2 , 13 }; // send braodcast to VLAN=3
+ trans_paths[7] = '{7 ,0 , 10 };//send broadcast to VLAN=1
+// trans_paths[2] = '{2 ,15 , 0 };
+
+ end
+*/
+ /** *************************** test scenario 51 ************************************* **/
+ /*
+ * VLAN + FF bug
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000010000000;
+
+ g_is_qvlan = 1; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ qmode = 2;
+// mac_br = 1; // fast forward broadcast
+ hp_prio_mask = 8'b0;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'hF , 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'hF0 , 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ // tx ,rx ,opt
+
+ trans_paths[7] = '{7 ,4 , 10 };//send broadcast to VLAN=1
+// trans_paths[0] = '{2 ,15 , 0 };
+
+ end
+*/
+
+ /** *************************** test scenario 52 ************************************* **/
+ /*
+ * debugging priorities and PSTATS counters for prios
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+
+ g_is_qvlan = 1; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+// pvid = 1; // mapping of priority here
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0 , 8'h0, 3'h0, 1'b0, 1'b0, 1'b1}, 0 , 1'b1 }; //disable VID=0
+ sim_vlan_tab[1] = '{'{32'hFFFF , 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ // tx ,rx ,opt
+
+ trans_paths[0] = '{0 ,1 , 205 };//different priorities
+
+
+ end
+/*/
+/** *************************** test scenario 53 ************************************* **/
+ /*
+ * debugging VLANs -> works on simulation -> seems to be timing problem when reading
+ * from RAM (VLAN tab)
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+
+ g_is_qvlan = 1; //send VLAN-tagged frames
+ g_do_vlan_config = 1; //enable vlan confgi
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0 , 8'h0, 3'h0, 1'b0, 1'b0, 1'b1}, 0 , 1'b1 }; //disable VID=0
+ sim_vlan_tab[1] = '{'{32'hFFFF , 8'h1, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ // tx ,rx ,opt
+
+ trans_paths[0] = '{0 ,1 , 10 }; // vid=1
+
+
+ end
+/*/
+/** *************************** test scenario 53 ************************************* **/
+ /*
+ * HP-traffic debugging
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ mac_br = 1;
+ g_is_qvlan = 0;
+// hp_prio_mask = 'b00000000;
+ hp_prio_mask = 'b00000010;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,1 , 1 }; // vid=1
+
+
+ end
+/*/
+ /** *************************** test scenario 54 ************************************* **/
+ /*
+ * simple LACP test - marker-based switch between link aggregation config:
+ * 1) send frames with first type of distribution function (aggregation between 4-7 and
+ * 12 &15 ports)
+ * 2) set new type of distribution function (aggregation between 4,5,7 and 12 % 15)
+ * 3) set transition config (rep for: "g_transition_scenario == 4") :
+ * tru.transition_config(1 , 4 , 0 , 7 , 1000 ,6 , 7 );
+ * - LACP-> marker (1)
+ * - pfilter class on which to trigger it (4)
+ * - mode of choice which priority should be affected (0)
+ * - protect only high priority (7)
+ * - block output queue for max 1000 quanta
+ * - transition from port 6 to 7
+ * 4) enable transition
+ * - active TRU table bank will be swapped (new config-> new distributin function activated)
+ * - output queue of port 7 will be blocked
+ * - Marker Response will be awated at port 6 (pfilter, if detected at port 6, bit 4 of plcass
+ * will be high
+ * - await max 1000 quanta
+ * 5) Marker response frame received, output queue of port 7 unblocked
+ * 6) Voila, we have new distribution without loosing frames at prio 7
+ *
+ * for this to work, the CPU
+ * @ the distributor switch should send Marker Request frame
+ * @ the collector switch should replay (when Marker Request is received) with Marker Response
+ * this might turn out to be slow....
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000000; // no frames this way
+ g_tru_enable = 1;
+ tru_config_opt = 2;
+ hp_prio_mask = 'b10000000;
+ g_transition_scenario= 4;
+ // tx ,rx ,opt
+// trans_paths[2] = '{5 ,0 , 444 };// not FEC traffic cause etherType is not 0xbabe (the rest is)
+ repeat_number = 50;
+ tries_number = 1;
+ g_LACP_scenario = 3;
+ mac_br = 1;
+ g_pfilter_enabled = 1;
+ g_do_vlan_config = 0; //to make simulation faster, we don't need VLAN config, default is OK
+ // limiting with VLAN
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0000F0F1, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+
+ mc.nop();
+ mc.cmp(0, 'hFFFF, 'hffff, PFilterMicrocode::MOV, 1); //FEC : setting bit 1 to HIGH if it
+ //FEC : is righ kind of frame, i.e:
+ //FEC : broadcast
+ mc.cmp(0, 'h0180, 'hffff, PFilterMicrocode::MOV, 6); //Marker: BPDU
+
+ mc.cmp(1, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); //FEC : broadcast
+ mc.cmp(1, 'hC200, 'hffff, PFilterMicrocode::AND, 6); //Marker: BPDU -> LACP Marker
+
+ mc.cmp(2, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); //FEC : broadcast
+ mc.cmp(2, 'h0002, 'hffff, PFilterMicrocode::AND, 6); //Marker: BPDU
+
+ mc.nop();
+ mc.nop();
+ mc.nop();
+
+ mc.cmp(6, 'h8809, 'hffff, PFilterMicrocode::AND, 6); //Marker: EtherType -> Marker
+ mc.cmp(7, 'h0201, 'hffff, PFilterMicrocode::AND, 6); //Marker: subtype+version
+
+ mc.cmp(8, 'hbabe, 'hffff, PFilterMicrocode::AND, 1); //FEC : EtherType -> FEC
+ mc.cmp(8, 'h0100, 'hff00, PFilterMicrocode::MOV, 7); //Marker: 0x02->Marker request
+ mc.cmp(8, 'h0200, 'hff00, PFilterMicrocode::MOV, 8); //Marker: 0x02->Marker response
+
+ mc.cmp(9, 'h0000, 'hffff, PFilterMicrocode::MOV, 2); //FEC : conversation ID
+ mc.cmp(9, 'h0001, 'hffff, PFilterMicrocode::MOV, 3); //FEC : conversation ID
+ mc.cmp(9, 'h0002, 'hffff, PFilterMicrocode::MOV, 4); //FEC : conversation ID
+ mc.cmp(9, 'h0003, 'hffff, PFilterMicrocode::MOV, 5); //FEC : conversation ID
+
+ mc.logic2(24, 2, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(25, 3, PFilterMicrocode::AND, 1); // recognizing class 1 in correct frame
+ mc.logic2(26, 4, PFilterMicrocode::AND, 1); // recognizing class 2 in correct frame
+ mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 3 in correct frame
+ mc.logic2(28, 8, PFilterMicrocode::AND, 6); // recognizing recognizing Marker Response Frame
+// mc.logic2(28, 7, PFilterMicrocode::AND, 6); // recognizing recognizing Marker Response Frame
+ end
+
+*/
+ /** *************************** test scenario 55 (works) ************************************* **/
+ /*
+ * LACP test: using special "LACP mode" in the TRU table - solved the problem of sending
+ * a frame received on link aggregation back to the ports of the aggregation (special LACP mode)
+ *
+ * TRU table configuraiton for LACP using special LACP-dedicated "mode". For this you need:
+ * 1) define "default" entry with "mode"=0x0 (here subentry_addr=0) which allows accepting
+ * frames all aggregation ports but does not allow forwarding ports to aggregation ports
+ * (ingres vs. egress)
+ * 2) define each link aggregation with "mode"=0x4 (group of ports which define link aggregation
+ * - the ingress mask is used to recognize that frame comes from link aggregation, it is
+ * not used to create final forwarding/accepting mask
+ * - the egress mask is used to define through which port of the link aggregation
+ * the particular frame (of a given conversation/group identified by pattern_match) should use
+ *
+ * see the place where confgi si done (grep for "tru_config_opt == 8")
+ **/
+/*
+ initial begin
+ g_min_pck_gap = 50; // cycles
+ g_max_pck_gap = 50; // cycles
+ portUnderTest = 18'b000000000000000100; // no frames this way
+ g_tru_enable = 1;
+ tru_config_opt = 8; //SEE description in the place where the config is done !!!!!!!
+ // tx ,rx ,opt
+ trans_paths[2] = '{5 ,0 , 444 };//
+ hp_prio_mask = 'b10000000;
+ repeat_number = 30;
+ tries_number = 1;
+ g_LACP_scenario = 2;
+ mac_br = 1;
+ g_pfilter_enabled = 1;
+ repeat_number = 20;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0000F0F1, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+
+ mc.nop();
+ mc.cmp(0, 'hFFFF, 'hffff, PFilterMicrocode::MOV, 1); //setting bit 1 to HIGH if it
+ mc.cmp(1, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // is righ kind of frame, i.e:
+ mc.cmp(2, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // 1. broadcast
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(8, 'hbabe, 'hffff, PFilterMicrocode::AND, 1); // 2. EtherType
+ mc.cmp(9, 'h0000, 'hffff, PFilterMicrocode::MOV, 2); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0001, 'hffff, PFilterMicrocode::MOV, 3); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0002, 'hffff, PFilterMicrocode::MOV, 4); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0003, 'hffff, PFilterMicrocode::MOV, 5); // veryfing info in the frame for aggregation ID
+ mc.logic2(24, 2, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(25, 3, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(26, 4, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ end
+*/
+ /** *************************** test scenario 56 (problematic- ToDo) ************************** **/
+ /*
+ * LACP test: - trying different way of solving the problem of forwarding frames back
+ * to the link aggregation -> does not work -> need further debugging
+ **/
+/*
+ initial begin
+ g_min_pck_gap = 50; // cycles
+ g_max_pck_gap = 50; // cycles
+ portUnderTest = 18'b000000000000000100; // no frames this way
+ g_tru_enable = 1;
+ tru_config_opt = 9; //SEE description in the place where the config is done !!!!!!!
+ // tx ,rx ,opt
+ trans_paths[2] = '{5 ,0 , 444 };//
+ hp_prio_mask = 'b10000000;
+ repeat_number = 30;
+ tries_number = 1;
+ g_LACP_scenario = 2;
+ mac_br = 1;
+ g_pfilter_enabled = 1;
+ repeat_number = 20;
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h0000F0F1, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0 , 1'b1 };
+
+ mc.nop();
+ mc.cmp(0, 'hFFFF, 'hffff, PFilterMicrocode::MOV, 1); //setting bit 1 to HIGH if it
+ mc.cmp(1, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // is righ kind of frame, i.e:
+ mc.cmp(2, 'hFFFF, 'hffff, PFilterMicrocode::AND, 1); // 1. broadcast
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.nop();
+ mc.cmp(8, 'hbabe, 'hffff, PFilterMicrocode::AND, 1); // 2. EtherType
+ mc.cmp(9, 'h0000, 'hffff, PFilterMicrocode::MOV, 2); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0001, 'hffff, PFilterMicrocode::MOV, 3); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0002, 'hffff, PFilterMicrocode::MOV, 4); // veryfing info in the frame for aggregation ID
+ mc.cmp(9, 'h0003, 'hffff, PFilterMicrocode::MOV, 5); // veryfing info in the frame for aggregation ID
+ mc.logic2(24, 2, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(25, 3, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(26, 4, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ mc.logic2(27, 5, PFilterMicrocode::AND, 1); // recognizing class 0 in correct frame
+ end
+*/
+ /** *************************** test scenario 57 ************************************* **/
+ /*
+ * testing forcing of full_match/fast_match -> for debugging
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b010101010101010101;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 700;
+ g_min_pck_gap = 100; // cycles
+ g_max_pck_gap = 100; // cycles
+ mac_single = 1;
+
+ // tx ,rx ,opt
+ rtu_dbg_f_fast_match = 0;
+ rtu_dbg_f_full_match = 0;
+ end
+ */
+ /** *************************** test scenario 58 ************************************* **/
+ /*
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b111111111111111111;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 700;
+ g_min_pck_gap = 100; // cycles
+ g_max_pck_gap = 100; // cycles
+ mac_single = 1;
+ vid_init_for_inc = 1;
+ g_is_qvlan = 1;
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,666};
+ trans_paths[1] = '{1 ,16 ,666};
+ trans_paths[2] = '{2 ,15 ,666};
+ trans_paths[3] = '{3 ,14 ,666};
+ trans_paths[4] = '{4 ,13 ,666};
+ trans_paths[5] = '{5 ,12 ,666};
+ trans_paths[6] = '{6 ,11 ,666};
+ trans_paths[7] = '{7 ,10 ,666};
+ trans_paths[8] = '{8 ,9 ,666};
+ trans_paths[9] = '{9 ,8 ,666};
+ trans_paths[10] = '{10 ,7 ,666};
+ trans_paths[11] = '{11 ,6 ,666};
+ trans_paths[12] = '{12 ,5 ,666};
+ trans_paths[13] = '{13 ,4 ,666};
+ trans_paths[14] = '{14 ,3 ,666};
+ trans_paths[15] = '{15 ,2 ,666};
+ trans_paths[16] = '{16 ,1 ,666};
+ trans_paths[17] = '{17 ,0 ,666};
+
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h000000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b1}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'b100000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'b010000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2 , 1'b1 };
+ sim_vlan_tab[3] = '{'{32'b001000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3 , 1'b1 };
+ sim_vlan_tab[4] = '{'{32'b000100000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4 , 1'b1 };
+ sim_vlan_tab[5] = '{'{32'b000010000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5 , 1'b1 };
+ sim_vlan_tab[6] = '{'{32'b000001000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6 , 1'b1 };
+ sim_vlan_tab[7] = '{'{32'b000000100000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7 , 1'b1 };
+ sim_vlan_tab[8] = '{'{32'b000000010000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8 , 1'b1 };
+ sim_vlan_tab[9] = '{'{32'b000000001000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9 , 1'b1 };
+ sim_vlan_tab[10] = '{'{32'b000000000100000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 10 , 1'b1 };
+ sim_vlan_tab[11] = '{'{32'b000000000010000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 11 , 1'b1 };
+ sim_vlan_tab[12] = '{'{32'b000000000001000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 12 , 1'b1 };
+ sim_vlan_tab[13] = '{'{32'b000000000000100000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 13 , 1'b1 };
+ sim_vlan_tab[14] = '{'{32'b000000000000010000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 14 , 1'b1 };
+ sim_vlan_tab[15] = '{'{32'b000000000000001000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 15 , 1'b1 };
+ sim_vlan_tab[16] = '{'{32'b000000000000000100, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 16 , 1'b1 };
+ sim_vlan_tab[17] = '{'{32'b000000000000000010, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 17 , 1'b1 };
+ sim_vlan_tab[18] = '{'{32'b000000000000000001, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 18 , 1'b1 };
+
+ rtu_dbg_f_fast_match = 0;
+ rtu_dbg_f_full_match = 0;
+ tru_config_opt = 10;
+ g_tru_enable = 1;
+ end
+*/
+ /** *************************** test scenario 59 ************************************* **/
+ /*
+ * bug fith FastMatch+prio
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b000000000000000001;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 700;
+ g_min_pck_gap = 100; // cycles
+ g_max_pck_gap = 100; // cycles
+ mac_br = 1;
+ hp_prio_mask = 'b01001010;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,205};
+ end
+ */
+ /** *************************** test scenario 60 ************************************* **/
+ /*
+ *
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b111111111111111111;
+ g_enable_pck_gaps = 1;
+ repeat_number = 200;
+ tries_number = 1;
+ g_force_payload_size = 64;
+ g_min_pck_gap = 100; // cycles
+ g_max_pck_gap = 100; // cycles
+ mac_single = 1;
+ vid_init_for_inc = 1;
+ g_is_qvlan = 1;
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,667};
+ trans_paths[1] = '{1 ,16 ,667};
+ trans_paths[2] = '{2 ,15 ,667};
+ trans_paths[3] = '{3 ,14 ,667};
+ trans_paths[4] = '{4 ,13 ,667};
+ trans_paths[5] = '{5 ,12 ,667};
+ trans_paths[6] = '{6 ,11 ,667};
+ trans_paths[7] = '{7 ,10 ,667};
+ trans_paths[8] = '{8 ,9 ,667};
+ trans_paths[9] = '{9 ,8 ,667};
+ trans_paths[10] = '{10 ,7 ,667};
+ trans_paths[11] = '{11 ,6 ,667};
+ trans_paths[12] = '{12 ,5 ,667};
+ trans_paths[13] = '{13 ,4 ,667};
+ trans_paths[14] = '{14 ,3 ,667};
+ trans_paths[15] = '{15 ,2 ,667};
+ trans_paths[16] = '{16 ,1 ,667};
+ trans_paths[17] = '{17 ,0 ,667};
+
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[0] = '{'{32'h000000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b1}, 0 , 1'b1 };
+ sim_vlan_tab[1] = '{'{32'b100000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1 , 1'b1 };
+ sim_vlan_tab[2] = '{'{32'b010000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2 , 1'b1 };
+ sim_vlan_tab[3] = '{'{32'b001000000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3 , 1'b1 };
+ sim_vlan_tab[4] = '{'{32'b000100000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4 , 1'b1 };
+ sim_vlan_tab[5] = '{'{32'b000010000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5 , 1'b1 };
+ sim_vlan_tab[6] = '{'{32'b000001000000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6 , 1'b1 };
+ sim_vlan_tab[7] = '{'{32'b000000100000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7 , 1'b1 };
+ sim_vlan_tab[8] = '{'{32'b000000010000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8 , 1'b1 };
+ sim_vlan_tab[9] = '{'{32'b000000001000000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9 , 1'b1 };
+ sim_vlan_tab[10] = '{'{32'b000000000100000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 10 , 1'b1 };
+ sim_vlan_tab[11] = '{'{32'b000000000010000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 11 , 1'b1 };
+ sim_vlan_tab[12] = '{'{32'b000000000001000000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 12 , 1'b1 };
+ sim_vlan_tab[13] = '{'{32'b000000000000100000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 13 , 1'b1 };
+ sim_vlan_tab[14] = '{'{32'b000000000000010000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 14 , 1'b1 };
+ sim_vlan_tab[15] = '{'{32'b000000000000001000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 15 , 1'b1 };
+ sim_vlan_tab[16] = '{'{32'b000000000000000100, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 16 , 1'b1 };
+ sim_vlan_tab[17] = '{'{32'b000000000000000010, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 17 , 1'b1 };
+ sim_vlan_tab[18] = '{'{32'b000000000000000001, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 18 , 1'b1 };
+
- // defining which ports send pcks -> forwarding is one-to-one
- // (port_1 to port_14, port_2 to port_13, etc)
+ end
+*/
+ /** *************************** test scenario 61 ************************************* **/
+ /*
+ * test 100% load
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b100000000000000001;
+// portUnderTest = 18'b111111111111111111;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500000;
+ tries_number = 1;
+// g_force_payload_size = 270; // translates into 288 bytes - size of the entire frame as in
+// // spirent
+ g_force_payload_size = 110; // translates into 128 bytes - size of the entire frame as in
+// // spirent
+
+// g_force_payload_size = 242; // translates into 256 bytes in spirent -> this exactly 2 pages
+// g_force_payload_size = 230;
+// g_force_payload_size = 1000;
+
+// g_force_payload_size = 46;
+ g_force_payload_size = 218; // tranlates into 326 bytes in spirent -> with this we sa the problem
+
+
+ g_is_qvlan = 0;
+ trans_paths[0] = '{0 ,17 ,0};
+ trans_paths[17] = '{17 ,0 ,0};
+ // tx ,rx ,opt
+// trans_paths[0] = '{0 ,17 ,1000};
+// trans_paths[17] = '{17 ,0 ,1000};
+ end
+*/
+
+ /** *************************** test scenario 62 ************************************* **/
+ /*
+ * test 100% (high) load for 2 streams of small frames
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b110000000000000011;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500000;
+ tries_number = 1;
+ g_force_payload_size = 46;
+
+ g_is_qvlan = 0;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,0};
+ trans_paths[17] = '{17 ,0 ,0};
+
+ trans_paths[1] = '{1 ,16 ,0};
+ trans_paths[16] = '{16 ,1 ,0};
+
+ end
+*/
+
+ /** *************************** test scenario 63 ************************************* **/
+ /*
+ * test 100% (high) load for tagged frames
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b100000000000000001;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500000;
+ tries_number = 1;
+ g_force_payload_size = 46;
+ g_is_qvlan = 1;
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,0};
+ trans_paths[17] = '{17 ,0 ,0};
+
+ end
+ //*/
+ /** *************************** test scenario 64 ************************************* **/
+ /*
+ * test 100% (high) with tagging/untagging
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b100000000000000001;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500000;
+ tries_number = 1;
+// g_force_payload_size = 331;//46;
+ g_force_payload_size = 88; // it should be 106 of the entire frame
+// g_set_untagging = 1;
+// qmode = 3;
+ g_is_qvlan = 0;
+
+ // strange config -> make some strange wholes.... check this
+// qmode = 3;
+// g_is_qvlan = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,0};
+ trans_paths[17] = '{17 ,0 ,0};
+
+ end
+*/
+ /** *************************** test scenario 65 ************************************* **/
+ /*
+ * test 100% (high) with tagging/untagging
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b100000000000000001;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500000;
+ tries_number = 1;
+ g_force_payload_size = 128;//46;
+ g_set_untagging = 1;
+// qmode = 3;
+// g_is_qvlan = 0;
+//
+ // strange config -> make some strange wholes.... check this
+ qmode = 3;
+ g_is_qvlan = 1;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,0};
+ trans_paths[17] = '{17 ,0 ,0};
+
+ end
+ */
+ /** *************************** test scenario 66 ************************************* **/
+ /*
+ * test 100% (high) with tagging/untagging
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b100000000000000001;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500;
+ tries_number = 1;
+ g_force_payload_size = 46;
+ rx_forward_on_fmatch_full = 1;
+ g_is_qvlan = 0;
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,0};
+ trans_paths[17] = '{17 ,0 ,0};
+
+ end
+ */
+ /** *************************** test scenario 67 ************************************* **/
+ /*
+ * stress test on all ports with Unicast
+ * problem - to be investigated - cuts frames
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b1111111111111111111;
+ g_enable_pck_gaps = 0;
+ repeat_number = 500000;
+ tries_number = 1;
+ g_force_payload_size = 46*7;
+
+ g_is_qvlan = 0;
+ // tx ,rx ,opt
+ end
+/*/
+
+ /** *************************** test scenario 68 ************************************* **/
+ /*
+ * stress test on all ports with Unicast
+ **/
+/*
+ initial begin
+ portUnderTest = 18'b1111111111111111111;
+ g_enable_pck_gaps = 0;
+ repeat_number = 10;
+ tries_number = 1;
+ g_force_payload_size = 300;
+
+ g_is_qvlan = 0;
+ // tx ,rx ,opt
+ end
+*/
+
+ /** *************************** test scenario 69 (BUG case *************************** **/
+ /*
+ * stress test on all ports with Braodcast+FastForward
+ * FIXME: dropping does not work well - swcore gets lost
+ **/
+/*
+ initial begin
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[ 0] = '{'{32'h00000001, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
+ sim_vlan_tab[ 1] = '{'{32'h00000002, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
+ sim_vlan_tab[ 2] = '{'{32'h00000004, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b1 };
+ sim_vlan_tab[ 3] = '{'{32'h00000008, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b1 };
+ sim_vlan_tab[ 4] = '{'{32'h00000010, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b1 };
+ sim_vlan_tab[ 5] = '{'{32'h00000020, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b1 };
+ sim_vlan_tab[ 6] = '{'{32'h00000040, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b1 };
+ sim_vlan_tab[ 7] = '{'{32'h00000080, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b1 };
+ sim_vlan_tab[ 8] = '{'{32'h00000100, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b1 };
+ sim_vlan_tab[ 9] = '{'{32'h00000200, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b1 };
+ sim_vlan_tab[10] = '{'{32'h00000400, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 10, 1'b1 };
+ sim_vlan_tab[11] = '{'{32'h00000800, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 11, 1'b1 };
+ sim_vlan_tab[12] = '{'{32'h00001000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 12, 1'b1 };
+ sim_vlan_tab[13] = '{'{32'h00002000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 13, 1'b1 };
+ sim_vlan_tab[14] = '{'{32'h00004000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 14, 1'b1 };
+ sim_vlan_tab[15] = '{'{32'h00008000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 15, 1'b1 };
+ sim_vlan_tab[16] = '{'{32'h00010000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 16, 1'b1 };
+ sim_vlan_tab[17] = '{'{32'h00020000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 17, 1'b1 };
+ sim_vlan_tab[18] = '{'{32'h00040000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 18, 1'b1 };
+
+// tx ,rx ,opt (send from port tx to rx with option opt)
+ trans_paths[ 0]='{0 ,17 , 668 }; // port 0:
+ trans_paths[ 1]='{1 ,16 , 668 }; // port 1
+ trans_paths[ 2]='{2 ,15 , 668 }; // port 2
+ trans_paths[ 3]='{3 ,14 , 668 }; // port 3
+ trans_paths[ 4]='{4 ,13 , 668 }; // port 4
+ trans_paths[ 5]='{5 ,12 , 668 }; // port 5
+ trans_paths[ 6]='{6 ,11 , 668 }; // port 6
+ trans_paths[ 7]='{7 ,10 , 668 }; // port 7
+ trans_paths[ 8]='{8 ,9 , 668 }; // port 8
+ trans_paths[ 9]='{9 ,8 , 668 }; // port 9
+ trans_paths[10]='{10 ,7 , 668 }; // port 10
+ trans_paths[11]='{11 ,6 , 668 }; // port 11
+ trans_paths[12]='{12 ,5 , 668 }; // port 12
+ trans_paths[13]='{13 ,4 , 668 }; // port 13
+ trans_paths[14]='{14 ,3 , 668 }; // port 14
+ trans_paths[15]='{15 ,2 , 668 }; // port 15
+ trans_paths[16]='{16 ,1 , 668 }; // port 16
+ trans_paths[17]='{17 ,0 , 668 }; // port 17
+
+ portUnderTest = 18'b1111111111111111111;
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 150;
+ g_max_pck_gap = 150;
+ repeat_number = 20;
+ tries_number = 1;
+ g_force_payload_size = 42;
+ rx_forward_on_fmatch_full = 0;
+// mac_br = 1;
+ g_is_qvlan = 1;
+ // tx ,rx ,opt
+ end
+/*/
+ /** *************************** test scenario 70 ************************************* **/
+ /*
+ * stress test on all ports with Braodcast+FastForward
+ * BUG: s_rcv_pck goes into S_PAUSE -> WHY ??? (important, size: 200)
+ *
+ **/
+/*
+ initial begin
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[ 0] = '{'{32'h00000001, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
+ sim_vlan_tab[ 1] = '{'{32'h00000002, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
+ sim_vlan_tab[ 2] = '{'{32'h00000004, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b1 };
+ sim_vlan_tab[ 3] = '{'{32'h00000008, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b1 };
+ sim_vlan_tab[ 4] = '{'{32'h00000010, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b1 };
+ sim_vlan_tab[ 5] = '{'{32'h00000020, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b1 };
+ sim_vlan_tab[ 6] = '{'{32'h00000040, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b1 };
+ sim_vlan_tab[ 7] = '{'{32'h00000080, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b1 };
+ sim_vlan_tab[ 8] = '{'{32'h00000100, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b1 };
+ sim_vlan_tab[ 9] = '{'{32'h00000200, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b1 };
+ sim_vlan_tab[10] = '{'{32'h00000400, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 10, 1'b1 };
+ sim_vlan_tab[11] = '{'{32'h00000800, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 11, 1'b1 };
+ sim_vlan_tab[12] = '{'{32'h00001000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 12, 1'b1 };
+ sim_vlan_tab[13] = '{'{32'h00002000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 13, 1'b1 };
+ sim_vlan_tab[14] = '{'{32'h00004000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 14, 1'b1 };
+ sim_vlan_tab[15] = '{'{32'h00008000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 15, 1'b1 };
+ sim_vlan_tab[16] = '{'{32'h00010000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 16, 1'b1 };
+ sim_vlan_tab[17] = '{'{32'h00020000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 17, 1'b1 };
+ sim_vlan_tab[18] = '{'{32'h00040000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 18, 1'b1 };
+
+// tx ,rx ,opt (send from port tx to rx with option opt)
+ trans_paths[ 0]='{0 ,17 , 668 }; // port 0:
+ trans_paths[ 1]='{1 ,16 , 668 }; // port 1
+ trans_paths[ 2]='{2 ,15 , 668 }; // port 2
+ trans_paths[ 3]='{3 ,14 , 668 }; // port 3
+ trans_paths[ 4]='{4 ,13 , 668 }; // port 4
+ trans_paths[ 5]='{5 ,12 , 668 }; // port 5
+ trans_paths[ 6]='{6 ,11 , 668 }; // port 6
+ trans_paths[ 7]='{7 ,10 , 668 }; // port 7
+ trans_paths[ 8]='{8 ,9 , 668 }; // port 8
+ trans_paths[ 9]='{9 ,8 , 668 }; // port 9
+ trans_paths[10]='{10 ,7 , 668 }; // port 10
+ trans_paths[11]='{11 ,6 , 668 }; // port 11
+ trans_paths[12]='{12 ,5 , 668 }; // port 12
+ trans_paths[13]='{13 ,4 , 668 }; // port 13
+ trans_paths[14]='{14 ,3 , 668 }; // port 14
+ trans_paths[15]='{15 ,2 , 668 }; // port 15
+ trans_paths[16]='{16 ,1 , 668 }; // port 16
+ trans_paths[17]='{17 ,0 , 668 }; // port 17
+
+ portUnderTest = 18'b1111111111111111111;
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 150;
+ g_max_pck_gap = 150;
+ repeat_number = 20;
+ tries_number = 1;
+ g_force_payload_size = 200;//42;
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 0;
+ g_is_qvlan = 1;
+ // tx ,rx ,opt
+ end
+ */
+ /** *************************** test scenario 71 ************************************* **/
+ /*
+ * stress test on all ports with Braodcast+FastForward
- reg [15:0] portUnderTest = 16'b0000000011111111;
+ *
+ **/
+/*
+ initial begin
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[ 0] = '{'{32'h00000001, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
+ sim_vlan_tab[ 1] = '{'{32'h00000002, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
+ sim_vlan_tab[ 2] = '{'{32'h00000004, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b1 };
+ sim_vlan_tab[ 3] = '{'{32'h00000008, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b1 };
+ sim_vlan_tab[ 4] = '{'{32'h00000010, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b1 };
+ sim_vlan_tab[ 5] = '{'{32'h00000020, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b1 };
+ sim_vlan_tab[ 6] = '{'{32'h00000040, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b1 };
+ sim_vlan_tab[ 7] = '{'{32'h00000080, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b1 };
+ sim_vlan_tab[ 8] = '{'{32'h00000100, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b1 };
+ sim_vlan_tab[ 9] = '{'{32'h00000200, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b1 };
+ sim_vlan_tab[10] = '{'{32'h00000400, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 10, 1'b1 };
+ sim_vlan_tab[11] = '{'{32'h00000800, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 11, 1'b1 };
+ sim_vlan_tab[12] = '{'{32'h00001000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 12, 1'b1 };
+ sim_vlan_tab[13] = '{'{32'h00002000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 13, 1'b1 };
+ sim_vlan_tab[14] = '{'{32'h00004000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 14, 1'b1 };
+ sim_vlan_tab[15] = '{'{32'h00008000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 15, 1'b1 };
+ sim_vlan_tab[16] = '{'{32'h00010000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 16, 1'b1 };
+ sim_vlan_tab[17] = '{'{32'h00020000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 17, 1'b1 };
+ sim_vlan_tab[18] = '{'{32'h00040000, 8'h0, 3'h0, 1'b0, 1'b0, 1'b0}, 18, 1'b1 };
+
+// tx ,rx ,opt (send from port tx to rx with option opt)
+ trans_paths[ 0]='{0 ,17 , 668 }; // port 0:
+ trans_paths[ 1]='{1 ,16 , 668 }; // port 1
+ trans_paths[ 2]='{2 ,15 , 668 }; // port 2
+ trans_paths[ 3]='{3 ,14 , 668 }; // port 3
+ trans_paths[ 4]='{4 ,13 , 668 }; // port 4
+ trans_paths[ 5]='{5 ,12 , 668 }; // port 5
+ trans_paths[ 6]='{6 ,11 , 668 }; // port 6
+ trans_paths[ 7]='{7 ,10 , 668 }; // port 7
+ trans_paths[ 8]='{8 ,9 , 668 }; // port 8
+ trans_paths[ 9]='{9 ,8 , 668 }; // port 9
+ trans_paths[10]='{10 ,7 , 668 }; // port 10
+ trans_paths[11]='{11 ,6 , 668 }; // port 11
+ trans_paths[12]='{12 ,5 , 668 }; // port 12
+ trans_paths[13]='{13 ,4 , 668 }; // port 13
+ trans_paths[14]='{14 ,3 , 668 }; // port 14
+ trans_paths[15]='{15 ,2 , 668 }; // port 15
+ trans_paths[16]='{16 ,1 , 668 }; // port 16
+ trans_paths[17]='{17 ,0 , 668 }; // port 17
+
+// portUnderTest = 18'b1111111111111111111;
+ portUnderTest = 18'b111111111111111111;
+// portUnderTest = 18'b100000000000000001;
+// portUnderTest = 18'b000000000000000001;
+// portUnderTest = 18'b111000000000000111;
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 150;
+ g_max_pck_gap = 150;
+ repeat_number = 100; //10
+ tries_number = 1;
+ g_force_payload_size = 42; //250;//42;
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 0;
+ g_is_qvlan = 1;
+ g_simple_allocator_unicast_check = 1;
+ // tx ,rx ,opt
+ end
+*/
+ /** *************************** test scenario 71 ************************************* **/
+ /*
+ * alloc test for lost pages
+ *
+ **/
+/*
+ initial begin
+
+ portUnderTest = 18'b111111111111111111;
+// portUnderTest = 18'b000000000000000001;
+ g_enable_pck_gaps = 1;
+ g_min_pck_gap = 0;
+ g_max_pck_gap = 400;
+ repeat_number = 30; //10
+ tries_number = 1;
+ g_force_payload_size = 0;//300;//46;//42; //250;//42;
+ rx_forward_on_fmatch_full = 0;
+ mac_br = 0;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 1;
+ g_simple_allocator_unicast_check = 1;
+ // tx ,rx ,opt
+ end
+*/
+ /** *************************** test scenario 72 (bug) ************************************* **/
+ /*
+ * stress-test: broadcast on all ports
+ * two problems
+ * * swcore->input_block: when nomem receoption of dta from EP is PAUSEd -> not good, should be only
+ * for HP traffic, otherwise dump
+ * * problem on tx-> getting infinitely retry from EP
-/* -----\/----- EXCLUDED -----\/-----
- tbi_clock_rst_gen
- #(
- .g_rbclk_period(8002))
- clkgen(
- .clk_sys_o(clk_sys),
- .clk_ref_o(clk_ref),
- .rst_n_o(rst_n)
- );
- -----/\----- EXCLUDED -----/\----- */
-
- always #2.5ns clk_swc_mpm_core <=~clk_swc_mpm_core;
- //always #5ns clk_swc_mpm_core <=~clk_swc_mpm_core;
+ *
+ **/
+/*
+ initial begin
+
+ // tx ,rx ,opt
+ trans_paths[0] = '{0 ,17 ,1};
+ trans_paths[1] = '{1 ,16 ,1};
+ trans_paths[2] = '{2 ,15 ,1};
+ trans_paths[3] = '{3 ,14 ,1};
+ trans_paths[4] = '{4 ,13 ,1};
+ trans_paths[5] = '{5 ,12 ,1};
+ trans_paths[6] = '{6 ,11 ,1};
+ trans_paths[7] = '{7 ,10 ,1};
+ trans_paths[8] = '{8 ,9 ,1};
+ trans_paths[9] = '{9 ,8 ,1};
+ trans_paths[10] = '{10 ,7 ,1};
+ trans_paths[11] = '{11 ,6 ,1};
+ trans_paths[12] = '{12 ,5 ,1};
+ trans_paths[13] = '{13 ,4 ,1};
+ trans_paths[14] = '{14 ,3 ,1};
+ trans_paths[15] = '{15 ,2 ,1};
+ trans_paths[16] = '{16 ,1 ,1};
+ trans_paths[17] = '{17 ,0 ,1};
+
+ portUnderTest = 18'b111111111111111111;
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 0;
+ g_max_pck_gap = 400;
+ repeat_number = 60; //10
+ tries_number = 1;
+ g_force_payload_size = 207; //1500;//300;//46;//42; //250;//42;
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 1;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 1;
+ g_simple_allocator_unicast_check = 1;
+ // tx ,rx ,opt
+ end
+ */
+ /** *************************** test scenario 73 ************************************* **/
+ /*
+ * simple
+ *
+ **/
+/*
+ initial begin
+
+
+ portUnderTest = 18'b100000000000000001;
+ trans_paths[ 0]='{0 ,17 , 0 }; // port 0:
+ trans_paths[17]='{17 ,0 , 0 }; // port 17
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 100;
+ g_max_pck_gap = 400;
+ repeat_number = 30; //10
+ tries_number = 1;
+ g_force_payload_size = 0;//300;//46;//42; //250;//42;
+ rx_forward_on_fmatch_full = 0;
+ mac_br = 0;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 0;
+ g_simple_allocator_unicast_check = 1;
+
+ // tx ,rx ,opt
+ end
+*/
+
+ /** *************************** test scenario 74 ************************************* **/
+ /*
+ * snake !!!!!!!!!!!!! (need to uncomment/commeent)
+ *
+ **/
+/*
+ initial begin
+
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[ 0] = '{'{32'hFFFFFFFF, 8'h0 , 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
+ sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
+ sim_vlan_tab[ 2] = '{'{32'h0000000C, 8'h2 , 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b1 };
+ sim_vlan_tab[ 3] = '{'{32'h00000030, 8'h3 , 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b1 };
+ sim_vlan_tab[ 4] = '{'{32'h000000C0, 8'h4 , 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b1 };
+ sim_vlan_tab[ 5] = '{'{32'h00000300, 8'h5 , 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b1 };
+ sim_vlan_tab[ 6] = '{'{32'h00000C00, 8'h6 , 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b1 };
+ sim_vlan_tab[ 7] = '{'{32'h00003000, 8'h7 , 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b1 };
+ sim_vlan_tab[ 8] = '{'{32'h0000C000, 8'h8 , 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b1 };
+ sim_vlan_tab[ 9] = '{'{32'h00030000, 8'h9 , 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b1 };
+ sim_vlan_tab[10] = '{'{32'h000C0000, 8'h10, 3'h0, 1'b0, 1'b0, 1'b0}, 10, 1'b1 };
+ sim_vlan_tab[11] = '{'{32'h00300000, 8'h11, 3'h0, 1'b0, 1'b0, 1'b0}, 11, 1'b1 };
+ sim_vlan_tab[12] = '{'{32'h00C00000, 8'h12, 3'h0, 1'b0, 1'b0, 1'b0}, 12, 1'b1 };
+ sim_vlan_tab[13] = '{'{32'h03000000, 8'h13, 3'h0, 1'b0, 1'b0, 1'b0}, 13, 1'b1 };
+ sim_vlan_tab[14] = '{'{32'h0C000000, 8'h14, 3'h0, 1'b0, 1'b0, 1'b0}, 14, 1'b1 };
+ sim_vlan_tab[15] = '{'{32'h30000000, 8'h15, 3'h0, 1'b0, 1'b0, 1'b0}, 15, 1'b1 };
+ sim_vlan_tab[16] = '{'{32'hC0000000, 8'h16, 3'h0, 1'b0, 1'b0, 1'b0}, 16, 1'b1 };
+ sim_vlan_tab[17] = '{'{32'h00000000, 8'h17, 3'h0, 1'b0, 1'b0, 1'b0}, 17, 1'b0 };
+ sim_vlan_tab[18] = '{'{32'h00000000, 8'h18, 3'h0, 1'b0, 1'b0, 1'b0}, 18, 1'b0 };
+
+ portUnderTest = 18'b100000000000000001;
+ // tx ,rx ,opt
+ trans_paths[ 0]='{0 ,17 , 1 }; // port 0:
+ trans_paths[17]='{17 ,0 , 1 }; // port 17
+
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 0;
+ g_max_pck_gap = 400;
+ repeat_number = 100;//2700; //10
+ tries_number = 1;
+ g_force_payload_size = 207;//47;// 0;//300;//46;//42; //250;//42;
+// g_force_payload_size = 482;// should be 500 in spirent
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 1;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 0;
+ g_simple_allocator_unicast_check = 1;
+
+ g_do_vlan_config = 2; // snake EP configuration (tagging proper VLANs on ports
+
+ g_set_untagging = 2; // untagging
+ end
+*/
+ /** *************************** test scenario 75 ************************************* **/
+ /*
+ * stress
+ *
+ **/
+/*
+ initial begin
+
+
+ portUnderTest = 18'b100000000000000001;
+ trans_paths[ 0]='{0 ,17 , 1 }; // port 0:
+ trans_paths[17]='{17 ,0 , 1 }; // port 17
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 100;
+ g_max_pck_gap = 400;
+ repeat_number = 300; //10
+ tries_number = 1;
+ g_force_payload_size = 47;//300;//46;//42; //250;//42;
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 0;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 0;
+ g_simple_allocator_unicast_check = 1;
+
+ // tx ,rx ,opt
+ end
+*/
+ /** *************************** test scenario 76 ************************************* **/
+ /*
+ * ptpd problems - solved ;-p
+ *
+ **/
+/*
+ initial begin
+
+
+ portUnderTest = 18'b100000000000000001;
+ trans_paths[ 0]='{0 ,17 , 1 }; // port 0:
+ trans_paths[17]='{17 ,0 , 1 }; // port 17
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 0;
+ g_max_pck_gap = 400;
+ repeat_number = 100; //10
+ tries_number = 1;
+ g_force_payload_size = 0;//47;//300;//46;//42; //250;//42;
+ rx_forward_on_fmatch_full = 1;
+ g_payload_range_min = 63;
+ g_payload_range_max = 500;
+ mac_br = 0;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 0;
+ g_simple_allocator_unicast_check = 1;
+ g_set_untagging = 3; // untagging
+ // tx ,rx ,opt
+ end
+*/
+ /** *************************** test scenario 77 ************************************* **/
+ /*
+ * page-edge-crossing problem
+ *
+ **/
+/*
+ initial begin
+
+
+ portUnderTest = 18'b100000000000000001;
+ trans_paths[ 0]='{0 ,17 , 0 }; // port 0:
+ trans_paths[17]='{17 ,0 , 0 }; // port 17
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 0;
+ g_max_pck_gap = 400;
+ repeat_number = 100; //10
+ tries_number = 1;
+
+ // 2xpage = 2x64
+ // payload = { 2x(2x64) [bytes in pages] - 14 [header] - 4 [crc]} [bytes]
+ // payload = 238 bytes ->page breaker :238/239
+ g_force_payload_size = 239;//47;//300;//46;//42; //250;//42;
+ rx_forward_on_fmatch_full = 1;
+
+ mac_br = 0;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 0;
+ g_simple_allocator_unicast_check = 1;
+ g_set_untagging = 3; // untagging
+ // tx ,rx ,opt
+ end
+*/
+ /** *************************** test scenario 78 ************************************* **/
+ /*
+ * snake !!!!!!!!!!!!! (need to uncomment/commeent)
+ *
+ **/
+/*
+ initial begin
+
+ // mask , fid , prio,has_p,overr, drop , vid, valid
+ sim_vlan_tab[ 0] = '{'{32'hFFFFFFFF, 8'h0 , 3'h0, 1'b0, 1'b0, 1'b0}, 0, 1'b1 };
+ sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
+ sim_vlan_tab[ 2] = '{'{32'h0000000C, 8'h2 , 3'h0, 1'b0, 1'b0, 1'b0}, 2, 1'b1 };
+ sim_vlan_tab[ 3] = '{'{32'h00000030, 8'h3 , 3'h0, 1'b0, 1'b0, 1'b0}, 3, 1'b1 };
+ sim_vlan_tab[ 4] = '{'{32'h000000C0, 8'h4 , 3'h0, 1'b0, 1'b0, 1'b0}, 4, 1'b1 };
+ sim_vlan_tab[ 5] = '{'{32'h00000300, 8'h5 , 3'h0, 1'b0, 1'b0, 1'b0}, 5, 1'b1 };
+ sim_vlan_tab[ 6] = '{'{32'h00000C00, 8'h6 , 3'h0, 1'b0, 1'b0, 1'b0}, 6, 1'b1 };
+ sim_vlan_tab[ 7] = '{'{32'h00003000, 8'h7 , 3'h0, 1'b0, 1'b0, 1'b0}, 7, 1'b1 };
+ sim_vlan_tab[ 8] = '{'{32'h0000C000, 8'h8 , 3'h0, 1'b0, 1'b0, 1'b0}, 8, 1'b1 };
+ sim_vlan_tab[ 9] = '{'{32'h00030000, 8'h9 , 3'h0, 1'b0, 1'b0, 1'b0}, 9, 1'b1 };
+ sim_vlan_tab[10] = '{'{32'h000C0000, 8'h10, 3'h0, 1'b0, 1'b0, 1'b0}, 10, 1'b1 };
+ sim_vlan_tab[11] = '{'{32'h00300000, 8'h11, 3'h0, 1'b0, 1'b0, 1'b0}, 11, 1'b1 };
+ sim_vlan_tab[12] = '{'{32'h00C00000, 8'h12, 3'h0, 1'b0, 1'b0, 1'b0}, 12, 1'b1 };
+ sim_vlan_tab[13] = '{'{32'h03000000, 8'h13, 3'h0, 1'b0, 1'b0, 1'b0}, 13, 1'b1 };
+ sim_vlan_tab[14] = '{'{32'h0C000000, 8'h14, 3'h0, 1'b0, 1'b0, 1'b0}, 14, 1'b1 };
+ sim_vlan_tab[15] = '{'{32'h30000000, 8'h15, 3'h0, 1'b0, 1'b0, 1'b0}, 15, 1'b1 };
+ sim_vlan_tab[16] = '{'{32'hC0000000, 8'h16, 3'h0, 1'b0, 1'b0, 1'b0}, 16, 1'b1 };
+ sim_vlan_tab[17] = '{'{32'h00000000, 8'h17, 3'h0, 1'b0, 1'b0, 1'b0}, 17, 1'b0 };
+ sim_vlan_tab[18] = '{'{32'h00000000, 8'h18, 3'h0, 1'b0, 1'b0, 1'b0}, 18, 1'b0 };
+
+ portUnderTest = 18'b100000000000000001;
+ // tx ,rx ,opt
+ trans_paths[ 0]='{0 ,17 , 1 }; // port 0:
+ trans_paths[17]='{17 ,0 , 1 }; // port 17
+
+ g_enable_pck_gaps = 0;
+ g_min_pck_gap = 0;
+ g_max_pck_gap = 400;
+ repeat_number = 10000;//2700; //10
+ tries_number = 1;
+ g_force_payload_size = 225-18; // header = 14 bytes | CRC = 4 bytes
+
+// g_force_payload_size = 207;//47;// 0;//300;//46;//42; //250;//42;
+// g_force_payload_size = 482;// should be 500 in spirent
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 1;
+ g_is_qvlan = 0;
+ g_ignore_rx_test_check = 0;
+ g_simple_allocator_unicast_check = 1;
+
+ g_do_vlan_config = 2; // snake EP configuration (tagging proper VLANs on ports
+
+ g_set_untagging = 2; // untagging
+ end
+*/
+ /** *************************** test scenario 79 ********************** **/ /*
+
+ */
+///*
+ initial begin
+ portUnderTest = 18'b101000000000000101; // we send pcks (Markers) in other place
+ // tx ,rx ,opt
+ trans_paths[ 0] ='{0 ,17 , 0 }; // port 0:
+ trans_paths[17] ='{17 ,0 , 0 }; // port 17
+// trans_paths[ 2] ='{2 ,15 , 0 }; // port 2:
+// trans_paths[15] ='{15 ,2 , 0 }; // port 15
+ repeat_number = 50;
+ tries_number = 1;
+ g_enable_pck_gaps = 0;
+ g_force_payload_size = 46;// 225-18;
+ g_injection_templates_programmed = 2;
+ g_limit_config_to_port_num = 4; //to speed up the config, don't configure VLANS and stuff
+ // in ports above nubmer 7
+ //g_test_inj_gen = 1; // inject test-frame scenario
+ g_test_inj_gen = 2; // inject test-frames + enable corruption + disable corrutption
+ inj_gen_frame_size = 64;
+ inj_gen_mode = 1;//0:default | 1: corrupt frames
+ inj_gen_if_gap_size = 100;
+ g_ignore_rx_test_check =1;
+ rx_forward_on_fmatch_full = 1;
+ mac_br = 0;
+ g_is_qvlan = 0;
+ end
+//*/
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+
+ always #2.66ns clk_swc_mpm_core <=~clk_swc_mpm_core;
+// always #4ns clk_swc_mpm_core <=~clk_swc_mpm_core;
always #8ns clk_sys <= ~clk_sys;
always #8ns clk_ref <= ~clk_ref;
-// always #8ns clk_sys <= ~clk_sys;
-// always #8ns clk_ref <= ~clk_ref;
+ initial begin
+ repeat(100) @(posedge clk_sys);
+ rst_n <= 1;
+ end
+/*
+ * wait ncycles
+ */
+ task automatic wait_cycles;
+ input [31:0] ncycles;
+ begin : wait_body
+ integer i;
+
+ for(i=0;i<ncycles;i=i+1) @(posedge clk_sys);
+
+ end
+ endtask // wait_cycles
+
+ task automatic tx_test(ref int seed, input int n_tries, input int is_q,input int unvid, ref EthPacketSource src, ref EthPacketSink sink, input int srcPort, input int dstPort, input int opt=0);
+ EthPacketGenerator gen = new;
+ EthPacket pkt, tmpl, pkt2;
+ EthPacket arr[];
+ integer pck_gap = 0;
+ integer dmac_dist = 0;
+ //int i,j;
+
+ if(g_enable_pck_gaps == 1)
+ if(g_min_pck_gap == g_max_pck_gap)
+ pck_gap = g_min_pck_gap;
+ else
+ pck_gap = $dist_uniform(seed,g_min_pck_gap,g_max_pck_gap);
+
+ arr = new[n_tries](arr);
+ if(opt !=3 && opt != 4)
+ gen.set_seed(seed);
+
+ tmpl = new;
+
+ if(opt == 0 || opt == 200 || opt == 201 || opt == 666 || opt == 667 || opt == 1000)
+ tmpl.src = '{srcPort, 2,3,4,5,6};
+ else if(opt == 101 | opt == 102)
+ tmpl.src = '{0,0,0,0,0,0};
+ else if(opt > 2 )
+ tmpl.src = '{0,2,3,4,5,6};
+ else
+ tmpl.src = '{srcPort, 2,3,4,5,6};
+
+ if(opt==0 || opt == 200 || opt == 202 || opt == 1000 )
+ tmpl.dst = '{dstPort, 'h50, 'hca, 'hfe, 'hba, 'hbe};
+ else if(opt==1)
+ tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF};
+ else if(opt==2 || opt==101)
+ tmpl.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h00}; //BPDU
+ else if(opt==3)
+ tmpl.dst = '{17, 'h50, 'hca, 'hfe, 'hba, 'hbe};
+ else if(opt==4 || opt==10 || opt==13 || opt==201 || opt == 203 || opt == 204 || opt == 205 || opt == 206 || opt == 207 || opt == 444 || opt==666|| opt==667 || opt==668)
+ tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}; // broadcast
+ else if(opt==5)
+ tmpl.dst = '{'h11, 'h50, 'hca, 'hfe, 'hba, 'hbe}; // single Fast Forward
+ else if(opt==6)
+ tmpl.dst = '{'h11, 'h11, 'h11, 'h11, 'h11, 'h11}; // single Fast Forward
+ else if(opt==7)
+ tmpl.dst = '{'h04, 'h50, 'hca, 'hfe, 'hba, 'hbe}; // in the middle of the range
+ else if(opt==8)
+ tmpl.dst = '{'h01, 'h1b, 'h19, 'h00, 'h00, 'h00}; // PTP
+ else if(opt==9 || opt==900 || opt == 901)
+ tmpl.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h01}; // PAUSE
+ else if(opt==11)
+ tmpl.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h0F}; // Marker (fast forward + CPU forward)
+ else if(opt==12)
+ tmpl.dst = '{'h01, 'h23, 'h45, 'h67, 'h89, 'h0AB}; // Unknown MAC
+ else
+ tmpl.dst = '{'h00, 'h00, 'h00, 'h00, 'h00, 'h00}; // link-limited
+
+
+
+ tmpl.has_smac = 1;
+ if(opt == 204)
+ tmpl.pcp = 3; //priority
+ else if(opt == 207)
+ tmpl.pcp = 6; //priority
+ else
+ tmpl.pcp = 0; //priority
+
+ if(opt==900 || opt == 901)
+ tmpl.is_q = 0;
+ else
+ tmpl.is_q = is_q;
+
+
+ if(opt==13)
+ tmpl.vid = 3;
+ else if(opt==10 )
+ tmpl.vid = 1;
+ else
+ tmpl.vid = 0;
+ if(opt==900 || opt == 901)
+ tmpl.ethertype = 'h8808;
+ else if(opt == 100 || opt == 101 || opt == 102)
+ tmpl.ethertype = 'hbabe;
+ else
+ tmpl.ethertype = 'h88f7;
+ //
+ gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::SEQ_ID);
+ gen.set_template(tmpl);
+ if(g_force_payload_size < 42)
+ begin
+ if(opt == 101 || opt == 102 || opt == 900 || opt == 901)
+ gen.set_size(64, 65);
+ else if(opt == 201 || opt == 202 || opt == 203 || opt == 204)
+ gen.set_size(63, 1001);
+ else if(opt == 200)
+ gen.set_size(1000, 1001);
+ else
+ gen.set_size(g_payload_range_min, g_payload_range_max);
+// gen.set_size(63, 257);
+ end
+ else
+ gen.set_size(g_force_payload_size, g_force_payload_size+1); // setting the precise size below
+
+ fork
+ begin // fork 1
+ integer vid_cnt=0;
+ for(int i=0;i<n_tries;i++)
+ begin
+
+ pkt = gen.gen();
+
+ if(g_force_payload_size >= 42) // min size of frame is 64,
+ if(opt == 1000)
+ pkt.set_size(g_force_payload_size + i%2);
+ else
+ pkt.set_size(g_force_payload_size);
+
+ pkt.oob = TX_FID;
+ $display("|=> TX: port = %2d, pck_i = %4d (opt=%1d, pck_gap=%3d, size=%2d, n=%d)" , srcPort, i,opt,pck_gap, pkt.payload.size, i);
+ if(opt == 100)
+ begin
+ pkt.payload[14] = 'h00;
+ pkt.payload[15] = 'h01;
+ end
+ else if(opt == 101)
+ begin
+ pkt.payload[0] = 'hba;
+ pkt.payload[1] = 'hbe;
+ end
+ else if(opt == 900) // "normal pause
+ begin
+ pkt.payload[0] = 'h00;
+ pkt.payload[1] = 'h01;
+ pkt.payload[2] = 'h00;
+ pkt.payload[3] = 'h01;
+ end
+ else if(opt == 901) // "per-prio pause
+ begin
+ pkt.payload[0] = 'h01;
+ pkt.payload[1] = 'h01;
+
+ // prio vector
+ pkt.payload[2] = 'h00;
+ pkt.payload[3] = 'h81;
+
+ //Quanta of prio 0
+ pkt.payload[4] = 'h00;
+ pkt.payload[5] = 'h0A;
+
+ //Quanta of prio 7
+ pkt.payload[18]= 'h00;
+ pkt.payload[19]= 'h14;
+ end
+
+ if(opt == 444)
+ pkt.src[4] = dmac_dist++;
+
+ if(opt == 205 || opt == 206)
+ pkt.pcp = i%8;
+
+ if(opt == 666)
+ pkt.vid = vid_init_for_inc+srcPort;
+ else if(opt== 667)
+ pkt.vid = (vid_init_for_inc+srcPort+i)%18;
+ else if(opt == 668)
+ pkt.vid = vid_init_for_inc+dstPort;
+ src.send(pkt);
+ arr[i] = pkt;
+// repeat(60) @(posedge clk_sys);
+// repeat(6) @(posedge clk_sys); //minimum interframe gap : 96 bits = 12 bytes = 6 words
+// repeat(2) @(posedge clk_sys); //it seems that in reality it's less
+// wait_cycles(pck_gap);
+ if(pck_gap)
+ wait_cycles(pck_gap);
+ end
+ tx_done = 1;
+ end // fork 1
+ begin // fork 2
+ if(opt != 101 && opt != 201 && opt != 900 && opt != 901 && opt != 206 && opt != 666 && opt != 667 && g_ignore_rx_test_check == 0)
+ for(int j=0;j<n_tries;j++)
+ begin
+ sink.recv(pkt2);
+ $display("|<= RX: port = %2d, pck_i = %4d (size=%2d)" , dstPort, j, pkt2.payload.size);
+ if(unvid)
+ arr[j].is_q = 0;
+ if((arr[j].payload.size != pkt2.payload.size) || !arr[j].equal(pkt2))
+ begin
+ $display("Fault at %d", j);
+ $display("Should be: ");
+ arr[j].dump();
+ $display("Is: ");
+ pkt2.dump();
+ end
+ end // for (i=0;i<n_tries;i++)
+ rx_done = 1;
+ end // fork 2
+ join
+ seed = gen.get_seed();
+
+ endtask // tx_test
- initial begin
- repeat(100) @(posedge clk_sys);
- rst_n <= 1;
- end
-/*
- * wait ncycles
- */
- task automatic wait_cycles;
- input [31:0] ncycles;
- begin : wait_body
- integer i;
-
- for(i=0;i<ncycles;i=i+1) @(posedge clk_sys);
-
- end
- endtask // wait_cycles
-
-// assign clk_ref = clk_sys;
-
- task automatic tx_test(ref int seed, input int n_tries, input int is_q,input int unvid, ref EthPacketSource src, ref EthPacketSink sink, input int srcPort, input int dstPort);
+ task automatic tx_distrib_test(ref int seed, input int n_tries, input int is_q, input int unvid, ref port_t p[$], input t_sim_port_distr portDist, input int opt=0);
+ /*
+ * options:
+ * 0: high priority, distribution/class in the first word
+ * 1: boradcast, distribution by looking at src MAC, bits 6 & 7
+ * 2: unicast, distribution by looking at dst MAC, bits 6 & 7
+ **/
EthPacketGenerator gen = new;
- EthPacket pkt, tmpl, pkt2;
- EthPacket arr[];
+ EthPacket pkt, tmpl;
+ EthPacket arr[4][];
+ int n_dist_tries[];
+
+ integer pck_gap = 0;
//int i,j;
- arr = new[n_tries](arr);
+ if(g_enable_pck_gaps == 1)
+ if(g_min_pck_gap == g_max_pck_gap)
+ pck_gap = g_min_pck_gap;
+ else
+ pck_gap = $dist_uniform(seed,g_min_pck_gap,g_max_pck_gap);
- gen.set_seed(seed);
+ arr[0] = new[n_tries](arr[0]);
+ arr[1] = new[n_tries](arr[1]);
+ arr[2] = new[n_tries](arr[2]);
+ arr[3] = new[n_tries](arr[3]);
+
+ if(opt !=3 && opt != 4)
+ gen.set_seed(seed);
tmpl = new;
- tmpl.src = '{srcPort, 2,3,4,5,6};
- tmpl.dst = '{dstPort, 'h50, 'hca, 'hfe, 'hba, 'hbe};
+
+ tmpl.src = '{1,2,3,4,5,6};
+ if(opt == 2)
+ tmpl.dst = '{1,2,3,4,5,6};
+ else
+ tmpl.dst = '{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF};
+
tmpl.has_smac = 1;
tmpl.is_q = is_q;
- tmpl.vid = 100;
- tmpl.ethertype = 'h88f7;
- //
+ tmpl.vid = 0;
+ tmpl.pcp = 7;
+ if(opt == 1)
+ tmpl.pcp = 5;
+ else
+ tmpl.pcp = 7;
+ tmpl.ethertype = 'hbabe;
+
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::SEQ_ID);
gen.set_template(tmpl);
gen.set_size(63, 257);
fork
- begin
- for(int i=0;i<n_tries;i++)
+ begin // fork 1
+ for(int i=0;i<n_tries;i++)
begin
+ automatic int srcPort, dstID, dstPort;
+
pkt = gen.gen();
pkt.oob = TX_FID;
+ dstID = (i % portDist.distPortN);
+ dstPort = portDist.distr[dstID];
+ srcPort = portDist.srcPort;
+ $display("|=> TX: srcPort = %2d,dstPort = %2d [dstId=%2d], pck_i = %2d (opt=%1d, pck_gap=%3d)",
+ srcPort, dstPort, dstID, i,opt,pck_gap);
- $display("[port %d] tx %d", srcPort, i);
-
- src.send(pkt);
- arr[i] = pkt;
- //pkt.dump();
- // repeat(3000) @(posedge clk_sys);
+ if(opt == 1)
+ pkt.src[4] = dstID;
+ else if(opt == 2)
+ pkt.dst[4] = dstID;
+ else
+ begin
+ pkt.payload[0] = 'h00;
+ pkt.payload[1] = 'h00FF & dstID;
+ end
- // $display("Send: %d [dsize %d]", i+1,pkt.payload.size() + 14);
-
- end
- end
- begin
- for(int j=0;j<n_tries;j++)
- begin
- sink.recv(pkt2);
- $display("rx %d", j);
- //pkt2.dump();
- if(unvid)
- arr[j].is_q = 0;
-
- if(!arr[j].equal(pkt2))
- begin
- $display("Fault at %d", j);
- $display("Should be: ");
- arr[j].dump();
- $display("Is: ");
- pkt2.dump();
- //$fatal("dupa"); //ML
- //sfp $stop;
- end
- end // for (i=0;i<n_tries;i++)
+ p[srcPort].send.send(pkt);
+ arr[dstID][ n_dist_tries[dstID]]=pkt;
+// n_dist_tries[dstPort]++;
+ if(opt != 5)
+ fork
+ begin
+ automatic EthPacket pkt2;
+ automatic int rxDstID = dstID;
+ automatic int j = n_dist_tries[dstID];
+ p[portDist.distr[rxDstID]].recv.recv(pkt2);
+ $display("|<= RX: port = %2d [dstID=%2d], pck_i = %4d" , portDist.distr[rxDstID], rxDstID, j);
+ if(unvid)
+ arr[rxDstID][j].is_q = 0;
+ if(!arr[rxDstID][j].equal(pkt2))
+ begin
+ $display("Fault at %d", j);
+ $display("Should be: ");
+ arr[rxDstID][j].dump();
+ $display("Is: ");
+ pkt2.dump();
+ end
+ end // fork
+ join
+ n_dist_tries[dstID]++;
+ repeat(60) @(posedge clk_sys);
+// repeat(6) @(posedge clk_sys);
+// wait_cycles(pck_gap);
end
- join
+ end // fork 1
+// begin // fork 2
+// for(int j=0;j<n_tries/portDist.distPortN;j++)
+// begin
+// automatic EthPacket pkt2;
+// automatic int dstID = 0;
+// p[portDist.distr[dstID]].recv.recv(pkt2);
+// $display("|<= RX: port = %2d [dstID=%2d], pck_i = %4d" , portDist.distr[dstID], dstID, j);
+// if(unvid)
+// arr[dstID][j].is_q = 0;
+// if(!arr[dstID][j].equal(pkt2))
+// begin
+// $display("Fault at %d", j);
+// $display("Should be: ");
+// arr[dstID][j].dump();
+// $display("Is: ");
+// pkt2.dump();
+// end
+//
+// end // for (i=0;i<n_tries;i++)
+// end // fork 2
+
+ join
seed = gen.get_seed();
+
+ endtask // tx_distrib_test
- if(g_enable_pck_gaps == 1)
- wait_cycles($dist_uniform(seed,g_min_pck_gap,g_max_pck_gap));
+ task automatic tx_special_pck(ref EthPacketSource src, input tx_special_pck_t opt=PAUSE,input integer user_value=0);
+ EthPacket pkt;
+
+ int i;
+ pkt = new(64);
+ case(opt)
+ PAUSE:
+ begin
+ pkt.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h01};
+ pkt.ethertype = 'h8808;
+ for(i=14;i<64;i++)
+ pkt.payload[i-14]=PAUSE_templ[i];
+ pkt.payload[2]= user_value>>8;
+ pkt.payload[3]= user_value;
+ end
+ BPDU_0:
+ begin
+ pkt.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h00};
+ pkt.ethertype = 'h2607;
+ for(i=14;i<64;i++)
+ pkt.payload[i-14]=BPDU_templ[i];
+ pkt.payload[6]= user_value>>8;
+ pkt.payload[7]= user_value;
+ end
+ MARKER:
+ begin
+ pkt.dst = '{'h01, 'h80, 'hC2, 'h00, 'h00, 'h02};
+ pkt.ethertype = 'h8809;
+ for(i=14;i<64;i++)
+ pkt.payload[i-14]=MARKER_templ[i];
+ pkt.payload[2]= user_value;
+ end
+ endcase;
+
+ pkt.has_smac = 0;
+ pkt.is_q = 0;
+ pkt.vid = 0;
+ pkt.oob = TX_FID;
+ src.send(pkt);
+ repeat(60) @(posedge clk_sys);
- endtask // tx_test
+ endtask // tx_special_pck
- scb_top_sim_svwrap
- #(
- .g_num_ports(g_num_ports)
- ) DUT (
+
+// `ifdef `snake_test
+// scb_snake_sim_svwrap
+// #(
+// .g_num_ports(g_num_ports)
+// ) DUT (
+// .clk_sys_i(clk_sys),
+// .clk_ref_i(clk_ref),
+// .rst_n_i(rst_n),
+// .cpu_irq(cpu_irq),
+// .clk_swc_mpm_core_i(clk_swc_mpm_core),
+// .ep_ctrl_i(ep_ctrl),
+// .ep_failure_type(ep_failure_type)
+// );
+// `else
+ scb_top_sim_svwrap
+ #(
+ .g_num_ports(g_num_ports)
+ ) DUT (
.clk_sys_i(clk_sys),
.clk_ref_i(clk_ref),
.rst_n_i(rst_n),
.cpu_irq(cpu_irq),
- .clk_swc_mpm_core_i(clk_swc_mpm_core)
+ .clk_swc_mpm_core_i(clk_swc_mpm_core),
+ .ep_ctrl_i(ep_ctrl),
+ .ep_failure_type(ep_failure_type)
);
+// `endif
+
- typedef struct {
- CSimDrv_WR_Endpoint ep;
- EthPacketSource send;
- EthPacketSink recv;
- } port_t;
-
- port_t ports[$];
- CSimDrv_NIC nic;
- CRTUSimDriver rtu;
- CSimDrv_TXTSU txtsu;
-
task automatic init_ports(ref port_t p[$], ref CWishboneAccessor wb);
- int i;
-
+ int i,j;
+
for(i=0;i<g_num_ports;i++)
begin
port_t tmp;
CSimDrv_WR_Endpoint ep;
ep = new(wb, 'h30000 + i * 'h400);
ep.init(i);
+ if(g_do_vlan_config == 2 & i < g_limit_config_to_port_num )
+ ep.vlan_config(ep_vlan_conf[i].qmode, ep_vlan_conf[i].fix_prio, ep_vlan_conf[i].prio_val, ep_vlan_conf[i].pvid, prio_map);
+ else if(g_do_vlan_config == 1 & i < g_limit_config_to_port_num )
+ ep.vlan_config(qmode, fix_prio, prio_val, pvid, prio_map);
+ else
+ ep.vlan_config(2, 0, 0, 0, '{0,1,2,3,4,5,6,7});//default
+
+ if(g_pfilter_enabled == 1 & i < g_limit_config_to_port_num )
+ begin
+ ep.pfilter_load_microcode(mc.assemble());
+ ep.pfilter_enable(1);
+ end
+ if(g_injection_templates_programmed == 1 & i < g_limit_config_to_port_num)
+ begin
+ ep.write_template(0, PAUSE_templ, 16);
+ ep.write_template(1, BPDU_templ, 20);
+ end
+ else if(g_injection_templates_programmed == 2 & i < g_limit_config_to_port_num)
+ begin
+ ep.inject_gen_ctrl_config(inj_gen_if_gap_size /*interframe gap*/,0 /*template sel id*/, inj_gen_mode /*mode of injection*/);
+ ep.write_inj_gen_frame(TEST_GEN_templ /*header template*/,inj_gen_frame_size /*frame gap*/);
+// ep.inject_gen_ctrl_enable();
+ end
+ if(g_pause_mode == 1)
+ ep.pause_config( 1/*txpause_802_3*/, 1/*rxpause_802_3*/, 0/*txpause_802_1q*/, 0/*rxpause_802_1q*/);
+ else if(g_pause_mode == 2)
+ ep.pause_config( 1/*txpause_802_3*/, 1/*rxpause_802_3*/, 1/*txpause_802_1q*/, 1/*rxpause_802_1q*/);
+
+ if(g_set_untagging == 1)
+ begin
+ for(j=0;j<g_limit_config_to_port_num; j++)
+ ep.vlan_egress_untag(j /*vlan*/ ,1);
+ end
+ else if(g_set_untagging == 2)
+ begin
+ for(j=0;j<g_limit_config_to_port_num; j++)
+ ep.vlan_egress_untag(ep_vlan_conf[j].pvid /*vlan*/ ,1);
+ end
+ else if(g_set_untagging == 3)
+ begin
+ ep.vlan_egress_untag_direct('hFFFF /*vlan*/ ,0);
+ ep.vlan_egress_untag_direct('hFFFF /*vlan*/ ,1);
+ end
tmp.ep = ep;
tmp.send = EthPacketSource'(DUT.to_port[i]);
tmp.recv = EthPacketSink'(DUT.from_port[i]);
@@ -200,24 +3226,356 @@ module main;
endtask // init_nic
+ task automatic init_tru(input CSimDrv_WR_TRU tru_drv);
+
+ $display(">>>>>>>>>>>>>>>>>>> TRU initialization <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tru_drv.pattern_config(1 /*replacement*/, 0 /*addition*/, 0 /*subtraction*/);
+
+ /*define distribution functions for hp, broadcast, unicast straffic*/
+ tru_drv.lacp_config(lacp_df_hp_id,lacp_df_br_id,lacp_df_un_id);
+
+ tru_drv.hw_frame_config(1/*tx_fwd_id*/, 1/*rx_fwd_id*/, 1/*tx_blk_id*/, 2 /*rx_blk_id*/);
+// tru_drv.rt_reconf_config(4 /*tx_frame_id*/, 4/*rx_frame_id*/, 1 /*mode*/);
+// tru_drv.rt_reconf_enable();
+
+ /*
+ * transition
+ **/
+// tru_drv.transition_config(0 /*mode */, 4 /*rx_id*/, 1, /*prio mode*/, 0 /*prio*/, 20 /*time_diff*/,
+// 3 /*port_a_id*/, 4 /*port_b_id*/);
+
+
+
+ /*
+ * | port | ingress | egress |
+ * |--------------------------|
+ * | 0 | 1 | 1 |
+ * | 1 | 0 | 1 |
+ * | 2 | 1 | 1 |
+ * | 3 | 1 | 1 |
+ * | 4 | 1 | 1 |
+ * | 5 | 0 | 1 |
+ * |--------------------------|
+ *
+ * 5 -> 1 -> 0
+ * ----------------
+ * port 1 is backup for 0
+ * port 5 is backup ofr 1
+ *
+ **/
+ // initial clean
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 4 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 5 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 6 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 7 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+
+ if(tru_config_opt == 1 || tru_config_opt == 4)
+ begin
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b000000000000001101 /* ports_egress */,32'b000000000000001101 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000011 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h000 /* mode */,
+ 32'b00000011 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 1 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b000000000011010000 /* ports_egress */,32'b000000000011010000 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 1 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00110000 /*pattern_mask*/, 32'b00010000 /* pattern_match*/,'h000 /* mode */,
+ 32'b00110000 /*ports_mask */, 32'b00100000 /* ports_egress */,32'b00100000 /* ports_ingress */);
+ end
+ else if(tru_config_opt == 2) // LACP (link aggregation of ports 4-1)
+ begin
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'b0000_0000_0000_0000 /*pattern_mask*/,32'b0000_0000_0000_0000 /* pattern_match*/,'h0 /* mode */,
+ 32'b0000_1111_0000_1111 /*ports_mask */, 32'b0000_1111_0000_1111 /* ports_egress */,32'b0000_1111_0000_1111 /* ports_ingress */);
+
+ // a bunch of link aggregation ports (ports 4 to 7 and 12&15)
+ // received FEC msg of class 0
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0001 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b1000_0000_0001_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 1
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0010 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b1000_0000_0010_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 2
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0100 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b0001_0000_0100_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 3
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 4 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_1000 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b0001_0000_1000_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+
+// // collector: receiving frames on the aggregation ports, forwarding to "normal" (others)
+// tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 5 /* subentry_addr*/,
+// 32'b1001_0000_1111_0000 /*pattern_mask*/, 32'b1001_0000_1111_0000 /* pattern_match*/,'h2 /* mode */,
+// 32'b1001_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0000_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+
+ tru_drv.pattern_config(4 /*replacement : use distributioon funciton defined by aggr_df_id */,
+ 5 /*addition : simple mask reflecting on which port frame was rx-ed*/,
+ 5 /*subtraction*/);
+ end
+ else if(tru_config_opt == 3)
+ begin
+ /* port 2 is backup for port 1*/
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b1100_0111 /* ports_egress */,32'b1100_0011 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000110 /*pattern_mask*/, 32'b00000010 /* pattern_match*/,'h000 /* mode */,
+ 32'b00000110 /*ports_mask */, 32'b00000110 /* ports_egress */,32'b00000100 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h00000 /*ports_mask */, 32'h00000 /* ports_egress */, 32'h00000 /* ports_ingress */);
+ end
+ else if(tru_config_opt == 5)
+ begin
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h0 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b111000000010100001 /* ports_egress */,32'b111000000010100001 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000011 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h0 /* mode */,
+ 32'b00000011 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+ end
+ else if(tru_config_opt == 6)
+ begin
+ tru_drv.pattern_config(1 /*replacement*/, 2 /*addition*/, 3 /*subtraction*/);
+ // basic config
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h0 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b111000000010100001 /* ports_egress */,32'b111000000010100001 /* ports_ingress */);
+ // backup if link down
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000011 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h0 /* mode */,
+ 32'b00000011 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+ // quick forward
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'b00000010 /*pattern_mask*/, 32'b00000010 /* pattern_match*/,'h2 /* mode */,
+ 32'b00000010 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+ // quick block
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'b00000001 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h3 /* mode */,
+ 32'b00000001 /*ports_mask */, 32'b00000001 /* ports_egress */,32'b00000001 /* ports_ingress */);
+
+ end
+ else if(tru_config_opt == 7) // TRU transparent but is there
+ begin
+ // basic config
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h0 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'h3FFFF /* ports_egress */, 32'h3FFFF /* ports_ingress */);
+ end
+ else if(tru_config_opt == 8) // LACP : using special LACP-dedicated
+ begin
+
+ // TRU table configuraiton for LACP using special LACP-dedicated "mode". For this you need:
+ // 1) define "default" entry with "mode"=0x0 (here subentry_addr=0) which allows accepting
+ // frames all aggregation ports but does not allow forwarding ports to aggregation ports
+ // (ingres vs. egress)
+ // 2) define each link aggregation with "mode"=0x4 (group of ports which define link aggregation
+ // - the ingress mask is used to recognize that frame comes from link aggregation, it is
+ // not used to create final forwarding/accepting mask
+ // - the egress mask is used to define through which port of the link aggregation
+ // the particular frame (of a given conversation/group identified by pattern_match) should use
+
+ // default configuraion
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'b0000_0000_0000_0000 /*pattern_mask*/,32'b0000_0000_0000_0000 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_1111_1111_1111 /*ports_mask */, 32'b0000_1111_0000_1111 /* ports_egress */,32'b1001_1111_1111_1111 /* ports_ingress */);
+
+ // first link aggregation of ports 4-7
+ // received FEC msg of class 0
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0001 /* pattern_match*/,'h4 /* mode */,
+ 32'b0000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0001_0000 /* ports_egress */,32'b0000_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 1
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0010 /* pattern_match*/,'h4 /* mode */,
+ 32'b0000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0010_0000 /* ports_egress */,32'b0000_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 2
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0100 /* pattern_match*/,'h4 /* mode */,
+ 32'b0000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0100_0000 /* ports_egress */,32'b0000_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 3
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 4 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_1000 /* pattern_match*/,'h4 /* mode */,
+ 32'b0000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_1000_0000 /* ports_egress */,32'b0000_0000_1111_0000 /* ports_ingress */);
+
+ // second link aggregation of ports 12 & 15
+ // received FEC msg of class 0 & 1
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 5 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0011 /* pattern_match*/,'h4 /* mode */,
+ 32'b1001_0000_0000_0000 /*ports_mask */, 32'b1000_0000_0000_0000 /* ports_egress */,32'b1001_0000_0000_0000 /* ports_ingress */);
+ // received FEC msg of class 2 & 3
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 6 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_1100 /* pattern_match*/,'h4 /* mode */,
+ 32'b1001_0000_0000_0000 /*ports_mask */, 32'b0001_0000_0000_0000 /* ports_egress */,32'b1001_0000_0000_0000 /* ports_ingress */);
+
+ tru_drv.pattern_config(4 /*replacement : use distributioon funciton defined by aggr_df_id */,
+ 5 /*addition : simple mask reflecting on which port frame was rx-ed*/,
+ 5 /*subtraction*/);
+ end
+ else if(tru_config_opt == 9) // LACP -> problematic - does not work - to be debugged
+ begin
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'b0000_0000_0000_0000 /*pattern_mask*/,32'b0000_0000_0000_0000 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_1111_1111_1111 /*ports_mask */, 32'b0000_1111_0000_1111 /* ports_egress */,32'b1001_1111_1111_1111 /* ports_ingress */);
+
+ // a bunch of link aggregation ports (ports 4 to 7 and 12&15)
+ // received FEC msg of class 0
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0001 /* pattern_match*/,'h0 /* mode */,
+ 32'b0001_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0001_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 1
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0010 /* pattern_match*/,'h0 /* mode */,
+ 32'b0001_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0010_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 2
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0100 /* pattern_match*/,'h0 /* mode */,
+ 32'b1000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_0100_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 3
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 4 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_1000 /* pattern_match*/,'h0 /* mode */,
+ 32'b1000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_1000_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // a bunch of link aggregation ports (ports 4 to 7 and 12&15)
+ // received FEC msg of class 0 & 1
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 5 /* subentry_addr*/,
+ 32'b0000_0000_1111_0000 /*pattern_mask*/, 32'b0000_0000_1111_0000 /* pattern_match*/,'h5 /* mode */,
+ 32'b0000_0000_1111_0000 /*ports_mask */, 32'b0000_0000_1111_0000 /* ports_egress */,32'b0000_0000_0000_0000 /* ports_ingress */);
+ // received FEC msg of class 2 & 3
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 6 /* subentry_addr*/,
+ 32'b1001_0000_0000_0000 /*pattern_mask*/, 32'b1001_0000_0000_0000 /* pattern_match*/,'h5 /* mode */,
+ 32'b1001_0000_0000_0000 /*ports_mask */, 32'b1001_0000_0000_0000 /* ports_egress */,32'b0000_0000_0000_0000 /* ports_ingress */);
+
+ tru_drv.pattern_config(4 /*replacement : use distributioon funciton defined by aggr_df_id */,
+ 5 /*addition : simple mask reflecting on which port frame was rx-ed*/,
+ 5 /*subtraction*/);
+ end
+ else if(tru_config_opt == 10) // test VID bug
+ begin
+ int i =0;
+ for(i=0;i<18;i++)
+ tru_drv.write_tru_tab( 1 /* valid */, i /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000000 /*pattern_mask*/, 32'h00000000 /* pattern_match*/,'h0 /* mode */,
+ 32'hFFFFFFFF /*ports_mask */, 32'hFFFFFFFF /* ports_egress */, 32'hFFFFFFFF /* ports_ingress*/);
+ end
+ else // default config == 0
+ begin
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h0 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b111000000010100001 /* ports_egress */,32'b111000000010100001 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000011 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h0 /* mode */,
+ 32'b00000011 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+ end
+
+
+
+// tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+// 32'b00000011 /*pattern_mask*/, 32'b00000001 /* pattern_match*/,'h0 /* pattern_mode */,
+// 32'b00000011 /*ports_mask */, 32'b00000010 /* ports_egress */,32'b00000010 /* ports_ingress */);
+//
+// tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+// 32'b00000011 /*pattern_mask*/, 32'b00000011 /* pattern_match*/,'h0 /* pattern_mode */,
+// 32'b00000111 /*ports_mask */, 32'b00000100 /* ports_egress */,32'b00000100 /* ports_ingress */);
+//
+// tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+// 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+// 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+
+ if(tru_config_opt == 2)
+ tru_drv.transition_config(0 /*mode */, 1 /*rx_id*/, 1 /*prio mode*/, 0 /*prio*/,
+ 20 /*time_diff*/, 0 /*port_a_id*/, 1 /*port_b_id*/);
+ else if(tru_config_opt == 3)
+ tru_drv.transition_config(0 /*mode */, 1 /*rx_id*/, 0 /*prio mode*/, 0 /*prio*/,
+ 100 /*time_diff*/,1 /*port_a_id*/, 2 /*port_b_id*/);
+
+ if(tru_config_opt == 4 || tru_config_opt == 5)
+ begin
+ tru_drv.rt_reconf_config(1 /*tx_frame_id*/, 1/*rx_frame_id*/, 1 /*mode*/);
+ tru_drv.hw_frame_config(1/*tx_fwd_id*/, 1/*rx_fwd_id*/, 1/*tx_blk_id*/, 2 /*rx_blk_id*/);
+ tru_drv.rt_reconf_enable();
+ end
+ if(tru_config_opt == 6)
+ begin
+ tru_drv.rt_reconf_config(1 /*tx_frame_id*/, 1/*rx_frame_id*/, 1 /*mode*/);
+ tru_drv.hw_frame_config(1/*tx_fwd_id*/, 1/*rx_fwd_id*/, 1/*tx_blk_id*/, 2 /*rx_blk_id*/);
+ tru_drv.rt_reconf_enable();
+ end
+
+ tru_drv.tru_swap_bank();
+
+ if(g_tru_enable)
+ tru_drv.tru_enable();
+// tru_drv.tru_port_config(0);
+ $display("TRU configured and enabled");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ endtask; //init_tru
initial begin
uint64_t msr;
int seed;
rtu_vlan_entry_t def_vlan;
+ int q;
+ int z;
-
-
CWishboneAccessor cpu_acc = DUT.cpu.get_accessor();
+ for(int gg=0;gg<g_num_ports;gg++)
+ begin
+ ep_ctrl[gg] = 'b1;
+ end
+
repeat(200) @(posedge clk_sys);
$display("Startup!");
cpu_acc.set_mode(PIPELINED);
cpu_acc.write('h10304, (1<<3));
-
+
+ // pps_gen for time code for Time-Aware Traffic Shaper
+ if(g_enable_WRtime == 1)
+ begin
+ cpu_acc.write('h10500, (1<<1)); // enable pps_gen counter
+ cpu_acc.write('h1051c, (1<<2)); // tm_valid HIGH
+ end
init_ports(ports, cpu_acc);
$display("InitNIC");
@@ -236,51 +3594,803 @@ module main;
rtu.set_bus(cpu_acc, 'h60000);
for (int dd=0;dd<g_num_ports;dd++)
begin
- rtu.set_port_config(dd, 1, 1, 1);
-
+ rtu.set_port_config(dd /*port ID*/, portRtuEnabled[dd] /*pass_all*/, 0 /*pass_bpdu*/, 1 /*learn_en*/);
+ end
+
+ //
+ rtu.set_port_config(g_num_ports, 1, 0, 0); // for NIC
+
+ rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h00}, (1<<18));
+ rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h01}, (1<<18));
+ rtu.add_static_rule('{'h01, 'h80, 'hc2, 'h00, 'h00, 'h02}, (1<<18));
+
+ rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 0 /*FID*/);
+// rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 1 /*FID*/);
+// rtu.add_static_rule('{'hFF, 'hFF, 'hFF, 'hFF, 'hFF, 'hFF}, 'hFFFFFFFF /*mask*/, 2 /*FID*/);
+
+ if(g_LACP_scenario == 2)
+ begin
+ for(int i = 0;i<LACPdistro.distPortN;i++)
+ rtu.add_static_rule('{0,2,i,4,5,6}, (1<<LACPdistro.distr[i]));
+ end
+ else
+ begin
+ if(portUnderTest[0]) rtu.add_static_rule('{17, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<17));
+ if(portUnderTest[1]) rtu.add_static_rule('{16, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<16));
+ if(portUnderTest[2]) rtu.add_static_rule('{15, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<15));
+ if(portUnderTest[3]) rtu.add_static_rule('{14, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<14));
+ if(portUnderTest[4]) rtu.add_static_rule('{13, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<13));
+ if(portUnderTest[5]) rtu.add_static_rule('{12, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<12));
+ if(portUnderTest[6]) rtu.add_static_rule('{11, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<11));
+ if(portUnderTest[7]) rtu.add_static_rule('{10, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<10));
+ if(portUnderTest[8]) rtu.add_static_rule('{ 9, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<9 ));
+ if(portUnderTest[9]) rtu.add_static_rule('{ 8, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<8 ));
+ if(portUnderTest[10]) rtu.add_static_rule('{ 7, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<7 ));
+ if(portUnderTest[11]) rtu.add_static_rule('{ 6, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<6 ));
+ if(portUnderTest[12]) rtu.add_static_rule('{ 5, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<5 ));
+ if(portUnderTest[13]) rtu.add_static_rule('{ 4, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<4 ));
+ if(portUnderTest[14]) rtu.add_static_rule('{ 3, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<3 ));
+ if(portUnderTest[15]) rtu.add_static_rule('{ 2, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<2 ));
+ if(portUnderTest[16]) rtu.add_static_rule('{ 1, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<1 ));
+ if(portUnderTest[17]) rtu.add_static_rule('{ 0, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<0 ));
end
- rtu.add_static_rule('{17, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<17 ));
- rtu.add_static_rule('{16, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<16 ));
+
+
// rtu.set_hash_poly();
-
- def_vlan.port_mask = 32'hffffffff;
- def_vlan.fid =0;
- def_vlan.drop = 0;
- def_vlan.has_prio =0;
- def_vlan.prio_override = 0;
+ $display(">>>>>>>>>>>>>>>>>>> RTU initialization <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ for(int dd=0;dd<g_mvlan;dd++)
+ begin
+ def_vlan.port_mask = sim_vlan_tab[dd].vlan_entry.port_mask;
+ def_vlan.fid = sim_vlan_tab[dd].vlan_entry.fid;
+ def_vlan.drop = sim_vlan_tab[dd].vlan_entry.drop;
+ def_vlan.prio = sim_vlan_tab[dd].vlan_entry.prio;
+ def_vlan.has_prio = sim_vlan_tab[dd].vlan_entry.has_prio;
+ def_vlan.prio_override = sim_vlan_tab[dd].vlan_entry.prio_override;
+ if(sim_vlan_tab[dd].valid == 1)
+ rtu.add_vlan_entry(sim_vlan_tab[dd].vlan_id, def_vlan);
+ end
- rtu.add_vlan_entry(0, def_vlan);
+// def_vlan.port_mask = vlan_port_mask;
+// def_vlan.fid = 0;
+// def_vlan.drop = 0;
+// def_vlan.prio = 0;
+// def_vlan.has_prio = 0;
+// def_vlan.prio_override = 0;
+// rtu.add_vlan_entry(0, def_vlan);
+ /////////////////////////// RTU extension settings: ////////////////////////////////
+
+ rtu.rx_add_ff_mac_single(0/*ID*/,1/*valid*/,'h1150cafebabe /*MAC*/);
+ rtu.rx_add_ff_mac_single(1/*ID*/,1/*valid*/,'h111111111111 /*MAC*/);
+ rtu.rx_add_ff_mac_single(2/*ID*/,1/*valid*/,'h0180C200000F /*MAC*/);
+ rtu.rx_add_ff_mac_range (0/*ID*/,1/*valid*/,'h0050cafebabe /*MAC_lower*/,'h0850cafebabe/*MAC_upper*/);
+// rtu.rx_set_port_mirror ('h00000002 /*mirror_src_mask*/,'h00000080 /*mirror_dst_mask*/,1/*rx*/,1/*tx*/);
+ rtu.rx_set_port_mirror (mirror_src_mask, mirror_dst_mask,mr_rx, mr_tx);
+ rtu.rx_set_hp_prio_mask (hp_prio_mask /*hp prio mask*/);
+// rtu.rx_set_hp_prio_mask ('b10000001 /*hp prio mask*/); //HP traffic set to 7th priority
+// rtu.rx_set_cpu_port ((1<<g_num_ports)/*mask: virtual port of CPU*/);
+ rtu.rx_read_cpu_port();
+ if(rx_forward_on_fmatch_full)
+ rtu.rx_forward_on_fmatch_full();
+ else
+ rtu.rx_drop_on_fmatch_full();
+ rtu.rx_feature_ctrl(mr, mac_ptp , mac_ll, mac_single, mac_range, mac_br);
+ rtu.rx_fw_to_CPU(hp_fw_cpu,unrec_fw_cpu);
+ rtu.rx_feature_dbg(rtu_dbg_f_fast_match, rtu_dbg_f_full_match);
+
+ ////////////////////////////////////////////////////////////////////////////////////////
rtu.enable();
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ ///TRU
+ tru = new(cpu_acc, 'h58000,g_num_ports,1 /*enable debugging*/);
+ init_tru(tru);
+
+ tatsu=new(cpu_acc, 'h59000);
+ if(g_tatsu_config == 1)
+ tatsu.drop_at_HP_enable();
+
+ hwdu=new(cpu_acc, 'h71000);
+ hwdu.dump_mpm_page_utilization(1);
+
+ fork
+ begin
+ if(g_fw_to_cpu_scenario == 1)
+ begin
+ wait_cycles(1000);
+ unrec_fw_cpu = 1; //
+ rtu.rx_fw_to_CPU(hp_fw_cpu,unrec_fw_cpu);
+ end
+ end
+ join_none
+
+ fork
+ begin
+ if(g_traffic_shaper_scenario == 1)
+ begin
+ // initial settings
+ tatsu.set_tatsu(8 /*pause quanta*/, 1 /*tm_tai*/, 1000 /*tm_cycles*/, 1/*prio_mask*/,
+ 3 /*port_mask */, 100 /*repeat_cycles*/);
+ tatsu.print_status();
+
+ // wait for it to start
+ wait_cycles(10000);
+
+ // wrong settings - we should be at tai >=1, so tai=0 is wrong setting for sure
+ tatsu.set_tatsu(8 /*pause quanta*/, 0 /*tm_tai*/, 1000 /*tm_cycles*/, 1/*prio_mask*/,
+ 3 /*port_mask */, 100 /*repeat_cycles*/);
+ // check that it says error
+ tatsu.print_status();
+
+ // set tm_valid LOW
+ cpu_acc.write('h1051c, (0<<2)); // tm_valid LOW
+
+ // new settings
+ wait_cycles(10);
+ tatsu.set_tatsu(8 /*pause quanta*/, 2 /*tm_tai*/, 1000 /*tm_cycles*/, 'b10000000/*prio_mask*/,
+ 32'b1010100 /*port_mask */, 100 /*repeat_cycles*/);
+ tatsu.print_status();
+
+ wait_cycles(15000); // we should be already after the time specifid
+ // set tm_valid HIGH again
+ cpu_acc.write('h1051c, (1<<2)); // tm_valid HIGH
+
+ wait_cycles(5000);
+ // test re-sync
+ cpu_acc.write('h1051c, (0<<2)); // tm_valid HIGH
+ wait_cycles(15000);
+ cpu_acc.write('h1051c, (1<<2)); // tm_valid HIGH
+ wait_cycles(500);
+ cpu_acc.write('h1051c, (0<<2)); // tm_valid HIGH
+ wait_cycles(50000);
+ end
+ if(g_traffic_shaper_scenario == 2)
+ begin
+
+ tatsu.set_tatsu(50 /* pause quanta */,
+ 0 , 7000 /* start time: tm_tai, tm_cycles */ ,
+ 8'b10000000 /* prio_mask */,
+ 32'b111111111111111111 /* port_mask */,
+ 8000 /* repeat_cycles */);
+ tatsu.print_status();
+
+ end
+ end
+ join_none
+
////////////// sending packest on all the ports (16) according to the portUnderTest mask.///////
fork
-//`ifdef none
begin
- if(portUnderTest[6])
- begin
- for(int g=0;g<20;g++)
- begin
- $display("Try f_5:%d", g);
- tx_test(seed /* seed */, 200 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[0].send /* src */, ports[16].recv /* sink */, 0 /* srcPort */ , 16 /* dstPort */);
- end
- end
- end // fork begin
-//`endif // `ifdef none
-
-// `ifdef none
+ if(g_failure_scenario == 1)
+ begin
+ wait_cycles(2000);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(600);
+ tru.tru_swap_bank();
+ end
+ else if(g_failure_scenario == 2 | g_failure_scenario == 3 | g_failure_scenario == 4)
+ begin
+ if(g_failure_scenario == 4)
+ wait_cycles(400);
+ else
+ wait_cycles(500);
+ ep_ctrl[g_backup_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 1 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(200);
+ rtu.set_port_config(1, 0, 0, 1); // disable port 1
+ wait_cycles(200);
+ ep_ctrl[g_backup_port] = 'b1;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 1 up <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(400);
+ rtu.set_port_config(1, 1, 0, 1); // enable port 1
+ if( g_failure_scenario == 3)
+ wait_cycles(350);
+ else
+ wait_cycles(500);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ end
+ if(g_failure_scenario == 5)
+ begin
+ wait_cycles(2000);
+ ep_ctrl[0] = 'b0;
+ ep_ctrl[4] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> links 0 & 4 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ end
+ if(g_failure_scenario == 6 || g_failure_scenario == 7)
+ begin
+ wait_cycles(500);
+ ep_ctrl[0] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> links 0 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ if(g_failure_scenario == 7)
+ begin
+ wait_cycles(500);
+ hp_fw_cpu = 1;
+ rtu.rx_fw_to_CPU(hp_fw_cpu,unrec_fw_cpu);
+ end
+ end
+ if(g_failure_scenario == 8)
+ begin
+ wait_cycles(2010);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(600);
+ /* port 1 is backup for port 2*/
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/,'h000 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b1100_0111 /* ports_egress */,32'b1100_0101 /* ports_ingress */);
+
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000110 /*pattern_mask*/, 32'b00000100 /* pattern_match*/,'h000 /* mode */,
+ 32'b00000110 /*ports_mask */, 32'b00000110 /* ports_egress */,32'b00000010 /* ports_ingress */);
+ tru.tru_swap_bank();
+ wait_cycles(600);
+ ep_ctrl[g_active_port] = 'b1;
+ end
+ if(g_failure_scenario == 9)
+ begin
+ wait_cycles(2030);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ rtu.set_port_config(1, 0, 0, 1); // disable port 1
+ wait_cycles(50);
+ ep_ctrl[g_active_port] = 'b1;
+ wait_cycles(50);
+ rtu.set_port_config(1, 1, 0, 1); // enable port 1
+ wait_cycles(100);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ rtu.set_port_config(1, 0, 0, 1); // disable port 1
+ wait_cycles(50);
+ ep_ctrl[g_active_port] = 'b1;
+ wait_cycles(50);
+ rtu.set_port_config(1, 1, 0, 1); // enable port 1
+ wait_cycles(100);
+ hwdu.dump_mpm_page_utilization(1);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ rtu.set_port_config(1, 0, 0, 1); // disable port 1
+ wait_cycles(50);
+ ep_ctrl[g_active_port] = 'b1;
+ wait_cycles(50);
+ rtu.set_port_config(1, 1, 0, 1); // enable port 1
+ wait_cycles(100);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ rtu.set_port_config(1, 0, 0, 1); // disable port 1
+ wait_cycles(50);
+ ep_ctrl[g_active_port] = 'b1;
+ wait_cycles(50);
+ rtu.set_port_config(1, 1, 0, 1); // enable port 1
+ wait_cycles(100);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ rtu.set_port_config(1, 0, 0, 1); // disable port 1
+ wait_cycles(50);
+ ep_ctrl[g_active_port] = 'b1;
+ wait_cycles(50);
+ rtu.set_port_config(1, 1, 0, 1); // enable port 1
+ wait_cycles(100);
+ hwdu.dump_mpm_page_utilization(1);
+ end
+ if(g_failure_scenario == 10)
+ begin
+ int thrash_cnt = 1;
+ wait_cycles(2030);
+
+ for(thrash_cnt=1;thrash_cnt<40;thrash_cnt++)
+ begin
+ ep_ctrl[g_active_port] = 'b0;
+ wait_cycles(thrash_cnt);
+ ep_ctrl[g_active_port] = 'b1;
+ wait_cycles(thrash_cnt);
+ end
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ hwdu.dump_mpm_page_utilization(1);
+
+ end
+ if(g_failure_scenario == 11)
+ begin
+ int thrash_cnt = 1;
+ wait_cycles(2015);
+ ep_ctrl[g_active_port] = 'b0;
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ wait_cycles(100);
+ hwdu.dump_mpm_page_utilization(1);
+ wait_cycles(1000);
+ hwdu.dump_mpm_page_utilization(1);
+ wait_cycles(1000);
+ hwdu.dump_mpm_page_utilization(1);
+
+ end
+ end
+ join_none; //
+
+
+ fork
+ begin
+ if(g_LACP_scenario == 1 )
+ begin
+ wait_cycles(200);
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Link Aggregation for HP <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_distrib_test(seed, /* seed */
+ repeat_number, /* n_tries */
+ 1, /* is_q */
+ 0, /* unvid */
+ ports, /* */
+ LACPdistro, /* port distribution */
+ 0); /* option */
+
+
+ end
+ if(g_LACP_scenario == 3 )
+ begin
+ wait_cycles(200);
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Link Aggregation for HP <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_distrib_test(seed, /* seed */
+ repeat_number, /* n_tries */
+ 1, /* is_q */
+ 0, /* unvid */
+ ports, /* */
+ LACPdistro, /* port distribution */
+ 5); /* option */
+
+
+ end
+ else if(g_LACP_scenario == 2)
+ begin
+ wait_cycles(200);
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Link Aggregation for HP <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_distrib_test(seed, /* seed */
+ repeat_number, /* n_tries */
+ 1, /* is_q */
+ 0, /* unvid */
+ ports, /* */
+ LACPdistro, /* port distribution */
+ 0); /* option */
+
+ wait_cycles(200);
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Link Aggregation for Broadcast <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_distrib_test(seed, /* seed */
+ repeat_number, /* n_tries */
+ 1, /* is_q */
+ 0, /* unvid */
+ ports, /* */
+ LACPdistro, /* port distribution */
+ 1); /* option */
+
+ wait_cycles(200);
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Link Aggregation for Unicast <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_distrib_test(seed, /* seed */
+ repeat_number, /* n_tries */
+ 1, /* is_q */
+ 0, /* unvid */
+ ports, /* */
+ LACPdistro, /* port distribution */
+ 2); /* option */
+
+
+
+ end
+ end
+ join_none; //
+
+ fork
+ begin
+ int dd;
+ if(g_transition_scenario == 1)
+ begin
+ wait_cycles(200);
+ //program other bank with alternate config
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'h00000 /*pattern_mask*/, 32'h00000 /* pattern_match*/, 'h0 /* mode */,
+ 32'h3FFFF /*ports_mask */, 32'b1000_0111 /* ports_egress */,32'b1000_0101 /* ports_ingress */);
+
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b00000110 /*pattern_mask*/, 32'b0100 /* pattern_match*/,'h0 /* mode */,
+ 32'b00000110 /*ports_mask */, 32'b1000_0111 /* ports_egress */,32'b1000_0011 /* ports_ingress */);
+ // enable transition
+ tru.transition_enable();
+ wait_cycles(200);
+
+ // send normal stuff
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[0].send /* src */,
+ ports[7].recv /* sink */,
+ 0 /* srcPort */ ,
+ 7 /* dstPort */,
+ 4 /*option=4 */);
+ wait_cycles(200);
+ //send some crap - is to be blocked by the port and counted
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ wait_cycles(200);
+ //send some crap - is to be blocked by the port and counted
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[2].send /* src */,
+ ports[2].recv /* sink */,
+ 2 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ wait_cycles(200);
+ //sent marker to port 1
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[2].send /* src */,
+ ports[2].recv /* sink */,
+ 2 /* srcPort */ ,
+ 0 /* dstPort */,
+ 101 /*option=4 */);
+ //send some crap - is to be blocked by the port and counted
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[2].send /* src */,
+ ports[2].recv /* sink */,
+ 2 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+
+ //send some crap - is to be blocked by the port and counted
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[2].send /* src */,
+ ports[2].recv /* sink */,
+ 2 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+
+ wait_cycles(200);
+ //sent marker to port 1
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 101 /*option=4 */);
+ wait_cycles(200);
+
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+
+
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[2].send /* src */,
+ ports[2].recv /* sink */,
+ 2 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[1].recv /* sink */,
+ 1 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[2].send /* src */,
+ ports[2].recv /* sink */,
+ 2 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ //send some crap - it should be forwarded/counted before transition
+ tx_test(seed /* seed */,
+ 1 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[0].send /* src */,
+ ports[0].recv /* sink */,
+ 0 /* srcPort */ ,
+ 0 /* dstPort */,
+ 201 /*non-blocking => does not wait for reception */);
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> transition 0 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+
+ for(dd=0;dd<8;dd++)
+ tru.ep_debug_read_pfilter(dd);
+
+ wait_cycles(10);
+ tru.ep_debug_clear_pfilter(1);
+ wait_cycles(10);
+ tru.ep_debug_read_pfilter(1);
+ wait_cycles(10);
+ tru.ep_debug_inject_packet(3,'h1234,1);
+ wait_cycles(10);
+ tru.ep_debug_inject_packet(4,'h1234,0);
+ wait_cycles(100);
+ tru.ep_debug_inject_packet(4,'hFFFF,1);
+ wait_cycles(100);
+ tru.ep_debug_inject_packet(4,'h1234,0);
+ wait_cycles(10);
+ tru.ep_debug_inject_packet(3,'h4321,0);
+ wait_cycles(10);
+
+ end
+
+ if(g_transition_scenario == 2)
+ begin
+ wait_cycles(200);
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> PAUSE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+ //program other bank with alternate config
+ tx_special_pck(ports[3].send,PAUSE /*opt*/,14/*pause time*/);
+
+ end
+ if(g_transition_scenario == 3)
+ begin
+ // send normal stuff
+ fork
+ begin
+ tx_test(seed /* seed */,
+ 5 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[0].send /* src */,
+ ports[7].recv /* sink */,
+ 0 /* srcPort */ ,
+ 7 /* dstPort */,
+ 4 /*option=4 */);
+ end
+ begin
+ tx_test(seed /* seed */,
+ 5 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[5].recv /* sink */,
+ 0 /* srcPort */ ,
+ 5 /* dstPort */,
+ 4 /*option=4 */);
+ end
+ join
+ fork
+ begin
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> CLOSE / OPEN port 0<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_special_pck(ports[0].send,BPDU_0 /*opt*/);
+ end
+ begin
+ wait_cycles(20);
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> CLOSE / OPEN port 1<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ tx_special_pck(ports[1].send,BPDU_0 /*opt*/);
+ end
+ join
+ fork
+ begin
+ tx_test(seed /* seed */,
+ 5 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[0].send /* src */,
+ ports[7].recv /* sink */,
+ 0 /* srcPort */ ,
+ 7 /* dstPort */,
+ 4 /*option=4 */);
+ end
+ begin
+ tx_test(seed /* seed */,
+ 5 /* n_tries */,
+ 0 /* is_q */,
+ 0 /* unvid */,
+ ports[1].send /* src */,
+ ports[5].recv /* sink */,
+ 0 /* srcPort */ ,
+ 5 /* dstPort */,
+ 4 /*option=4 */);
+ end
+ join
+
+ end
+ if(g_transition_scenario == 4)
+ begin
+ wait_cycles(9000);
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 32'b0000_0000_0000_0000 /*pattern_mask*/,32'b0000_0000_0000_0000 /* pattern_match*/,'h0 /* mode */,
+ 32'b0000_1111_0000_1111 /*ports_mask */, 32'b0000_1111_0000_1111 /* ports_egress */,32'b0000_1111_0000_1111 /* ports_ingress */);
+
+ // a bunch of link aggregation ports (ports 4 to 7 and 12&15)
+ // received FEC msg of class 0
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0001 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b1000_0000_0001_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 1
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0010 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b1000_0000_0010_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 2
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_0100 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b0001_0000_1000_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+ // received FEC msg of class 3
+ tru.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 4 /* subentry_addr*/,
+ 32'b0000_0000_0000_1111 /*pattern_mask*/, 32'b0000_0000_0000_1000 /* pattern_match*/,'h0 /* mode */,
+ 32'b1001_0000_1111_0000 /*ports_mask */, 32'b0001_0000_1000_0000 /* ports_egress */,32'b1001_0000_1111_0000 /* ports_ingress */);
+
+ tru.transition_config(1 /*mode */, 4 /*rx_id*/, 0 /*prio mode*/, 7 /*prio*/,
+ 1000 /*time_diff*/,6 /*port_a_id*/, 7 /*port_b_id*/);
+
+ tru.transition_enable();
+
+ wait_cycles(4000);
+
+ $display("");
+ $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> MARKER <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+ $display("");
+
+ tx_special_pck(ports[6].send,MARKER /*opt*/,2/*response*/);
+
+ end
+ end
+ join_none; //
+
+ fork
begin
- if(portUnderTest[5])
+ if(g_test_inj_gen == 1)
+ begin
+ wait_cycles(400);
+ ports[2].ep.inject_gen_ctrl_enable();
+ wait_cycles(4000);
+ ports[2].ep.inject_gen_ctrl_disable();
+ wait_cycles(4000);
+ ports[2].ep.inject_gen_ctrl_enable();
+ wait_cycles(4000);
+ ports[2].ep.inject_gen_ctrl_disable();
+ end
+ if(g_test_inj_gen == 2)
+ begin
+ wait_cycles(400);
+ ports[2].ep.inject_gen_ctrl_enable();
+ wait_cycles(500);
+ ports[2].ep.inject_gen_ctrl_mode(1);
+ wait_cycles(500);
+ ports[2].ep.inject_gen_ctrl_mode(0);
+ wait_cycles(500);
+ ports[2].ep.inject_gen_ctrl_disable();
+ wait_cycles(1000);
+ ports[2].ep.inject_gen_ctrl_enable();
+ wait_cycles(1000);
+ ports[2].ep.inject_gen_ctrl_disable();
+ end
+ end
+ join_none; //
+
+
+ for(q=0; q<g_max_ports; q++)
+ fork
+ automatic int qq=q;
+ begin
+ if(portUnderTest[qq])
begin
- for(int g=0;g<20;g++)
- begin
- $display("Try f_6:%d", g);
- tx_test(seed /* seed */, 200 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[1].send /* src */, ports[17] .recv /* sink */, 1 /* srcPort */ , 17 /* dstPort */);
- end
- end
- end
-// `endif
+ wait_cycles(start_send_init_delay[qq]);
+ for(int g=0;g<tries_number;g++)
+ begin
+ $display("Try port_%d:%d", qq, g);
+ tx_test(seed /* seed */,
+ repeat_number /* n_tries */,
+ g_is_qvlan /* is_q */,
+ 0 /* unvid */,
+ ports[trans_paths[qq].tx].send /* src */,
+ ports[trans_paths[qq].rx].recv /* sink */,
+ trans_paths[qq].tx /* srcPort */ ,
+ trans_paths[qq].rx /* dstPort */,
+ trans_paths[qq].op /*option=4 */);
+ end //for
+ txrx_done[qq]=1;
+ end //if
+
+ end //thread
+ join_none;//fork
+
+ fork
forever begin
nic.update(DUT.U_Top.U_Wrapped_SCBCore.vic_irqs[0]);
@(posedge clk_sys);
@@ -290,55 +4400,127 @@ module main;
@(posedge clk_sys);
end
join_none
-
-
- end
-
-/* -----\/----- EXCLUDED -----\/-----
-
-
- #3us;
+// for(q=z; q<g_max_ports; z++)
+// fork
+// forever begin
+// automatic int zz=z;
+// if(portUnderTest[zz])
+// begin
+// if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.alloc_done_o[zz])
+// mmu_alloc_cnt[zz]++;
+// if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.set_usecnt_done_o[zz])
+// mmu_usecnt_cnt[zz]++;
+// if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.free_done_o[zz])
+// mmu_free_cnt[zz]++;
+// if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.force_free_done_o[zz])
+// mmu_f_free_cnt[zz]++;
+// end //if
+// @(posedge clk_sys);
+// end //thread
+// join_none;//fork
+
- $display("Startup");
- acc.write('h10304, (1<<3));
+ end
+
+ initial begin
+ int q =0;
+ while(!rst_n) @(posedge clk_sys);
+
+ if(g_simple_allocator_unicast_check)
+ forever begin
+ for(q=0;q<g_max_ports;q++) begin
+ if(portUnderTest[q]) begin
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.alloc_done_o[q])
+ mmu_alloc_cnt[q]++;
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.set_usecnt_done_o[q])
+ mmu_usecnt_cnt[q]++;
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.free_done_o[q])
+ mmu_free_cnt[q]++;
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.force_free_done_o[q])
+ mmu_f_free_cnt[q]++;
+ end //if
+ end // for
+ @(posedge clk_sys);
+ end //forever
+ end //initial begin
+
+
- for (i=0;i<18;i++)
- begin
- acc.read('h30034 + i*'h400, msr);
- $display("IDCODE [%d]: %x", i, msr);
- end
-
-
- ep = new (acc, 'h31000);
- ep.init();
+ initial begin
+ int l = 0;
+ int pg_cnt =0;
+ while(!rst_n) @(posedge clk_sys);
+ while(txrx_done != portUnderTest || g_transition_scenario != 0) @(posedge clk_sys);
+ wait_cycles(100);
+ while(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages < 985) @(posedge clk_sys);
+ $display("free pages: %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages);
+ if(!g_simple_allocator_unicast_check)
+ begin
+ wait_cycles(2000);// wait so we can do other stuff (i.e. display the other alloc check
+ $stop; //$finish; // finish sim
+ end
+ if(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.g_with_RESOURCE_MGR) begin
+ $display("unknown: %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.dbg_o[9 : 0]);
+ $display("special: %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.dbg_o[19:10]);
+ $display("normal : %4d",DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.dbg_o[29:20]);
+ end
+ $display("------------------- this check works only for unicast traffic ------------------------");
+ for(l=0;l<g_max_ports+1;l++)
+ begin
+ pg_cnt = mmu_alloc_cnt[trans_paths[l].tx]-mmu_f_free_cnt[trans_paths[l].tx]-mmu_free_cnt[trans_paths[l].rx];
+ if(pg_cnt == 2) // very simple sanity check
+ $display("CNT: tx_port=%2d: alloc=%3d; usecnt=%3d; force free=%3d | rx_port=%2d: free=%3d [OK]",trans_paths[l].tx, mmu_alloc_cnt[trans_paths[l].tx], mmu_usecnt_cnt[trans_paths[l].tx],mmu_f_free_cnt[trans_paths[l].tx], trans_paths[l].rx, mmu_free_cnt[trans_paths[l].rx]);
+ else
+ $display("CNT: tx_port=%2d: alloc=%3d; usecnt=%3d; force free=%3d | rx_port=%2d: free=%3d [--]",trans_paths[l].tx, mmu_alloc_cnt[trans_paths[l].tx], mmu_usecnt_cnt[trans_paths[l].tx],mmu_f_free_cnt[trans_paths[l].tx], trans_paths[l].rx, mmu_free_cnt[trans_paths[l].rx]);
+ end//if
+ $display("------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ------------------------");
+ end //initla begin
- nic = new (acc, 'h20000);
- nic.init();
-
- $display("waiting for link");
-
-
- fork
-
- begin
- tx_test(3, 0, 0, nic_src, nic_snk);
- end
- begin
- forever begin
- nic.update(!cpu_irq_n);
- @(posedge clk_sys);
- end
-
- end
+ initial begin
+ int l = 0;
+ int pg_cnt =0;
+ init_alloc_tab();
+ while(!rst_n) @(posedge clk_sys);
+ forever begin
+ alloc_check(
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_alloc_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_usecnt_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_free_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.done_force_free_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.usecnt_alloc,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.usecnt_set,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.pgaddr_free,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.alloc_req_d1.pgaddr_usecnt,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.pgaddr_o,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.rsp_vec_o
+ );
+ @(posedge clk_sys);
+ end
+ end //initla begin
- join
+ initial begin
+ int l = 0;
+ int pg_cnt =0;
+ init_alloc_tab();
+ while(!rst_n) @(posedge clk_sys);
+ while(txrx_done != portUnderTest || g_transition_scenario != 0) @(posedge clk_sys);
+ wait_cycles(1000);
+// while(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages < (1024-2*(g_num_ports+1))) @(posedge clk_sys);
+ while(DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.MEMORY_MANAGEMENT_UNIT.ALLOC_CORE.free_pages < 985) @(posedge clk_sys);
+ wait_cycles(1000);
+ dump_results(
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.dbg_pckstart_pageaddr,
+ DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.dbg_pckinter_pageaddr);
+// for(l=0;l<19;l++)
+// $display("[p%2d] Pre-allocated pckstart_pageaddr=0x%3p | pckinter_pageaddr=0x%3p", l,
+// DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.dbg_pckstart_pageaddr[((l+1)*10):(l*10)],
+// DUT.U_Top.U_Wrapped_SCBCore.gen_network_stuff.U_Swcore.dbg_pckinter_pageaddr[((l+1)*10):(l*10)]
+// );
+ $stop;
+ end //initla begin
- end // initial begin
- -----/\----- EXCLUDED -----/\----- */
-
-
endmodule // main
diff --git a/testbench/scb_top/run.do b/testbench/scb_top/run.do
index a3334be4bf50a5b4a17520678bb738c3ccb12968..0cbfebf08c122dfa3726323280a09e8eb1427234 100644
--- a/testbench/scb_top/run.do
+++ b/testbench/scb_top/run.do
@@ -3,7 +3,9 @@ make -f Makefile
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
-do wave.do
+ do wave.do
+#do wave_new.do
+#do wave-master.do
#do wave-allports.do
radix -hexadecimal
run 4000us
diff --git a/testbench/scb_top/scb_snake_sim_svwrap.svh b/testbench/scb_top/scb_snake_sim_svwrap.svh
new file mode 100644
index 0000000000000000000000000000000000000000..e10ce52191879313aba295cd9aa6f29d7f1f212f
--- /dev/null
+++ b/testbench/scb_top/scb_snake_sim_svwrap.svh
@@ -0,0 +1,352 @@
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "simdrv_wr_endpoint.svh"
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+
+/*
+function automatic bit f_next_8b10b_disparity8(bit cur_disp, bit k, bit [7:0] data);
+ const bit[0:31] c_disPar_6b = 32'b11101000100000011000000110010111;
+ const bit [0:7] c_disPar_4b = 8'b10001001;
+ bit dp4bit, dp6bit, new_disp;
+
+ dp4bit = c_disPar_4b[data[7:5]];
+ dp6bit = c_disPar_6b[data[4:0]];
+ new_disp = cur_disp;
+
+
+ case (cur_disp)
+ 1'b0: if (k ^ dp6bit ^ dp4bit)
+ new_disp = 1;
+ 1'b1: if (k ^ dp6bit ^ dp4bit)
+ new_disp = 0;
+ endcase // case (cur_disp)
+
+ if ( data[1:0] != 2'b0 && k)
+ new_disp = cur_disp;
+
+ return new_disp;
+endfunction // f_next_8b10b_disparity8
+
+function automatic bit f_next_8b10b_disparity16(bit cur_disp,bit[1:0] k, bit[15:0] data);
+ bit tmp;
+ bit [7:0] msb;
+
+ msb = data[15:0];
+ tmp = f_next_8b10b_disparity8(cur_disp, k[1], msb);
+ tmp = f_next_8b10b_disparity8(tmp, k[0], data[7:0]);
+ return tmp;
+endfunction // f_next_8b10b_disparity16*/
+
+module scb_snake_sim_svwrap
+ (
+ clk_sys_i,
+ clk_ref_i,
+ rst_n_i,
+ cpu_irq,
+ clk_swc_mpm_core_i,
+ ep_ctrl_i,
+ ep_failure_type
+ );
+
+ parameter g_num_ports = 6;
+
+ reg [15:0] tx_data_invalid[g_num_ports];
+ reg [ 1:0] tx_k_invalid[g_num_ports];
+
+ input clk_sys_i, clk_ref_i,rst_n_i,clk_swc_mpm_core_i;
+ input bit[g_num_ports-1:0] ep_ctrl_i;
+ output cpu_irq;
+ input [15:0] ep_failure_type;
+
+ wire [g_num_ports-1:0] rbclk;
+
+ wire [18 * g_num_ports - 1:0] td, rd;
+
+ typedef struct {
+ logic rst;
+ logic loopen;
+ logic enable;
+ logic syncen;
+ logic [15:0] tx_data;
+ logic [1:0] tx_k;
+ } t_phyif_output;
+
+
+ typedef struct {
+ logic ref_clk;
+ logic tx_disparity;
+ logic tx_enc_err ;
+ logic [15:0] rx_data ;
+ logic rx_clk ;
+ logic [1:0] rx_k ;
+ logic rx_enc_err ;
+ logic rx_bitslide ;
+ } t_phyif_input;
+
+ t_phyif_output phys_out[g_num_ports];
+ t_phyif_input phys_in[g_num_ports];
+
+ WBPacketSource to_port[g_num_ports];
+ WBPacketSink from_port[g_num_ports];
+ int seed2;
+
+ IWishboneMaster #(32, 32) cpu(clk_sys_i, rst_n_i);
+
+ initial
+ begin
+ cpu.settings.cyc_on_stall = 1;
+ cpu.settings.addr_gran = BYTE;
+ end
+
+ reg [g_num_ports-1:0] clk_ref_phys = 0;
+ time periods[g_num_ports];
+
+
+
+
+
+
+ generate
+ genvar i;
+
+
+
+ for(i=0; i<g_num_ports; i++)
+ begin
+
+ // generate sim_PHY only for first/alst port
+ if(i==0 || i == (g_num_ports-1)) begin
+ initial forever #(periods[i]) clk_ref_phys[i] <= ~clk_ref_phys[i];
+ initial periods[i] = 8ns;
+ IWishboneMaster U_ep_wb (clk_sys_i, rst_n_i) ;
+ IWishboneMaster #(2,16) U_ep_src (clk_sys_i, rst_n_i) ;
+ IWishboneSlave #(2,16) U_ep_snk (clk_sys_i, rst_n_i) ;
+
+ wr_endpoint
+ #(
+ .g_simulation (1),
+ .g_pcs_16bit(1),
+ .g_rx_buffer_size (1024),
+ .g_with_rx_buffer (0),
+ .g_with_timestamper (1),
+ .g_with_dpi_classifier (1),
+ .g_with_vlans (1),
+ .g_with_rtu (0)
+ ) DUT (
+ .clk_ref_i (clk_ref_phys[i]),
+ .clk_sys_i (clk_sys_i),
+ .clk_dmtd_i (clk_ref_i),
+ .rst_n_i (rst_n_i),
+ .pps_csync_p1_i (1'b0),
+
+ .phy_rst_o (phys_out[i].rst),
+ .phy_loopen_o (),
+ .phy_enable_o (),
+ .phy_syncen_o (),
+
+ .phy_ref_clk_i (phys_in[i].ref_clk),
+ .phy_tx_data_o (phys_out[i].tx_data),
+ .phy_tx_k_o (phys_out[i].tx_k),
+ .phy_tx_disparity_i (phys_in[i].tx_disparity),
+ .phy_tx_enc_err_i (phys_in[i].tx_enc_err),
+
+ .phy_rx_data_i (phys_in[i].rx_data),
+ .phy_rx_clk_i (phys_in[i].rx_clk),
+ .phy_rx_k_i (phys_in[i].rx_k),
+ .phy_rx_enc_err_i (phys_in[i].rx_enc_err),
+ .phy_rx_bitslide_i (5'b0),
+
+ .src_dat_o (U_ep_snk.slave.dat_i),
+ .src_adr_o (U_ep_snk.slave.adr),
+ .src_sel_o (U_ep_snk.slave.sel),
+ .src_cyc_o (U_ep_snk.slave.cyc),
+ .src_stb_o (U_ep_snk.slave.stb),
+ .src_we_o (U_ep_snk.slave.we),
+ .src_stall_i (U_ep_snk.slave.stall),
+ .src_ack_i (U_ep_snk.slave.ack),
+ .src_err_i(1'b0),
+
+ .snk_dat_i (U_ep_src.master.dat_o[15:0]),
+ .snk_adr_i (U_ep_src.master.adr[1:0]),
+ .snk_sel_i (U_ep_src.master.sel[1:0]),
+ .snk_cyc_i (U_ep_src.master.cyc),
+ .snk_stb_i (U_ep_src.master.stb),
+ .snk_we_i (U_ep_src.master.we),
+ .snk_stall_o (U_ep_src.master.stall),
+ .snk_ack_o (U_ep_src.master.ack),
+ .snk_err_o (U_ep_src.master.err),
+ .snk_rty_o (U_ep_src.master.rty),
+
+ .txtsu_ack_i (1'b1),
+
+ .rtu_full_i (1'b0),
+
+ .wb_cyc_i(U_ep_wb.master.cyc),
+ .wb_stb_i(U_ep_wb.master.stb),
+ .wb_we_i (U_ep_wb.master.we),
+ .wb_sel_i(U_ep_wb.master.sel),
+ .wb_adr_i(U_ep_wb.master.adr[7:0]),
+ .wb_dat_i(U_ep_wb.master.dat_o),
+ .wb_dat_o(U_ep_wb.master.dat_i),
+ .wb_ack_o (U_ep_wb.master.ack),
+
+ // new stuff
+ .pfilter_pclass_o (),
+ .pfilter_drop_o (),
+ .pfilter_done_o (),
+ .fc_tx_pause_req_i (1'b0),
+ .fc_tx_pause_delay_i (16'b0),
+ .fc_tx_pause_ready_o (),
+ .inject_req_i (1'b0),
+ .inject_ready_o (),
+ .inject_packet_sel_i (3'b0),
+ .inject_user_value_i (16'b0),
+ .led_link_o (),
+ .led_act_o (),
+ .link_kill_i ((~ep_ctrl_i[i])),
+// .link_kill_i (1'b0),
+ .link_up_o ()
+
+// .tru_status_o(),
+// .tru_ctrlRd_o(),
+// .tru_rx_pck_o(),
+// .tru_rx_pck_class_o(),
+//
+// .tru_ctrlWr_i(ep_ctrl_i[i]),
+// .tru_tx_pck_i(1'b0),
+// .tru_tx_pck_class_i(8'b0),
+// .tru_pauseSend_i(1'b0),
+// .tru_pauseTime_i(16'b0),
+// .tru_outQueueBlockMask_i(8'b0)
+ );
+
+ initial begin
+ CWishboneAccessor ep_acc;
+ CSimDrv_WR_Endpoint ep_drv;
+
+ U_ep_src.settings.gen_random_throttling = 0;
+ U_ep_snk.settings.gen_random_stalls = 0;
+
+
+ @(posedge rst_n_i);
+ repeat(100) @(posedge clk_sys_i);
+
+ ep_acc = U_ep_wb.get_accessor();
+ ep_drv = new (ep_acc, 0);
+ ep_drv.init(0);
+
+ from_port[i] = new (U_ep_snk.get_accessor());
+ to_port[i] = new (U_ep_src.get_accessor());
+
+
+ end
+ end //if
+ end // for (i=0; i<g_num_ports; i++)
+ endgenerate
+
+
+ generate
+ genvar j;
+
+ //clocks
+ for(j=0;j<g_num_ports;j++) begin
+ assign rbclk[j] = clk_ref_i;// clk_ref_phys[j];
+ end
+
+
+
+ for(j=0;j<g_num_ports;j++) begin // just first and last
+
+ // connect to sim_phy first and last port
+ if(j==0 || j==(g_num_ports-1)) begin
+ assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : tx_data_invalid[j];
+ assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : tx_k_invalid[j];
+
+ // causing transmission error in the driving simulation
+ assign phys_in[j].tx_enc_err = ~ep_ctrl_i[j];
+ ///////////////////////////////////////////////////////
+
+ assign phys_in[j].ref_clk = clk_ref_phys[j];
+ assign phys_in[j].rx_data = rd[18 * j + 15 : 18 * j];
+ assign phys_in[j].rx_k = rd[18 * j + 17 : 18 * j + 16];
+ assign phys_in[j].rx_clk = clk_ref_i;
+ // assign phys_in[j].tx_enc_err = 0;
+ assign phys_in[j].rx_enc_err = 0;
+
+ always@(posedge clk_ref_i) begin : gen_disparity
+ if(phys_out[j].rst)
+ phys_in[j].tx_disparity = 0;
+ else
+ phys_in[j].tx_disparity = f_next_8b10b_disparity16
+ (
+ phys_in[j].tx_disparity,
+ phys_out[j].tx_k,
+ phys_out[j].tx_data);
+ end
+ end
+ end // for
+
+ // interconnct all ports but first/last
+ for(j=1;j<(g_num_ports-2);j=j+2) begin
+ assign td[18 * j + 15 : 18 * j] = rd[18 * (j+1) + 15 : 18 * (j+1)];
+ assign td[18 * j + 17 : 18 * j + 16] = rd[18 * (j+1) + 17 : 18 * (j+1) + 16];
+ assign td[18 * (j+1) + 15 : 18 * (j+1)] = rd[18 * j + 15 : 18 * j];
+ assign td[18 * (j+1) + 17 : 18 * (j+1) + 16] = rd[18 * j + 17 : 18 * j + 16];
+
+ end
+ endgenerate
+
+
+scb_top_sim
+ #(
+ .g_num_ports(g_num_ports)
+ )
+ U_Top
+ (
+ .sys_rst_n_i ( rst_n_i),
+ .clk_startup_i ( clk_sys_i),
+ .clk_ref_i ( clk_ref_i),
+ .clk_dmtd_i ( clk_ref_i),
+// .clk_sys_i ( clk_sys_i),
+ .clk_aux_i ( clk_swc_mpm_core_i),
+ .wb_adr_i ( cpu.master.adr),
+ .wb_dat_i ( cpu.master.dat_o),
+ .wb_dat_o ( cpu.master.dat_i),
+ .wb_cyc_i ( cpu.master.cyc),
+ .wb_sel_i ( cpu.master.sel),
+ .wb_stb_i ( cpu.master.stb),
+ .wb_we_i ( cpu.master.we),
+ .wb_ack_o ( cpu.master.ack),
+ .wb_stall_o ( cpu.master.stall),
+ .wb_irq_o ( cpu_irq ),
+ .pps_i ( 1'b0 ),
+// .pps_o ( pps_o),
+// .dac_helper_sync_n_o ( dac_helper_sync_n_o),
+// .dac_helper_sclk_o ( dac_helper_sclk_o),
+// .dac_helper_data_o ( dac_helper_data_o),
+// .dac_main_sync_n_o ( dac_main_sync_n_o),
+// .dac_main_sclk_o ( dac_main_sclk_o),
+// .dac_main_data_o ( dac_main_data_o),
+// .pll_status_i ( pll_status_i),
+// .pll_mosi_o ( pll_mosi_o),
+// .pll_miso_i ( pll_miso_i),
+// .pll_sck_o ( pll_sck_o),
+// .pll_cs_n_o ( pll_cs_n_o),
+// .pll_sync_n_o ( pll_sync_n_o),
+// .pll_reset_n_o ( pll_reset_n_o),
+// .uart_txd_o ( uart_txd_o),
+// .uart_rxd_i ( uart_rxd_i),
+// .clk_en_o ( clk_en_o),
+// .clk_sel_o ( clk_sel_o),
+ .td_o ( rd),
+ .rd_i ( td),
+ .rbclk_i ( rbclk)
+// .led_link_o ( led_link_o),
+// .led_act_o ( led_act_o);
+ );
+
+
+endmodule // scb_top_sim_svwrap
+
diff --git a/testbench/scb_top/scb_top_sim_svwrap.svh b/testbench/scb_top/scb_top_sim_svwrap.svh
index 779e4accd904a125fbf6a32debb8d107c0f3b649..c1dd85d7f4fb4e399ff5b5625f8254fbdff8733d 100644
--- a/testbench/scb_top/scb_top_sim_svwrap.svh
+++ b/testbench/scb_top/scb_top_sim_svwrap.svh
@@ -45,16 +45,20 @@ module scb_top_sim_svwrap
clk_ref_i,
rst_n_i,
cpu_irq,
- clk_swc_mpm_core_i
+ clk_swc_mpm_core_i,
+ ep_ctrl_i,
+ ep_failure_type
);
parameter g_num_ports = 6;
-
+ reg [15:0] tx_data_invalid[g_num_ports];
+ reg [ 1:0] tx_k_invalid[g_num_ports];
input clk_sys_i, clk_ref_i,rst_n_i,clk_swc_mpm_core_i;
+ input bit[g_num_ports-1:0] ep_ctrl_i;
output cpu_irq;
-
+ input [15:0] ep_failure_type;
wire [g_num_ports-1:0] rbclk;
@@ -130,7 +134,7 @@ module scb_top_sim_svwrap
.g_with_rx_buffer (0),
.g_with_timestamper (1),
.g_with_dpi_classifier (1),
- .g_with_vlans (0),
+ .g_with_vlans (1),
.g_with_rtu (0)
) DUT (
.clk_ref_i (clk_ref_phys[i]),
@@ -188,7 +192,36 @@ module scb_top_sim_svwrap
.wb_adr_i(U_ep_wb.master.adr[7:0]),
.wb_dat_i(U_ep_wb.master.dat_o),
.wb_dat_o(U_ep_wb.master.dat_i),
- .wb_ack_o (U_ep_wb.master.ack)
+ .wb_ack_o (U_ep_wb.master.ack),
+
+ // new stuff
+ .pfilter_pclass_o (),
+ .pfilter_drop_o (),
+ .pfilter_done_o (),
+ .fc_tx_pause_req_i (1'b0),
+ .fc_tx_pause_delay_i (16'b0),
+ .fc_tx_pause_ready_o (),
+ .inject_req_i (1'b0),
+ .inject_ready_o (),
+ .inject_packet_sel_i (3'b0),
+ .inject_user_value_i (16'b0),
+ .led_link_o (),
+ .led_act_o (),
+ .link_kill_i ((~ep_ctrl_i[i])),
+// .link_kill_i (1'b0),
+ .link_up_o ()
+
+// .tru_status_o(),
+// .tru_ctrlRd_o(),
+// .tru_rx_pck_o(),
+// .tru_rx_pck_class_o(),
+//
+// .tru_ctrlWr_i(ep_ctrl_i[i]),
+// .tru_tx_pck_i(1'b0),
+// .tru_tx_pck_class_i(8'b0),
+// .tru_pauseSend_i(1'b0),
+// .tru_pauseTime_i(16'b0),
+// .tru_outQueueBlockMask_i(8'b0)
);
initial begin
@@ -214,25 +247,31 @@ module scb_top_sim_svwrap
end // for (i=0; i<g_num_ports; i++)
endgenerate
-
generate
genvar j;
-
-
-
+
+
for(j=0;j<g_num_ports;j++) begin
assign rbclk[j] = clk_ref_phys[j];
+ ///////////////// nasty hack by Maciej /////////////////
+ // causing sync error in the Switch
+// assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : 'h00BC;
+// assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : 2'b01;
+ assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : tx_data_invalid[j];
+ assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : tx_k_invalid[j];
- assign td[18 * j + 15 : 18 * j] = phys_out[j].tx_data;
- assign td[18 * j + 17 : 18 * j + 16] = phys_out[j].tx_k;
+ // causing transmission error in the driving simulation
+ assign phys_in[j].tx_enc_err = ~ep_ctrl_i[j];
+ ///////////////////////////////////////////////////////
assign phys_in[j].ref_clk = clk_ref_phys[j];
assign phys_in[j].rx_data = rd[18 * j + 15 : 18 * j];
assign phys_in[j].rx_k = rd[18 * j + 17 : 18 * j + 16];
assign phys_in[j].rx_clk = clk_ref_i;
- assign phys_in[j].tx_enc_err = 0;
+// assign phys_in[j].tx_enc_err = 0;
assign phys_in[j].rx_enc_err = 0;
+
always@(posedge clk_ref_i) begin : gen_disparity
if(phys_out[j].rst)
@@ -245,7 +284,34 @@ module scb_top_sim_svwrap
phys_out[j].tx_data);
end
- end
+
+ always@(posedge clk_sys_i) begin
+ integer jj;
+ if(ep_ctrl_i[j] == 1) begin
+ tx_data_invalid[j] = 'h00BC;
+ tx_k_invalid[j] = 2'b01 ;
+ jj = 0;
+ end
+ else begin
+ if(ep_failure_type == 1) begin
+ $display("Link failure type: 1 [generate some random noise, starting with data='h00BC, k = 'b01]");
+ while(jj++<100) begin
+ tx_data_invalid[j] = 'h00BC + jj;
+ tx_k_invalid[j] = 2'b01 & jj;
+ @(posedge clk_sys_i);
+ end
+ tx_data_invalid[j] = 'h00BC;
+ tx_k_invalid[j] = 2'b01 ;
+ end
+ else begin //including 0
+ $display("Link failure type: 0 [simply off the link: data='h00BC, k = 'b01]");
+ tx_data_invalid[j] = 'h00BC;
+ tx_k_invalid[j] = 2'b01 ;
+ end
+ end;
+ end
+
+ end
endgenerate
diff --git a/testbench/scb_top/simdrv_wr_endpoint.svh b/testbench/scb_top/simdrv_wr_endpoint.svh
index db3b08df4fe30ac74fe1d706be56161c3124fc85..f1ef42eb7d06daf8ffe49a65bd2d5b49d242a39c 100644
--- a/testbench/scb_top/simdrv_wr_endpoint.svh
+++ b/testbench/scb_top/simdrv_wr_endpoint.svh
@@ -9,16 +9,115 @@ class CSimDrv_WR_Endpoint;
protected CBusAccessor m_acc;
protected uint64_t m_base;
+ protected uint16_t untag_tab[256];
function new(CBusAccessor acc, uint64_t base);
+ int i;
m_acc = acc;
m_base = base;
+// for(i=0;i<10;i++)
+// untag_tab[i]=0;
endfunction // new
task vlan_egress_untag(int vid, int untag);
- m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
+ uint64_t wval=0;
+ if(untag>0)
+ untag_tab[(vid>>4)] = untag_tab[(vid>>4)] | (1<<('h000F & vid));
+ else
+ untag_tab[(vid>>4)] = untag_tab[(vid>>4)] & ! (1<<('h000F & vid));
+
+ wval = (untag_tab[(vid>>4)] << 10) | ('h000003FF & (vid>>4));
+
+ $display("[vlan_egress_untag], write offset: %d, data: 0x%x (val=0x%x)",
+ (vid>>4),untag_tab[(vid>>4)], wval);
+ m_acc.write(m_base + `ADDR_EP_VCR1, wval);
+
+ // m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
+ endtask // vlan_egress_untag
+
+ task vlan_egress_untag_direct(uint16_t mask, uint16_t addr);
+ uint64_t wval=0;
+ wval = (mask << 10) | ('h000003FF & addr);
+ $display("[vlan_egress_untag], write offset: %d, data: 0x%x ", addr,wval);
+ m_acc.write(m_base + `ADDR_EP_VCR1, wval);
endtask // vlan_egress_untag
+ task vcr1_buffer_write(int is_vlan, int addr, uint64_t data);
+// $display("addr=0x%x , data=0x%x",addr,data);
+ m_acc.write(m_base + `ADDR_EP_VCR1,
+ (((is_vlan ? 0 : 'h200) + addr) << `EP_VCR1_OFFSET_OFFSET)
+ | (data << `EP_VCR1_DATA_OFFSET));
+ endtask // vlan_buffer_write
+
+ task write_template(int slot, byte data[], int user_offset=-1);
+ int i;
+
+ if(data.size() & 1)
+ $fatal("CSimDrv_WR_Endpoint::write_template(): data size must be even");
+
+ if(user_offset >= data.size()-2)
+ $fatal("CSimDrv_WR_Endpoint::write_template(): user_offset cannot be set to the last word of the template");
+
+ if(user_offset & 1)
+ $fatal("CSimDrv_WR_Endpoint::write_template(): user_offset must be even");
+
+
+ $display("write_template: size %d", data.size());
+
+ for(i=0;i<data.size();i+=2)
+ begin
+ uint64_t v = 0;
+
+ v = ((data[i] << 8) | data[i+1]) & 64'h0000FFFF;
+ if(i == 0)
+ v |= (1<<16); // start of template
+ if(i == data.size() - 2)
+ v |= (1<<16); // end of template
+
+ if(i == user_offset)
+ v |= (1<<17);
+
+ vcr1_buffer_write(0, slot * 64 + i/2, v);
+ end
+ endtask // write_template
+
+ task write_inj_gen_frame(byte header[], int frame_size);
+ int i;
+ int slot = 0;
+
+ if(header.size() & 1)
+ $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): header size must be even");
+ if(frame_size < 64)
+ $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): frame size needs to be greater than 64");
+ if(frame_size > 1024)
+ $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): frame size needs to be less than 1024 (to be modified)");
+
+ $display("write_template: size %d",frame_size);
+
+ frame_size = frame_size -4;//CRC which is automaticly suffixed
+ for(i=0;i<frame_size;i+=2)
+ begin
+ uint64_t v = 0;
+ if(i < header.size())
+ v = ((header[i] << 8) | header[i+1]) & 64'h0000FFFF;
+ else
+ v = 0;
+
+ if(i == 0)
+ v |= (1<<16); // start of template
+
+ if((frame_size & 1) && (i == (frame_size - 1))) // end of template with odd size
+ v |= (1<<16) | (1<<17);
+ else if(i == (frame_size - 2)) // end of template with even size
+ v |= (1<<16);
+
+ if(i == header.size())
+ v |= (1<<17); // place for frame ID
+
+ vcr1_buffer_write(0, slot * 64 + i/2, v);
+ end
+ endtask // write_template
+
task pfilter_load_microcode(uint64_t mcode[]);
int i;
@@ -30,14 +129,21 @@ class CSimDrv_WR_Endpoint;
(i << `EP_PFCR0_MM_ADDR_OFFSET) |
(((mcode[i] >> 12) & 'hffffff) << `EP_PFCR0_MM_DATA_MSB_OFFSET) |
`EP_PFCR0_MM_WRITE);
+
+ $display("code_pos=%2d : PFCR0=0x%4x PFCR1=0x%4x ",i,
+ ((i << `EP_PFCR0_MM_ADDR_OFFSET) |
+ (((mcode[i] >> 12) & 'hffffff) << `EP_PFCR0_MM_DATA_MSB_OFFSET) |
+ `EP_PFCR0_MM_WRITE ),
+ ((mcode[i] & 'hfff) << `EP_PFCR1_MM_DATA_LSB_OFFSET));
end
+ $display("pfilter: loaded code [size=%d] ",mcode.size());
endtask // pfilter_load_microcde
task pfilter_enable(int enable);
m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0);
endtask // pfilter_enable
-`define EP_QMODE_VLAN_DISABLED 3
+`define EP_QMODE_VLAN_DISABLED 2
task init(int port_id);
m_acc.write(m_base + `ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN | (port_id << `EP_ECR_PORTID_OFFSET)) ;
@@ -78,6 +184,66 @@ class CSimDrv_WR_Endpoint;
up= (rval & `MDIO_MSR_LSTATUS) ? 1 : 0;
endtask // check_link
+ task automatic vlan_config(int qmode,int fix_prio, int prio_val, int pvid, int prio_map[]);
+ uint64_t wval;
+ int i;
+ wval = (qmode << `EP_VCR0_QMODE_OFFSET ) & `EP_VCR0_QMODE |
+ (fix_prio << `EP_VCR0_FIX_PRIO_OFFSET ) & `EP_VCR0_FIX_PRIO |
+ (prio_val << `EP_VCR0_PRIO_VAL_OFFSET ) & `EP_VCR0_PRIO_VAL |
+ (pvid << `EP_VCR0_PVID_OFFSET ) & `EP_VCR0_PVID;
+
+ m_acc.write(m_base + `ADDR_EP_VCR0, wval);
+ wval = 0;
+ for(i=0;i<8;i++)
+ wval = ('h7 & prio_map[i]) << (i*3) | wval;
+
+ m_acc.write(m_base + `ADDR_EP_TCAR, `EP_TCAR_PCP_MAP & (wval << `EP_TCAR_PCP_MAP_OFFSET));
+
+ $display("VLAN cofig: qmode=%1d, fix_prio=%1d, prio_val=%1d, pvid=%1d, prio_map=%1d-%1d-%1d-%1d-%1d-%1d-%1d-%1d",
+ qmode,fix_prio, prio_val, pvid, prio_map[7],prio_map[6],prio_map[5],prio_map[4],
+ prio_map[3],prio_map[2],prio_map[1],prio_map[0]);
+ endtask // automatic
+
+ task automatic pause_config(int txpause_802_3,int rxpause_802_3, int txpause_802_1q, int rxpause_802_1q);
+ uint64_t wval;
+ wval = (txpause_802_1q << `EP_FCR_TXPAUSE_802_1Q_OFFSET) & `EP_FCR_TXPAUSE_802_1Q | // Tx
+ (rxpause_802_1q << `EP_FCR_RXPAUSE_802_1Q_OFFSET) & `EP_FCR_RXPAUSE_802_1Q | // Rx
+ (txpause_802_3 << `EP_FCR_TXPAUSE_OFFSET ) & `EP_FCR_TXPAUSE | // Tx
+ (rxpause_802_3 << `EP_FCR_RXPAUSE_OFFSET ) & `EP_FCR_RXPAUSE; // Rx
+ m_acc.write(m_base + `ADDR_EP_FCR, wval);
+ $display("PAUSE cofig: tx_802.3 en=%1d, rx_802.3 en=%1d, tx_801.2Q (prio-based)=%1d, rx_802.1Q (prio-based)=%1d",
+ txpause_802_3, rxpause_802_3, txpause_802_1q, rxpause_802_1q);
+ endtask // automatic
+
+ task automatic inject_gen_ctrl_config(int interframe_gap, int sel_id, int mode);
+ uint64_t wval = 0;
+ wval = (interframe_gap << `EP_INJ_CTRL_PIC_CONF_IFG_OFFSET) & `EP_INJ_CTRL_PIC_CONF_IFG |
+ (sel_id << `EP_INJ_CTRL_PIC_CONF_SEL_OFFSET) & `EP_INJ_CTRL_PIC_CONF_SEL |
+ (mode << `EP_INJ_CTRL_PIC_MODE_ID_OFFSET ) & `EP_INJ_CTRL_PIC_MODE_ID_OFFSET |
+ `EP_INJ_CTRL_PIC_CONF_VALID | `EP_INJ_CTRL_PIC_MODE_VALID;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: interframe gap=%1d, pattern sel id=%1d, mode = %1d",interframe_gap,sel_id, mode);
+ endtask // automatic
+ task automatic inject_gen_ctrl_enable();
+ uint64_t wval = 0;
+ wval = `EP_INJ_CTRL_PIC_ENA;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: enabled");
+ endtask // automatic
+ task automatic inject_gen_ctrl_disable();
+ uint64_t wval = 0;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: disabled");
+ endtask // automatic
+
+ task automatic inject_gen_ctrl_mode(int mode );
+ uint64_t wval = 0;
+ wval = (mode << `EP_INJ_CTRL_PIC_MODE_ID_OFFSET ) & `EP_INJ_CTRL_PIC_MODE_ID |
+ `EP_INJ_CTRL_PIC_MODE_VALID | `EP_INJ_CTRL_PIC_ENA;
+ m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+ $display("INJ ctrl cofig: mode = %1d",mode);
+ endtask // automatic
+
endclass // CSimDrv_WR_Endpoint
diff --git a/testbench/swcore/allocator/Manifest.py b/testbench/swcore/allocator/Manifest.py
index d6c75b901ab49a2aa92673989d2f35df34219a18..7d53150af2b7693c5134afa1e8d56e161fafe833 100644
--- a/testbench/swcore/allocator/Manifest.py
+++ b/testbench/swcore/allocator/Manifest.py
@@ -1,7 +1,7 @@
target = "xilinx" # "altera" #
action = "simulation"
-#fetchto = "../../ip_cores"
+fetchto = "../../../ip_cores"
files = [
"main.sv"
@@ -11,8 +11,9 @@ vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/si
modules = {"local":
[
- "../../../ip_cores/wr-cores",
- "../../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/",
- "../../../modules/wrsw_swcore",
+ "../../../",
+ #"../../../ip_cores/wr-cores",
+ #"../../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/",
+ #"../../../modules/wrsw_swcore"
],
}
diff --git a/testbench/swcore/allocator/common.svh b/testbench/swcore/allocator/common.svh
index 0b7f011f48cffd16d14b27765c5d0f2036f77bc7..2fe1c46e8f80610106dd53a34264cf3392723d1a 100644
--- a/testbench/swcore/allocator/common.svh
+++ b/testbench/swcore/allocator/common.svh
@@ -219,6 +219,7 @@ interface IAllocatorPort (input clk_i);
endinterface // IAllocatorPort
+`ifdef dupa1234
typedef virtual IAllocatorPort VIAllocatorPort;
task automatic execute_requests(VIAllocatorPort port, ref alloc_request_t rqs[$], input int verbose =0);
@@ -272,3 +273,4 @@ task automatic execute_requests(VIAllocatorPort port, ref alloc_request_t rqs[$]
endcase // case (rqs[i].t)
end
endtask // execute_requests
+`endif
\ No newline at end of file
diff --git a/testbench/swcore/allocator/main.sv b/testbench/swcore/allocator/main.sv
index 1d412d545ad54234ce03aecd347c7b8c504b6937..2ae2c4fe1453298b198886b189cb8afe2f38e068 100644
--- a/testbench/swcore/allocator/main.sv
+++ b/testbench/swcore/allocator/main.sv
@@ -14,6 +14,7 @@ typedef struct {
int page;
} alloc_request_t;
+
function automatic int first_free(int tab[]);
int i;
diff --git a/testbench/swcore/allocator/run.do b/testbench/swcore/allocator/run.do
index af56b55a0600da032ffddcfb31a0ca57db032959..eda37854a1ae9bf8745a9e411522dac2adf803da 100644
--- a/testbench/swcore/allocator/run.do
+++ b/testbench/swcore/allocator/run.do
@@ -1,5 +1,6 @@
make -f Makefile
-vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim multiport.sv
+# vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim multiport.sv
+vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
diff --git a/testbench/swcore/optimized_allocator/Manifest.py b/testbench/swcore/optimized_allocator/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..19a509d72365e7787c125ce5de79c61057cfcd25
--- /dev/null
+++ b/testbench/swcore/optimized_allocator/Manifest.py
@@ -0,0 +1,16 @@
+target = "xilinx" # "altera" #
+action = "simulation"
+
+fetchto = "../../../ip_cores"
+
+files = [
+ "main.sv"
+ ]
+
+vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/sim/fabric_emu"
+
+modules = {"local":
+ [
+ "../../../"
+ ],
+ }
diff --git a/testbench/swcore/optimized_allocator/common.svh b/testbench/swcore/optimized_allocator/common.svh
new file mode 100644
index 0000000000000000000000000000000000000000..ac91f1b988f3eda7dfad2924374167b2e03c4ead
--- /dev/null
+++ b/testbench/swcore/optimized_allocator/common.svh
@@ -0,0 +1,289 @@
+
+typedef enum
+ {
+ ALLOC,
+ FREE,
+ FORCE_FREE,
+ SET_USECOUNT
+ } alloc_req_type_t ;
+
+typedef struct {
+ alloc_req_type_t t;
+ int use_count;
+ int id, origin;
+ int page;
+ time t_event;
+} alloc_request_t;
+
+function automatic int first_free(int tab[]);
+ int i;
+
+ for(i=0;i<tab.size;i++)
+ if(tab[i] < 0)
+ return i;
+endfunction // first_free
+
+
+
+function automatic int lookup_origin_page(ref alloc_request_t rqs[$], int id);
+ foreach(rqs[i])
+ begin
+ if(rqs[i].id == id)
+ begin
+ // $display("Found t%d page %d\n", rqs[i].t, rqs[i].page);
+
+ return rqs[i].page;
+ end
+
+ end
+ $fatal("ID Not found: %i", id);
+endfunction // lookup_origin_page
+
+
+task automatic count_occupied_pages(ref alloc_request_t rqs[$], ref int peak, output int occupied, input int up_to=0, int verbose=0, int reserve_pages=1);
+ int i, n =0;
+ int page_table[1024]; /* fixme: this is ugly */
+ int pages_allocated = 0;
+ string s = "";
+
+
+ peak = 0;
+
+ if(!up_to)
+ up_to = rqs.size() - 1;
+
+ for(i=0;i<1024;i++) page_table[i] = -1;
+ // $display("----\n");
+
+ for(i=0;i<=up_to;i++)
+ begin
+ case(rqs[i].t)
+ ALLOC:begin
+ int page = reserve_pages?first_free(page_table) : rqs[i].page;
+ rqs[i].page = page;
+ page_table[page] = rqs[i].use_count;
+ pages_allocated++;
+ if(verbose) $display("%d : alloc %d [cnt=%d, used=%d]",i, rqs[i].page, rqs[i].use_count, pages_allocated);
+
+ end
+ SET_USECOUNT: begin
+ int page = reserve_pages?lookup_origin_page(rqs, rqs[i].origin):rqs[i].page;
+ if(verbose) $display("%d : set_ucnt %d [cnt=%d]", i, page, rqs[i].use_count);
+ page_table[page] = rqs[i].use_count;
+ end
+ FREE: begin
+ int page = reserve_pages?lookup_origin_page(rqs, rqs[i].origin):rqs[i].page;
+
+ if(page_table[page] < 0)
+ $fatal("attempt to free a free page\n");
+
+ page_table[page]--;
+ if(!page_table[page])
+ begin
+ page_table[page] = -1;
+ pages_allocated--;
+ end
+
+ if(verbose) $display("%d : free %d, used = %d", i, page, pages_allocated);
+
+ end
+
+ FORCE_FREE:begin
+ int page = reserve_pages?lookup_origin_page(rqs, rqs[i].origin):rqs[i].page;
+
+ page_table[page] = -1;
+ pages_allocated--;
+ if(verbose) $display("%d : force_free %d, used = %d", i, page, pages_allocated);
+
+ end
+ endcase // case (rqs[i].t)
+
+ if(pages_allocated > peak) peak = pages_allocated;
+
+ end
+
+
+ for(i=0;i<1024;i++) begin
+ if(page_table[i] >= 0) begin
+ n++;
+ $sformat(s, "%s %-1d", s, i);
+ end
+ end
+
+ if(verbose) $display("Pages occupied after test: %s", s);
+
+ occupied = n;
+endtask // count_occupied_pages
+
+
+function automatic int my_dist_uniform(ref int seed, input int start, int _end);
+ if(start >= _end)
+ return start;
+
+ return $dist_uniform(seed, start, _end);
+endfunction // my_dist_uniform
+
+
+
+
+task automatic gen_random_requests(ref alloc_request_t rqs[$], input int n, int seed, int max_occupied_pages = 0, int max_use_count = 3);
+ int i;
+ static int uniq_id = 0;
+ int temp_page = 0;
+
+
+ for(i=0;i<=n;i++)
+ begin
+ alloc_request_t rq;
+
+ int orig_id = uniq_id++;
+ int j;
+ int use_count = my_dist_uniform(seed, 0, max_use_count);
+ int orig_idx;
+ int idx, peak, occupied;
+
+ idx = my_dist_uniform(seed, 0, rqs.size()-1);
+
+ orig_idx = idx;
+
+ // $display("Gen %d", i);
+
+ rq.t = ALLOC;
+ rq.id = orig_id;
+ rq.use_count = use_count;
+
+ rqs.insert(idx, rq);
+
+
+
+
+ if(!use_count) /* Insert a "set use count" command somewhere after the allocation request */
+ begin
+ int idx = my_dist_uniform(seed, orig_idx + 1, rqs.size()), peak, occupied;
+ // $display("InsertUseCnt page=%d at=%d",temp_page-1, idx);
+
+ rq.t = SET_USECOUNT;
+ rq.origin = orig_id;
+ rq.id = -1;
+ use_count = my_dist_uniform(seed, 1, max_use_count);
+ rq.use_count = use_count;
+ rqs.insert(idx, rq);
+ orig_idx = idx;
+ end
+
+ for(j=0; j<use_count;j++)
+ begin
+ orig_idx = my_dist_uniform(seed, orig_idx + 1, rqs.size());
+ rq.t = FREE;
+ rq.id = -1 ;
+ rq.origin = orig_id;
+
+ if(my_dist_uniform(seed, 1, 100) < 20)
+ begin
+ rq.t = FORCE_FREE;
+ end
+
+ // $display("Insertidx: %d size %d", idx, rqs.size());
+
+ rqs.insert(orig_idx, rq);
+ if(rq.t == FORCE_FREE)
+ break;
+ end // for (j=0; j<use_count;j++)
+
+ temp_page++;
+
+ end
+endtask // gen_random_requests
+
+
+interface IAllocatorPort (input clk_i);
+
+ // make sure they are the same as in the main one
+ parameter g_page_addr_width= 10;
+ parameter g_usecnt_width = 5;
+
+ logic alloc=0, free=0, force_free=0, set_usecnt=0, done;
+ logic alloc_done, free_done, force_free_done, set_usecnt_done;
+ logic free_last_usecnt;
+ logic no_mem;
+
+
+ logic [g_page_addr_width-1:0] pg_addr_free;
+ logic [g_page_addr_width-1:0] pg_addr_force_free;
+ logic [g_page_addr_width-1:0] pg_addr_usecnt;
+ logic [g_page_addr_width-1:0] pg_addr_alloc, pg_addr_muxed;
+ logic [g_usecnt_width-1:0] usecnt;
+
+ assign pg_addr_muxed = free ? pg_addr_free :
+ force_free ? pg_addr_force_free :
+ pg_addr_usecnt;
+
+endinterface // IAllocatorPort
+
+// `ifdef dupa1234
+typedef virtual IAllocatorPort VIAllocatorPort;
+
+task automatic execute_requests(VIAllocatorPort port, ref alloc_request_t rqs[$], input int verbose =0);
+
+ int i,j=0, idx;
+ for(idx=0;idx<rqs.size();idx++)
+ begin
+// if(port.no_mem) begin
+// while(rqs[idx+j].t == ALLOC && idx+j < rqs.size())
+// j++;
+// while(rqs[idx+j].origin > rqs[idx].id && idx+j < rqs.size())
+// j++;
+// end
+// i = idx+j;
+ i = idx;
+// $display("Request id=%d", i);
+ case(rqs[i].t)
+ ALLOC: begin
+ port.alloc <= 1;
+ port.usecnt <= rqs[i].use_count;
+
+ @(posedge port.clk_i);
+ while(!port.done) @(posedge port.clk_i);
+ port.alloc <= 0;
+ rqs[i].page = port.pg_addr_alloc;
+ if(verbose)$display("Alloc [id=%-1d, usecount=%-1d, page=%-1d]", rqs[i].id, rqs[i].use_count, rqs[i].page);
+ end
+
+ SET_USECOUNT:begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose) $display("Set_Usecount [origin=%-1d, usecount=%-1d, page=%-1d]", rqs[i].origin, rqs[i].use_count, rqs[i].page);
+ port.pg_addr_usecnt <= rqs[i].page;
+ port.usecnt <= rqs[i].use_count;
+ port.set_usecnt <= 1;
+ @(posedge port.clk_i);
+ while(!port.done) @(posedge port.clk_i);
+ port.set_usecnt <= 0;
+ end
+
+ FREE: begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose)$display("Free [origin=%-1d, page=%-1d]", rqs[i].origin, rqs[i].page);
+ port.pg_addr_free <= rqs[i].page;
+ port.free <= 1;
+ @(posedge port.clk_i);
+ while(!port.done) @(posedge port.clk_i);
+ port.free <= 0;
+// if(idx != i) rqs.delete(i); //delete executed command (so that we don't repeat later)
+ end
+
+ FORCE_FREE: begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose)$display("Forced Free [origin=%-1d, page=%-1d]", rqs[i].origin, rqs[i].page);
+ port.pg_addr_force_free <= rqs[i].page;
+ port.force_free <= 1;
+ @(posedge port.clk_i);
+ while(!port.done) @(posedge port.clk_i);
+ port.force_free <= 0;
+// if(idx != i) rqs.delete(i); //delete executed command (so that we don't repeat later)
+ end
+
+ endcase // case (rqs[i].t)
+// @(posedge port.clk_i);
+ end
+ endtask // execute_requests
+// `endif
\ No newline at end of file
diff --git a/testbench/swcore/optimized_allocator/main.sv b/testbench/swcore/optimized_allocator/main.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b5620ed32b0a4ea828fa9ab073437830b20dd098
--- /dev/null
+++ b/testbench/swcore/optimized_allocator/main.sv
@@ -0,0 +1,557 @@
+
+typedef enum
+ {
+ ALLOC,
+ FREE,
+ FORCE_FREE,
+ SET_USECOUNT
+ } alloc_req_type_t ;
+
+typedef struct {
+ alloc_req_type_t t; // request type
+ int use_count;// use count
+ int id; //
+ int origin; //
+ int page; // page_num_index
+ int port_id; // id of port made the requested
+} alloc_request_t;
+
+//return the index of the first free page (eq: -1)
+function automatic int first_free(int tab[]);
+ int i;
+ for(i=0;i<tab.size;i++)
+ if(tab[i] < 0)
+ return i;
+endfunction // first_free
+
+//
+function automatic int lookup_origin_page(ref alloc_request_t rqs[$], int id);
+ foreach(rqs[i])
+ begin
+ if(rqs[i].id == id)
+ return rqs[i].page;
+ end
+ $fatal("ID Not found: %i", id);
+endfunction // lookup_origin_page
+
+
+task automatic count_occupied_pages(ref alloc_request_t rqs[$], ref int peak, output int occupied, input int up_to=0, int verbose=0);
+ int i, n =0;
+ int page_table[1024]; /* fixme: this is ugly */
+ int pages_allocated = 0;
+
+
+ peak = 0;
+
+ if(!up_to)
+ up_to = rqs.size() - 1;
+
+ for(i=0;i<1024;i++) page_table[i] = -1;
+
+ for(i=0;i<=up_to;i++)
+ begin
+ case(rqs[i].t)
+ ALLOC:begin
+ int page = first_free(page_table);
+ rqs[i].page = page;
+ page_table[page] = rqs[i].use_count;
+ pages_allocated++;
+ if(verbose) $display("%d : alloc %d [cnt=%d, used=%d]",i, rqs[i].page, rqs[i].use_count, pages_allocated);
+ end
+ SET_USECOUNT: begin
+ int page = lookup_origin_page(rqs, rqs[i].origin);
+ page_table[page] = rqs[i].use_count;
+ if(verbose) $display("%d : set_ucnt %d [cnt=%d]", i, page, rqs[i].use_count);
+ end
+ FREE: begin
+ int page = lookup_origin_page(rqs, rqs[i].origin);
+ if(page_table[page] < 0)
+ $fatal("attempt to free a free page\n");
+ page_table[page]--;
+ if(!page_table[page])
+ begin
+ page_table[page] = -1;
+ pages_allocated--;
+ end
+ if(verbose) $display("%d : free %d, used = %d", i, page, pages_allocated);
+ end
+ FORCE_FREE:begin
+ int page = lookup_origin_page(rqs, rqs[i].origin);
+ page_table[page] = -1;
+ pages_allocated--;
+ if(verbose) $display("%d : force_free %d, used = %d", i, page, pages_allocated);
+ end
+ endcase // case (rqs[i].t)
+
+ //check the max accolcated page
+ if(pages_allocated > peak) peak = pages_allocated;
+ end
+
+ for(i=0;i<1024;i++) if(page_table[i] >= 0) n++;
+ occupied = n;
+endtask // count_occupied_pages
+
+function automatic int my_dist_uniform(ref int seed, input int start, int _end);
+ if(start >= _end)
+ return start;
+
+ return $dist_uniform(seed, start, _end);
+endfunction // my_dist_uniform
+
+// fill in fifo/queue with different requrests (which make sense) -> WOW
+task automatic gen_random_requests(ref alloc_request_t rqs[$], input int n, int seed, int max_occupied_pages = 0, int max_use_count = 3, int max_port_num=18);
+ int i;
+ static int uniq_id = 0;
+ int temp_page = 0;
+
+ for(i=0;i<=n;i++)
+ begin
+ alloc_request_t rq;
+
+ int orig_id = uniq_id++;
+ int j;
+ int use_count = my_dist_uniform(seed, 0, max_use_count);
+ int orig_idx;
+ int idx, peak, occupied;
+
+ idx = my_dist_uniform(seed, 0, rqs.size()-1);
+// $display("idx = %d", idx);
+
+ orig_idx = idx;
+
+ // $display("Gen %d", i);
+
+ rq.t = ALLOC;
+ rq.id = orig_id;
+ rq.use_count = use_count;
+ rq.port_id = i;// my_dist_uniform(seed, 0, max_port_num-1);
+
+ rqs.insert(idx, rq);
+ if(!use_count) /* Insert a "set use count" command somewhere after the allocation request */
+ begin
+ int idx = my_dist_uniform(seed, orig_idx + 1, rqs.size()), peak, occupied;
+ // $display("InsertUseCnt page=%d at=%d",temp_page-1, idx);
+
+ rq.t = SET_USECOUNT;
+ rq.origin = orig_id;
+ rq.id = -1;
+ use_count = my_dist_uniform(seed, 1, max_use_count);
+ rq.use_count = use_count;
+ rqs.insert(idx, rq);
+ orig_idx = idx;
+ end
+ for(j=0; j<use_count;j++)
+ begin
+ orig_idx = my_dist_uniform(seed, orig_idx + 1, rqs.size());
+ rq.t = FREE;
+ rq.id = -1 ;
+ rq.origin = orig_id;
+
+ if(my_dist_uniform(seed, 1, 100) < 20)
+ begin
+ rq.t = FORCE_FREE;
+ end
+ rqs.insert(orig_idx, rq);
+ if(rq.t == FORCE_FREE)
+ break;
+ end // for (j=0; j<use_count;j++)
+ temp_page++;
+ end
+endtask // gen_random_requests
+
+task automatic gen_simple_requests(ref alloc_request_t rqs[$], input int max_port_num=18);
+ int i;
+ // req_typ ,usecnt, id, origin, page,port_id
+ alloc_request_t rq[] = '{'{ALLOC , 1 , 0 , 0 , 0 , 0},
+ '{ALLOC , 0 , 1 , 0 , 0 , 1},
+ '{SET_USECOUNT, 3 , 2 , 1 , 1 , 2},
+ '{ALLOC , 0 , 3 , 0 , 0 , 3},
+ '{FREE , 0 , 4 , 1 , 1 , 4},
+ '{ALLOC , 3 , 5 , 0 , 0 , 5},
+ '{FORCE_FREE , 0 , 6 , 1 , 1 , 6},
+ '{ALLOC , 3 , 7 , 0 , 0 , 7},
+ '{FREE , 0 , 8 , 0 , 0 , 8},
+ '{FREE , 0 , 9 , 5 , 0 , 8},
+ '{FREE , 0 , 9 , 5 , 0 , 8},
+ '{FREE , 0 , 9 , 5 , 0 , 8}
+ };
+ for(i=0;i<rq.size();i++)
+ rqs.insert(i, rq[i]);
+
+endtask // gen_random_requests
+
+
+interface IAllocatorPort (input clk_i);
+
+ parameter g_page_addr_width = 10;
+ parameter g_usecnt_width = 4;
+ parameter g_num_ports = 18;
+
+ logic alloc=0, free=0, force_free=0, set_usecnt=0, done;
+ logic alloc_done, free_done, force_free_done, set_usecnt_done;
+ logic free_last_usecnt;
+ logic no_mem;
+
+
+ logic [g_page_addr_width-1:0] pg_addr_free;
+ logic [g_page_addr_width-1:0] pg_addr_force_free;
+ logic [g_page_addr_width-1:0] pg_addr_usecnt;
+ logic [g_page_addr_width-1:0] pg_addr_alloc, pg_addr_muxed;
+ logic [g_num_ports -1:0] pg_addr_req_vec;
+ logic [g_num_ports -1:0] pg_addr_rsp_vec;
+ logic [g_usecnt_width -1:0] usecnt;
+
+ assign pg_addr_muxed = free ? pg_addr_free :
+ force_free ? pg_addr_force_free :
+ 'hx;
+
+// assign pg_addr_muxed = free ? pg_addr_free :
+// force_free ? pg_addr_force_free :
+// pg_addr_usecnt;
+
+endinterface // IAllocatorPort
+
+typedef virtual IAllocatorPort VIAllocatorPort;
+
+task automatic execute_requests(VIAllocatorPort port, ref alloc_request_t rqs[$], input int space=0, input int verbose =0);
+
+ fork
+ begin // make requets
+ automatic int i;
+ for(i=0;i<rqs.size();i++)
+ begin
+
+ port.pg_addr_req_vec <= rqs[i].port_id;
+
+ case(rqs[i].t)
+ ALLOC: begin
+ port.alloc <= 1;
+ port.usecnt <= rqs[i].use_count;
+ @(posedge port.clk_i);
+ port.alloc <= 0;
+ port.usecnt <= 32'hx;
+ if(verbose)$display("REQ[%-1d]: Alloc [id=%-1d, usecount=%-1d, port_id==%-1d]", i, rqs[i].id, rqs[i].use_count, rqs[i].port_id);
+ end
+
+ SET_USECOUNT:begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose) $display("REQ[%-1d]: Set_Usecount [origin=%-1d, usecount=%-1d, port_id==%-1d, page=%-1d]", i, rqs[i].origin, rqs[i].use_count, rqs[i].port_id, rqs[i].page);
+ port.pg_addr_usecnt <= rqs[i].page;
+ port.usecnt <= rqs[i].use_count;
+ port.set_usecnt <= 1;
+ @(posedge port.clk_i);
+ port.pg_addr_usecnt <= 32'hx;
+ port.usecnt <= 32'hx;
+ port.set_usecnt <= 0;
+ end
+
+ FREE: begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose)$display("REQ[%-1d]: Free [origin=%-1d, port_id==%-1d, page=%-1d]", i, rqs[i].origin, rqs[i].port_id, rqs[i].page);
+ port.pg_addr_free <= rqs[i].page;
+ port.free <= 1;
+ @(posedge port.clk_i);
+ port.free <= 0;
+ port.pg_addr_free <= 32'hx;
+ end
+
+ FORCE_FREE: begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose)$display("REQ[%-1d]: Forced Free [origin=%-1d, port_id==%-1d, page=%-1d]", i,rqs[i].origin, rqs[i].port_id, rqs[i].page);
+ port.pg_addr_force_free <= rqs[i].page;
+ port.force_free <= 1;
+ @(posedge port.clk_i);
+ port.force_free <= 0;
+ port.pg_addr_force_free <= 32'hx;
+ end
+
+ endcase // case (rqs[i].t)
+ if(space)
+ repeat(space) @(posedge port.clk_i);
+ end
+ end // finish thread for with requets
+ begin // start thread with respoinses
+ automatic int j;
+ for(j=0;j<rqs.size();j++)
+ begin
+
+ while(!port.done)
+ begin
+ $display("wait [page=%-1d, done=%-1d, port_id==%-1d]", port.pg_addr_alloc,port.done, port.pg_addr_rsp_vec );
+ @(posedge port.clk_i);
+ end
+ $display("end wait [page=%-1d, done=%-1d, port_id==%-1d]", port.pg_addr_alloc,port.done, port.pg_addr_rsp_vec );
+ if(rqs[j].port_id != port.pg_addr_rsp_vec)
+ $display("RSP[%-1d]: Response for wrong port [pg_addr_rsp_vec (port_id) should be 0x%x but is 0x%x]", j, rqs[j].id, rqs[j].port_id, rqs[j].port_id);
+ case(rqs[j].t)
+ ALLOC: begin
+ rqs[j].page = port.pg_addr_alloc;
+ if(verbose)$display("RSP[%-1d]: Alloc [id=%-1d, usecount=%-1d, port_id==%-1d, page=%-1d]", j, rqs[j].id, rqs[j].use_count, rqs[j].port_id, rqs[j].page);
+ end
+
+ SET_USECOUNT:begin
+ if(verbose) $display("RSP[%-1d]: Set_Usecount [origin=%-1d, usecount=%-1d, port_id==%-1d, page=%-1d]", j, rqs[j].origin, rqs[j].use_count, rqs[j].port_id, rqs[j].page);
+ end
+
+ FREE: begin
+ if(verbose)$display("RSP[%-1d]: Free [origin=%-1d, port_id==%-1d, page=%-1d, free_last=%-1d]", j, rqs[j].origin, rqs[j].port_id, rqs[j].page, port.free_last_usecnt);
+ end
+
+ FORCE_FREE: begin
+ if(verbose)$display("REQ[%-1d]: Forced Free [origin=%-1d, port_id==%-1d, page=%-1d]", j,rqs[j].origin, rqs[j].port_id, rqs[j].page);
+ end
+
+ endcase // case (rqs[i].t)
+ end
+ end // finish thread with respoinses
+ join
+
+
+ endtask // execute_requests
+
+
+task automatic execute_requests_2(VIAllocatorPort port, ref alloc_request_t rqs[$], input int space=0, input int verbose =0);
+
+ int i=0,j=0;
+ int wait_space = space;
+ int origin_d0 = -1;
+ int origin_d1 = -1;
+
+ while(j<rqs.size()) begin
+
+ if(wait_space == space && i<rqs.size()) begin
+
+
+ if(rqs[i].t == ALLOC) begin
+ origin_d1 = origin_d0;
+ origin_d0 = rqs[i].id;
+ end
+ else begin
+ if((origin_d0 == rqs[i].origin || origin_d1 == rqs[i].origin) && space < 3) begin
+ if(verbose) $display("enforce space because origin=%-1d is the same as previous [d0=%-1d or d1=%-1d] ", rqs[i].origin, origin_d0, origin_d1);
+ wait_space = 3;
+ origin_d1 = -1;
+ origin_d0 = -1;
+ end
+ else begin
+ origin_d1 = origin_d0;
+ origin_d0 = -1;
+ end
+ end
+ end
+
+ if(port.done) begin
+// if(rqs[j].port_id != port.pg_addr_rsp_vec)
+ if(j != port.pg_addr_rsp_vec)
+ $display("RSP[%-1d]: Response for wrong port [pg_addr_rsp_vec (port_id) should be 0x%x but is 0x%x]", j, rqs[j].id, rqs[j].port_id, rqs[j].port_id);
+ else begin
+ case(rqs[j].t)
+ ALLOC: begin
+ rqs[j].page = port.pg_addr_alloc;
+ if(verbose) $display("RSP[%-1d]: Alloc [id=%-1d, usecount=%-1d, port_id==%-1d, page=%-1d]", j, rqs[j].id, rqs[j].use_count, rqs[j].port_id, rqs[j].page);
+ end
+
+ SET_USECOUNT:begin
+ if(verbose) $display("RSP[%-1d]: Set_Usecount [origin=%-1d, usecount=%-1d, port_id==%-1d, page=%-1d]", j, rqs[j].origin, rqs[j].use_count, rqs[j].port_id, rqs[j].page);
+ end
+
+ FREE: begin
+ if(verbose) $display("RSP[%-1d]: Free [origin=%-1d, port_id==%-1d, page=%-1d, free_last=%-1d]", j, rqs[j].origin, rqs[j].port_id, rqs[j].page, port.free_last_usecnt);
+ end
+
+ FORCE_FREE: begin
+ if(verbose) $display("RSP[%-1d]: Forced Free [origin=%-1d, port_id==%-1d, page=%-1d]", j,rqs[j].origin, rqs[j].port_id, rqs[j].page);
+ end
+ endcase // case (rqs[i].t)
+ end //else begin
+ j++;
+ end //if(port.done) begin
+
+ if(wait_space == space && i<rqs.size()) begin
+
+ port.pg_addr_req_vec <= i;
+ case(rqs[i].t)
+ ALLOC: begin
+ port.alloc <= 1;
+ port.usecnt <= rqs[i].use_count;
+ if(verbose) $display("REQ[%-1d]: Alloc [id=%-1d, usecount=%-1d, port_id==%-1d]", i, rqs[i].id, rqs[i].use_count, rqs[i].port_id);
+ end
+
+ SET_USECOUNT:begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose) $display("REQ[%-1d]: Set_Usecount [origin=%-1d, usecount=%-1d, port_id==%-1d, page=%-1d]", i, rqs[i].origin, rqs[i].use_count, rqs[i].port_id, rqs[i].page);
+ port.pg_addr_usecnt <= rqs[i].page;
+ port.usecnt <= rqs[i].use_count;
+ port.set_usecnt <= 1;
+ end
+
+ FREE: begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose) $display("REQ[%-1d]: Free [origin=%-1d, port_id==%-1d, page=%-1d]", i, rqs[i].origin, rqs[i].port_id, rqs[i].page);
+ port.pg_addr_free <= rqs[i].page;
+ port.free <= 1;
+ end
+
+ FORCE_FREE: begin
+ rqs[i].page = lookup_origin_page(rqs, rqs[i].origin);
+ if(verbose) $display("REQ[%-1d]: Forced Free [origin=%-1d, port_id==%-1d, page=%-1d]", i,rqs[i].origin, rqs[i].port_id, rqs[i].page);
+ port.pg_addr_force_free <= rqs[i].page;
+ port.force_free <= 1;
+ end
+ endcase // case (rqs[i].t)
+ i++;
+ end //if(wait == space) begin
+
+
+
+ @(posedge port.clk_i);
+
+ port.alloc <= 0;
+ port.usecnt <= 32'hx;
+ port.pg_addr_usecnt <= 32'hx;
+ port.usecnt <= 32'hx;
+ port.set_usecnt <= 0;
+ port.free <= 0;
+ port.pg_addr_free <= 32'hx;
+ port.force_free <= 0;
+ port.pg_addr_force_free <= 32'hx;
+
+ if(wait_space)
+ wait_space--;
+ else
+ wait_space = space ;
+ end // for(i=0;i<rqs.size();i++) begin
+ endtask // execute_requests
+
+
+
+module main;
+
+
+ reg clk = 0;
+ reg rst_n = 0;
+
+ IAllocatorPort alloc_port (clk);
+ VIAllocatorPort valloc_port = alloc_port;
+
+ assign alloc_port.set_usecnt_done = alloc_port.done;
+ assign alloc_port.alloc_done = alloc_port.done;
+ assign alloc_port.free_done = alloc_port.done;
+ assign alloc_port.force_free_done = alloc_port.done;
+
+
+ swc_page_allocator_new
+ #(
+ .g_num_pages (1024),
+ .g_page_addr_width (alloc_port.g_page_addr_width),
+ .g_num_ports (alloc_port.g_num_ports),
+ .g_usecount_width (alloc_port.g_usecnt_width)
+ ) DUT (
+ .clk_i (clk),
+ .rst_n_i (rst_n),
+ .alloc_i (alloc_port.alloc),
+ .free_i(alloc_port.free),
+ .force_free_i(alloc_port.force_free),
+ .set_usecnt_i(alloc_port.set_usecnt),
+ .usecnt_set_i(alloc_port.usecnt),
+ .usecnt_alloc_i(alloc_port.usecnt),
+ .pgaddr_free_i(alloc_port.pg_addr_muxed),
+ .pgaddr_usecnt_i(alloc_port.pg_addr_usecnt),
+ .req_vec_i(alloc_port.pg_addr_req_vec),
+ .rsp_vec_o(alloc_port.pg_addr_rsp_vec),
+ .pgaddr_o(alloc_port.pg_addr_alloc),
+ .free_last_usecnt_o (alloc_port.free_last_usecnt),
+ .done_o (alloc_port.done),
+ .nomem_o (alloc_port.no_mem)
+ );
+
+ const int MAX_USE_COUNT=3;
+ int uniq_id = 0;
+
+/*
+ * wait ncycles
+ */
+ task automatic wait_cycles;
+ input [31:0] ncycles;
+ begin : wait_body
+ integer i;
+ for(i=0;i<ncycles;i=i+1) @(posedge clk);
+ end
+ endtask // wait_cycles
+
+
+ always #5ns clk <= ~clk;
+ initial begin
+ repeat(3) @(posedge clk);
+ rst_n = 1;
+ end
+
+
+ initial begin
+ alloc_request_t rqs[$], simple_rqs[$];
+ int seed;
+ int repeat_n = 8; // 100000
+ int requests_num = 10;
+
+ while(!rst_n) @(posedge clk);
+
+//seed;
+
+ rst_n <= 0;
+ @(posedge clk);
+ rst_n <= 1;
+ @(posedge clk);
+
+ while(DUT.initializing)
+ @(posedge clk);
+
+ wait_cycles(50);
+
+// simple_rqs = '{};
+// gen_simple_requests(simple_rqs, 18);
+// execute_requests_2(valloc_port, simple_rqs, 3, 1); // 3 cycles between requests
+//
+// wait_cycles(30);
+//
+// execute_requests_2(valloc_port, simple_rqs, 0, 1); // no cycles between requests
+//
+// wait_cycles(50);
+
+ for(seed = 0; seed < repeat_n; seed++)
+ begin
+ automatic int init_seed = seed;
+ int occupied, peak;
+
+ rst_n <= 0;
+ @(posedge clk);
+ rst_n <= 1;
+ @(posedge clk);
+
+ while(DUT.initializing)
+ @(posedge clk);
+
+ wait_cycles(50);
+
+ rqs = '{};
+ gen_random_requests(rqs, requests_num, init_seed, 1000);
+ count_occupied_pages(rqs, peak, occupied, rqs.size()-1, 0);
+
+ //$display("Pages occupied after test: %-1d, peak page usage %-1d", occupied, peak);
+
+
+ execute_requests_2(valloc_port, rqs, 0 /*space*/, 0 /*verbose*/);
+ #1;
+
+ $display("AtTheEnd: free_blocks = %-1d", DUT.free_pages);
+ if(DUT.free_pages != 1023) break;
+
+ if(requests_num < 1000)
+ requests_num = 10* requests_num;
+ else
+ requests_num = 2000;
+
+
+ end
+ end // initial begin
+
+endmodule // main
diff --git a/testbench/swcore/optimized_allocator/multiport.sv b/testbench/swcore/optimized_allocator/multiport.sv
new file mode 100644
index 0000000000000000000000000000000000000000..565b15406efeef0fe570cbefca38146941ada60e
--- /dev/null
+++ b/testbench/swcore/optimized_allocator/multiport.sv
@@ -0,0 +1,159 @@
+`timescale 1ns/1ns
+
+`include "common.svh"
+
+module main;
+
+ // make sure they are the same as in the interface
+ `define c_num_ports 7
+ `define c_page_addr_width 10
+ `define c_use_count_width 5
+
+ reg clk = 0;
+ reg rst_n = 0;
+ int page_cnt = 0;
+
+ IAllocatorPort
+ #(
+ .g_page_addr_width (`c_page_addr_width),
+ .g_usecnt_width (`c_use_count_width)) alloc_port[`c_num_ports] (clk) ;
+ VIAllocatorPort valloc_port[`c_num_ports] = alloc_port;
+
+
+ genvar i;
+
+ wire [`c_num_ports-1:0] alloc_v, free_v, force_free_v, set_usecnt_v;
+ wire [`c_num_ports-1:0] alloc_done_v, free_done_v, force_free_done_v, set_usecnt_done_v;
+ wire [`c_num_ports * `c_page_addr_width - 1 : 0] pgaddr_free_v, pgaddr_force_free_v, pgaddr_usecnt_v;
+ wire [`c_num_ports * `c_use_count_width - 1 : 0] usecnt_set_v;
+ wire [`c_num_ports * `c_use_count_width - 1 : 0] usecnt_alloc_v;
+ wire [`c_page_addr_width-1:0] pg_addr_alloc;
+ wire pg_nomem;
+
+
+ generate
+ for(i=0;i<`c_num_ports;i++)
+ begin
+
+ assign alloc_v[i] = alloc_port[i].alloc;
+ assign free_v[i] = alloc_port[i].free;
+ assign force_free_v[i] = alloc_port[i].force_free;
+ assign set_usecnt_v[i] = alloc_port[i].set_usecnt;
+ assign alloc_port[i].done = (alloc_done_v[i] | free_done_v[i] | force_free_done_v[i] | set_usecnt_done_v[i]);
+ assign alloc_port[i].pg_addr_alloc = pg_addr_alloc;
+ assign alloc_port[i].no_mem = pg_nomem;
+ assign pgaddr_free_v[(i+1) * `c_page_addr_width - 1: i * `c_page_addr_width] = alloc_port[i].pg_addr_free;
+ assign pgaddr_force_free_v[(i+1) * `c_page_addr_width - 1: i * `c_page_addr_width] = alloc_port[i].pg_addr_force_free;
+ assign pgaddr_usecnt_v[(i+1) * `c_page_addr_width - 1: i * `c_page_addr_width] = alloc_port[i].pg_addr_usecnt;
+ assign usecnt_set_v[(i+1) * `c_use_count_width - 1 : i * `c_use_count_width]=alloc_port[i].usecnt;
+ assign usecnt_alloc_v[(i+1) * `c_use_count_width - 1 : i * `c_use_count_width]=alloc_port[i].usecnt;
+ end
+
+ endgenerate
+
+
+
+
+ swc_multiport_page_allocator
+ #(
+ .g_page_num (1024),
+ .g_page_addr_width (`c_page_addr_width),
+ .g_num_ports (`c_num_ports),
+ .g_usecount_width (`c_use_count_width)
+ ) DUT (
+ .clk_i (clk),
+ .rst_n_i (rst_n),
+
+ .alloc_i (alloc_v),
+ .free_i(free_v),
+ .force_free_i(force_free_v),
+ .set_usecnt_i(set_usecnt_v),
+
+ .alloc_done_o(alloc_done_v),
+ .free_done_o(free_done_v),
+ .force_free_done_o(force_free_done_v),
+ .set_usecnt_done_o(set_usecnt_done_v),
+
+ .pgaddr_free_i(pgaddr_free_v),
+ .pgaddr_force_free_i(pgaddr_force_free_v),
+ .pgaddr_usecnt_i(pgaddr_usecnt_v),
+// .usecnt_i(usecnt_v),
+ .usecnt_set_i(usecnt_set_v),
+ .usecnt_alloc_i(usecnt_alloc_v),
+
+ .pgaddr_alloc_o(pg_addr_alloc),
+ .nomem_o(pg_nomem)
+ );
+
+ const int MAX_USE_COUNT=3;
+ int uniq_id = 0;
+
+
+
+ always #8ns clk <= ~clk;
+ initial begin
+ repeat(3) @(posedge clk);
+ rst_n = 1;
+ end
+
+ task automatic test_port(VIAllocatorPort port, int initial_seed, int n_seeds, int n_requests);
+
+ alloc_request_t rqs[$];
+ int seed;
+
+ for(seed = initial_seed; seed < initial_seed + n_seeds; seed++)
+ begin
+ automatic int init_seed = seed;
+ int occupied, peak;
+
+ rqs = '{};
+ gen_random_requests(rqs, n_requests, init_seed, 100 /*max_page_occ*/, 17 /*usecnt*/);
+ count_occupied_pages(rqs, peak, occupied, rqs.size()-1);
+ $display("Peak Page Usage: %d\n", peak);
+
+ execute_requests(port, rqs, 0);
+ end
+ endtask // test_port
+
+ initial begin
+ int port_idx;
+
+ while(!rst_n) @(posedge clk);
+ repeat(3000) @(posedge clk);// initializign
+
+ for(port_idx=0;port_idx < `c_num_ports; port_idx++)
+ fork
+ automatic int k_idx = port_idx;
+ test_port(valloc_port[k_idx], k_idx * 100 /*initial seed*/, 10/*100 n_seed*/, 200/*200 requets*/);
+ join_none
+
+ repeat(100000) @(posedge clk);
+
+ $display("free_blocks = %-1d vs. page_cnt = %-1d", DUT.ALLOC_CORE.free_pages, page_cnt);
+ if(DUT.ALLOC_CORE.free_blocks != 1023)
+ $fatal("Pages missing");
+
+ end // initial begin
+
+
+ initial begin
+
+ while(!rst_n) @(posedge clk);
+
+ page_cnt = DUT.ALLOC_CORE.free_pages;
+
+ forever begin
+ if(DUT.ALLOC_CORE.alloc_req_d1.alloc)
+ page_cnt = page_cnt-1;
+ else if(DUT.ALLOC_CORE.alloc_req_d1.f_free)
+ page_cnt=page_cnt+1;
+ else if(DUT.pg_free_last_usecnt)
+ page_cnt=page_cnt+1;
+ @(posedge clk);
+// $display("free_blocks = %-1d vs. page_cnt = %-1d", DUT.ALLOC_CORE.free_pages, page_cnt);
+ end
+
+
+ end // initial begin
+
+endmodule // main
diff --git a/testbench/swcore/optimized_allocator/run-multiport.do b/testbench/swcore/optimized_allocator/run-multiport.do
new file mode 100644
index 0000000000000000000000000000000000000000..2891c4e52a857af28b1475ec764422c0dd319653
--- /dev/null
+++ b/testbench/swcore/optimized_allocator/run-multiport.do
@@ -0,0 +1,12 @@
+make -f Makefile
+vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim multiport.sv
+
+vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave-multiport.do
+radix -hexadecimal
+run 60us
+wave zoomfull
+radix -hexadecimal
\ No newline at end of file
diff --git a/testbench/swcore/optimized_allocator/run.do b/testbench/swcore/optimized_allocator/run.do
new file mode 100644
index 0000000000000000000000000000000000000000..9d92fea8d0c9e12e6b7e238aed8699d4b4d3efce
--- /dev/null
+++ b/testbench/swcore/optimized_allocator/run.do
@@ -0,0 +1,12 @@
+make -f Makefile
+vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
+
+vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 1000us
+wave zoomfull
+radix -hexadecimal
\ No newline at end of file
diff --git a/testbench/swcore/swc_core_generic.sv b/testbench/swcore/swc_core_generic.sv
index 810ff1ee5528b6450f5122a43a8241fd1695068d..f178e8e9a333b77c68bcddd6bbd00fd69eff54cc 100644
--- a/testbench/swcore/swc_core_generic.sv
+++ b/testbench/swcore/swc_core_generic.sv
@@ -57,7 +57,7 @@
`include "allocator/common.svh"
-//`define DBG_ALLOC //if defined, the allocation debugging is active: we track the number of allocated
+`define DBG_ALLOC //if defined, the allocation debugging is active: we track the number of allocated
//and de-allocated pages
typedef struct {
@@ -223,15 +223,20 @@ module main_generic;
//pkt.set_size(100);
q.push_back(pkt);
+ //set_rtu_rsp(port,1 /*valid*/,drop /*drop*/,prio /*prio*/,mask /*mask*/);
// fork
// begin
src[port].send(pkt);
// end
// begin
// automatic int tmp_rtu_wait = (77*((global_seed*100)/3))%400 ;
- wait_cycles(tmp_rtu_wait);
- $display("rtu wait: %4d cycles",tmp_rtu_wait);
- set_rtu_rsp(port,1 /*valid*/,drop /*drop*/,prio /*prio*/,mask /*mask*/);
+
+
+ //wait_cycles(tmp_rtu_wait);
+ //$display("rtu wait: %4d cycles",tmp_rtu_wait);
+
+
+ set_rtu_rsp(port,1 /*valid*/,drop /*drop*/,prio /*prio*/,mask /*mask*/);
// end
// join
if(dbg) $display("Sent @ port_%1d to mask=0x%x [with prio=%1d, drop=%1d ]!", port, mask, prio, drop);
@@ -424,8 +429,11 @@ module main_generic;
EthPacketGenerator gen;
int j;
int n_ports = `c_num_ports;
- int mask_opt=1;
- int n_packets =500;
+ //int mask_opt=0; // sent to "random" ports;
+ int mask_opt=1;// send to the same port (one);
+ //int mask_opt=2;// send to N+1 port (one);
+ //int mask_opt=3;// send to port 0;
+ int n_packets =200; //200
// initialization
initPckSrcAndSink(src, sink, n_ports);
gen = new;
@@ -434,108 +442,188 @@ module main_generic;
@(posedge rst_n);
@(posedge clk);
- wait_cycles(500);
+ wait_cycles(600);
// for(j=0;j<30;j++)
// send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 1 /*mask*/);
//for(j=0;j<`c_num_ports;j++) begin
- //U_wrf_sink[0].permanent_stall_enable();
+ U_wrf_sink[0].permanent_stall_enable();
+
+ U_wrf_sink[0].settings.gen_random_stalls = 0;
+ U_wrf_sink[1].settings.gen_random_stalls = 0;
+ U_wrf_sink[2].settings.gen_random_stalls = 0;
+ U_wrf_sink[3].settings.gen_random_stalls = 0;
+ U_wrf_sink[4].settings.gen_random_stalls = 0;
+ U_wrf_sink[5].settings.gen_random_stalls = 0;
+ U_wrf_sink[6].settings.gen_random_stalls = 0;
-
//////////////////////////////////////////////////////////////////////////////////////////////////
fork
begin
automatic int p = 0;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
//automatic bit [`c_num_ports:0] mask;
for(int z=0; z<n_packets; z++) begin
- //if(mask_opt == 0)
+ if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
- // else
- // mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
+ else
+ $display("wrong mask_opt");
+
+ prio = (z%8);
+ if (prio == 7) prio = 7;
+ else if(prio == 6) prio = 2;
+ else prio = 0;
+ send_random_packet(src,txed, p, 0, prio, mask);
end
end
+
begin
automatic int p = 1;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
//automatic bit [`c_num_ports:0] mask;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ $display("wrong mask_opt");
+ prio = (z%8);
+ if (prio == 7) prio = 7;
+ else if(prio == 6) prio = 2;
+ else prio = 0;
+ send_random_packet(src,txed, p, 0, prio , mask);
end
end
-
+
begin
automatic int p = 2;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ $display("wrong mask_opt");
+ mask = 4;
+ prio = (z%8);
+ send_random_packet(src,txed, p, 0,prio , mask);
end
end
begin
automatic int p = 3;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ $display("wrong mask_opt");
+ prio = (z%8);
+ send_random_packet(src,txed, p, 0,prio , mask);
end
end
begin
automatic int p = 4;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ $display("wrong mask_opt");
+ prio = (z%8);
+ send_random_packet(src,txed, p, 0,prio , mask);
end
end
begin
automatic int p = 5;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ $display("wrong mask_opt");
+ prio = (z%8);
+ send_random_packet(src,txed, p, 0,prio , mask);
end
end
+
begin
automatic int p = 6;
automatic bit [`c_num_ports:0] mask;
+ automatic bit [`c_num_ports:0] prio;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
- send_random_packet(src,txed, p, 0,7 , mask);
+ $display("wrong mask_opt");
+ prio = (z%8);
+ send_random_packet(src,txed, p, 0,prio , mask);
end
end
+ /*
begin
automatic int p = 7;
automatic bit [`c_num_ports:0] mask;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -545,8 +633,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -556,8 +650,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -567,8 +667,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -578,8 +684,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -589,8 +701,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -600,8 +718,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -611,8 +735,14 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
end
@@ -622,11 +752,18 @@ module main_generic;
for(int z=0; z<n_packets; z++) begin
if(mask_opt == 0)
mask = mask^(1<<(z%(`c_num_ports)));
+ else if (mask_opt == 1)
+ mask = (1<<((p)%(`c_num_ports)));
+ else if (mask_opt == 2)
+ mask = (1<<((p+1)%(`c_num_ports)));
+ else if (mask_opt == 3)
+ mask = 1;
else
- mask = (1<<(p%(`c_num_ports)));
+ $display("wrong mask_opt");
send_random_packet(src,txed, p, 0,7 , mask);
end
- end
+ end
+*/
join_any
//////////////////////////////////////////////////////////////////////////////////////////////////
@@ -644,13 +781,13 @@ module main_generic;
*/
-`define MMU DUT_xswcore_wrapper.DUT_swc_core.xswcore.memory_management_unit
+ `define MMU DUT_xswcore_wrapper.DUT_swc_core.xswcore.memory_management_unit
`define MMUC DUT_xswcore_wrapper.DUT_swc_core.xswcore.memory_management_unit.alloc_core
- wait_cycles(1000);
- // U_wrf_sink[0].permanent_stall_disable();
+ wait_cycles(7000);
+ U_wrf_sink[0].permanent_stall_disable();
- wait_cycles(40000);
+ wait_cycles(80000);
transferReport(); // here we wait for all pcks to be received and then make statistics
memoryLeakageReport();
@@ -788,22 +925,24 @@ module main_generic;
- always @(posedge clk) if(`MMU.pg_alloc & `MMU.pg_done)
+ always @(posedge clk) if(`MMU.pg_alloc != 0 && `MMU.pg_done != 0)
begin
int address;
int usecnt;
+ int port;
- usecnt = `MMU.pg_usecnt;
+ usecnt = `MMU.pg_usecnt;
+ port = `MMU.in_sel;
- // wait(`MMU.pg_addr_valid);
+ wait_cycles(2);
+ address = `MMU.pg_addr_alloc;
- address = `MMU.pgaddr_alloc_o;
pg_alloc_cnt[address][pg_alloc_cnt[address][0]+1]= usecnt;
pg_alloc_cnt[address][0]++;
alloc_table[address].usecnt[alloc_table[address].cnt] = usecnt;
- alloc_table[address].port[alloc_table[address].cnt] = 0;//onehot2int(`MMU.in_sel;
+ alloc_table[address].port[alloc_table[address].cnt] = port;
alloc_table[address].cnt++;
end
diff --git a/testbench/swcore/swc_core_wrapper_7ports.vhd b/testbench/swcore/swc_core_wrapper_7ports.vhd
index 1417ff1e8c3d7f356097a84e67a7d8b069a7cf15..a48650a49b5e40cd338198d4f033e947e3233e90 100644
--- a/testbench/swcore/swc_core_wrapper_7ports.vhd
+++ b/testbench/swcore/swc_core_wrapper_7ports.vhd
@@ -252,12 +252,13 @@ begin
U_xswc_core: xswc_core
generic map(
g_prio_num => 8,
+ g_output_queue_num => 8,
g_max_pck_size => 10 * 1024,
g_max_oob_size => 3,
g_num_ports => 7,
g_pck_pg_free_fifo_size => ((65536/64)/2) ,
g_input_block_cannot_accept_data => "drop_pck",
- g_output_block_per_prio_fifo_size => 64,
+ g_output_block_per_queue_fifo_size => 64,
g_wb_data_width => 16,
g_wb_addr_width => 2,
@@ -268,7 +269,8 @@ U_xswc_core: xswc_core
g_mpm_page_size => 64,
g_mpm_ratio => 2,
g_mpm_fifo_size => 4,
- g_mpm_fetch_next_pg_in_advance => false
+ g_mpm_fetch_next_pg_in_advance => false,
+ g_drop_outqueue_head_on_full => true
)
port map(
clk_i => clk_i,
diff --git a/testbench/swcore/swc_core_wrapper_generic.svh b/testbench/swcore/swc_core_wrapper_generic.svh
index 3568bf4663cf7f227198ad176c796e890e1b673f..8dae3d589a5290b8a648a16a735932a64cd824dc 100644
--- a/testbench/swcore/swc_core_wrapper_generic.svh
+++ b/testbench/swcore/swc_core_wrapper_generic.svh
@@ -58,12 +58,13 @@ module swc_core_wrapper_generic
swc_core
#(
.g_prio_num (`c_prio_num),
+ .g_output_queue_num (`c_output_queue_num),
.g_max_pck_size (`c_max_pck_size),
.g_max_oob_size (`c_max_oob_size),
.g_num_ports (`c_num_ports),
.g_pck_pg_free_fifo_size (`c_pck_pg_free_fifo_size),
.g_input_block_cannot_accept_data (`c_input_block_cannot_accept_data),
- .g_output_block_per_prio_fifo_size (`c_output_block_per_prio_fifo_size),
+ .g_output_block_per_queue_fifo_size (`c_output_block_per_queue_fifo_size),
.g_wb_data_width (`c_wb_data_width),
.g_wb_addr_width (`c_wb_addr_width),
@@ -74,7 +75,8 @@ module swc_core_wrapper_generic
.g_mpm_page_size (`c_mpm_page_size),
.g_mpm_ratio (`c_mpm_ratio),
.g_mpm_fifo_size (`c_mpm_fifo_size),
- .g_mpm_fetch_next_pg_in_advance (`c_mpm_fetch_next_pg_in_advance)
+ .g_mpm_fetch_next_pg_in_advance (`c_mpm_fetch_next_pg_in_advance),
+ .g_drop_outqueue_head_on_full (`c_drop_outqueue_head_on_full)
) DUT_swc_core(
.clk_i (clk_i),
.clk_mpm_core_i (clk_mpm_core_i),
diff --git a/testbench/swcore/swc_param_defs.svh b/testbench/swcore/swc_param_defs.svh
index edddaba3610b78077234fc75858e27dbda7d00da..666cec15cb8ee12247d5bd4f4eb71c33618482cc 100644
--- a/testbench/swcore/swc_param_defs.svh
+++ b/testbench/swcore/swc_param_defs.svh
@@ -25,6 +25,7 @@
////////////////////////////////////////////////////////////////
`define c_prio_num 8 // c_swc_output_prio_num, [does not work, output block]
+`define c_output_queue_num 8 // number of output queues,
`define c_max_pck_size 10 * 1024 // 10kB -- c_swc_max_pck_size,
`define c_max_oob_size 3 // max size of OOB or USER data
@@ -33,6 +34,7 @@
`define c_mpm_ratio 4
`define c_mpm_fifo_size 4
`define c_mpm_fetch_next_pg_in_advance 0
+`define c_drop_outqueue_head_on_full 1
// these are hard-coded into testbench
`define c_wb_data_width 16 //c_swc_data_width,
@@ -42,7 +44,7 @@
`define c_pck_pg_free_fifo_size ((65536/64)/2) //c_swc_freeing_fifo_size,
`define c_input_block_cannot_accept_data "drop_pck" //"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
-`define c_output_block_per_prio_fifo_size 64 //c_swc_output_fifo_size,
+`define c_output_block_per_queue_fifo_size 16 //c_swc_output_fifo_size,
`define array_copy(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
diff --git a/testbench/tru/Manifest.py b/testbench/tru/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..627fe4699f7e8777ed2bdf44442a82bbf5768e69
--- /dev/null
+++ b/testbench/tru/Manifest.py
@@ -0,0 +1,17 @@
+target = "xilinx" # "altera" #
+action = "simulation"
+
+
+
+files = [
+ "tru.sv"
+ ]
+
+vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
+
+modules = {"local":
+ [
+ "../../modules/wrsw_tru",
+ "../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/"
+ ],
+ }
\ No newline at end of file
diff --git a/testbench/tru/run.do b/testbench/tru/run.do
new file mode 100644
index 0000000000000000000000000000000000000000..abd0101211ba8b4dddb9ca497f63a2126ef8680a
--- /dev/null
+++ b/testbench/tru/run.do
@@ -0,0 +1,11 @@
+make -f Makefile
+
+vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 100us
+wave zoomfull
+radix -hexadecimal
diff --git a/testbench/tru/simdrv_wr_tru.svh b/testbench/tru/simdrv_wr_tru.svh
new file mode 100644
index 0000000000000000000000000000000000000000..6268be8149eb04827782ac5cd13db55fb5883d41
--- /dev/null
+++ b/testbench/tru/simdrv_wr_tru.svh
@@ -0,0 +1,129 @@
+`ifndef __SIMDRV_WR_TRU_SVH
+`define __SIMDRV_WR_TRU_SVH 1
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "tru_wb_regs.v"
+
+class CSimDrv_WR_TRU;
+
+ protected CBusAccessor m_acc;
+ protected uint64_t m_base;
+
+ function new(CBusAccessor acc, uint64_t base);
+ m_acc = acc;
+ m_base = base;
+ endfunction // new
+
+ task write_tru_tab(int valid, int fid, int subfid,
+ int patrn_mask, int patrn_match, int patrn_mode,
+ int ports_mask, int ports_egress, int ports_ingress);
+
+ m_acc.write(m_base + `ADDR_TRU_TTR1, ports_ingress);
+ m_acc.write(m_base + `ADDR_TRU_TTR2, ports_egress);
+ m_acc.write(m_base + `ADDR_TRU_TTR3, ports_mask);
+ m_acc.write(m_base + `ADDR_TRU_TTR4, patrn_match);
+ m_acc.write(m_base + `ADDR_TRU_TTR5, patrn_mask);
+ // write
+ m_acc.write(m_base + `ADDR_TRU_TTR0, fid << `TRU_TTR0_FID_OFFSET |
+ subfid << `TRU_TTR0_SUB_FID_OFFSET |
+ valid << `TRU_TTR0_MASK_VALID_OFFSET |
+ patrn_mode << `TRU_TTR0_PATRN_MODE_OFFSET |
+ 1 << `TRU_TTR0_UPDATE_OFFSET );
+ endtask;
+
+ task transition_config(int mode, int rx_id, int prio, int time_diff,
+ int port_a_id, int port_b_id);
+
+ m_acc.write(m_base +`ADDR_TRU_TCGR, mode << `TRU_TCGR_TRANS_MODE_OFFSET |
+ rx_id << `TRU_TCGR_TRANS_RX_ID_OFFSET |
+ prio << `TRU_TCGR_TRANS_PRIO_OFFSET |
+ time_diff << `TRU_TCGR_TRANS_TIME_DIFF_OFFSET);
+
+ m_acc.write(m_base +`ADDR_TRU_TCPR, port_a_id << `TRU_TCPR_TRANS_PORT_A_ID_OFFSET |
+ 1 << `TRU_TCPR_TRANS_PORT_A_VALID_OFFSET |
+ port_b_id << `TRU_TCPR_TRANS_PORT_B_ID_OFFSET |
+ 1 << `TRU_TCPR_TRANS_PORT_B_VALID_OFFSET);
+ endtask;
+
+ task transition_enable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_TCGR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_TCGR, tmp | 1 << `TRU_TCGR_TRANS_ENA_OFFSET);
+ endtask;
+
+ task transition_disable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_TCGR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_TCGR, tmp & ! (1 << `TRU_TCGR_TRANS_ENA_OFFSET));
+ endtask;
+
+ task transition_clear();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_TCGR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_TCGR, tmp & 1 << `TRU_TCGR_TRANS_CLEAR_OFFSET);
+ endtask;
+
+ task pattern_config(int replacement, int addition);
+ m_acc.write(m_base +`ADDR_TRU_MCR, replacement << `TRU_MCR_PATTERN_MODE_REP_OFFSET |
+ addition << `TRU_MCR_PATTERN_MODE_ADD_OFFSET);
+ endtask;
+
+ task tru_enable();
+ m_acc.write(m_base + `ADDR_TRU_GCR, 1 << `TRU_GCR_G_ENA_OFFSET);
+ endtask;
+
+ task tru_swap_bank();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_GCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_GCR, tmp | 1 << `TRU_GCR_TRU_BANK_OFFSET);
+ endtask;
+
+ task tru_rx_frame_reset(int reset_rx);
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_GCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_GCR, tmp | reset_rx << `TRU_GCR_RX_FRAME_RESET_OFFSET);
+ endtask;
+
+ task rt_reconf_config(int tx_frame_id, int rx_frame_id, int mode);
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp & 'h000F |
+ mode << `TRU_RTRCR_RTR_MODE_OFFSET |
+ rx_frame_id << `TRU_RTRCR_RTR_RX_OFFSET |
+ tx_frame_id << `TRU_RTRCR_RTR_TX_OFFSET );
+ endtask;
+
+ task rt_reconf_enable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp | 1 << `TRU_RTRCR_RTR_ENA_OFFSET);
+ endtask;
+
+ task rt_reconf_disable();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp | !(1 << `TRU_RTRCR_RTR_ENA_OFFSET));
+ endtask;
+
+ task rt_reconf_reset();
+ uint64_t tmp;
+ m_acc.read(m_base + `ADDR_TRU_RTRCR, tmp, 4);
+ m_acc.write(m_base +`ADDR_TRU_RTRCR, tmp | 1 << `TRU_RTRCR_RTR_RESET_OFFSET);
+ endtask;
+
+ task read_status(output int bank, output int ports_up, output int ports_stb_up);
+ uint64_t tmp;
+
+ m_acc.read(m_base + `ADDR_TRU_GSR0, tmp, 4);
+ bank = (tmp & `TRU_GSR0_STAT_BANK) >> `TRU_GSR0_STAT_BANK_OFFSET;
+ ports_stb_up = (tmp & `TRU_GSR0_STAT_STB_UP) >> `TRU_GSR0_STAT_STB_UP_OFFSET;
+
+ m_acc.read(m_base + `ADDR_TRU_GSR1, tmp, 4);
+ ports_up = (tmp & `TRU_GSR1_STAT_UP) >> `TRU_GSR1_STAT_UP_OFFSET;
+
+ endtask;
+
+endclass // CSimDrv_WR_TRU
+
+`endif // `ifndef __SIMDRV_WR_TRU_SVH
diff --git a/testbench/tru/tru.sv b/testbench/tru/tru.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d65dac0e8c94ae9d95443c0bf4f2d7d4694d8642
--- /dev/null
+++ b/testbench/tru/tru.sv
@@ -0,0 +1,854 @@
+`timescale 1ns/1ps
+
+`include "if_wb_master.svh"
+`include "simdrv_wr_tru.svh"
+
+`define array_copy(a, ah, al, b, bl) \
+ for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
+
+ `define c_num_ports 8
+ `define c_tru_addr_width 8
+ `define c_tru_subentry_num 8
+ `define c_tru_subentry_width (1+5*`c_num_ports+`c_pattern_mode_width) //49 //(3*24+3*8+1)
+ `define c_patternID_width 4
+ `define c_pattern_mode_width 4 // needs to be the same as num_port
+ `define c_stableUP_treshold 100 // numbers of cycles after which port is assumed to be stably UP
+ `define c_pclass_number 8
+ `define c_pause_delay_width 16
+ `define c_swc_max_queue_number 8
+ `define c_fid_width 8
+ `define c_mac_addr_width 48
+ `define c_tru2ep_record_width (3+`c_pclass_number+`c_pause_delay_width+`c_swc_max_queue_number)
+ `define c_ep2tru_record_width (3+`c_pclass_number)
+ `define c_rtu2tru_record_width (3*`c_num_ports+`c_num_ports*`c_prio_width)
+ `define c_tru_req_record_width (1+2*`c_mac_addr_width+`c_fid_width+2+`c_num_ports)
+ `define c_tru_resp_record_width (1+`c_num_ports+1+`c_num_ports)
+ `define c_tru_tab_size 256 // max 256
+ `define c_vlan_tab_size 2048
+ `define c_mt_trans_max_fr_cnt 1000
+ `define c_prio_width 3
+
+typedef struct packed {
+ bit has_prio;
+ bit[ 2:0] prio;
+ bit prio_override;
+ bit drop;
+ bit[ 7:0] fid;
+ bit[`c_num_ports-1:0] port_mask;
+} vlan_tab_entry_p_s;
+
+typedef struct packed {
+ bit[`c_num_ports-1 :0] reqMask;
+ bit isBR;
+ bit isHP;
+ bit[ 7:0] fid;
+ bit[47:0] dmac;
+ bit[47:0] smac;
+ bit valid;
+} tru_req_p_s;
+
+typedef struct packed {
+ bit[`c_num_ports-1 :0] respMask;
+ bit drop;
+ bit[`c_num_ports-1 :0] portMask;
+ bit valid;
+} tru_resp_p_s;
+
+typedef struct packed {
+ bit[`c_num_ports-1:0] rxFrameMaskReg;
+ bit[`c_num_ports-1:0] rxFrameMask;
+ bit[`c_num_ports-1:0] portStateMask;
+} tru_endpoint_p_s;
+
+typedef struct packed {
+ bit[`c_prio_width-1:0][`c_num_ports-1:0] priorities;
+ bit[`c_num_ports-1:0] request_valid;
+ bit[`c_num_ports-1:0] forward_bpdu_only;
+ bit[`c_num_ports-1:0] pass_all;
+} tru_rtu_p_s;
+
+
+typedef struct packed {
+ bit[`c_pclass_number-1:0] rx_pck_class;
+ bit rx_pck;
+ bit ctrlRd;
+ bit status;
+} tru_ep2tru_p_s;
+
+typedef struct packed {
+ bit[`c_swc_max_queue_number-1:0] outQueueBlockMask;
+ bit[`c_pause_delay_width-1:0] pauseTime;
+ bit pauseSend;
+ bit[`c_pclass_number-1:0] tx_pck_class;
+ bit tx_pck;
+ bit ctrlWr;
+} tru_tru2ep_p_s;
+
+
+module main;
+
+ genvar kk;
+ reg clk = 0;
+ reg rst_n = 0;
+
+ reg nasty_one_bit = 0;
+
+ reg [`c_tru_req_record_width-1: 0] tru_req;
+ tru_req_p_s t_req;
+
+ wire[`c_tru_resp_record_width-1 : 0] tru_resp;
+ tru_resp_p_s t_resp;
+
+ reg[`c_rtu2tru_record_width-1:0] tru_rtu;
+ tru_rtu_p_s t_rtu;
+
+ reg[`c_num_ports*`c_ep2tru_record_width-1:0] tru_ep2tru;
+ tru_ep2tru_p_s[`c_num_ports-1:0] t_ep2tru;
+
+ wire[`c_num_ports*`c_tru2ep_record_width-1:0] tru_tru2ep;
+ tru_tru2ep_p_s[`c_num_ports-1:0] t_tru2ep;
+
+ wire[`c_num_ports-1:0] tru_swc2tru;
+
+ IWishboneMaster #(32, 32) U_tru_wb (clk, rst_n) ;
+
+ wrsw_tru_wb
+ #(
+ .g_num_ports (`c_num_ports),
+ .g_tru_subentry_num (`c_tru_subentry_num),
+ .g_tru_subentry_width (`c_tru_subentry_width),
+// .g_tru_addr_width (`c_tru_addr_width),
+ .g_pattern_mode_width (`c_pattern_mode_width),
+ .g_patternID_width (`c_patternID_width),
+ .g_stableUP_treshold (`c_stableUP_treshold),
+ .g_pclass_number (`c_pclass_number),
+ .g_tru2ep_record_width (`c_tru2ep_record_width),
+ .g_ep2tru_record_width (`c_ep2tru_record_width),
+ .g_rtu2tru_record_width (`c_rtu2tru_record_width),
+ .g_tru_req_record_width (`c_tru_req_record_width),
+ .g_tru_resp_record_width (`c_tru_resp_record_width),
+ .g_mt_trans_max_fr_cnt (`c_mt_trans_max_fr_cnt),
+ .g_prio_width (`c_prio_width),
+ .g_tru_entry_num (`c_tru_tab_size)
+ ) DUT (
+ .clk_i (clk),
+ .rst_n_i (rst_n),
+ .tru_req_i (tru_req),
+ .tru_resp_o (tru_resp),
+ .rtu_i (tru_rtu),
+ .ep_i (tru_ep2tru),
+ .ep_o (tru_tru2ep),
+ .swc_o (tru_swc2tru),
+
+ .wb_addr_i (U_tru_wb.master.adr[5:0]),
+ .wb_data_i (U_tru_wb.master.dat_o),
+ .wb_data_o (U_tru_wb.master.dat_i),
+ .wb_cyc_i (U_tru_wb.master.cyc),
+ .wb_sel_i (U_tru_wb.master.sel),
+ .wb_stb_i (U_tru_wb.master.stb),
+ .wb_we_i (U_tru_wb.master.we),
+ .wb_ack_o (U_tru_wb.master.ack)
+ );
+
+ initial
+ begin
+// U_tru_wb.settings.cyc_on_stall = 1;
+ U_tru_wb.settings.addr_gran = BYTE;
+ end
+
+ assign tru_req = t_req;
+ assign t_resp = tru_resp;
+ assign tru_rtu = t_rtu;
+ assign tru_ep2tru = t_ep2tru;
+ assign t_tru2ep = tru_tru2ep;
+ /*
+ * wait ncycles
+ */
+ task automatic wait_cycles;
+ input [31:0] ncycles;
+ begin : wait_body
+ integer i;
+ for(i=0;i<ncycles;i=i+1) @(posedge clk);
+ end
+ endtask // wait_cycles
+
+ // simulate endpoint ctrl
+ always @(posedge clk) //@(posedge clk)
+ begin
+ integer i;
+ for(i=0;i<`c_num_ports;i++) begin
+ t_ep2tru[i].ctrlRd = t_tru2ep[i].ctrlWr;
+ end;
+ end
+
+ // track responses from TRU -> print info
+ always @(posedge clk) if(t_resp.valid == 1)
+ begin
+ integer i, cnt;
+ cnt=0;
+ for (i=0;i<`c_num_ports;i++)
+ if(t_resp.respMask[i] == 1) break;
+ else cnt++;
+
+ if(t_resp.drop == 1) $display("Resp @ port %2d: drop\n",cnt);
+ else $display("Resp @ port %2d: pass, %b [0x%x]\n",cnt,t_resp.portMask,t_resp.portMask);
+ end
+
+ // track HW-sent frames
+ generate
+ genvar i;
+ for(i=0; i<`c_num_ports; i++) begin
+ always @(posedge clk) if(t_tru2ep[i].tx_pck == 1)
+ begin
+ $display("TRU -> EP[%2d]: Send WR-generated frame [class = %bd]",i, t_tru2ep[i].tx_pck_class);
+ end
+ always @(posedge clk) if(t_tru2ep[i].pauseSend == 1)
+ begin
+ $display("TRU -> EP[%2d]: Send WR-generated pause [pauseTime = %2d us]",i, t_tru2ep[i].pauseTime);
+ end
+ always @(posedge t_tru2ep[i].ctrlWr)
+ begin
+ $display("TRU -> EP[%2d]: ON",i);
+ end
+ always @(negedge t_tru2ep[i].ctrlWr)
+ begin
+ $display("TRU -> EP[%2d]: OFF",i);
+ end
+ always @(posedge t_tru2ep[i].outQueueBlockMask)
+ begin
+ integer j, cnt;
+ cnt = 0;
+ for (j=0;j<`c_num_ports;j++)
+ if(t_tru2ep[i].outQueueBlockMask[j] == 1) break;
+ else cnt++;
+ $display("TRU -> SWcore [%2d]: block outque %2d",i, cnt);
+ end
+ end
+ endgenerate;
+
+ // print detailed info about output mask decision process
+ `define dut_port DUT.X_TRU.U_T_PORT
+ always @(posedge clk) if(DUT.X_TRU.U_T_PORT.s_valid_d0 == 1)
+ begin
+ integer i, cnt;
+ $display("\tMATCH USED inputs: patterns{replacement[mode=0] = 0x%x, addition[mode=1]= 0x%x}, state{portsUp=%b, rx_frame_reg=%b}",
+ `dut_port.s_patternRep_d0,
+ `dut_port.s_patternAdd_d0,
+ `dut_port.endpoints_i.status,
+ `dut_port.endpoints_i.rxFrameMaskReg[`dut_port.ADD_PATTERN.rxFrameNumber],);
+ $display("\t-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------");
+ for(i=0;i<`dut_port.g_tru_subentry_num;i++) if(`dut_port.tru_tab_entry_i[i].valid == 1)
+ $display("\tTRU_TAB[fid=%2d, sub_fid=%1d]: pattern{mode=%1d, mask=0x%4x, match=0x%4x}, ports{mask=0x%4x, ingress=%b, egress=%b}",
+ `dut_port.tru_tab_addr_o,
+ i,
+ `dut_port.tru_tab_entry_i[i].pattern_mode,
+ `dut_port.tru_tab_entry_i[i].pattern_mask,
+ `dut_port.tru_tab_entry_i[i].pattern_match,
+ `dut_port.tru_tab_entry_i[i].ports_mask,
+ `dut_port.tru_tab_entry_i[i].ports_ingress,
+ `dut_port.tru_tab_entry_i[i].ports_egress);
+ $display("\t-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------");
+ end
+
+ task print_tru_state;
+ input CSimDrv_WR_TRU tru_drv;
+ begin
+ bit[`c_num_ports-1:0] endp_up;
+ integer i;
+ integer bank,ports_up, ports_stb_up;
+
+ tru_drv.read_status(bank,ports_up, ports_stb_up);
+
+ for(i=0;i<`c_num_ports;i++)
+ endp_up[i]=t_ep2tru[i].status;
+ $display("\n------------------------ STATUS DUMP -----------------------------");
+ $display("[RTU_config ]: ports forwarding : %32b",t_rtu.pass_all);
+ $display("[Endpoint ]: ports up : %32b",endp_up);
+ $display("[TRU_status ]: ports up : %32b",ports_up);
+ $display("[TRU_status ]: ports up (stable): %32b",ports_stb_up);
+ $display("[TRU_status ]: active bank : %1d",bank);
+ $display("------------------------------------------------------------------\n");
+ end
+ endtask;
+
+ task ep_ports_up_all;
+ integer i;
+
+ for(i=0;i<`c_num_ports; i++) ep_port_up(i);
+
+ endtask;
+
+ ////////////////// simulating inputs from RTU ///////////////////
+ task automatic rtu_enable_port;
+ input[31:0] portId;
+ begin
+ t_rtu.pass_all[portId] = 1;
+ $display("[RTU_config ] port %d forwarding", portId);
+ end;
+ endtask;
+
+ task automatic rtu_disable_port;
+ input[31:0] portId;
+ begin
+ t_rtu.pass_all[portId] = 0;
+ $display("[RTU_config ] port %d blocking", portId);
+ end;
+ endtask;
+ //////////////// simulated endpoint inputs //////////////////
+ task automatic ep_port_up;
+ input[31:0] portId;
+ begin
+ t_ep2tru[portId].status = 1;
+ $display("[Endpoint in] port %d UP", portId);
+ end;
+ endtask;
+
+ task automatic ep_port_down;
+ input[31:0] portId;
+ begin
+ t_ep2tru[portId].status = 0;
+ $display("[Endpoint in] port %d DOWN", portId);
+ end;
+ endtask;
+
+ task automatic ep_port_rx_quick_fw;
+ input[31:0] portId;
+ input[31:0] classID;
+ begin
+ t_ep2tru[portId].rx_pck_class[classID] = 1;
+ t_ep2tru[portId].rx_pck = 1;
+ wait_cycles(1);
+ t_ep2tru[portId].rx_pck_class[classID] = 0;
+ t_ep2tru[portId].rx_pck = 0;
+ $display("[Endpoint in] port %d UP", portId);
+ end;
+ endtask;
+
+ task automatic init_stuff;
+ input CSimDrv_WR_TRU tru_drv;
+ begin
+ integer i;
+
+ t_req.valid = 0;
+ t_req.smac = 0;
+ t_req.dmac = 0;
+ t_req.fid = 0;
+ t_req.isHP = 0;
+ t_req.isBR = 0;
+ t_req.reqMask = 0;
+
+ t_rtu.pass_all = 0;
+ t_rtu.forward_bpdu_only = 0;
+ t_rtu.request_valid = 0;
+
+ for(i=0;i<`c_num_ports;i++)
+ t_ep2tru[i] = 0;
+
+ /*
+ * Globacl Config Register
+ **/
+
+ wait_cycles(100);
+ tru_drv.pattern_config(1 /*replacement*/ ,2 /*addition*/);
+ tru_drv.rt_reconf_config(4 /*tx_frame_id*/, 4/*rx_frame_id*/, 1 /*mode*/);
+ tru_drv.rt_reconf_enable();
+
+ /*
+ * transition
+ **/
+ tru_drv.transition_config(0 /*mode */, 4 /*rx_id*/, 0 /*prio*/, 20 /*time_diff*/,
+ 3 /*port_a_id*/, 4 /*port_b_id*/);
+ tru_drv.tru_enable();
+ $display("TRU initiated\n");
+
+ wait_cycles(5);
+ ep_port_up(0);
+ ep_port_up(1);
+ ep_port_up(2);
+ ep_port_up(3);
+ ep_port_up(4);
+ ep_port_up(5);
+ ep_port_up(6);
+ ep_port_up(7);
+ wait_cycles(5);
+ rtu_enable_port(0);
+ rtu_enable_port(1);
+ rtu_enable_port(2);
+ rtu_enable_port(3);
+ rtu_enable_port(4);
+ rtu_enable_port(5);
+ rtu_enable_port(6);
+ rtu_enable_port(7);
+ $display("Ports up");
+ end;
+ endtask;
+
+
+
+ task tru_tab_config_1;
+ input CSimDrv_WR_TRU tru_drv;
+ begin
+ /*
+ **/
+ //////////////////////////////////////////// ENTRY 0 ///////////////////////////////////////
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/, 'h0 /* pattern_mode */,
+ 'h0F /*ports_mask */, 'h02 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h02 /* pattern_match*/,'h1 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h04 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h30 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+
+
+ //////////////////////////////////////////// ENTRY 1 ///////////////////////////////////////
+ tru_drv.write_tru_tab( 1 /* valid */, 1 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h12 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 1 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h0F /*pattern_mask*/, 'h02 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'h0F /*ports_mask */, 'h04 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 1 /* entry_addr */, 2 /* subentry_addr*/,
+ 'hF0 /*pattern_mask*/, 'h10 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hF0 /*ports_mask */, 'h20 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 1 /* entry_addr */, 3 /* subentry_addr*/,
+ 'hFF /*pattern_mask*/, 'hC0 /* pattern_match*/,'h2 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'hC0 /* ports_egress */,'hC0 /* ports_ingress */);
+
+ tru_drv.tru_swap_bank();
+ $display("configuration 1");
+ end;
+ endtask;
+
+ task tru_tab_config_2;
+ input CSimDrv_WR_TRU tru_drv;
+ begin
+ /*
+ * | port | ingress | egress |
+ * |--------------------------|
+ * | 0 | 1 | 1 |
+ * | 1 | 0 | 1 |
+ * | 2 | 1 | 1 |
+ * | 3 | 1 | 1 |
+ * | 4 | 1 | 1 |
+ * | 5 | 0 | 1 |
+ * |--------------------------|
+ *
+ * 5 -> 1 -> 0
+ * ----------------
+ * port 1 is backup for 0
+ * port 5 is backup ofr 1
+ *
+ **/
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/, 'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3F /* ports_egress */,'h1D /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h03 /*pattern_mask*/, 'h01 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3E /* ports_egress */,'h1E /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 'h03 /*pattern_mask*/, 'h03 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3C /* ports_egress */,'h3C /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.tru_swap_bank();
+ $display("configuration 2");
+ end;
+ endtask;
+
+ task simulate_transition ;
+ input[31:0] portA;
+ input[31:0] portB;
+ input[31:0] timeDiff;
+ input[31:0] rx_frame_id;
+ input[31:0] prio;
+ begin
+
+ $display("\t > ------------ Simulating transition -----------< ");
+ $display("\t > \t\t From portA %2d \t\t <",portA);
+ $display("\t > \t\t To portB %2d \t\t <",portB);
+ $display("\t > \t\t At Priority %2d \t\t <",prio);
+ $display("\t > \t\t With TimeDiff %2d \t\t <",timeDiff);
+ $display("\t > \t\t Using RxFrames %2d \t\t <",rx_frame_id);
+ $display("\t > ----------------------------------------------< ");
+ wait_cycles(1);
+
+ t_rtu.priorities[portA] = prio;
+ t_rtu.priorities[portB] = prio;
+
+ t_ep2tru[portB].rx_pck_class[rx_frame_id] = 1;
+ t_ep2tru[portB].rx_pck = 1;
+ wait_cycles(1);
+ t_ep2tru[portB].rx_pck_class[rx_frame_id] = 0;
+ t_ep2tru[portB].rx_pck = 0;
+ wait_cycles(10);
+ t_rtu.request_valid[portB] = 1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portB]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portB]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(timeDiff);
+ t_ep2tru[portA].rx_pck_class[rx_frame_id] = 1;
+ t_ep2tru[portA].rx_pck = 1;
+ wait_cycles(1);
+ t_ep2tru[portA].rx_pck_class[rx_frame_id] = 0;
+ t_ep2tru[portA].rx_pck = 0;
+
+ t_rtu.request_valid[portA]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portA]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portA]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portA]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(10);
+
+
+ end;
+ endtask;
+ task automatic tru_request;
+ input[47:0] smac;
+ input[47:0] dmac;
+ input[ 7:0] fid;
+ input isHP;
+ input isBR;
+ input[`c_num_ports-1:0] portID;
+ begin
+ t_req.valid = 1;
+ t_req.smac = smac;
+ t_req.dmac = dmac;
+ t_req.fid = fid;
+ t_req.isHP = isHP;
+ t_req.isBR = isBR;
+ t_req.reqMask = 1 << portID;
+
+ wait_cycles(1);
+
+ t_req.valid = 0;
+ t_req.smac = 0;
+ t_req.dmac = 0;
+ t_req.fid = 0;
+ t_req.isHP = 0;
+ t_req.isBR = 0;
+ t_req.reqMask = 0;
+
+ if(isHP==1) $display("\nReq @ port %2d: fid=%2d, smac=0x%x, dmac=0x%x, high prio traffic", portID, fid, smac, dmac);
+ else if(isBR==1) $display("\nReq @ port %2d: fid=%2d, smac=0x%x, dmac=0x%x, broadcast traffic", portID, fid, smac, dmac);
+ else $display("\nReq @ port %2d: fid=%2d, smac=0x%x, dmac=0x%x, normal traffic", portID, fid, smac, dmac);
+
+ end;
+ endtask;
+
+ task automatic all_ports_up;
+ begin
+ integer i;
+ for(i=0;i<`c_num_ports;i++) begin
+ ep_port_up(i);
+ rtu_disable_port(i);
+ end;
+ wait_cycles(101);
+ for(i=0;i<`c_num_ports;i++) begin
+ rtu_enable_port(i);
+ end;
+ end;
+ endtask;
+
+
+ always #5ns clk <= ~clk;
+ initial begin
+ repeat(3) @(posedge clk);
+ rst_n = 1;
+ end
+
+ task test_1;
+ input CSimDrv_WR_TRU tru_drv;
+ begin
+ integer i;
+ $display("\n");
+ $display("-------------------------------------------------------------------------------");
+ $display("------------------------ TEST 1 -----------------------");
+ $display("------------------------ [ START ] -----------------------");
+ $display("-------------------------------------------------------------------------------");
+ $display("Simple test to check normal response, respons with port broken and transition");
+ $display("-------------------------------------------------------------------------------");
+ $display("\n");
+
+ wait_cycles(100);
+
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,0/*portID*/);
+ wait_cycles(20);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,1/*portID*/);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,2/*portID*/);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 2/*fid*/, 0/*isHP*/, 0/*isBR*/,3/*portID*/);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,4/*portID*/);
+
+ ep_port_down(1);
+
+ wait_cycles(10);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,0/*portID*/);
+ wait_cycles(10);
+ ep_port_down(4);
+ wait_cycles(1);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,0/*portID*/);
+ wait_cycles(10);
+ ep_port_down(5);
+ wait_cycles(1);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,0/*portID*/);
+
+ print_tru_state(tru_drv);
+
+ wait_cycles(20);
+ for(i=0;i<10;i++) begin
+ ep_port_up(1);
+ wait_cycles(2);
+ ep_port_down(1);
+ wait_cycles(2);
+ end;
+
+ ep_port_up(1);
+
+ rtu_disable_port(1);
+ wait_cycles(101);
+ rtu_enable_port(1);
+
+ all_ports_up();
+
+ wait_cycles(20);
+ ep_port_rx_quick_fw(7 /*portId*/, 4 /*classID*/);
+ //ep_port_rx_quick_fw(6 /*portId*/, 4 /*classID*/);
+
+ wait_cycles(10);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,0/*portID*/);
+
+ tru_drv.transition_enable();
+
+ wait_cycles(100);
+ simulate_transition(3 /*portA*/,4 /*portB*/,20/*timeDiff*/,4 /*rx_frame_id*/,0/*priority*/);
+ $display("-------------------------------------------------------------------------------");
+ $display("------------------------ TEST 1 -----------------------");
+ $display("------------------------ [ FINISH ] -----------------------");
+ $display("-------------------------------------------------------------------------------");
+
+
+ end;
+ endtask;
+
+ task test_2;
+ input CSimDrv_WR_TRU tru_drv;
+ begin
+ integer i;
+ $display("\n");
+ $display("-------------------------------------------------------------------------------");
+ $display("------------------------ TEST 2 -----------------------");
+ $display("------------------------ [ START ] -----------------------");
+ $display("-------------------------------------------------------------------------------");
+ $display("Simple test to check normal response, respons with port broken and transition");
+ $display("-------------------------------------------------------------------------------");
+ $display("\n");
+
+ wait_cycles(100);
+ ep_ports_up_all();
+ wait_cycles(10);
+ print_tru_state(tru_drv); // port 1 should indicate stable up
+ /*
+ * All is working
+ **/
+ $display("\n>>>>>>>>>>> (1) send frame from each port, all ports OK: <<<<<<<<<<<<<<<\n");
+ for(i=0;i<`c_num_ports; i++)
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,i/*portID*/);
+
+ /*
+ * A single port (number 0) goes down, it has backup
+ **/
+ wait_cycles(10);
+ ep_port_down(0);
+ wait_cycles(10);
+
+ $display("\n>>>>>>>>>>> (2) send frame from each port, port 0 down: <<<<<<<<<<<<<<<\n");
+ for(i=0;i<`c_num_ports; i++)
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,i/*portID*/);
+
+ /*
+ * The backup port (numbet 1) goes down as well, it has backup
+ **/
+ wait_cycles(10);
+ ep_port_down(1);
+ wait_cycles(10);
+
+ $display("\n>>>>>>>>>>> (3) send frame from each port, porgs 0 and 1 down: <<<<<<<<<<<<<<<\n");
+ for(i=0;i<`c_num_ports; i++)
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,i/*portID*/);
+
+ wait_cycles(10);
+ $display("\n>>>>>>>>>>> (4) re-configure table <<<<<<<<<<<<<<<\n");
+ /*
+ * eRSTP reconfigures topology to include new arrangement (with two ports down)
+ **/
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/, 'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3C /* ports_egress */,'h3C /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h03 /*pattern_mask*/, 'h01 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3E /* ports_egress */,'h1E /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 'h03 /*pattern_mask*/, 'h03 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3C /* ports_egress */,'h3C /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+
+ tru_drv.tru_swap_bank(); // flush TRU TAB
+ wait_cycles(10);
+
+ $display("\n>>>>>>>>>>> (5) disable non-working ports <<<<<<<<<<<<<<<\n");
+ // disable not used / working ports
+ rtu_disable_port(0);
+ rtu_disable_port(1);
+ wait_cycles(10);
+
+ print_tru_state(tru_drv); // ports
+
+ wait_cycles(10);
+ $display("\n>>>>>>>>>>> (6) send frame from each port, all enabled/configured ports OK: <<<<<<<<<<<<<<<\n");
+ for(i=0;i<`c_num_ports; i++)
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,i/*portID*/);
+
+ wait_cycles(10);
+ $display("\n>>>>>>>>>>> (7) reviving port 0<<<<<<<<<<<<<<<\n");
+ // revive port 0
+ ep_port_up(0);
+ wait_cycles(10);
+ $display("\n port 0 just come up so not stable, but seen up because is disabled");
+ print_tru_state(tru_drv); // ports
+ wait_cycles(100);
+ $display("\n port 0 up and stable\n");
+ print_tru_state(tru_drv); // port 1 should indicate stable up
+ wait_cycles(10);
+
+ wait_cycles(10);
+ $display("\n>>>>>>>>>>> (8) enabling port 0 in RTU, no config in TRU <<<<<<<<<<<<<<<\n");
+ rtu_enable_port(0);
+
+ wait_cycles(10);
+
+ $display("\n>>>>>>>>>>> (9) send frame from each port, all enabled/configured ports OK: <<<<<<<<<<<<<<<\n");
+ for(i=0;i<`c_num_ports; i++)
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,i/*portID*/);
+
+ wait_cycles(10);
+
+ $display("\n>>>>>>>>>>> (10) reconfig TRU TAB without changing banks <<<<<<<<<<<<<<<\n");
+ wait_cycles(10);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/, 'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3F /* ports_egress */,'h1D /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h03 /*pattern_mask*/, 'h01 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3E /* ports_egress */,'h1E /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 'h03 /*pattern_mask*/, 'h03 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h3C /* ports_egress */,'h3C /* ports_ingress */);
+
+ tru_drv.write_tru_tab( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+ wait_cycles(10) ;
+ $display("\n>>>>>>>>>>> (11) configure transition <<<<<<<<<<<<<<<\n");
+ wait_cycles(10);
+
+ tru_drv.transition_config(0 /*mode */, 4 /*rx_id*/, 0 /*prio*/, 20 /*time_diff*/,
+ 5 /*port_a_id*/, 0 /*port_b_id*/);
+ tru_drv.transition_enable();
+ $display("\n>>>>>>>>>>> (12) perform transition <<<<<<<<<<<<<<<\n");
+ wait_cycles(100);
+ simulate_transition(5 /*portA*/,0 /*portB*/,20/*timeDiff*/,4 /*rx_frame_id*/, 0/*priority*/);
+ wait_cycles(100);
+
+ print_tru_state(tru_drv); // port 1 should indicate stable up
+ wait_cycles(10);
+
+ $display("\n>>>>>>>>>>> (13) send frame from each port, all enabled/configured ports OK: <<<<<<<<<<<<<<<\n");
+ for(i=0;i<`c_num_ports; i++)
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,i/*portID*/);
+
+
+ wait_cycles(10);
+ $display("-------------------------------------------------------------------------------");
+ $display("------------------------ TEST 2 -----------------------");
+ $display("------------------------ [ FINISH ] -----------------------");
+ $display("-------------------------------------------------------------------------------");
+
+
+ end;
+ endtask;
+
+
+ initial begin
+
+ integer i;
+ CWishboneAccessor tru_acc;
+ CSimDrv_WR_TRU tru_drv;
+
+ /******************************* INIT STUFF **********************************/
+ tru_acc = U_tru_wb.get_accessor();
+ tru_acc.set_mode(PIPELINED);
+ tru_drv = new(tru_acc, 0);
+
+ init_stuff(tru_drv);
+
+ /******************************* Simulate stuff *******************************/
+
+// tru_tab_config_1(tru_drv);
+// test_1(tru_drv);
+
+ tru_tab_config_2(tru_drv);
+ test_2(tru_drv);
+ end
+
+endmodule // main
+
diff --git a/testbench/tru/tru_old.sv b/testbench/tru/tru_old.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2d9a19ac1135713c9cd525aced93d62ec999263f
--- /dev/null
+++ b/testbench/tru/tru_old.sv
@@ -0,0 +1,651 @@
+`timescale 1ns/1ps
+
+`define array_copy(a, ah, al, b, bl) \
+ for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
+
+ `define c_num_ports 8
+ `define c_tru_addr_width 8
+ `define c_tru_subentry_num 8
+ `define c_tru_subentry_width (1+5*`c_num_ports+`c_pattern_mode_width) //49 //(3*24+3*8+1)
+ `define c_patternID_width 4
+ `define c_pattern_mode_width 4 // needs to be the same as num_port
+ `define c_stableUP_treshold 100 // numbers of cycles after which port is assumed to be stably UP
+ `define c_pclass_number 8
+ `define c_pause_delay_width 16
+ `define c_swc_max_queue_number 8
+ `define c_fid_width 8
+ `define c_mac_addr_width 48
+ `define c_tru2ep_record_width (3+`c_pclass_number+`c_pause_delay_width+`c_swc_max_queue_number)
+ `define c_ep2tru_record_width (3+`c_pclass_number)
+ `define c_rtu2tru_record_width (3*`c_num_ports+`c_num_ports*`c_prio_width)
+ `define c_tru_req_record_width (1+2*`c_mac_addr_width+`c_fid_width+2+`c_num_ports)
+ `define c_tru_resp_record_width (1+`c_num_ports+1+`c_num_ports)
+ `define c_tru_tab_size 256 // max 256
+ `define c_vlan_tab_size 2048
+ `define c_mt_trans_max_fr_cnt 1000
+ `define c_prio_width 3
+
+typedef struct packed {
+ bit[`c_pattern_mode_width -1:0] pattern_mode ;
+ bit[`c_num_ports-1:0] pattern_mask ;
+ bit[`c_num_ports-1:0] pattern_match;
+ bit[`c_num_ports-1:0] ports_mask ;
+ bit[`c_num_ports-1:0] ports_egress ;
+ bit[`c_num_ports-1:0] ports_ingress;
+ bit valid;
+} tru_tab_subentry_p_s;
+
+typedef struct packed {
+ tru_tab_subentry_p_s [`c_tru_subentry_num-1:0] subent;
+} tru_tab_entry_p_s;
+
+typedef struct packed {
+ bit has_prio;
+ bit[ 2:0] prio;
+ bit prio_override;
+ bit drop;
+ bit[ 7:0] fid;
+ bit[`c_num_ports-1:0] port_mask;
+} vlan_tab_entry_p_s;
+
+typedef struct packed {
+ bit[`c_num_ports-1 :0] reqMask;
+ bit isBR;
+ bit isHP;
+ bit[ 7:0] fid;
+ bit[47:0] dmac;
+ bit[47:0] smac;
+ bit valid;
+} tru_req_p_s;
+
+typedef struct packed {
+ bit[`c_num_ports-1 :0] respMask;
+ bit[47:0] drop;
+ bit[`c_num_ports-1 :0] portID;
+ bit valid;
+} tru_resp_p_s;
+
+typedef struct packed {
+ bit[`c_num_ports-1:0] rxFrameMaskReg;
+ bit[`c_num_ports-1:0] rxFrameMask;
+ bit[`c_num_ports-1:0] portStateMask;
+} tru_endpoint_p_s;
+
+typedef struct packed {
+ bit[`c_prio_width-1:0][`c_num_ports-1:0] priorities;
+ bit[`c_num_ports-1:0] request_valid;
+ bit[`c_num_ports-1:0] forward_bpdu_only;
+ bit[`c_num_ports-1:0] pass_all;
+} tru_rtu_p_s;
+
+
+typedef struct packed {
+ bit[`c_pclass_number-1:0] rx_pck_class;
+ bit rx_pck;
+ bit ctrlRd;
+ bit status;
+} tru_ep2tru_p_s;
+
+typedef struct packed {
+ bit[`c_swc_max_queue_number-1:0] outQueueBlockMask;
+ bit[`c_pause_delay_width-1:0] pauseTime;
+ bit pauseSend;
+ bit[`c_pclass_number-1:0] tx_pck_class;
+ bit tx_pck;
+ bit ctrlWr;
+} tru_tru2ep_p_s;
+
+
+typedef struct {
+ bit gcr_g_ena;
+ bit gcr_tru_bank;
+ bit[23:0] gcr_rx_frame_reset;
+ bit[ 3:0] mcr_pattern_mode_rep;
+ bit[ 3:0] mcr_pattern_mode_add;
+ bit[ 3:0] lacr_agg_gr_num;
+ bit[ 3:0] lacr_agg_df_br_id;
+ bit[ 3:0] lacr_agg_df_un_id;
+ bit[8*4-1:0] lagt_gr_id_mask;
+ bit tcr_trans_ena;
+ bit tcr_trans_clr;
+ bit[ 2:0] tcr_trans_mode;
+ bit[ 2:0] tcr_trans_rx_id;
+ bit[ 2:0] tcr_trans_prio;
+ bit[ 5:0] tcr_trans_port_a_id;
+ bit[15:0] tcr_trans_port_a_pause;
+ bit tcr_trans_port_a_valid;
+ bit[ 5:0] tcr_trans_port_b_id;
+ bit[15:0] tcr_trans_port_b_pause;
+ bit tcr_trans_port_b_valid;
+ bit rtrcr_rtr_ena;
+ bit rtrcr_rtr_reset;
+ bit[ 3:0] rtrcr_rtr_mode;
+ bit[ 3:0] rtrcr_rtr_rx ;
+} tru_config_s;
+
+
+module main;
+
+
+ genvar kk;
+ reg clk = 0;
+ reg rst_n = 0;
+
+ reg nasty_one_bit = 0;
+// reg [`c_tru_entry_width -1:0] tru_tab [`c_tru_tab_size];
+ tru_tab_subentry_p_s[`c_tru_subentry_num-1:0] tru_tab[`c_tru_tab_size];
+// tru_tab_entry_p_s tru_tab[`c_tru_tab_size];
+ reg[`c_tru_subentry_num*`c_tru_subentry_width-1:0] tru_tab_entry;
+ wire[`c_tru_addr_width -1:0] tru_tab_addr;
+
+
+ reg [`c_tru_req_record_width-1: 0] tru_req;
+ tru_req_p_s t_req;
+
+ wire[`c_tru_resp_record_width-1 : 0] tru_resp;
+ tru_resp_p_s t_resp;
+
+ reg[`c_rtu2tru_record_width-1:0] tru_rtu;
+ tru_rtu_p_s t_rtu;
+
+ reg[`c_num_ports*`c_ep2tru_record_width-1:0] tru_ep2tru;
+ tru_ep2tru_p_s[`c_num_ports-1:0] t_ep2tru;
+
+ wire[`c_num_ports*`c_tru2ep_record_width-1:0] tru_tru2ep;
+ tru_tru2ep_p_s[`c_num_ports-1:0] t_tru2ep;
+
+ wire[`c_num_ports-1:0] tru_swc2tru;
+
+ tru_config_s t_conf;
+
+ wrsw_tru
+ #(
+ .g_num_ports (`c_num_ports),
+ .g_tru_subentry_num (`c_tru_subentry_num),
+ .g_tru_subentry_width (`c_tru_subentry_width),
+ .g_tru_addr_width (`c_tru_addr_width),
+ .g_pattern_mode_width (`c_num_ports),
+ .g_patternID_width (`c_patternID_width),
+ .g_stableUP_treshold (`c_stableUP_treshold),
+ .g_pclass_number (`c_pclass_number),
+ .g_tru2ep_record_width (`c_tru2ep_record_width),
+ .g_ep2tru_record_width (`c_ep2tru_record_width),
+ .g_rtu2tru_record_width (`c_rtu2tru_record_width),
+ .g_tru_req_record_width (`c_tru_req_record_width),
+ .g_tru_resp_record_width (`c_tru_resp_record_width),
+ .g_mt_trans_max_fr_cnt (`c_mt_trans_max_fr_cnt),
+ .g_prio_width (`c_prio_width),
+ .g_tru_entry_num (`c_tru_tab_size)
+ ) DUT (
+ .clk_i (clk),
+ .rst_n_i (rst_n),
+ .tru_req_i (tru_req),
+ .tru_resp_o (tru_resp),
+ .rtu_i (tru_rtu),
+ .ep_i (tru_ep2tru),
+ .ep_o (tru_tru2ep),
+ .swc_o (tru_swc2tru),
+
+ /////// temp ///////
+ .tru_tab_addr_o (tru_tab_addr),
+ .tru_tab_entry_i (tru_tab_entry),
+
+ .gcr_g_ena_i (t_conf.gcr_g_ena),
+ .gcr_tru_bank_i (t_conf.gcr_tru_bank),
+ .gcr_rx_frame_reset_i (t_conf.gcr_rx_frame_reset),
+ .mcr_pattern_mode_rep_i (t_conf.mcr_pattern_mode_rep),
+ .mcr_pattern_mode_add_i (t_conf.mcr_pattern_mode_add),
+ .lacr_agg_gr_num_i (t_conf.lacr_agg_gr_num),
+ .lacr_agg_df_br_id_i (t_conf.lacr_agg_df_br_id),
+ .lacr_agg_df_un_id_i (t_conf.lacr_agg_df_un_id),
+ .lagt_gr_id_mask_i (t_conf.lagt_gr_id_mask),
+ .tcr_trans_ena_i (t_conf.tcr_trans_ena),
+ .tcr_trans_mode_i (t_conf.tcr_trans_mode),
+ .tcr_trans_clr_i (t_conf.tcr_trans_clr),
+ .tcr_trans_rx_id_i (t_conf.tcr_trans_rx_id),
+ .tcr_trans_prio_i (t_conf.tcr_trans_prio),
+ .tcr_trans_port_a_id_i (t_conf.tcr_trans_port_a_id),
+ .tcr_trans_port_a_pause_i (t_conf.tcr_trans_port_a_pause),
+ .tcr_trans_port_a_valid_i (t_conf.tcr_trans_port_a_valid),
+ .tcr_trans_port_b_id_i (t_conf.tcr_trans_port_b_id),
+ .tcr_trans_port_b_pause_i (t_conf.tcr_trans_port_b_pause),
+ .tcr_trans_port_b_valid_i (t_conf.tcr_trans_port_b_valid),
+ .rtrcr_rtr_ena_i (t_conf.rtrcr_rtr_ena),
+ .rtrcr_rtr_reset_i (t_conf.rtrcr_rtr_reset),
+ .rtrcr_rtr_mode_i (t_conf.rtrcr_rtr_mode),
+ .rtrcr_rtr_rx_i (t_conf.rtrcr_rtr_rx)
+ );
+
+ assign tru_req = t_req;
+ assign t_resp = tru_resp;
+ assign tru_rtu = t_rtu;
+ assign tru_ep2tru = t_ep2tru;
+ assign t_tru2ep = tru_tru2ep;
+ /*
+ * wait ncycles
+ */
+ task automatic wait_cycles;
+ input [31:0] ncycles;
+ begin : wait_body
+ integer i;
+ for(i=0;i<ncycles;i=i+1) @(posedge clk);
+ end
+ endtask // wait_cycles
+
+ always @(posedge clk) //@(posedge clk)
+ begin
+
+ tru_tab_entry = tru_tab[tru_tab_addr];
+ end
+
+ always @(posedge clk) //@(posedge clk)
+ begin
+ integer i;
+ for(i=0;i<`c_num_ports;i++) begin
+ t_ep2tru[i].ctrlRd = t_tru2ep[i].ctrlWr;
+ end;
+
+ end
+
+ task automatic set_tru_subentry;
+ input valid;
+ input[31:0] tru_entry_addr;
+ input[31:0] tru_subentry_addr;
+ input[`c_num_ports-1:0] pattern_mask ;
+ input[`c_num_ports-1:0] pattern_match;
+ input[`c_pattern_mode_width-1:0] pattern_mode ;
+ input[`c_num_ports-1:0] ports_mask ;
+ input[`c_num_ports-1:0] ports_egress ;
+ input[`c_num_ports-1:0] ports_ingress;
+ begin
+
+ tru_tab[tru_entry_addr][tru_subentry_addr].pattern_mode = pattern_mode;
+ tru_tab[tru_entry_addr][tru_subentry_addr].pattern_mask = pattern_mask;
+ tru_tab[tru_entry_addr][tru_subentry_addr].pattern_match = pattern_match;
+ tru_tab[tru_entry_addr][tru_subentry_addr].ports_mask = ports_mask;
+ tru_tab[tru_entry_addr][tru_subentry_addr].ports_egress = ports_egress;
+ tru_tab[tru_entry_addr][tru_subentry_addr].ports_ingress = ports_ingress;
+ tru_tab[tru_entry_addr][tru_subentry_addr].valid = valid;
+
+ end;
+ endtask;
+
+ task automatic rtu_enable_port;
+ input[31:0] portId;
+ begin
+ t_rtu.pass_all[portId] = 1;
+ end;
+ endtask;
+
+ task automatic rtu_disable_port;
+ input[31:0] portId;
+ begin
+ t_rtu.pass_all[portId] = 0;
+ end;
+ endtask;
+
+ task automatic ep_port_up;
+ input[31:0] portId;
+ begin
+ t_ep2tru[portId].status = 1;
+ end;
+ endtask;
+
+ task automatic ep_port_down;
+ input[31:0] portId;
+ begin
+ t_ep2tru[portId].status = 0;
+ end;
+ endtask;
+
+ task automatic ep_port_rx_quick_fw;
+ input[31:0] portId;
+ input[31:0] classID;
+ begin
+ t_ep2tru[portId].rx_pck_class[classID] = 1;
+ t_ep2tru[portId].rx_pck = 1;
+ wait_cycles(1);
+ t_ep2tru[portId].rx_pck_class[classID] = 0;
+ t_ep2tru[portId].rx_pck = 0;
+ end;
+ endtask;
+
+ task automatic trans_config;
+ input[ 2:0] mode;
+ input[ 2:0] rx_id;
+ input[ 2:0] prio;
+ input[ 5:0] port_a_id;
+ input[15:0] port_a_pause;
+ input[ 5:0] port_b_id;
+ input[15:0] port_b_pause;
+ begin
+
+ /*
+ * transition
+ **/
+ t_conf.tcr_trans_clr = 0 ;
+ t_conf.tcr_trans_mode = mode;
+
+ t_conf.tcr_trans_rx_id = rx_id;
+
+ t_conf.tcr_trans_port_a_valid = 1;
+ t_conf.tcr_trans_port_a_pause = port_a_pause;
+ t_conf.tcr_trans_port_a_id = port_a_id;
+
+ t_conf.tcr_trans_port_b_valid = 1;
+ t_conf.tcr_trans_port_b_pause = port_b_pause;
+ t_conf.tcr_trans_port_b_id = port_b_id;
+ end;
+ endtask;
+
+
+ task automatic trans_enable;
+ begin
+ t_conf.tcr_trans_clr = 0 ;
+ wait_cycles(1);
+ t_conf.tcr_trans_ena = 1 ;
+ end;
+ endtask;
+
+ task automatic trans_disable;
+ begin
+ t_conf.tcr_trans_clr = 0 ;
+ t_conf.tcr_trans_ena = 1 ;
+ end;
+ endtask;
+
+
+ task automatic init_stuff;
+
+ begin
+ vlan_tab_entry_p_s vt ;
+ tru_tab_entry_p_s tt;
+ integer i;
+
+ t_req.valid = 0;
+ t_req.smac = 0;
+ t_req.dmac = 0;
+ t_req.fid = 0;
+ t_req.isHP = 0;
+ t_req.isBR = 0;
+ t_req.reqMask = 0;
+
+ t_rtu.pass_all = 0;
+ t_rtu.forward_bpdu_only = 0;
+ t_rtu.request_valid = 0;
+
+ for(i=0;i<`c_tru_tab_size;i++)
+ tru_tab[i] = 0;
+
+ for(i=0;i<`c_num_ports;i++)
+ t_ep2tru[i] = 0;
+
+ /*
+ * Globacl Config Register
+ **/
+ t_conf.gcr_g_ena = 1; // enable the module
+ t_conf.mcr_pattern_mode_rep = 1;
+ t_conf.mcr_pattern_mode_add = 2;
+ t_conf.rtrcr_rtr_rx = 4;
+ t_conf.rtrcr_rtr_mode = 1;
+ t_conf.rtrcr_rtr_ena = 1;
+
+ /*
+ * transition
+ **/
+ trans_config(0 /*mode*/, 4 /*rx_id*/, 0 /*prio*/,
+ 3 /*port_a_id*/,20 /*port_a_pause*/,
+ 4 /*port_b_id*/,20 /*port_b_pause*/);
+
+ /*
+ * General ifno regarding entries:
+ * we use replace pattern, the add pattern is especially set such that it will never match
+ * (the pattern is outside of pattern mask)
+ **/
+ //////////////////////////////////////////// ENTRY 0 ///////////////////////////////////////
+ set_tru_subentry( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/, 'h0 /* pattern_mode */,
+ 'h0F /*ports_mask */, 'h02 /* ports_egress */,'h01 /* ports_ingress */);
+
+ set_tru_subentry( 0 /* valid */, 0 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h02 /* pattern_match*/,'h1 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h04 /* ports_egress */,'h01 /* ports_ingress */);
+
+ set_tru_subentry( 0 /* valid */, 0 /* entry_addr */, 2 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h30 /* ports_egress */,'h01 /* ports_ingress */);
+
+ set_tru_subentry( 0 /* valid */, 0 /* entry_addr */, 3 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h20 /* pattern_mode */,
+ 'h00 /*ports_mask */, 'h40 /* ports_egress */,'h01 /* ports_ingress */);
+
+
+ //////////////////////////////////////////// ENTRY 1 ///////////////////////////////////////
+ set_tru_subentry( 1 /* valid */, 1 /* entry_addr */, 0 /* subentry_addr*/,
+ 'h00 /*pattern_mask*/, 'h00 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'h12 /* ports_egress */,'h01 /* ports_ingress */);
+
+ set_tru_subentry( 1 /* valid */, 1 /* entry_addr */, 1 /* subentry_addr*/,
+ 'h0F /*pattern_mask*/, 'h02 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'h0F /*ports_mask */, 'h04 /* ports_egress */,'h01 /* ports_ingress */);
+
+ set_tru_subentry( 1 /* valid */, 1 /* entry_addr */, 2 /* subentry_addr*/,
+ 'hF0 /*pattern_mask*/, 'h10 /* pattern_match*/,'h0 /* pattern_mode */,
+ 'hF0 /*ports_mask */, 'h20 /* ports_egress */,'h01 /* ports_ingress */);
+
+ set_tru_subentry( 1 /* valid */, 1 /* entry_addr */, 3 /* subentry_addr*/,
+ 'hFF /*pattern_mask*/, 'hC0 /* pattern_match*/,'h2 /* pattern_mode */,
+ 'hFF /*ports_mask */, 'hC0 /* ports_egress */,'hC0 /* ports_ingress */);
+
+ //////////////////////////////////////////// ENTRY 2 ///////////////////////////////////////
+// set_tru_subentry( 1 /* valid */, 2 /* entry_addr */, 0 /* subentry_addr*/,
+// 'h0F /*pattern_mask*/, 'h10 /* pattern_match*/, 0 /* pattern_mode */,
+// 'hFF /*ports_mask */, 'h11 /* ports_egress */,'h05 /* ports_ingress */);
+//
+// set_tru_subentry( 1 /* valid */, 2 /* entry_addr */, 1 /* subentry_addr*/,
+// 'h0F /*pattern_mask*/, 'h10 /* pattern_match*/, 1 /* pattern_mode */,
+// 'hFF /*ports_mask */, 'h22 /* ports_egress */,'h06 /* ports_ingress */);
+//
+// set_tru_subentry( 1 /* valid */, 2 /* entry_addr */, 2 /* subentry_addr*/,
+// 'h0F /*pattern_mask*/, 'h10 /* pattern_match*/, 2 /* pattern_mode */,
+// 'hFF /*ports_mask */, 'h33 /* ports_egress */,'h07 /* ports_ingress */);
+//
+// set_tru_subentry( 1 /* valid */, 2 /* entry_addr */, 3 /* subentry_addr*/,
+// 'h0F /*pattern_mask*/, 'h10 /* pattern_match*/, 3 /* pattern_mode */,
+// 'hFF /*ports_mask */, 'h44 /* ports_egress */,'h08 /* ports_ingress */);
+
+ wait_cycles(5);
+ ep_port_up(0);
+ ep_port_up(1);
+ ep_port_up(2);
+ ep_port_up(3);
+ ep_port_up(4);
+ ep_port_up(5);
+ ep_port_up(6);
+ ep_port_up(7);
+ wait_cycles(5);
+ rtu_enable_port(0);
+ rtu_enable_port(1);
+ rtu_enable_port(2);
+ rtu_enable_port(3);
+ rtu_enable_port(4);
+ rtu_enable_port(5);
+ rtu_enable_port(6);
+ rtu_enable_port(7);
+
+ end;
+ endtask;
+
+ task simulate_transition ;
+ input[31:0] portA;
+ input[31:0] portB;
+ input[31:0] timeDiff;
+ begin
+
+
+ t_ep2tru[portA].rx_pck_class[t_conf.tcr_trans_rx_id] = 1;
+ t_ep2tru[portA].rx_pck = 1;
+ wait_cycles(1);
+ t_ep2tru[portA].rx_pck_class[t_conf.tcr_trans_rx_id] = 0;
+ t_ep2tru[portA].rx_pck = 0;
+ wait_cycles(10);
+ t_rtu.request_valid[portA] = 1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portA]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portA]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portA]=0;
+
+ wait_cycles(timeDiff);
+ t_ep2tru[portB].rx_pck_class[t_conf.tcr_trans_rx_id] = 1;
+ t_ep2tru[portB].rx_pck = 1;
+ wait_cycles(1);
+ t_ep2tru[portB].rx_pck_class[t_conf.tcr_trans_rx_id] = 0;
+ t_ep2tru[portB].rx_pck = 0;
+
+ t_rtu.request_valid[portB]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portB]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portB]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(10);
+ t_rtu.request_valid[portB]=1;
+ wait_cycles(1);
+ t_rtu.request_valid[portB]=0;
+
+ wait_cycles(10);
+
+
+ end;
+ endtask;
+ task automatic tru_request;
+ input[47:0] smac;
+ input[47:0] dmac;
+ input[ 7:0] fid;
+ input isHP;
+ input isBR;
+ input[`c_num_ports-1:0] reqMask;
+ begin
+ t_req.valid = 1;
+ t_req.smac = smac;
+ t_req.dmac = dmac;
+ t_req.fid = fid;
+ t_req.isHP = isHP;
+ t_req.isBR = isBR;
+ t_req.reqMask = reqMask;
+
+ wait_cycles(1);
+
+ t_req.valid = 0;
+ t_req.smac = 0;
+ t_req.dmac = 0;
+ t_req.fid = 0;
+ t_req.isHP = 0;
+ t_req.isBR = 0;
+ t_req.reqMask = 0;
+
+ end;
+ endtask;
+
+ task automatic all_ports_up;
+ begin
+ integer i;
+ for(i=0;i<`c_num_ports;i++) begin
+ ep_port_up(i);
+ rtu_disable_port(i);
+ end;
+ wait_cycles(101);
+ for(i=0;i<`c_num_ports;i++) begin
+ rtu_enable_port(i);
+ end;
+ end;
+ endtask;
+
+
+ always #5ns clk <= ~clk;
+ initial begin
+ repeat(3) @(posedge clk);
+ rst_n = 1;
+ end
+
+ initial begin
+ repeat(3) @(posedge clk);
+ rst_n = 1;
+ end
+
+ initial begin
+
+ integer i;
+ init_stuff();
+ wait_cycles(10);
+
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,1/*reqMask*/);
+ wait_cycles(20);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,2/*reqMask*/);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,4/*reqMask*/);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 2/*fid*/, 0/*isHP*/, 0/*isBR*/,8/*reqMask*/);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 0/*fid*/, 0/*isHP*/, 0/*isBR*/,16/*reqMask*/);
+
+ ep_port_down(1);
+
+ wait_cycles(10);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,1/*reqMask*/);
+ wait_cycles(10);
+ ep_port_down(4);
+ wait_cycles(1);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,1/*reqMask*/);
+ wait_cycles(10);
+ ep_port_down(5);
+ wait_cycles(1);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,1/*reqMask*/);
+
+
+ wait_cycles(20);
+ for(i=0;i<10;i++) begin
+ ep_port_up(1);
+ wait_cycles(2);
+ ep_port_down(1);
+ wait_cycles(2);
+ end;
+
+
+ ep_port_up(1);
+
+ rtu_disable_port(1);
+ wait_cycles(101);
+ rtu_enable_port(1);
+
+ all_ports_up();
+
+ wait_cycles(20);
+ ep_port_rx_quick_fw(7 /*portId*/, 4 /*classID*/);
+ //ep_port_rx_quick_fw(6 /*portId*/, 4 /*classID*/);
+
+ wait_cycles(10);
+ tru_request (1234/*smac*/, 5678/*dmac*/, 1/*fid*/, 0/*isHP*/, 0/*isBR*/,1/*reqMask*/);
+
+ trans_enable();
+
+ wait_cycles(100);
+ simulate_transition(3 /*portA*/,4 /*portB*/,20/*timeDiff*/);
+
+ end
+
+endmodule // main
+
diff --git a/testbench/tru/tru_wb_regs.v b/testbench/tru/tru_wb_regs.v
new file mode 100644
index 0000000000000000000000000000000000000000..8decbcb887c654b0870bbbd34bbbe119f63d44a3
--- /dev/null
+++ b/testbench/tru/tru_wb_regs.v
@@ -0,0 +1,108 @@
+`define ADDR_TRU_GCR 6'h0
+`define TRU_GCR_G_ENA_OFFSET 0
+`define TRU_GCR_G_ENA 32'h00000001
+`define TRU_GCR_TRU_BANK_OFFSET 1
+`define TRU_GCR_TRU_BANK 32'h00000002
+`define TRU_GCR_RX_FRAME_RESET_OFFSET 8
+`define TRU_GCR_RX_FRAME_RESET 32'hffffff00
+`define ADDR_TRU_GSR0 6'h4
+`define TRU_GSR0_STAT_BANK_OFFSET 0
+`define TRU_GSR0_STAT_BANK 32'h00000001
+`define TRU_GSR0_STAT_STB_UP_OFFSET 8
+`define TRU_GSR0_STAT_STB_UP 32'hffffff00
+`define ADDR_TRU_GSR1 6'h8
+`define TRU_GSR1_STAT_UP_OFFSET 0
+`define TRU_GSR1_STAT_UP 32'hffffffff
+`define ADDR_TRU_MCR 6'hc
+`define TRU_MCR_PATTERN_MODE_REP_OFFSET 0
+`define TRU_MCR_PATTERN_MODE_REP 32'h0000000f
+`define TRU_MCR_PATTERN_MODE_ADD_OFFSET 8
+`define TRU_MCR_PATTERN_MODE_ADD 32'h00000f00
+`define ADDR_TRU_LACR 6'h10
+`define TRU_LACR_AGG_GR_NUM_OFFSET 0
+`define TRU_LACR_AGG_GR_NUM 32'h0000000f
+`define TRU_LACR_AGG_DF_BR_ID_OFFSET 8
+`define TRU_LACR_AGG_DF_BR_ID 32'h00000f00
+`define TRU_LACR_AGG_DF_UN_ID_OFFSET 16
+`define TRU_LACR_AGG_DF_UN_ID 32'h000f0000
+`define ADDR_TRU_LAGT 6'h14
+`define TRU_LAGT_LAGT_GR_ID_MASK_0_OFFSET 0
+`define TRU_LAGT_LAGT_GR_ID_MASK_0 32'h0000000f
+`define TRU_LAGT_LAGT_GR_ID_MASK_1_OFFSET 4
+`define TRU_LAGT_LAGT_GR_ID_MASK_1 32'h000000f0
+`define TRU_LAGT_LAGT_GR_ID_MASK_2_OFFSET 8
+`define TRU_LAGT_LAGT_GR_ID_MASK_2 32'h00000f00
+`define TRU_LAGT_LAGT_GR_ID_MASK_3_OFFSET 12
+`define TRU_LAGT_LAGT_GR_ID_MASK_3 32'h0000f000
+`define TRU_LAGT_LAGT_GR_ID_MASK_4_OFFSET 16
+`define TRU_LAGT_LAGT_GR_ID_MASK_4 32'h000f0000
+`define TRU_LAGT_LAGT_GR_ID_MASK_5_OFFSET 20
+`define TRU_LAGT_LAGT_GR_ID_MASK_5 32'h00f00000
+`define TRU_LAGT_LAGT_GR_ID_MASK_6_OFFSET 24
+`define TRU_LAGT_LAGT_GR_ID_MASK_6 32'h0f000000
+`define TRU_LAGT_LAGT_GR_ID_MASK_7_OFFSET 28
+`define TRU_LAGT_LAGT_GR_ID_MASK_7 32'hf0000000
+`define ADDR_TRU_TCGR 6'h18
+`define TRU_TCGR_TRANS_ENA_OFFSET 0
+`define TRU_TCGR_TRANS_ENA 32'h00000001
+`define TRU_TCGR_TRANS_CLEAR_OFFSET 1
+`define TRU_TCGR_TRANS_CLEAR 32'h00000002
+`define TRU_TCGR_TRANS_MODE_OFFSET 4
+`define TRU_TCGR_TRANS_MODE 32'h00000070
+`define TRU_TCGR_TRANS_RX_ID_OFFSET 8
+`define TRU_TCGR_TRANS_RX_ID 32'h00000700
+`define TRU_TCGR_TRANS_PRIO_OFFSET 12
+`define TRU_TCGR_TRANS_PRIO 32'h00007000
+`define TRU_TCGR_TRANS_TIME_DIFF_OFFSET 16
+`define TRU_TCGR_TRANS_TIME_DIFF 32'hffff0000
+`define ADDR_TRU_TCPR 6'h1c
+`define TRU_TCPR_TRANS_PORT_A_ID_OFFSET 0
+`define TRU_TCPR_TRANS_PORT_A_ID 32'h0000003f
+`define TRU_TCPR_TRANS_PORT_A_VALID_OFFSET 8
+`define TRU_TCPR_TRANS_PORT_A_VALID 32'h00000100
+`define TRU_TCPR_TRANS_PORT_B_ID_OFFSET 16
+`define TRU_TCPR_TRANS_PORT_B_ID 32'h003f0000
+`define TRU_TCPR_TRANS_PORT_B_VALID_OFFSET 24
+`define TRU_TCPR_TRANS_PORT_B_VALID 32'h01000000
+`define ADDR_TRU_TSR 6'h20
+`define TRU_TSR_TRANS_STAT_ACTIVE_OFFSET 0
+`define TRU_TSR_TRANS_STAT_ACTIVE 32'h00000001
+`define TRU_TSR_TRANS_STAT_FINISHED_OFFSET 1
+`define TRU_TSR_TRANS_STAT_FINISHED 32'h00000002
+`define ADDR_TRU_RTRCR 6'h24
+`define TRU_RTRCR_RTR_ENA_OFFSET 0
+`define TRU_RTRCR_RTR_ENA 32'h00000001
+`define TRU_RTRCR_RTR_RESET_OFFSET 1
+`define TRU_RTRCR_RTR_RESET 32'h00000002
+`define TRU_RTRCR_RTR_MODE_OFFSET 8
+`define TRU_RTRCR_RTR_MODE 32'h00000f00
+`define TRU_RTRCR_RTR_RX_OFFSET 16
+`define TRU_RTRCR_RTR_RX 32'h000f0000
+`define TRU_RTRCR_RTR_TX_OFFSET 24
+`define TRU_RTRCR_RTR_TX 32'h0f000000
+`define ADDR_TRU_TTR0 6'h28
+`define TRU_TTR0_FID_OFFSET 0
+`define TRU_TTR0_FID 32'h000000ff
+`define TRU_TTR0_SUB_FID_OFFSET 8
+`define TRU_TTR0_SUB_FID 32'h0000ff00
+`define TRU_TTR0_UPDATE_OFFSET 16
+`define TRU_TTR0_UPDATE 32'h00010000
+`define TRU_TTR0_MASK_VALID_OFFSET 17
+`define TRU_TTR0_MASK_VALID 32'h00020000
+`define TRU_TTR0_PATRN_MODE_OFFSET 24
+`define TRU_TTR0_PATRN_MODE 32'h0f000000
+`define ADDR_TRU_TTR1 6'h2c
+`define TRU_TTR1_PORTS_INGRESS_OFFSET 0
+`define TRU_TTR1_PORTS_INGRESS 32'hffffffff
+`define ADDR_TRU_TTR2 6'h30
+`define TRU_TTR2_PORTS_EGRESS_OFFSET 0
+`define TRU_TTR2_PORTS_EGRESS 32'hffffffff
+`define ADDR_TRU_TTR3 6'h34
+`define TRU_TTR3_PORTS_MASK_OFFSET 0
+`define TRU_TTR3_PORTS_MASK 32'hffffffff
+`define ADDR_TRU_TTR4 6'h38
+`define TRU_TTR4_PATRN_MATCH_OFFSET 0
+`define TRU_TTR4_PATRN_MATCH 32'hffffffff
+`define ADDR_TRU_TTR5 6'h3c
+`define TRU_TTR5_PATRN_MASK_OFFSET 0
+`define TRU_TTR5_PATRN_MASK 32'hffffffff
diff --git a/testbench/tru/wave.do b/testbench/tru/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..dc29870e49a75ee0d89d84c75572e68cced6a135
--- /dev/null
+++ b/testbench/tru/wave.do
@@ -0,0 +1,188 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/clk
+add wave -noupdate /main/nasty_one_bit
+add wave -noupdate /main/rst_n
+add wave -noupdate /main/t_ep2tru
+add wave -noupdate /main/t_req
+add wave -noupdate /main/t_resp
+add wave -noupdate /main/t_rtu
+add wave -noupdate /main/t_tru2ep
+add wave -noupdate /main/tru_ep2tru
+add wave -noupdate /main/tru_req
+add wave -noupdate /main/tru_resp
+add wave -noupdate /main/tru_rtu
+add wave -noupdate /main/tru_swc2tru
+add wave -noupdate /main/tru_tru2ep
+add wave -noupdate -divider xTRU
+add wave -noupdate /main/DUT/X_TRU/g_num_ports
+add wave -noupdate /main/DUT/X_TRU/g_pattern_mode_width
+add wave -noupdate /main/DUT/X_TRU/g_pattern_width
+add wave -noupdate /main/DUT/X_TRU/g_patternID_width
+add wave -noupdate /main/DUT/X_TRU/g_pclass_number
+add wave -noupdate /main/DUT/X_TRU/g_prio_width
+add wave -noupdate /main/DUT/X_TRU/g_stableUP_treshold
+add wave -noupdate /main/DUT/X_TRU/g_tru_addr_width
+add wave -noupdate /main/DUT/X_TRU/g_tru_entry_num
+add wave -noupdate /main/DUT/X_TRU/g_tru_subentry_num
+add wave -noupdate /main/DUT/X_TRU/req_i
+add wave -noupdate /main/DUT/X_TRU/resp_o
+add wave -noupdate /main/DUT/X_TRU/rst_n_i
+add wave -noupdate /main/DUT/X_TRU/rtu_i
+add wave -noupdate /main/DUT/X_TRU/s_bank_swap_on_trans
+add wave -noupdate /main/DUT/X_TRU/s_config
+add wave -noupdate /main/DUT/X_TRU/s_endpoint_array
+add wave -noupdate /main/DUT/X_TRU/s_endpoints
+add wave -noupdate /main/DUT/X_TRU/s_regs_fromwb
+add wave -noupdate /main/DUT/X_TRU/s_regs_towb
+add wave -noupdate /main/DUT/X_TRU/s_trans_ep_ctr
+add wave -noupdate /main/DUT/X_TRU/s_trans_rxFrameMask
+add wave -noupdate /main/DUT/X_TRU/s_transitionActive
+add wave -noupdate /main/DUT/X_TRU/s_transitionFinished
+add wave -noupdate /main/DUT/X_TRU/s_tru_rd_addr
+add wave -noupdate /main/DUT/X_TRU/s_tru_tab_addr
+add wave -noupdate /main/DUT/X_TRU/s_tru_tab_bank
+add wave -noupdate /main/DUT/X_TRU/s_tru_tab_entry
+add wave -noupdate /main/DUT/X_TRU/s_tru_tab_rd_subentry_arr
+add wave -noupdate /main/DUT/X_TRU/s_tru_tab_wr_index
+add wave -noupdate /main/DUT/X_TRU/s_tru_tab_wr_subentry_arr
+add wave -noupdate /main/DUT/X_TRU/s_tru_wr_addr
+add wave -noupdate /main/DUT/X_TRU/s_tru_wr_data
+add wave -noupdate /main/DUT/X_TRU/s_tru_wr_ena
+add wave -noupdate /main/DUT/X_TRU/s_tx_rt_reconf_FRM
+add wave -noupdate /main/DUT/X_TRU/swc_o
+add wave -noupdate /main/DUT/X_TRU/wb_i
+add wave -noupdate /main/DUT/X_TRU/wb_in
+add wave -noupdate /main/DUT/X_TRU/wb_o
+add wave -noupdate /main/DUT/X_TRU/wb_out
+add wave -noupdate -divider WB_Adapter
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/clk_sys_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/fsm_state
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/g_master_use_struct
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/g_slave_granularity
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/g_slave_mode
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/g_slave_use_struct
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_ack_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_adr_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_cyc_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_dat_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_dat_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_err_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_int_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_rty_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_sel_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_stall_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_stb_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/ma_we_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/master_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/master_in
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/master_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/master_out
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/rst_n_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_ack_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_adr_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_cyc_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_dat_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_dat_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_err_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_int_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_rty_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_sel_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_stall_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_stb_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/sl_we_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/slave_i
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/slave_in
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/slave_o
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/slave_out
+add wave -noupdate /main/DUT/X_TRU/U_WB_ADAPTER/stored_we
+add wave -noupdate -divider Port
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/g_num_ports
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/g_pattern_width
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/g_patternID_width
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/g_tru_addr_width
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/g_tru_subentry_num
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/rst_n_i
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_drop
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_egress_mask
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_ingress_mask
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_patternAdd
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_patternAdd_d0
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_patternRep
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_patternRep_d0
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_port_mask
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_portID_vec
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_reqMask_d0
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_reqMask_d1
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_resp_masks
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_self_mask
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_status_mask
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_valid_d0
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_valid_d1
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/s_zeros
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/tru_req_i
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/tru_resp_o
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/tru_tab_addr_o
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/tru_tab_entry_i
+add wave -noupdate /main/DUT/X_TRU/U_T_PORT/txFrameMask_o
+add wave -noupdate -divider Endpoint_0
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/g_num_ports
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/g_pattern_width
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/g_patternID_width
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/g_pclass_number
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/g_stableUP_treshold
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/g_tru_subentry_num
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/port_if_ctrl_o
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/port_if_i
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/reset_rxFlag_i
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/rst_n_i
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/rtu_pass_all_i
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_port_down
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_port_status_d0
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_rxFrameMask
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_rxFrameMaskReg
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_stableUp_cnt
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_tru_port_state
+add wave -noupdate /main/DUT/X_TRU/G_ENDP(0)/U_T_ENDPOINT/s_zeros
+add wave -noupdate -divider Transition
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/g_num_ports
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/g_prio_width
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/rst_n_i
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/rtu_i
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/rxFrameMask_i
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_ep_ctr_A
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_ep_ctr_B
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_ep_zero
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_port_A_mask
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_port_A_prio
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_port_A_rtu_srobe
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_port_B_mask
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_port_B_prio
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_port_B_rtu_srobe
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_portA_frame_cnt
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_portB_frame_cnt
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_start_transition
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_statTransActive
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_statTransFinished
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/s_tru_trans_state
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/statTransActive_o
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/statTransFinished_o
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/tru_tab_bank_i
+add wave -noupdate /main/DUT/X_TRU/U_TRANSITION/TRANS_MARKER_TRIG/tru_tab_bank_o
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {12304389440 fs} 0}
+configure wave -namecolwidth 224
+configure wave -valuecolwidth 81
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 fs} {105 us}
diff --git a/testbench/tru/wrsw_tru_wb.vhd b/testbench/tru/wrsw_tru_wb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fb94119ce277b6ba5e83fee24cddf61806b22fec
--- /dev/null
+++ b/testbench/tru/wrsw_tru_wb.vhd
@@ -0,0 +1,167 @@
+-------------------------------------------------------------------------------
+-- Title : Topology Resolution Unit (wrapper with WB I/F)
+-- Project : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File : tru_port_wrapper.vhd
+-- Author : Maciej Lipinski
+-- Company : CERN BE-CO-HT
+-- Created : 2012-08-28
+-- Last update: 2012-09-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Wrapper of the xwrsw_tru top entity to be used for simulation.
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012 Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2012-08-31 1.0 mlipinsk Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+library work;
+use work.wrsw_shared_types_pkg.all; -- need this for:
+ -- * t_rtu_request
+
+use work.rtu_private_pkg.all; -- we need it for RTU's datatypes (records):
+ -- * t_rtu_vlan_tab_entry
+
+use work.gencores_pkg.all; -- for f_rr_arbitrate
+use work.wrsw_tru_pkg.all;
+
+entity wrsw_tru_wb is
+ generic(
+ g_num_ports : integer;
+ g_tru_subentry_num : integer;
+ g_tru_subentry_width : integer;
+ g_pattern_mode_width : integer;
+ g_patternID_width : integer;
+ g_stableUP_treshold : integer;
+ g_tru_addr_width : integer;
+ g_pclass_number : integer;
+ g_tru2ep_record_width : integer;
+ g_ep2tru_record_width : integer;
+ g_rtu2tru_record_width: integer;
+ g_tru_req_record_width: integer;
+ g_tru_resp_record_width:integer;
+ g_mt_trans_max_fr_cnt : integer;
+ g_prio_width : integer;
+ g_tru_entry_num : integer
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ------------------------------- I/F with RTU ----------------------------------
+ --t_tru_request
+ tru_req_i : in std_logic_vector(g_tru_req_record_width-1 downto 0);
+
+ --rtu_resp_o
+ tru_resp_o : out std_logic_vector(g_tru_resp_record_width-1 downto 0);
+
+ rtu_i : in std_logic_vector(g_rtu2tru_record_width-1 downto 0);
+
+ ep_i : in std_logic_vector(g_num_ports*g_ep2tru_record_width-1 downto 0);
+ ep_o : out std_logic_vector(g_num_ports*g_tru2ep_record_width-1 downto 0);
+
+ swc_o : out std_logic_vector(g_num_ports-1 downto 0); -- for pausing
+
+ wb_addr_i : in std_logic_vector(3 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic
+ );
+end wrsw_tru_wb;
+
+architecture rtl of wrsw_tru_wb is
+ type t_tru_tab_subentry_array is array(integer range <>) of
+ std_logic_vector(g_tru_subentry_width-1 downto 0);
+ type t_ep_array is array(integer range <>) of std_logic_vector(g_ep2tru_record_width-1 downto 0);
+
+ signal s_tru_req : t_tru_request;
+ signal s_tru_resp : t_tru_response;
+ signal s_tru_tab_entry : t_tru_tab_entry(g_tru_subentry_num-1 downto 0);
+ signal s_config : t_tru_config;
+ signal s_tru_tab_subentry_arr : t_tru_tab_subentry_array(g_tru_subentry_num-1 downto 0);
+ signal s_rtu : t_rtu2tru;
+ signal s_ep_in : t_ep2tru_array(g_num_ports-1 downto 0);
+ signal s_ep_out : t_tru2ep_array(g_num_ports-1 downto 0);
+ signal s_ep_arr : t_ep_array(g_num_ports-1 downto 0);
+begin
+
+ X_TRU: xwrsw_tru
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num => g_tru_subentry_num,
+ g_patternID_width => g_patternID_width,
+ g_pattern_width => g_num_ports,
+ g_stableUP_treshold=> g_stableUP_treshold,
+ g_tru_addr_width => g_tru_addr_width,
+ g_pclass_number => g_pclass_number,
+ g_mt_trans_max_fr_cnt=> g_mt_trans_max_fr_cnt,
+ g_prio_width => g_prio_width,
+ g_pattern_mode_width => g_pattern_mode_width,
+ g_tru_entry_num => g_tru_entry_num
+ )
+ port map(
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ req_i => s_tru_req,
+ resp_o => s_tru_resp,
+ rtu_i => s_rtu,
+ ep_i => s_ep_in,
+ ep_o => s_ep_out,
+ swc_o => swc_o,
+
+ wb_addr_i => wb_addr_i,
+ wb_data_i => wb_data_i,
+ wb_data_o => wb_data_o,
+ wb_cyc_i => wb_cyc_i,
+ wb_sel_i => wb_sel_i,
+ wb_stb_i => wb_stb_i,
+ wb_we_i => wb_we_i,
+ wb_ack_o => wb_ack_o
+
+ );
+
+ s_tru_req <= f_unpack_tru_request (tru_req_i, g_num_ports);
+ tru_resp_o <= f_pack_tru_response (s_tru_resp, g_num_ports);
+ s_rtu <= f_unpack_rtu (rtu_i, g_num_ports);
+
+ G3: for i in 0 to g_num_ports-1 generate
+ s_ep_arr(i) <= ep_i((i+1)*g_ep2tru_record_width-1 downto i*g_ep2tru_record_width);
+ s_ep_in(i) <= f_unpack_ep2tru(s_ep_arr(i));
+ ep_o((i+1)*g_tru2ep_record_width-1 downto i*g_tru2ep_record_width) <= f_pack_tru2ep(s_ep_out(i));
+ end generate G3;
+
+end rtl;
diff --git a/testbench/wrsw_pstats/Manifest.py b/testbench/wrsw_pstats/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..509dad24bd22dabebcccda5a8c2b19138092ca32
--- /dev/null
+++ b/testbench/wrsw_pstats/Manifest.py
@@ -0,0 +1,11 @@
+target = "xilinx"
+action = "simulation"
+syn_device = "XC6VLX130T"
+fetchto = "../../ip_cores"
+vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
+
+files = [ "main.sv" ]
+
+modules ={"local" : ["../../ip_cores/general-cores",
+ "../../modules/wrsw_pstats",
+ "../../modules/wrsw_pstats/wrsw_dummy"] };
diff --git a/testbench/wrsw_pstats/main.sv b/testbench/wrsw_pstats/main.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1c26274e7e2014ff3ed893a4dd5f14a84f652f35
--- /dev/null
+++ b/testbench/wrsw_pstats/main.sv
@@ -0,0 +1,163 @@
+`include "pstats_gen.sv"
+`include "if_wb_master.svh"
+
+`define TRIG_WIDTH 17
+`define NPORTS 8
+
+module main;
+
+ reg clk_sys = 1'b0;
+ reg rst_n = 1'b0;
+
+ wire [`NPORTS * `TRIG_WIDTH-1:0]trigs;
+
+ always #5ns clk_sys <= ~clk_sys;
+ initial begin
+ repeat(3) @(posedge clk_sys);
+ rst_n <= 1'b1;
+ end
+
+ pstats_gen
+ #(
+ .g_trig_width(`NPORTS * `TRIG_WIDTH))
+ TRIG_GEN
+ (
+ .rst_n_i(rst_n),
+ .clk_i(clk_sys),
+ .trig_o(trigs)
+ );
+
+ //assign trigs[7:4] = 'h0;
+
+ wrsw_pstats
+ #(
+ .g_nports(`NPORTS),
+ .g_cnt_pp(`TRIG_WIDTH),
+ .g_cnt_pw(4),
+ .g_keep_ov(1))
+ DUT
+ (
+ .rst_n_i(rst_n),
+ .clk_i(clk_sys),
+ .events_i(trigs),
+
+ .wb_adr_i(WB.master.adr[3:0]),
+ .wb_dat_i(WB.master.dat_o),
+ .wb_dat_o(WB.master.dat_i),
+ .wb_cyc_i(WB.master.cyc),
+ .wb_sel_i(4'b1111),
+ .wb_stb_i(WB.master.stb),
+ .wb_we_i(WB.master.we),
+ .wb_ack_o(WB.master.ack),
+ .wb_stall_o(WB.master.stall)
+ );
+
+ dummy_rmon
+ #(
+ .g_nports(1),
+ .g_cnt_pp(`NPORTS * `TRIG_WIDTH))
+ DUMMY
+ (
+ .rst_n_i(rst_n),
+ .clk_i(clk_sys),
+ .events_i(trigs)
+ );
+
+ IWishboneMaster WB (
+ .clk_i(clk_sys),
+ .rst_n_i(rst_n));
+
+ initial begin
+ CWishboneAccessor acc;
+ uint64_t dat;
+ integer rnd;
+
+ acc = WB.get_accessor();
+ acc.set_mode(PIPELINED);
+ #2us;
+
+ //while(1)
+ //begin
+ // rnd = $urandom()%10;
+ //if(rnd < 5) acc.write('h0, 'h1);
+ // #50ns;
+ //acc.read('h8, dat);
+ //if(dat[7:0]=='h1f)
+ //begin
+ #1us;
+ //enable interrupts
+ acc.write('h24, 'hffffffff);
+ #21000us;
+ //read irq state
+ acc.read('h2c, dat);
+
+ acc.write('h0, 'h000002);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h01);
+ acc.write('h0, 'h000102);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h02);
+ acc.write('h0, 'h000202);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h04);
+ acc.write('h0, 'h000302);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h08);
+ acc.write('h0, 'h000402);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h10);
+ acc.write('h0, 'h000502);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h20);
+ acc.write('h0, 'h000602);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h40);
+ acc.write('h0, 'h000702);
+ acc.read('h4, dat);
+ acc.write('h2c, 'h80);
+ #1us;
+
+ acc.write('h0, 'h80000000); //reset counters
+
+ #5us;
+ //acc.write('h0, 'h000002);
+ acc.write('h0, 'h000001);
+ acc.read('h4, dat);
+ acc.read('h8, dat);
+ acc.write('h0, 'h010001);
+ acc.read('h4, dat);
+ acc.read('h8, dat);
+ acc.write('h0, 'h000101);
+ acc.read('h4, dat);
+ acc.read('h8, dat);
+ acc.write('h0, 'h010101);
+ acc.read('h4, dat);
+ acc.read('h8, dat);
+ acc.write('h0, 'h000201);
+ acc.read('h4, dat);
+ acc.read('h8, dat);
+ acc.write('h0, 'h010201);
+ acc.write('h0, 'h000301);
+ acc.write('h0, 'h010301);
+ acc.write('h0, 'h000401);
+ acc.write('h0, 'h010401);
+ // acc.write('h0, 'h010001);
+ // acc.read('h4, dat);
+ // acc.write('h0, 'h020001);
+ // acc.read('h4, dat);
+ // acc.write('h0, 'h030001);
+ // acc.read('h4, dat);
+ // acc.write('h0, 'h040001);
+ // acc.read('h4, dat);
+ //end
+ //end
+
+ //#500ns
+ //acc.read('h4, dat);
+
+ end
+
+endmodule // main
+
+
+
diff --git a/testbench/wrsw_pstats/run.do b/testbench/wrsw_pstats/run.do
new file mode 100644
index 0000000000000000000000000000000000000000..943d23319127bf0ae16edf49820b751cbd35aa12
--- /dev/null
+++ b/testbench/wrsw_pstats/run.do
@@ -0,0 +1,10 @@
+vlog -sv main.sv +incdir+"." +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim
+make -f Makefile
+vsim -t 10fs work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 21500us
+wave zoomfull
+radix -hexadecimal
diff --git a/testbench/wrsw_pstats/wave.do b/testbench/wrsw_pstats/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..964f9279bb0f1e6e2b195518413d8334f44f7cdf
--- /dev/null
+++ b/testbench/wrsw_pstats/wave.do
@@ -0,0 +1,103 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/rst_n
+add wave -noupdate /main/DUT/nrst_cntrs
+add wave -noupdate /main/clk_sys
+add wave -noupdate /main/DUT/g_keep_ov
+add wave -noupdate /main/TRIG_GEN/trig_o
+add wave -noupdate -divider
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_adr_d1
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ov_cnt_o
+
+add wave -noupdate -divider <NULL>
+add wave -noupdate -divider <NULL>
+add wave -noupdate /main/DUT/L2_events
+add wave -noupdate /main/DUT/L3_events
+
+add wave -noupdate -divider <NULL>
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/dbg_evt_ov_o
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/dbg_cnt_ov_o
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/cnt_ov
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ov_cnt_o
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_i
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_reg
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_clr
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_sub
+add wave -noupdate -height 16 /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/cnt_state
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_adr
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_wr
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_dat_in
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_dat_out
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_grant
+add wave -noupdate -expand /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/RAM_A1/gen_single_clk/U_RAM_SC/ram
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ext_adr_i
+add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ext_dat_o
+
+add wave -noupdate -divider <NULL>
+add wave -noupdate /main/DUT/L2_CNT/dbg_evt_ov_o
+add wave -noupdate /main/DUT/L2_CNT/dbg_cnt_ov_o
+add wave -noupdate /main/DUT/L2_CNT/events_reg
+add wave -noupdate /main/DUT/L2_CNT/events_clr
+add wave -noupdate /main/DUT/L2_CNT/events_sub
+add wave -noupdate /main/DUT/L2_CNT/cnt_state
+add wave -noupdate /main/DUT/L2_CNT/mem_adr
+add wave -noupdate /main/DUT/L2_CNT/mem_wr
+add wave -noupdate /main/DUT/L2_CNT/mem_dat_in
+add wave -noupdate /main/DUT/L2_CNT/mem_dat_out
+add wave -noupdate -expand /main/DUT/L2_CNT/RAM_A1/gen_single_clk/U_RAM_SC/ram
+add wave -noupdate /main/DUT/L2_CNT/ext_adr_i
+add wave -noupdate /main/DUT/L2_CNT/ext_dat_o
+
+add wave -noupdate -divider
+add wave -noupdate /main/DUT/irq
+add wave -noupdate /main/DUT/CNTRS_IRQ/cnt_state
+
+add wave -noupdate /main/DUT/CNTRS_IRQ/irq_i
+add wave -noupdate /main/DUT/CNTRS_IRQ/events_reg
+add wave -noupdate /main/DUT/CNTRS_IRQ/events_clr
+add wave -noupdate /main/DUT/CNTRS_IRQ/events_sub
+add wave -noupdate /main/DUT/CNTRS_IRQ/events_grant
+add wave -noupdate -expand /main/DUT/CNTRS_IRQ/RAM_A1/gen_single_clk/U_RAM_SC/ram
+add wave -noupdate /main/DUT/port_irq
+add wave -noupdate /main/DUT/port_irq_reg
+add wave -noupdate /main/DUT/port_irq_ack
+add wave -noupdate /main/DUT/IRQ_cyc
+add wave -noupdate /main/DUT/IRQ_adr
+add wave -noupdate /main/DUT/IRQ_we
+add wave -noupdate /main/DUT/IRQ_dat_out
+add wave -noupdate /main/DUT/wb_int_o
+
+add wave -noupdate -divider <NULL>
+add wave -noupdate -divider <NULL>
+add wave -noupdate /main/DUT/wb_adr_i
+add wave -noupdate /main/DUT/wb_dat_i
+add wave -noupdate /main/DUT/wb_dat_o
+add wave -noupdate /main/DUT/wb_cyc_i
+add wave -noupdate /main/DUT/wb_ack_o
+add wave -noupdate /main/DUT/wb_stall_o
+add wave -noupdate -height 16 /main/DUT/rd_state
+add wave -noupdate /main/DUT/wb_regs_out.cr_rd_en_o
+add wave -noupdate /main/DUT/wb_regs_out.cr_rd_en_load_o
+add wave -noupdate /main/DUT/wb_regs_out.cr_port_o
+add wave -noupdate /main/DUT/wb_regs_out.cr_addr_o
+add wave -noupdate /main/DUT/wb_regs_in.cr_rd_en_i
+add wave -noupdate /main/DUT/wb_regs_in.L1_cnt_val_i
+add wave -noupdate -divider <NULL>
+add wave -noupdate /main/DUMMY/regs
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 fs} {111300 ns}
diff --git a/top/bare_top/scb_top_bare.vhd b/top/bare_top/scb_top_bare.vhd
index 67dfa4a0443e182395cc0470cc140364b24748ce..65ffacfa68e2b090bc6ff1f4510d48adf715535f 100644
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -4,7 +4,7 @@
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
-
+use ieee.math_real.CEIL;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
@@ -13,7 +13,8 @@ use work.wrsw_txtsu_pkg.all;
use work.hwinfo_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
-
+use work.wrsw_tru_pkg.all;
+use work.wrsw_tatsu_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
@@ -22,7 +23,11 @@ entity scb_top_bare is
generic(
g_num_ports : integer := 6;
g_simulation : boolean := false;
- g_without_network : boolean := false
+ g_without_network : boolean := false;
+ g_with_TRU : boolean := false;
+ g_with_TATSU : boolean := false;
+ g_with_HWDU : boolean := false;
+ g_with_PSTATS : boolean := true
);
port (
sys_rst_n_i : in std_logic; -- global reset
@@ -43,7 +48,6 @@ entity scb_top_bare is
-- Muxed system clock
clk_sys_o : out std_logic;
-
-------------------------------------------------------------------------------
-- Master wishbone bus (from the CPU bridge)
-------------------------------------------------------------------------------
@@ -136,11 +140,22 @@ end scb_top_bare;
architecture rtl of scb_top_bare is
- constant c_NUM_WB_SLAVES : integer := 12;
+ constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"04_02_14_00"; --DD_MM_YY_VV
+ constant c_NUM_WB_SLAVES : integer := 13;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;
-
-
+ constant c_NUM_GL_PAUSE : integer := 2; -- number of output global PAUSE sources for SWcore
+ constant c_RTU_EVENTS : integer := 9; -- number of RMON events per port
+ constant c_DBG_V_SWCORE : integer := (3*10) + 2 + -- 3 resources, each has with of CNT of 10 bits +2 to make it 32
+ (g_num_ports+1)*16 + -- states of input blocks (including NIC)
+ (g_num_ports+1)*8; -- states of output blocks (including NIC)
+ constant c_DBG_N_REGS : integer := 1 + integer(ceil(real(c_DBG_V_SWCORE)/real(32))); -- 32-bits debug registers which go to HWDU
+ constant c_TRU_EVENTS : integer := 1;
+ constant c_ALL_EVENTS : integer := c_TRU_EVENTS + c_RTU_EVENTS + c_epevents_sz;
+ constant c_DUMMY_RMON : boolean := false; -- define TRUE to enable dummy_rmon module for debugging PSTAT
+ constant c_NUM_GPIO_PINS : integer := 1;
+ constant c_NUM_IRQS : integer := 4;
+-- constant c_epevents_sz : integer := 15;
-------------------------------------------------------------------------------
-- Interconnect & memory layout
-------------------------------------------------------------------------------
@@ -152,19 +167,23 @@ architecture rtl of scb_top_bare is
constant c_SLAVE_TXTSU : integer := 4;
constant c_SLAVE_RTU : integer := 5;
constant c_SLAVE_GPIO : integer := 6;
- constant c_SLAVE_MBL_I2C0 : integer := 7;
- constant c_SLAVE_MBL_I2C1 : integer := 8;
- constant c_SLAVE_SENSOR_I2C : integer := 9;
- constant c_SLAVE_PWM : integer := 10;
- constant c_SLAVE_HWIU : integer := 11;
+ constant c_SLAVE_I2C : integer := 7;
+ constant c_SLAVE_PWM : integer := 8;
+ constant c_SLAVE_TRU : integer := 9;
+ constant c_SLAVE_TATSU : integer := 10;
+ constant c_SLAVE_PSTATS : integer := 11;
+ constant c_SLAVE_HWDU : integer := 12;
+ --constant c_SLAVE_DUMMY : integer := 13;
constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(
- x"00057800", -- HW Info Unit
- x"00057000", -- PWM Controller
- x"00056000", -- Sensors-I2C
- x"00055000", -- MBL-I2C1
- x"00054000", -- MBL-I2C0
+ --x"00070000", -- Dummy counters
+ x"00059000", -- HWDU / HWIU
+ x"00058000", -- PStats counters
+ x"00057000", -- TATSU
+ x"00056000", -- TRU
+ x"00055000", -- PWM Controller
+ x"00054000", -- I2C (0, 1, Sensors)
x"00053000", -- GPIO
x"00060000", -- RTU
x"00051000", -- TXTsu
@@ -175,8 +194,10 @@ architecture rtl of scb_top_bare is
x"00000000"); -- RT Subsys
constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
- (x"000ff800",
- x"000ff800",
+ (--x"000ff000",
+ x"000ff000",
+ x"000ff000",
+ x"000ff000",
x"000ff000",
x"000ff000",
x"000ff000",
@@ -247,7 +268,7 @@ architecture rtl of scb_top_bare is
signal rtu_req : t_rtu_request_array(c_NUM_PORTS downto 0);
signal rtu_rsp : t_rtu_response_array(c_NUM_PORTS downto 0);
- signal rtu_req_ack, rtu_full, rtu_rsp_ack : std_logic_vector(c_NUM_PORTS downto 0);
+ signal rtu_req_ack, rtu_full, rtu_rsp_ack, rtu_rq_abort, rtu_rsp_abort: std_logic_vector(c_NUM_PORTS downto 0);
-- System clock selection: 0 = startup clock, 1 = PLL clock
signal sel_clk_sys, sel_clk_sys_int : std_logic;
@@ -258,17 +279,32 @@ architecture rtl of scb_top_bare is
signal txtsu_timestamps_ack : std_logic_vector(c_NUM_PORTS-1 downto 0);
signal txtsu_timestamps : t_txtsu_timestamp_array(c_NUM_PORTS-1 downto 0);
- signal dummy : std_logic_vector(31 downto 0);
+ signal tru_enabled : std_logic;
+
+ -- PSTAT: RMON counters
+ signal rtu_events : std_logic_vector(c_NUM_PORTS*c_RTU_EVENTS -1 downto 0); --
+ signal ep_events : std_logic_vector(c_NUM_PORTS*c_epevents_sz -1 downto 0); --
+ signal rmon_events : std_logic_vector(c_NUM_PORTS*c_ALL_EVENTS -1 downto 0); --
+
+ --TEMP
+ signal dummy_events : std_logic_vector(c_NUM_PORTS*2-1 downto 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
- signal vic_irqs : std_logic_vector(31 downto 0);
+ signal vic_irqs : std_logic_vector(c_NUM_IRQS-1 downto 0);
+ type t_trig is array(integer range <>) of std_logic_vector(31 downto 0);
signal control0 : std_logic_vector(35 downto 0);
- signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
+ signal trig0, trig1, trig2, trig3 : t_trig(7 downto 0);--std_logic_vector(31 downto 0);
+ signal t0, t1, t2, t3 : std_logic_vector(31 downto 0);
signal rst_n_periph : std_logic;
+ signal link_kill : std_logic_vector(c_NUM_PORTS-1 downto 0);
+
+
+
+
function f_fabric_2_slv (
in_i : t_wrf_sink_in;
@@ -318,8 +354,49 @@ architecture rtl of scb_top_bare is
TRIG3 : in std_logic_vector(31 downto 0));
end component;
- signal gpio_out : std_logic_vector(31 downto 0);
+ signal gpio_out : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
+ signal gpio_in : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
+ signal dummy : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
+ -----------------------------------------------------------------------------
+ -- TRU stuff
+ -----------------------------------------------------------------------------
+ signal tru_req : t_tru_request;
+ signal tru_resp : t_tru_response;
+ signal rtu2tru : t_rtu2tru;
+ signal ep2tru : t_ep2tru_array(g_num_ports-1 downto 0);
+ signal tru2ep : t_tru2ep_array(g_num_ports-1 downto 0);
+ signal swc2tru_req: t_global_pause_request; -- for pause
+ -----------------------------------------------------------------------------
+ -- Time-Aware Traffic Shaper
+ -----------------------------------------------------------------------------
+
+ signal tm_utc : std_logic_vector(39 downto 0);
+ signal tm_cycles : std_logic_vector(27 downto 0);
+ signal tm_time_valid : std_logic;
+ signal shaper_request : t_global_pause_request;
+ signal shaper_drop_at_hp_ena : std_logic;
+ signal fc_rx_pause : t_pause_request_array(g_num_ports+1-1 downto 0);
+ constant c_zero_pause : t_pause_request :=('0',x"0000", x"00");
+ constant c_zero_gl_pause : t_global_pause_request :=('0',x"0000", x"00",(others=>'0'));
+ signal global_pause : t_global_pause_request_array(c_NUM_GL_PAUSE-1 downto 0);
+
+ signal dbg_n_regs : std_logic_vector(c_DBG_N_REGS*32 -1 downto 0);
+
+ type t_ep_dbg_data_array is array(integer range <>) of std_logic_vector(15 downto 0);
+ type t_ep_dbg_k_array is array(integer range <>) of std_logic_vector(1 downto 0);
+ type t_ep_dbg_rx_buf_array is array(integer range <>) of std_logic_vector(7 downto 0);
+ type t_ep_dbg_fab_pipes_array is array(integer range <>) of std_logic_vector(63 downto 0);
+ type t_ep_dbg_tx_pcs_array is array(integer range <>) of std_logic_vector(5+4 downto 0);
+
+ signal ep_dbg_data_array : t_ep_dbg_data_array(g_num_ports-1 downto 0);
+ signal ep_dbg_k_array : t_ep_dbg_k_array(g_num_ports-1 downto 0);
+ signal ep_dbg_rx_buf_array : t_ep_dbg_rx_buf_array(g_num_ports-1 downto 0);
+ signal ep_dbg_fab_pipes_array : t_ep_dbg_fab_pipes_array(g_num_ports-1 downto 0);
+ signal ep_dbg_tx_pcs_wr_array : t_ep_dbg_tx_pcs_array(g_num_ports-1 downto 0);
+ signal ep_dbg_tx_pcs_rd_array : t_ep_dbg_tx_pcs_array(g_num_ports-1 downto 0);
+ signal dbg_chps_id : std_logic_vector(7 downto 0);
+
begin
@@ -330,6 +407,7 @@ begin
--CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
+
-- CLK => clk_sys,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
@@ -427,6 +505,11 @@ begin
pps_ext_o => pps_o,
sel_clk_sys_o => sel_clk_sys,
+
+ tm_utc_o => tm_utc,
+ tm_cycles_o => tm_cycles,
+ tm_time_valid_o => tm_time_valid,
+
pll_status_i => '0',
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
@@ -439,7 +522,7 @@ begin
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
- g_num_interrupts => 32)
+ g_num_interrupts => c_NUM_IRQS)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
@@ -453,7 +536,8 @@ begin
U_Nic : xwrsw_nic
generic map (
g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
+ g_address_granularity => BYTE,
+ g_port_mask_bits => c_NUM_PORTS+1)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
@@ -461,14 +545,16 @@ begin
snk_o => endpoint_snk_out(c_NUM_PORTS),
src_i => endpoint_src_in(c_NUM_PORTS),
src_o => endpoint_src_out(c_NUM_PORTS),
- rtu_dst_port_mask_o => rtu_rsp(c_NUM_PORTS).port_mask(31 downto 0),
+ rtu_dst_port_mask_o => rtu_rsp(c_NUM_PORTS).port_mask(c_NUM_PORTS downto 0),
rtu_prio_o => rtu_rsp(c_NUM_PORTS).prio,
rtu_drop_o => rtu_rsp(c_NUM_PORTS).drop,
rtu_rsp_valid_o => rtu_rsp(c_NUM_PORTS).valid,
rtu_rsp_ack_i => rtu_rsp_ack(c_NUM_PORTS),
wb_i => cnx_master_out(c_SLAVE_NIC),
wb_o => cnx_master_in(c_SLAVE_NIC));
-
+
+ rtu_rsp(c_NUM_PORTS).hp <= '0';
+ fc_rx_pause(c_NUM_PORTS) <= c_zero_pause; -- no pause for NIC
U_Endpoint_Fanout : xwb_crossbar
generic map (
@@ -496,13 +582,16 @@ begin
g_pcs_16bit => true,
g_rx_buffer_size => 1024,
g_with_rx_buffer => true,
- g_with_flow_control => false,
+ g_with_flow_control => false,-- useless: flow control commented out
g_with_timestamper => true,
- g_with_dpi_classifier => false,
- g_with_vlans => false,
+ g_with_dpi_classifier => true,
+ g_with_vlans => true,
g_with_rtu => true,
g_with_leds => true,
- g_with_dmtd => false)
+ g_with_dmtd => false,
+ g_with_packet_injection => true,
+ g_use_new_rxcrc => true,
+ g_use_new_txcrc => true)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys,
@@ -516,8 +605,8 @@ begin
phy_loopen_o => phys_o(i).loopen,
phy_enable_o => phys_o(i).enable,
phy_ref_clk_i => phys_i(i).ref_clk,
- phy_tx_data_o => phys_o(i).tx_data,
- phy_tx_k_o => phys_o(i).tx_k,
+ phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
+ phy_tx_k_o => ep_dbg_k_array(i), -- phys_o(i).tx_k, --
phy_tx_disparity_i => phys_i(i).tx_disparity,
phy_tx_enc_err_i => phys_i(i).tx_enc_err,
phy_rx_data_i => phys_i(i).rx_data,
@@ -535,6 +624,7 @@ begin
rtu_full_i => rtu_full(i),
rtu_rq_strobe_p1_o => rtu_req(i).valid,
+ rtu_rq_abort_o => rtu_rq_abort(i),
rtu_rq_smac_o => rtu_req(i).smac,
rtu_rq_dmac_o => rtu_req(i).dmac,
rtu_rq_prio_o => rtu_req(i).prio,
@@ -542,21 +632,56 @@ begin
rtu_rq_has_vid_o => rtu_req(i).has_vid,
rtu_rq_has_prio_o => rtu_req(i).has_prio,
-
-
src_o => endpoint_src_out(i),
src_i => endpoint_src_in(i),
snk_o => endpoint_snk_out(i),
snk_i => endpoint_snk_in(i),
wb_i => cnx_endpoint_out(i),
wb_o => cnx_endpoint_in(i),
+
+ ----- TRU stuff ------------
+ pfilter_pclass_o => ep2tru(i).pfilter_pclass,
+ pfilter_drop_o => ep2tru(i).pfilter_drop,
+ pfilter_done_o => ep2tru(i).pfilter_done,
+ fc_tx_pause_req_i => tru2ep(i).fc_pause_req, -- we don't use it, use inject instead
+ fc_tx_pause_delay_i => tru2ep(i).fc_pause_delay, -- we don't use it, use inject instead
+ fc_tx_pause_ready_o => ep2tru(i).fc_pause_ready, -- we don't use it, use inject instead
+ inject_req_i => tru2ep(i).inject_req,
+ inject_ready_o => ep2tru(i).inject_ready,
+ inject_packet_sel_i => tru2ep(i).inject_packet_sel,
+ inject_user_value_i => tru2ep(i).inject_user_value,
+ link_kill_i => tru2ep(i).link_kill, --'0' , --link_kill(i), -- to change
+ link_up_o => ep2tru(i).status,
+ ------ PAUSE to SWcore ------------
+ fc_rx_pause_start_p_o => fc_rx_pause(i).req,
+ fc_rx_pause_quanta_o => fc_rx_pause(i).quanta,
+ fc_rx_pause_prio_mask_o => fc_rx_pause(i).classes,
+ ----------------------------
+
+ rmon_events_o => ep_events((i+1)*c_epevents_sz-1 downto i*c_epevents_sz),
+
led_link_o => led_link_o(i),
- led_act_o => led_act_o(i));
+ led_act_o => led_act_o(i)
+ );
- txtsu_timestamps(i).port_id(5) <= '0';
+ phys_o(i).tx_data <= ep_dbg_data_array(i);
+ phys_o(i).tx_k <= ep_dbg_k_array(i);
+ txtsu_timestamps(i).port_id(5) <= '0';
+
+ ------- TEMP ---------
+-- link_kill(i) <= not tru2ep(i).ctrlWr;
+-- tru2ep(i).fc_pause_req <= '0';
+-- tru2ep(i).fc_pause_delay <= (others =>'0');
+-- tru2ep(i).inject_req <= '0';
+-- tru2ep(i).inject_packet_sel <= (others => '0');
+-- tru2ep(i).inject_user_value <= (others => '0');
+-- ep2tru(i).rx_pck <= '0';
+-- ep2tru(i).rx_pck_class <= (others => '0');
+ ---------------------------
clk_rx_vec(i) <= phys_i(i).rx_clk;
+
end generate gen_endpoints_and_phys;
gen_terminate_unused_eps : for i in c_NUM_PORTS to c_MAX_PORTS-1 generate
@@ -568,33 +693,36 @@ begin
--txtsu_timestamps(i).valid <= '0';
end generate gen_terminate_unused_eps;
-
- gen_txtsu_debug : for i in 0 to c_NUM_PORTS-1 generate
- TRIG0(i) <= txtsu_timestamps(i).stb;
- trig1(i) <= txtsu_timestamps_ack(i);
- trig2(0) <= vic_irqs(0);
- trig2(1) <= vic_irqs(1);
- trig2(2) <= vic_irqs(2);
- end generate gen_txtsu_debug;
+-- gen_txtsu_debug : for i in 0 to c_NUM_PORTS-1 generate
+-- TRIG0(i) <= txtsu_timestamps(i).stb;
+-- trig1(i) <= txtsu_timestamps_ack(i);
+-- trig2(0) <= vic_irqs(0);
+-- trig2(1) <= vic_irqs(1);
+-- trig2(2) <= vic_irqs(2);
+-- end generate gen_txtsu_debug;
U_Swcore : xswc_core
generic map (
g_prio_num => 8,
+ g_output_queue_num => 8,
g_max_pck_size => 10 * 1024,
g_max_oob_size => 3,
g_num_ports => g_num_ports+1,
g_pck_pg_free_fifo_size => 512,
g_input_block_cannot_accept_data => "drop_pck",
- g_output_block_per_prio_fifo_size => 64,
+ g_output_block_per_queue_fifo_size=> 64,
g_wb_data_width => 16,
g_wb_addr_width => 2,
g_wb_sel_width => 2,
g_wb_ob_ignore_ack => false,
- g_mpm_mem_size => 67584,
- g_mpm_page_size => 66,
- g_mpm_ratio => 6, --f_swc_ratio, --2
+ g_mpm_mem_size => 65536, --test: 61440,--old: 65536,
+ g_mpm_page_size => 64, --test: 60,--old: 64,
+ g_mpm_ratio => 8, --test: 10,--old: 8, --f_swc_ratio, --2
g_mpm_fifo_size => 8,
- g_mpm_fetch_next_pg_in_advance => false)
+ g_mpm_fetch_next_pg_in_advance => false,
+ g_drop_outqueue_head_on_full => true,
+ g_num_global_pause => c_NUM_GL_PAUSE,
+ g_num_dbg_vector_width => c_DBG_V_SWCORE)
port map (
clk_i => clk_sys,
clk_mpm_core_i => clk_aux_i,
@@ -605,10 +733,25 @@ begin
snk_i => endpoint_src_out,
snk_o => endpoint_src_in,
- rtu_rsp_i => rtu_rsp,
- rtu_ack_o => rtu_rsp_ack
+ shaper_drop_at_hp_ena_i => shaper_drop_at_hp_ena,
+
+ -- pause stuff
+ global_pause_i => global_pause,
+ perport_pause_i => fc_rx_pause,
+
+ dbg_o => dbg_n_regs(32+c_DBG_V_SWCORE-1 downto 32),
+
+ rtu_rsp_i => rtu_rsp,
+ rtu_ack_o => rtu_rsp_ack,
+ rtu_abort_o =>rtu_rsp_abort-- open --rtu_rsp_abort
);
+
+ -- SWcore global pause nr=0 assigned to TRU
+ global_pause(0) <= swc2tru_req;
+ -- SWcore global pause nr=1 assigned to TATSU
+ global_pause(1) <= shaper_request;
+
-- NIC sink
--TRIG0 <= f_fabric_2_slv(endpoint_snk_in(1), endpoint_snk_out(1));
---- NIC source
@@ -623,27 +766,105 @@ begin
--TRIG3(0) <= rtu_rsp(c_NUM_PORTS).valid;
--TRIG3(1) <= rtu_rsp_ack(c_NUM_PORTS);
-
-
-
- U_RTU : xwrsw_rtu
+ U_RTU : xwrsw_rtu_new
+-- U_RTU : xwrsw_rtu
generic map (
g_prio_num => 8,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ports => g_num_ports,
+ g_cpu_port_num => g_num_ports, -- g_num_ports-nt port is connected to CPU
g_port_mask_bits => g_num_ports+1,
- g_handle_only_single_req_per_port => true)
+ g_handle_only_single_req_per_port => true,
+ g_rmon_events_bits_pp => c_RTU_EVENTS)
port map (
clk_sys_i => clk_sys,
- rst_n_i => rst_n_periph,
+ rst_n_i => rst_n_sys,--rst_n_periph,
req_i => rtu_req(g_num_ports-1 downto 0),
req_full_o => rtu_full(g_num_ports-1 downto 0),
rsp_o => rtu_rsp(g_num_ports-1 downto 0),
rsp_ack_i => rtu_rsp_ack(g_num_ports-1 downto 0),
+ rsp_abort_i=> rtu_rsp_abort(g_num_ports-1 downto 0), -- this is request from response receiving node
+ rq_abort_i => rtu_rq_abort(g_num_ports-1 downto 0), -- this is request from requesting module
+ ------ new TRU stuff ----------
+ tru_req_o => tru_req,
+ tru_resp_i => tru_resp,
+ rtu2tru_o => rtu2tru,
+ tru_enabled_i => tru_enabled,
+ -------------------------------
+ rmon_events_o => rtu_events,
wb_i => cnx_master_out(c_SLAVE_RTU),
wb_o => cnx_master_in(c_SLAVE_RTU));
+ gen_TRU : if(g_with_TRU = true) generate
+ U_TRU: xwrsw_tru
+ generic map(
+ g_num_ports => g_num_ports,
+ g_tru_subentry_num => 8,
+ g_patternID_width => 4,
+ g_pattern_width => g_num_ports,
+ g_stableUP_treshold => 100,
+ g_pclass_number => 8,
+ g_mt_trans_max_fr_cnt => 1000,
+ g_prio_width => 3,
+ g_pattern_mode_width => 4,
+ g_tru_entry_num => 256,
+ g_interface_mode => PIPELINED,
+ g_address_granularity => BYTE
+ )
+ port map(
+ clk_i => clk_sys,
+ rst_n_i => rst_n_periph,
+ req_i => tru_req,
+ resp_o => tru_resp,
+ rtu_i => rtu2tru,
+ ep_i => ep2tru,
+ ep_o => tru2ep,
+ swc_block_oq_req_o => swc2tru_req,
+ enabled_o => tru_enabled,
+ wb_i => cnx_master_out(c_SLAVE_TRU),
+ wb_o => cnx_master_in(c_SLAVE_TRU));
+
+ end generate gen_TRU;
+
+ gen_no_TRU : if(g_with_TRU = false) generate
+ swc2tru_req <= c_zero_gl_pause;
+ tru2ep <= (others => c_tru2ep_zero);
+ tru_resp <= c_tru_response_zero;
+ tru_enabled <= '0';
+ cnx_master_in(c_SLAVE_TRU).ack <= '1';
+ end generate gen_no_TRU;
+
+ gen_TATSU: if(g_with_TATSU = true) generate
+ U_TATSU: xwrsw_tatsu
+ generic map(
+ g_num_ports => g_num_ports,
+ g_simulation => g_simulation,
+ g_interface_mode => PIPELINED,
+ g_address_granularity => BYTE
+ )
+ port map(
+ clk_sys_i => clk_sys,
+ clk_ref_i => clk_ref_i,
+ rst_n_i => rst_n_sys,
+
+ shaper_request_o => shaper_request,
+ shaper_drop_at_hp_ena_o => shaper_drop_at_hp_ena,
+ tm_utc_i => tm_utc,
+ tm_cycles_i => tm_cycles,
+ tm_time_valid_i => tm_time_valid,
+ wb_i => cnx_master_out(c_SLAVE_TATSU),
+ wb_o => cnx_master_in(c_SLAVE_TATSU)
+ );
+
+ end generate gen_TATSU;
+
+ gen_no_TATSU: if(g_with_TATSU = false) generate
+ shaper_request <= c_zero_gl_pause;
+ shaper_drop_at_hp_ena <= '0';
+ cnx_master_in(c_SLAVE_TATSU).ack <= '1';
+ end generate gen_no_TATSU;
+
end generate gen_network_stuff;
gen_no_network_stuff : if(g_without_network = true) generate
@@ -653,8 +874,6 @@ begin
end generate gen_dummy_resets;
end generate gen_no_network_stuff;
-
-
U_Tx_TSU : xwrsw_tx_tsu
generic map (
g_num_ports => c_NUM_PORTS,
@@ -677,7 +896,7 @@ begin
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
- g_num_pins => 32,
+ g_num_pins => c_NUM_GPIO_PINS,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys,
@@ -686,63 +905,121 @@ begin
slave_o => cnx_master_in(c_SLAVE_GPIO),
gpio_b => dummy,
gpio_out_o => gpio_out,
- gpio_in_i => gpio_i);
+ gpio_in_i => gpio_in);
- uart_sel_o <= gpio_out(31);
+ uart_sel_o <= gpio_out(0);
- gpio_o <= gpio_out;
+ gpio_o(0) <= gpio_out(0);
+ gpio_in(0) <= gpio_i(0);
- U_MiniBackplane_I2C0 : xwb_i2c_master
- generic map (
- g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
- port map (
- clk_sys_i => clk_sys,
- rst_n_i => rst_n_periph,
- slave_i => cnx_master_out(c_SLAVE_MBL_I2C0),
- slave_o => cnx_master_in(c_SLAVE_MBL_I2C0),
- desc_o => open,
- scl_pad_i => i2c_scl_i(0),
- scl_pad_o => i2c_scl_o(0),
- scl_padoen_o => i2c_scl_oen_o(0),
- sda_pad_i => i2c_sda_i(0),
- sda_pad_o => i2c_sda_o(0),
- sda_padoen_o => i2c_sda_oen_o(0));
-
- U_MiniBackplane_I2C1 : xwb_i2c_master
- generic map (
- g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
- port map (
- clk_sys_i => clk_sys,
- rst_n_i => rst_n_periph,
- slave_i => cnx_master_out(c_SLAVE_MBL_I2C1),
- slave_o => cnx_master_in(c_SLAVE_MBL_I2C1),
- desc_o => open,
- scl_pad_i => i2c_scl_i(1),
- scl_pad_o => i2c_scl_o(1),
- scl_padoen_o => i2c_scl_oen_o(1),
- sda_pad_i => i2c_sda_i(1),
- sda_pad_o => i2c_sda_o(1),
- sda_padoen_o => i2c_sda_oen_o(1));
-
- U_Sensors_I2C : xwb_i2c_master
+ U_MiniBackplane_I2C : xwb_i2c_master
generic map (
g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
+ g_address_granularity => BYTE,
+ g_num_interfaces => 3)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_periph,
- slave_i => cnx_master_out(c_SLAVE_SENSOR_I2C),
- slave_o => cnx_master_in(c_SLAVE_SENSOR_I2C),
+ slave_i => cnx_master_out(c_SLAVE_I2C),
+ slave_o => cnx_master_in(c_SLAVE_I2C),
desc_o => open,
- scl_pad_i => i2c_scl_i(2),
- scl_pad_o => i2c_scl_o(2),
- scl_padoen_o => i2c_scl_oen_o(2),
- sda_pad_i => i2c_sda_i(2),
- sda_pad_o => i2c_sda_o(2),
- sda_padoen_o => i2c_sda_oen_o(2));
+ scl_pad_i => i2c_scl_i,
+ scl_pad_o => i2c_scl_o,
+ scl_padoen_o => i2c_scl_oen_o,
+ sda_pad_i => i2c_sda_i,
+ sda_pad_o => i2c_sda_o,
+ sda_padoen_o => i2c_sda_oen_o);
+
+ --=====================================--
+ -- PSTATS --
+ --=====================================--
+ gen_PSTATS: if(g_with_PSTATS = true) generate
+ U_PSTATS : xwrsw_pstats
+ generic map(
+ g_interface_mode => PIPELINED,
+ g_address_granularity => BYTE,
+ g_nports => c_NUM_PORTS,
+ g_cnt_pp => c_ALL_EVENTS,
+ g_cnt_pw => 4)
+ port map(
+ rst_n_i => rst_n_periph,
+ clk_i => clk_sys,
+
+ events_i => rmon_events,
+
+ wb_i => cnx_master_out(c_SLAVE_PSTATS),
+ wb_o => cnx_master_in(c_SLAVE_PSTATS));
+
+ end generate;
+
+ gen_no_PSTATS: if(g_with_PSTATS = false) generate
+ cnx_master_in(c_SLAVE_PSTATS).ack <= '1';
+ cnx_master_in(c_SLAVE_PSTATS).int <= '0';
+ end generate;
+
+ gen_events_assemble : for i in 0 to c_NUM_PORTS-1 generate
+ rmon_events((i+1)*c_ALL_EVENTS-1 downto i*c_ALL_EVENTS) <=
+ std_logic(tru_resp.respMask(i) and tru_resp.valid) &
+ rtu_events((i+1)*c_RTU_EVENTS-1 downto i*c_RTU_EVENTS) &
+ ep_events ((i+1)*c_epevents_sz-1 downto i*c_epevents_sz);
+ end generate gen_events_assemble;
+
+ --=====================================--
+ -- HWDU --
+ --=====================================--
+ gen_HWDU: if(g_with_HWDU = true) generate
+ U_HWDU : xwrsw_hwdu
+ generic map(
+ g_interface_mode => PIPELINED,
+ g_address_granularity => BYTE,
+ g_nregs => c_DBG_N_REGS)
+ port map(
+ rst_n_i => rst_n_periph,
+ clk_i => clk_sys,
+
+ dbg_regs_i => dbg_n_regs,
+ dbg_chps_id_o => dbg_chps_id,
+ wb_i => cnx_master_out(c_SLAVE_HWDU),
+ wb_o => cnx_master_in(c_SLAVE_HWDU));
+
+ dbg_n_regs( 32-1 downto 0) <= c_GW_VERSION;
+-- dbg_n_regs(2*32-1 downto c_DBG_V_SWCORE+32) <= (others=>'0');
+ end generate;
+ gen_no_HWDU: if(g_with_HWDU = false) generate
+ cnx_master_in(c_SLAVE_HWDU).ack <= '1';
+ cnx_master_in(c_SLAVE_HWDU).dat <= c_GW_VERSION;--x"deadbeef";
+ cnx_master_in(c_SLAVE_HWDU).err <= '0';
+ cnx_master_in(c_SLAVE_HWDU).stall <= '0';
+ cnx_master_in(c_SLAVE_HWDU).rty <= '0';
+ dbg_chps_id <= (others =>'0');
+ end generate;
+
+
+ -- debugging for RMONS, not to be included into final release
+ --gen_dummy_rmon: if(c_DUMMY_RMON = true) generate
+ -- U_DUMMY: dummy_rmon
+ -- generic map(
+ -- g_interface_mode => PIPELINED,
+ -- g_address_granularity => BYTE,
+ -- g_nports => c_NUM_PORTS,
+ -- g_cnt_pp => 2)
+ -- port map(
+ -- rst_n_i => rst_n_periph,
+ -- clk_i => clk_sys,
+ -- events_i => dummy_events,
+ -- wb_i => cnx_master_out(c_SLAVE_DUMMY),
+ -- wb_o => cnx_master_in(c_SLAVE_DUMMY));
+
+ -- gen_dummy_events_assemble : for i in 0 to c_NUM_PORTS-1 generate
+ -- dummy_events((i+1)*2-1 downto i*2) <= rmon_events((i+1)*c_epevents_sz-1 downto (i+1)*c_epevents_sz-2);
+ -- end generate gen_dummy_events_assemble;
+
+ --end generate gen_dummy_rmon;
+ --
+ --gen_no_dummy_rmon: if(c_DUMMY_RMON = false) generate
+ -- cnx_master_in(c_SLAVE_DUMMY).ack <= '1';
+ --end generate gen_no_dummy_rmon;
-----------------------------------------------------------------------------
-- PWM Controlle for mini-backplane fan drive
@@ -751,6 +1028,7 @@ begin
U_PWM_Controller : xwb_simple_pwm
generic map (
g_num_channels => 2,
+ g_regs_size => 8,
g_default_period => 255,
g_default_presc => 30,
g_default_val => 255,
@@ -771,7 +1049,7 @@ begin
vic_irqs(0) <= cnx_master_in(c_SLAVE_NIC).int;
vic_irqs(1) <= cnx_master_in(c_SLAVE_TXTSU).int;
vic_irqs(2) <= cnx_master_in(c_SLAVE_RTU).int;
- vic_irqs(31 downto 3) <= (others => '0');
+ vic_irqs(3) <= cnx_master_in(c_SLAVE_PSTATS).int;
-------------------------------------------------------------------------------
-- Various constant-driven I/Os
@@ -785,17 +1063,393 @@ begin
-----------------------------------------------------------------------------
-- Hardware Info Unit providing firmware version for software
-----------------------------------------------------------------------------
- U_HWIU: xwrsw_hwiu
- generic map(
- g_interface_mode => PIPELINED,
- g_address_granularity => BYTE,
- g_ver_major => 3,
- g_ver_minor => 3,
- g_build => 1)
- port map(
- rst_n_i => rst_n_periph,
- clk_i => clk_sys,
- wb_i => cnx_master_out(c_SLAVE_HWIU),
- wb_o => cnx_master_in(c_SLAVE_HWIU));
+-- U_HWIU: xwrsw_hwiu
+-- generic map(
+-- g_interface_mode => PIPELINED,
+-- g_address_granularity => BYTE,
+-- g_ver_major => 3,
+-- g_ver_minor => 3,
+-- g_build => 1)
+-- port map(
+-- rst_n_i => rst_n_periph,
+-- clk_i => clk_sys,
+-- wb_i => cnx_master_out(c_SLAVE_HWIU),
+-- wb_o => cnx_master_in(c_SLAVE_HWIU));
+
+--
+-- CS_ICON : chipscope_icon
+-- port map (
+-- CONTROL0 => CONTROL0);
+-- CS_ILA : chipscope_ila
+-- port map (
+-- CONTROL => CONTROL0,
+-- CLK => clk_sys, --phys_i(0).rx_clk,
+-- TRIG0 => T0,
+-- TRIG1 => T1,
+-- TRIG2 => T2,
+-- TRIG3 => T3);
+--
+-- T0 <= TRIG0(to_integer(unsigned(dbg_chps_id)));
+-- T1 <= TRIG1(to_integer(unsigned(dbg_chps_id)));
+-- T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
+-- T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
+
+ --------------------------- dbg_epj
+-- TRIG0(15 downto 0) <= phys_i(0).rx_data;
+-- TRIG0(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(23 downto 19) <= phys_i(0).rx_bitslide;
+-- TRIG0(31 downto 24) <= ep_dbg_rx_buf_array(0);
+--
+-- TRIG1(15 downto 0) <= phys_i(7).rx_data;
+-- TRIG1(17 downto 16) <= phys_i(7).rx_k;
+-- TRIG1( 18) <= phys_i(7).rx_enc_err;
+-- TRIG1(23 downto 19) <= phys_i(7).rx_bitslide;
+-- TRIG1(31 downto 24) <= ep_dbg_rx_buf_array(7);
+--
+-- TRIG2(15 downto 0) <= ep_dbg_data_array(0);
+-- TRIG2(17 downto 16) <= ep_dbg_k_array(0);
+-- TRIG2( 18) <= phys_i(0).tx_enc_err;
+-- TRIG2( 19) <= phys_i(0).tx_disparity;
+-- TRIG2(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+--
+-- TRIG3(15 downto 0) <= ep_dbg_data_array(7);
+-- TRIG3(17 downto 16) <= ep_dbg_k_array(7);
+-- TRIG3( 18) <= phys_i(7).tx_enc_err;
+-- TRIG3( 19) <= phys_i(7).tx_disparity;
+-- TRIG3(29 downto 20) <= dbg_n_regs(61 downto 52) ; -- normal resources
+
+-- ----------------------------- dbg_epj.v2
+-- TRIG0(1)(15 downto 0) <= phys_i(0).rx_data;
+-- TRIG0(1)(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0(1)( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(1)(23 downto 19) <= phys_i(0).rx_bitslide;
+-- TRIG0(1)(31 downto 24) <= ep_dbg_rx_buf_array(0);
+--
+-- TRIG1(1)(29 downto 0) <= ep_dbg_fab_pipes_array(0)(29 downto 0); -- rx_path
+--
+-- TRIG2(1)(11 downto 0) <= ep_dbg_fab_pipes_array(7)(43 downto 32); -- tx_path
+-- TRIG2(1)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+--
+-- TRIG3(1)(15 downto 0) <= ep_dbg_data_array(7);
+-- TRIG3(1)(17 downto 16) <= ep_dbg_k_array(7);
+-- TRIG3(1)( 18) <= phys_i(7).tx_enc_err;
+-- TRIG3(1)( 19) <= phys_i(7).tx_disparity;
+-- TRIG3(1)(29 downto 20) <= dbg_n_regs(61 downto 52) ; -- normal resources
+
+-- ----------------------------- dbg_epj.v3
+-- TRIG0(15 downto 0) <= phys_i(0).rx_data;
+-- TRIG0(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(23 downto 19) <= phys_i(0).rx_bitslide;
+-- TRIG0(31 downto 24) <= ep_dbg_rx_buf_array(0);
+--
+-- TRIG1(15 downto 0) <= endpoint_src_out(0).dat;
+-- TRIG1(17 downto 16) <= endpoint_src_out(0).adr;
+-- TRIG1( 18) <= endpoint_src_out(0).cyc;
+-- TRIG1( 19) <= endpoint_src_out(0).stb;
+-- TRIG1( 20) <= endpoint_src_out(0).stb;
+-- TRIG1( 21) <= endpoint_src_in(0).stall;
+-- TRIG1( 22) <= endpoint_src_in(0).ack;
+-- TRIG1( 23) <= endpoint_src_in(0).err;
+-- TRIG1(31 downto 24) <= ep_dbg_rx_buf_array(7);
+--
+--
+-- TRIG2(15 downto 0) <= endpoint_snk_in(0).dat;
+-- TRIG2(17 downto 16) <= endpoint_snk_in(0).adr;
+-- TRIG2( 18) <= endpoint_snk_in(0).cyc;
+-- TRIG2( 19) <= endpoint_snk_in(0).stb;
+-- TRIG2( 20) <= endpoint_snk_in(0).stb;
+-- TRIG2( 21) <= endpoint_snk_out(0).stall;
+-- TRIG2( 22) <= endpoint_snk_out(0).ack;
+-- TRIG2( 23) <= endpoint_snk_out(0).err;
+-- TRIG2(31 downto 24) <= dbg_n_regs(39 downto 32) ; -- unknow resources
+--
+-- TRIG3(15 downto 0) <= ep_dbg_data_array(7);
+-- TRIG3(17 downto 16) <= ep_dbg_k_array(7);
+-- TRIG3( 18) <= phys_i(7).tx_enc_err;
+-- TRIG3( 19) <= phys_i(7).tx_disparity;
+-- TRIG3(29 downto 20) <= dbg_n_regs(61 downto 52) ; -- normal resources
+
+-- ----------------------------- dbg_epj.v4
+-- TRIG0(15 downto 0) <= phys_i(0).rx_data;
+-- TRIG0(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(23 downto 19) <= phys_i(0).rx_bitslide;
+-- TRIG0(31 downto 24) <= ep_dbg_rx_buf_array(0);
+--
+-- TRIG1(15 downto 0) <= endpoint_src_out(0).dat;
+-- TRIG1( 16) <= endpoint_src_out(0).cyc;
+-- TRIG1( 17) <= endpoint_src_out(0).stb;
+-- TRIG1( 18) <= endpoint_src_in(0).stall;
+-- TRIG1( 19) <= endpoint_src_in(0).err;
+-- TRIG1(25 downto 20) <= ep_dbg_tx_pcs_wr_array(7);
+-- TRIG1(31 downto 26) <= ep_dbg_tx_pcs_rd_array(7);
+--
+--
+-- TRIG2(15 downto 0) <= endpoint_snk_in(7).dat;
+-- TRIG2(17 downto 16) <= endpoint_snk_in(7).adr;
+-- TRIG2( 18) <= endpoint_snk_in(7).cyc;
+-- TRIG2( 19) <= endpoint_snk_in(7).stb;
+-- TRIG2( 20) <= endpoint_snk_in(7).stb;
+-- TRIG2( 21) <= endpoint_snk_out(7).stall;
+-- TRIG2( 22) <= endpoint_snk_out(7).ack;
+-- TRIG2( 23) <= endpoint_snk_out(7).err;
+-- TRIG2(31 downto 24) <= dbg_n_regs(39 downto 32) ; -- unknow resources
+--
+-- TRIG3(15 downto 0) <= ep_dbg_data_array(7);
+-- TRIG3(17 downto 16) <= ep_dbg_k_array(7);
+-- TRIG3( 18) <= phys_i(7).tx_enc_err;
+-- TRIG3( 19) <= phys_i(7).tx_disparity;
+-- TRIG3(29 downto 20) <= dbg_n_regs(61 downto 52) ; -- normal resources
+--
+
+ ----------------------------- dbg_epj.v6
+-- TRIG0(15 downto 0) <= phys_i(0).rx_data;
+-- TRIG0(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(31 downto 22) <= ep_dbg_tx_pcs_wr_array(7);
+--
+-- TRIG1(15 downto 0) <= endpoint_src_out(0).dat;
+-- TRIG1( 16) <= endpoint_src_out(0).cyc;
+-- TRIG1( 17) <= endpoint_src_out(0).stb;
+-- TRIG1( 18) <= endpoint_src_in(0).stall;
+-- TRIG1( 19) <= endpoint_src_in(0).err;
+-- TRIG1(31 downto 22) <= ep_dbg_tx_pcs_rd_array(7);
+--
+--
+-- TRIG2(15 downto 0) <= endpoint_snk_in(7).dat;
+-- TRIG2(17 downto 16) <= endpoint_snk_in(7).adr;
+-- TRIG2( 18) <= endpoint_snk_in(7).cyc;
+-- TRIG2( 19) <= endpoint_snk_in(7).stb;
+-- TRIG2( 20) <= endpoint_snk_in(7).stb;
+-- TRIG2( 21) <= endpoint_snk_out(7).stall;
+-- TRIG2( 22) <= endpoint_snk_out(7).ack;
+-- TRIG2( 23) <= endpoint_snk_out(7).err;
+-- TRIG2(31 downto 24) <= dbg_n_regs(39 downto 32) ; -- unknow resources
+--
+-- TRIG3(15 downto 0) <= ep_dbg_data_array(7);
+-- TRIG3(17 downto 16) <= ep_dbg_k_array(7);
+-- TRIG3( 18) <= phys_i(7).tx_enc_err;
+-- TRIG3( 19) <= phys_i(7).tx_disparity;
+-- TRIG3(29 downto 20) <= dbg_n_regs(61 downto 52) ; -- normal resources
+
+
+ ----------------------------- dbg_id0
+ TRIG0(0)(15 downto 0) <= phys_i(0).rx_data;
+ TRIG0(0)(17 downto 16) <= phys_i(0).rx_k;
+ TRIG0(0)( 18) <= phys_i(0).rx_enc_err;
+ TRIG0(0)(20 downto 19) <= ep_dbg_k_array(7);
+
+ TRIG0(0)( 24) <= endpoint_src_out(0).cyc;
+ TRIG0(0)( 25) <= endpoint_src_out(0).stb;
+ TRIG0(0)( 26) <= endpoint_src_in(0).stall;
+ TRIG0(0)( 27) <= endpoint_src_in(0).err;
+ TRIG0(0)( 28) <= endpoint_src_in(0).ack;
+ TRIG0(0)( 29) <= endpoint_snk_in(7).cyc;
+ TRIG0(0)( 30) <= endpoint_snk_in(7).stb;
+ TRIG0(0)( 31) <= endpoint_snk_out(7).stall;
+
+
+ TRIG1(0)(29 downto 0) <= ep_dbg_fab_pipes_array(0)(29 downto 0); -- rx_path
+ TRIG1(0)( 30) <= endpoint_snk_out(7).ack;
+ TRIG1(0)( 31) <= endpoint_snk_out(7).err;
+
+ TRIG2(0)(11 downto 0) <= ep_dbg_fab_pipes_array(7)(41 downto 30); -- tx_path
+ TRIG2(0)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+ TRIG2(0)( 30) <= phys_i(7).tx_enc_err;
+ TRIG2(0)( 31) <= phys_i(7).tx_disparity;
+
+
+ TRIG3(0)(15 downto 0) <= ep_dbg_data_array(7);
+ TRIG3(0)(23 downto 16) <= endpoint_snk_in(7).dat(7 downto 0);
+
+ gen_18P_out_blk_states: if(g_num_ports = 18 ) generate
+ TRIG3(0)(31 downto 24) <= dbg_n_regs(431 downto 424); --p7 for 18 ports: should be states of output block i SWcore
+ TRIG3(1)(31 downto 24) <= dbg_n_regs(431 downto 424); --p7 for 18 ports: should be states of output block i SWcore
+ TRIG3(2)(31 downto 24) <= dbg_n_regs(503 downto 496); --p16 for 18 ports: should be states of output block i SWcore
+ TRIG3(3)(31 downto 24) <= dbg_n_regs(511 downto 504); --p17 for 18 ports: should be states of output block i SWcore
+ TRIG3(4)(31 downto 24) <= dbg_n_regs(375 downto 368); --p0 for 18 ports: should be states of output block i SWcore
+ TRIG3(5)(31 downto 24) <= dbg_n_regs(383 downto 376); --p1 for 18 ports: should be states of output block i SWcore
+ end generate gen_18P_out_blk_states;
+ gen_8P_out_blk_states: if(g_num_ports = 8 ) generate
+ TRIG3(0)(31 downto 24) <= dbg_n_regs(271 downto 264); -- for 8 ports: should be states of output block i SWcore
+ TRIG3(1)(31 downto 24) <= dbg_n_regs(271 downto 264); -- for 8 ports: should be states of output block i SWcore
+ TRIG3(4)(31 downto 24) <= dbg_n_regs(215 downto 208); --p0 for 18 ports: should be states of output block i SWcore
+ TRIG3(5)(31 downto 24) <= dbg_n_regs(223 downto 216); --p1 for 18 ports: should be states of output block i SWcore
+
+ end generate gen_8P_out_blk_states;
+
+ ----------------------------- dbg_id1
+ TRIG0(1)(15 downto 0) <= endpoint_snk_in(7).dat; -- 0 -15
+ TRIG0(1)(17 downto 16) <= endpoint_snk_in(7).adr(1 downto 0); -- 16-17
+ TRIG0(1)( 18) <= endpoint_snk_out(7).ack; -- 17
+-- TRIG0(1)(20 downto 19) <= ep_dbg_k_array(7);
+ TRIG0(1)(28 downto 19) <= ep_dbg_tx_pcs_rd_array(7);-- pcs new
+-- TRIG0(1)( 28) <= endpoint_snk_out(7).err;
+ TRIG0(1)( 29) <= endpoint_snk_in(7).cyc; -- 29
+ TRIG0(1)( 30) <= endpoint_snk_in(7).stb; -- 30
+ TRIG0(1)( 31) <= endpoint_snk_out(7).stall; -- 31
+
+ TRIG1(1)(21 downto 0) <= ep_dbg_fab_pipes_array(7)(63 downto 42); -- tx_path: 32 - 53
+ TRIG1(1)(31 downto 22) <= ep_dbg_tx_pcs_wr_array(7); -- pcs new: pcs tx write to FIFO
+
+ TRIG2(1)(11 downto 0) <= ep_dbg_fab_pipes_array(7)(41 downto 30); -- tx_path : 64- 75
+ TRIG2(1)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+ TRIG2(1)( 30) <= phys_i(7).tx_enc_err;
+ TRIG2(1)( 31) <= endpoint_snk_out(7).err;--phys_i(7).tx_disparity;
+
+ TRIG3(1)(15 downto 0) <= ep_dbg_data_array(7);
+
+ gen_18P_chip: if(g_num_ports = 18 ) generate
+ ----------------------------- dbg_id2
+ TRIG0(2)(15 downto 0) <= endpoint_snk_in(16).dat;
+ TRIG0(2)(17 downto 16) <= endpoint_snk_in(16).adr(1 downto 0);
+ TRIG0(2)( 18) <= endpoint_snk_out(16).ack;
+ --TRIG0(2)(20 downto 19) <= ep_dbg_k_array(16);
+ TRIG0(2)(28 downto 19) <= ep_dbg_tx_pcs_rd_array(16); -- pcs new
+-- TRIG0(2)( 28) <= endpoint_snk_out(16).err;
+ TRIG0(2)( 29) <= endpoint_snk_in(16).cyc;
+ TRIG0(2)( 30) <= endpoint_snk_in(16).stb;
+ TRIG0(2)( 31) <= endpoint_snk_out(16).stall;
+
+ TRIG1(2)(21 downto 0) <= ep_dbg_fab_pipes_array(16)(63 downto 42);
+ TRIG1(2)(31 downto 22) <= ep_dbg_tx_pcs_wr_array(16); -- pcs new: pcs tx write to FIFO
+
+ TRIG2(2)(11 downto 0) <= ep_dbg_fab_pipes_array(16)(41 downto 30); -- tx_path
+ TRIG2(2)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+ TRIG2(2)( 30) <= phys_i(16).tx_enc_err;
+ TRIG2(2)( 31) <= endpoint_snk_out(16).err;
+
+ TRIG3(2)(15 downto 0) <= ep_dbg_data_array(16);
+
+ ----------------------------- dbg_id3
+ TRIG0(3)(15 downto 0) <= endpoint_snk_in(17).dat;
+ TRIG0(3)(17 downto 16) <= endpoint_snk_in(17).adr(1 downto 0);
+ TRIG0(3)( 18) <= endpoint_snk_out(17).ack;
+-- TRIG0(3)(20 downto 19) <= ep_dbg_k_array(17);
+ TRIG0(3)(28 downto 19) <= ep_dbg_tx_pcs_rd_array(17); -- pcs new
+-- TRIG0(3)( 28) <= endpoint_snk_out(17).err;
+ TRIG0(3)( 29) <= endpoint_snk_in(17).cyc;
+ TRIG0(3)( 30) <= endpoint_snk_in(17).stb;
+ TRIG0(3)( 31) <= endpoint_snk_out(17).stall;
+
+ TRIG1(3)(21 downto 0) <= ep_dbg_fab_pipes_array(17)(63 downto 42);
+ TRIG1(3)(31 downto 22) <= ep_dbg_tx_pcs_wr_array(17); -- pcs new: pcs tx write to FIFO
+
+ TRIG2(3)(11 downto 0) <= ep_dbg_fab_pipes_array(17)(41 downto 30); -- tx_path
+ TRIG2(3)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+ TRIG2(3)( 30) <= phys_i(17).tx_enc_err;
+ TRIG2(3)( 31) <= endpoint_snk_out(17).err;--phys_i(17).tx_disparity;
+
+ TRIG3(3)(15 downto 0) <= ep_dbg_data_array(17);
+
+ ----------------------------- dbg_id4
+ TRIG0(4)(15 downto 0) <= endpoint_snk_in(0).dat;
+ TRIG0(4)(17 downto 16) <= endpoint_snk_in(0).adr(1 downto 0);
+ TRIG0(4)( 18) <= endpoint_snk_out(0).ack;
+-- TRIG0(4)(20 downto 19) <= ep_dbg_k_array(0);
+ TRIG0(4)(28 downto 19) <= ep_dbg_tx_pcs_rd_array(0); -- pcs new
+-- TRIG0(4)( 28) <= endpoint_snk_out(0).err;
+ TRIG0(4)( 29) <= endpoint_snk_in(0).cyc;
+ TRIG0(4)( 30) <= endpoint_snk_in(0).stb;
+ TRIG0(4)( 31) <= endpoint_snk_out(0).stall;
+
+ TRIG1(4)(21 downto 0) <= ep_dbg_fab_pipes_array(0)(63 downto 42);
+ TRIG1(4)(31 downto 22) <= ep_dbg_tx_pcs_wr_array(0); -- pcs new: pcs tx write to FIFO
+
+ TRIG2(4)(11 downto 0) <= ep_dbg_fab_pipes_array(0)(41 downto 30); -- tx_path
+ TRIG2(4)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+ TRIG2(4)( 30) <= phys_i(0).tx_enc_err;
+ TRIG2(4)( 31) <= endpoint_snk_out(0).err;--phys_i(0).tx_disparity;
+
+ TRIG3(4)(15 downto 0) <= ep_dbg_data_array(0);
+
+ ----------------------------- dbg_id5
+ TRIG0(5)(15 downto 0) <= endpoint_snk_in(1).dat;
+ TRIG0(5)(17 downto 16) <= endpoint_snk_in(1).adr(1 downto 0);
+ TRIG0(5)( 18) <= endpoint_snk_out(1).ack;
+-- TRIG0(5)(20 downto 19) <= ep_dbg_k_array(1);
+ TRIG0(5)(28 downto 19) <= ep_dbg_tx_pcs_rd_array(1); -- pcs new
+-- TRIG0(5)( 28) <= endpoint_snk_out(1).err;
+ TRIG0(5)( 29) <= endpoint_snk_in(1).cyc;
+ TRIG0(5)( 30) <= endpoint_snk_in(1).stb;
+ TRIG0(5)( 31) <= endpoint_snk_out(1).stall;
+
+ TRIG1(5)(21 downto 0) <= ep_dbg_fab_pipes_array(1)(63 downto 42);
+ TRIG1(5)(31 downto 22) <= ep_dbg_tx_pcs_wr_array(1); -- pcs new: pcs tx write to FIFO
+ TRIG2(5)(11 downto 0) <= ep_dbg_fab_pipes_array(1)(41 downto 30); -- tx_path
+ TRIG2(5)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+ TRIG2(5)( 30) <= phys_i(1).tx_enc_err;
+ TRIG2(5)( 31) <= endpoint_snk_out(1).err;--phys_i(1).tx_disparity;
+
+ TRIG3(5)(15 downto 0) <= ep_dbg_data_array(1);
+
+ end generate gen_18P_chip;
+
+ ----------------------------- dbg_epj new - v8
+-- TRIG0(2)(15 downto 0) <= phys_i(0).rx_data ;
+-- TRIG0(2)(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0(2)( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(2)(20 downto 19) <= ep_dbg_k_array(7);
+--
+-- TRIG0(2)( 24) <= endpoint_src_out(0).cyc;
+-- TRIG0(2)( 25) <= endpoint_src_out(0).stb;
+-- TRIG0(2)( 26) <= endpoint_src_in(0).stall;
+-- TRIG0(2)( 27) <= endpoint_src_in(0).err;
+-- TRIG0(2)( 28) <= endpoint_src_in(0).ack;
+-- TRIG0(2)( 29) <= endpoint_snk_in(7).cyc;
+-- TRIG0(2)( 30) <= endpoint_snk_in(7).stb;
+-- TRIG0(2)( 31) <= endpoint_snk_out(7).stall;
+--
+--
+-- TRIG1(2)(29 downto 0) <= ep_dbg_fab_pipes_array(0)(29 downto 0); -- rx_path
+-- TRIG1(2)( 30) <= endpoint_snk_out(7).ack;
+-- TRIG1(2)( 31) <= endpoint_snk_out(7).err;
+--
+-- TRIG2(2)(11 downto 0) <= ep_dbg_fab_pipes_array(7)(43 downto 32); -- tx_path
+-- TRIG2(2)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+-- TRIG2(2)( 30) <= phys_i(7).tx_enc_err;
+-- TRIG2(2)( 31) <= phys_i(7).tx_disparity;
+--
+-- TRIG3(2)(7 downto 0) <= dbg_n_regs(239 downto 232);
+-- TRIG3(2)(21 downto 12) <= ep_dbg_tx_pcs_wr_array(0);
+-- TRIG3(2)(31 downto 22) <= ep_dbg_tx_pcs_rd_array(7);
+--
+-- ----------------------------- dbg_epj new-v7
+-- TRIG0(3)(15 downto 0) <= phys_i(0).rx_data ;
+-- TRIG0(3)(17 downto 16) <= phys_i(0).rx_k;
+-- TRIG0(3)( 18) <= phys_i(0).rx_enc_err;
+-- TRIG0(3)(20 downto 19) <= ep_dbg_k_array(7);
+--
+-- TRIG0(3)( 24) <= endpoint_src_out(0).cyc;
+-- TRIG0(3)( 25) <= endpoint_src_out(0).stb;
+-- TRIG0(3)( 26) <= endpoint_src_in(0).stall;
+-- TRIG0(3)( 27) <= endpoint_src_in(0).err;
+-- TRIG0(3)( 28) <= endpoint_src_in(0).ack;
+-- TRIG0(3)( 29) <= endpoint_snk_in(1).cyc;
+-- TRIG0(3)( 30) <= endpoint_snk_in(1).stb;
+-- TRIG0(3)( 31) <= endpoint_snk_out(1).stall;
+--
+--
+-- TRIG1(3)(29 downto 0) <= ep_dbg_fab_pipes_array(0)(29 downto 0); -- rx_path
+-- TRIG1(3)( 30) <= endpoint_snk_out(1).ack;
+-- TRIG1(3)( 31) <= endpoint_snk_out(1).err;
+--
+-- TRIG2(3)(11 downto 0) <= ep_dbg_fab_pipes_array(1)(43 downto 32); -- tx_path
+-- TRIG2(3)(29 downto 20) <= dbg_n_regs(41 downto 32) ; -- unknow resources
+-- TRIG2(3)( 30) <= phys_i(1).tx_enc_err;
+-- TRIG2(3)( 31) <= phys_i(1).tx_disparity;
+--
+--
+-- TRIG3(3)(15 downto 0) <= ep_dbg_data_array(1);
+-- TRIG3(3)(23 downto 16) <= endpoint_snk_in(7).dat(7 downto 0);
+-- gen_18P_out_blk_states: if(g_num_ports = 18 ) generate
+-- TRIG3(3)(31 downto 24) <= dbg_n_regs(431 downto 424); -- for 18 ports: should be states of output block i SWcore
+-- end generate gen_18P_out_blk_states;
+-- gen_8P_out_blk_states: if(g_num_ports = 8 ) generate
+-- TRIG3(3)(31 downto 24) <= dbg_n_regs(271 downto 264); -- for 8 ports: should be states of output block i SWcore
+-- end generate gen_8P_out_blk_states;
+
end rtl;
diff --git a/top/bare_top/scb_top_sim.vhd b/top/bare_top/scb_top_sim.vhd
index 1537d3795eceed057a02fab45eccd546fab49632..42260cca31c7eb5ae03581aa420760aeed772267 100644
--- a/top/bare_top/scb_top_sim.vhd
+++ b/top/bare_top/scb_top_sim.vhd
@@ -137,7 +137,10 @@ begin -- rtl
generic map (
g_num_ports => g_num_ports,
g_simulation => true,
- g_without_network => false)
+ g_without_network => false,
+ g_with_TRU => true,
+ g_with_TATSU => true,
+ g_with_HWDU => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_startup_i,
diff --git a/top/bare_top/wrsw_components_pkg.vhd b/top/bare_top/wrsw_components_pkg.vhd
index ca6530e3d092b291149fbbc7c57bdf505040b676..e91a93829548856520961aa51d7f47b50855806d 100644
--- a/top/bare_top/wrsw_components_pkg.vhd
+++ b/top/bare_top/wrsw_components_pkg.vhd
@@ -140,7 +140,8 @@ package wrsw_components_pkg is
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
- g_src_cyc_on_stall : boolean := false);
+ g_src_cyc_on_stall : boolean := false;
+ g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -148,7 +149,7 @@ package wrsw_components_pkg is
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
@@ -182,6 +183,9 @@ package wrsw_components_pkg is
pps_p_o : out std_logic;
pps_raw_i : in std_logic;
sel_clk_sys_o : out std_logic;
+ tm_utc_o : out std_logic_vector(39 downto 0);
+ tm_cycles_o : out std_logic_vector(27 downto 0);
+ tm_time_valid_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
@@ -211,12 +215,13 @@ package wrsw_components_pkg is
component xswc_core is
generic(
g_prio_num : integer ;
+ g_output_queue_num : integer ;
g_max_pck_size : integer ;
g_max_oob_size : integer ;
g_num_ports : integer ;
g_pck_pg_free_fifo_size : integer ;
g_input_block_cannot_accept_data : string ;
- g_output_block_per_prio_fifo_size : integer ;
+ g_output_block_per_queue_fifo_size : integer ;
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
@@ -227,7 +232,10 @@ package wrsw_components_pkg is
g_mpm_page_size : integer ;
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
- g_mpm_fetch_next_pg_in_advance : boolean
+ g_mpm_fetch_next_pg_in_advance : boolean ;
+ g_drop_outqueue_head_on_full : boolean ;
+ g_num_global_pause : integer ;
+ g_num_dbg_vector_width : integer := 8
);
port (
clk_i : in std_logic;
@@ -239,9 +247,14 @@ package wrsw_components_pkg is
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
-
+
+ global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
+ perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
+ shaper_drop_at_hp_ena_i : in std_logic := '0';
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
- rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
+ rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
end component;
component xwrsw_rtu
@@ -259,10 +272,79 @@ package wrsw_components_pkg is
req_full_o : out std_logic_vector(g_num_ports-1 downto 0);
rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
+ -------- new stuff for TRU --------
+ tru_req_o : in t_tru_request;
+ ru_resp_i : out t_tru_response;
+ rtu2tru_o : out t_rtu2tru;
+ tru_enabled_i: in std_logic;
+ -----------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
+ component xwrsw_rtu_new
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_handle_only_single_req_per_port : boolean := FALSE;
+ g_prio_num : integer;
+ g_num_ports : integer;
+ g_cpu_port_num : integer := -1;
+ g_match_req_fifo_size : integer := 32;
+ g_port_mask_bits : integer;
+ g_rmon_events_bits_pp : integer := 8);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ req_i : in t_rtu_request_array(g_num_ports-1 downto 0);
+ req_full_o : out std_logic_vector(g_num_ports-1 downto 0);
+ rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
+ rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rq_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rsp_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
+ tru_req_o : out t_tru_request;
+ tru_resp_i : in t_tru_response;
+ rtu2tru_o : out t_rtu2tru;
+ tru_enabled_i: in std_logic;
+ rmon_events_o : out std_logic_vector(g_num_ports*g_rmon_events_bits_pp-1 downto 0);
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+ );
+ end component;
+
+ component xwrsw_pstats
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nports : integer := 2;
+ g_cnt_pp : integer := 16;
+ g_cnt_pw : integer := 4);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out );
+ end component;
+
+ component xwrsw_hwdu
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nregs : integer := 1;
+ g_rwidth : integer := 32);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+ dbg_chps_id_o : out std_logic_vector(7 downto 0);
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+ end component;
+
component xwrsw_hwiu
generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
@@ -280,5 +362,22 @@ package wrsw_components_pkg is
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
+
+ --TEMP
+ component dummy_rmon
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nports : integer := 8;
+ g_cnt_pp : integer := 2);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+ end component;
+
+
end wrsw_components_pkg;
diff --git a/top/bare_top/wrsw_top_pkg.vhd b/top/bare_top/wrsw_top_pkg.vhd
index 6db5b5c34b165766d326a95e8ec258c690023417..43cd0f5b657023a3c22d9d6ae264bc2362deda2f 100644
--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -142,7 +142,8 @@ package wrsw_top_pkg is
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
- g_src_cyc_on_stall : boolean := false);
+ g_src_cyc_on_stall : boolean := false;
+ g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -150,7 +151,7 @@ package wrsw_top_pkg is
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
- rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
+ rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
@@ -187,6 +188,9 @@ package wrsw_top_pkg is
pps_ext_i : in std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
+ tm_utc_o : out std_logic_vector(39 downto 0);
+ tm_cycles_o : out std_logic_vector(27 downto 0);
+ tm_time_valid_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
@@ -217,7 +221,10 @@ package wrsw_top_pkg is
generic (
g_num_ports : integer;
g_simulation : boolean;
- g_without_network : boolean);
+ g_without_network : boolean;
+ g_with_TRU : boolean := false;
+ g_with_TATSU : boolean := false;
+ g_with_HWDU : boolean := false);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
@@ -262,25 +269,27 @@ package wrsw_top_pkg is
end component;
component xswc_core is
generic(
- g_prio_num : integer ;
- g_max_pck_size : integer ;
+ g_prio_num : integer ;--:= c_swc_output_prio_num; [works only for value of 8, output_block-causes problem]
+ g_output_queue_num : integer ;
+ g_max_pck_size : integer ;-- in 16bits words --:= c_swc_max_pck_size
g_max_oob_size : integer ;
- g_num_ports : integer ;
- g_pck_pg_free_fifo_size : integer ;
- g_input_block_cannot_accept_data : string ;
- g_output_block_per_prio_fifo_size : integer ;
-
+ g_num_ports : integer ;--:= c_swc_num_ports
+ g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
+ g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
+ g_output_block_per_queue_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
- g_wb_ob_ignore_ack : boolean ;
-
- g_mpm_mem_size : integer ;
- g_mpm_page_size : integer ;
+ g_wb_ob_ignore_ack : boolean := true ;
+ g_mpm_mem_size : integer ; -- in 16bits words
+ g_mpm_page_size : integer ; -- in 16bits words
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
- g_mpm_fetch_next_pg_in_advance : boolean
- );
+ g_mpm_fetch_next_pg_in_advance : boolean ;
+ g_drop_outqueue_head_on_full : boolean ;
+ g_num_global_pause : integer ;
+ g_num_dbg_vector_width : integer := 8
+ );
port (
clk_i : in std_logic;
clk_mpm_core_i : in std_logic;
@@ -292,8 +301,13 @@ package wrsw_top_pkg is
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
+ global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
+ perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
+ shaper_drop_at_hp_ena_i : in std_logic := '0';
+ dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
- rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
+ rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
+ rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
end component;
@@ -312,10 +326,43 @@ package wrsw_top_pkg is
req_full_o : out std_logic_vector(g_num_ports-1 downto 0);
rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
+ tru_req_o : out t_tru_request;
+ tru_resp_i : in t_tru_response;
+ rtu2tru_o : out t_rtu2tru;
+ tru_enabled_i: in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
-
+ component xwrsw_rtu_new
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_handle_only_single_req_per_port : boolean := FALSE;
+ g_prio_num : integer;
+ g_num_ports : integer;
+ g_cpu_port_num : integer := -1;
+ g_match_req_fifo_size : integer := 32;
+ g_port_mask_bits : integer;
+ g_rmon_events_bits_pp : integer := 8);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ req_i : in t_rtu_request_array(g_num_ports-1 downto 0);
+ req_full_o : out std_logic_vector(g_num_ports-1 downto 0);
+ rsp_o : out t_rtu_response_array(g_num_ports-1 downto 0);
+ rsp_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rq_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
+ rsp_abort_i : in std_logic_vector(g_num_ports-1 downto 0);
+ tru_req_o : out t_tru_request;
+ tru_resp_i : in t_tru_response;
+ rtu2tru_o : out t_rtu2tru;
+ tru_enabled_i: in std_logic;
+ rmon_events_o : out std_logic_vector(g_num_ports*g_rmon_events_bits_pp-1 downto 0);
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out
+ );
+ end component;
+
component pll200MhZ is
port
(-- Clock in ports (62.5MhZ)
@@ -325,4 +372,56 @@ package wrsw_top_pkg is
);
end component;
+ component xwrsw_pstats
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nports : integer := 2;
+ g_cnt_pp : integer := 16;
+ g_cnt_pw : integer := 4);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out );
+ end component;
+
+ component xwrsw_hwdu
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nregs : integer := 1;
+ g_rwidth : integer := 32);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+
+ dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+ dbg_chps_id_o : out std_logic_vector(7 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+ end component;
+
+
+ --TEMP
+ component dummy_rmon
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := PIPELINED;
+ g_address_granularity : t_wishbone_address_granularity := BYTE;
+ g_nports : integer := 8;
+ g_cnt_pp : integer := 2);
+ port(
+ rst_n_i : in std_logic;
+ clk_i : in std_logic;
+ events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
+
+ wb_i : in t_wishbone_slave_in;
+ wb_o : out t_wishbone_slave_out);
+ end component;
+
+
end wrsw_top_pkg;
diff --git a/top/scb_15ports/scb_top_synthesis.ucf b/top/scb_15ports/scb_top_synthesis.ucf
index 96a10a31e2445be5f02db3150d5b3708e3ea1c17..7f5b6c433b1eccec832c438580e4600d00ed7e93 100644
--- a/top/scb_15ports/scb_top_synthesis.ucf
+++ b/top/scb_15ports/scb_top_synthesis.ucf
@@ -13,6 +13,9 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
+NET "sensors_scl_b" LOC=G13;
+NET "sensors_sda_b" LOC=H14;
+
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
@@ -96,7 +99,7 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
-NET "pll_status_i" LOC="AE18";
+NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="E11";
@@ -137,18 +140,20 @@ NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
-#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
-#NET "gtx_rxn_i[0]" LOC="AP6";
-#NET "gtx_txp_o[0]" LOC="AP1";
-#NET "gtx_txn_o[0]" LOC="AP2";
-#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
-#NET "gtx_rxn_i[1]" LOC="AM6";
-#NET "gtx_txp_o[1]" LOC="AN3";
-#NET "gtx_txn_o[1]" LOC="AN4";
-#NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
-#NET "gtx_rxn_i[2]" LOC="AL4";
-#NET "gtx_txp_o[2]" LOC="AM1";
-#NET "gtx_txn_o[2]" LOC="AM2";
+#NET "gtx_rxp_i[17]" LOC="AP5"; # gtx0
+#NET "gtx_rxn_i[17]" LOC="AP6";
+#NET "gtx_txp_o[17]" LOC="AP1";
+#NET "gtx_txn_o[17]" LOC="AP2";
+
+#NET "gtx_rxp_i[16]" LOC="AM5"; # gtx1
+#NET "gtx_rxn_i[16]" LOC="AM6";
+#NET "gtx_txp_o[16]" LOC="AN3";
+#NET "gtx_txn_o[16]" LOC="AN4";
+
+#NET "gtx_rxp_i[15]" LOC="AL3"; # gtx2
+#NET "gtx_rxn_i[15]" LOC="AL4";
+#NET "gtx_txp_o[15]" LOC="AM1";
+#NET "gtx_txn_o[15]" LOC="AM2";
NET "gtx_rxp_i[14]" LOC="AJ3";
NET "gtx_rxn_i[14]" LOC="AJ4";
@@ -258,13 +263,19 @@ NET "led_act_o[12]" LOC="AC29";
NET "led_act_o[13]" LOC="AC32";
NET "led_act_o[14]" LOC="AD31";
-
+#NET "led_act_o[15]" LOC="AE32";
+#NET "led_act_o[16]" LOC="AC28";
+#NET "led_act_o[17]" LOC="AG33";
NET "mbl_scl_b[0]" LOC="AF31";
NET "mbl_sda_b[0]" LOC="AG32";
NET "mbl_scl_b[1]" LOC="AC25";
NET "mbl_sda_b[1]" LOC="AG31";
+NET "clk_dmtd_divsel_o" LOC="AN15";
+NET "mb_fan1_pwm_o" LOC="C12";
+NET "mb_fan2_pwm_o" LOC="D12";
+
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
@@ -340,9 +351,9 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
-NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
-INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
+#INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
@@ -613,7 +624,8 @@ INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wra
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.U_RTU/U_Wrapped_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
+INST "U_Real_Top/gen_network_stuff.U_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.U_RTU/U_Wrapped_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_en_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_rst_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_set_sync0" TNM = Ignore_sync_ffs;
@@ -639,37 +651,21 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
diff --git a/top/scb_15ports/scb_top_synthesis.vhd b/top/scb_15ports/scb_top_synthesis.vhd
index 361fac8bfd3268cd697a8f93055472ede2e07c4f..51e9c623060cce179ab8eb74a4f3bd511972cdfe 100644
--- a/top/scb_15ports/scb_top_synthesis.vhd
+++ b/top/scb_15ports/scb_top_synthesis.vhd
@@ -99,6 +99,8 @@ entity scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
+ -- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
+ clk_dmtd_divsel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
@@ -132,7 +134,13 @@ entity scb_top_synthesis is
led_act_o : out std_logic_vector(14 downto 0);
mbl_scl_b : inout std_logic_vector(1 downto 0);
- mbl_sda_b : inout std_logic_vector(1 downto 0)
+ mbl_sda_b : inout std_logic_vector(1 downto 0);
+
+ sensors_scl_b: inout std_logic;
+ sensors_sda_b: inout std_logic;
+
+ mb_fan1_pwm_o : out std_logic;
+ mb_fan2_pwm_o : out std_logic
);
@@ -161,8 +169,11 @@ architecture Behavioral of scb_top_synthesis is
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
-
- -----------------------------------------------------------------------------
+ attribute maxskew: string;
+ attribute maxskew of clk_dmtd : signal is "0.5ns";
+ attribute buffer_type : string;
+
+ -----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
@@ -197,6 +208,13 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
+
+
+ attribute buffer_type of clk_dmtd : signal is "BUFG";
+ attribute buffer_type of clk_ref : signal is "BUFG";
+ attribute buffer_type of clk_aux : signal is "BUFG";
+ attribute buffer_type of clk_sys : signal is "BUFG";
+
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
@@ -204,16 +222,22 @@ architecture Behavioral of scb_top_synthesis is
signal top_master_in, bridge_master_in : t_wishbone_master_in;
signal top_master_out, bridge_master_out : t_wishbone_master_out;
- signal i2c_mbl_scl_oen : std_logic_vector(1 downto 0);
- signal i2c_mbl_scl_out : std_logic_vector(1 downto 0);
- signal i2c_mbl_sda_oen : std_logic_vector(1 downto 0);
- signal i2c_mbl_sda_out : std_logic_vector(1 downto 0);
+ signal i2c_scl_oen : std_logic_vector(2 downto 0);
+ signal i2c_scl_out : std_logic_vector(2 downto 0);
+ signal i2c_sda_oen : std_logic_vector(2 downto 0);
+ signal i2c_sda_out : std_logic_vector(2 downto 0);
+ signal i2c_sda_in : std_logic_vector(2 downto 0);
+ signal i2c_scl_in : std_logic_vector(2 downto 0);
component scb_top_bare
generic (
g_num_ports : integer;
g_simulation : boolean;
- g_without_network : boolean);
+ g_without_network : boolean;
+ g_with_TRU : boolean;
+ g_with_TATSU : boolean;
+ g_with_HWDU : boolean;
+ g_with_PSTATS : boolean);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
@@ -243,18 +267,22 @@ architecture Behavioral of scb_top_synthesis is
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
+ clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
- i2c_mbl_scl_oen_o : out std_logic_vector(1 downto 0);
- i2c_mbl_scl_o : out std_logic_vector(1 downto 0);
- i2c_mbl_scl_i : in std_logic_vector(1 downto 0) := "11";
- i2c_mbl_sda_oen_o : out std_logic_vector(1 downto 0);
- i2c_mbl_sda_o : out std_logic_vector(1 downto 0);
- i2c_mbl_sda_i : in std_logic_vector(1 downto 0) := "11");
+ i2c_scl_oen_o : out std_logic_vector(2 downto 0);
+ i2c_scl_o : out std_logic_vector(2 downto 0);
+ i2c_scl_i : in std_logic_vector(2 downto 0) := "111";
+ i2c_sda_oen_o : out std_logic_vector(2 downto 0);
+ i2c_sda_o : out std_logic_vector(2 downto 0);
+ i2c_sda_i : in std_logic_vector(2 downto 0) := "111";
+ mb_fan1_pwm_o : out std_logic;
+ mb_fan2_pwm_o : out std_logic
+ );
end component;
component chipscope_icon
@@ -279,10 +307,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
- gen_i2c_tribufs : for i in 0 to 1 generate
- mbl_scl_b(i) <= i2c_mbl_scl_out(i) when i2c_mbl_scl_oen(i) = '0' else 'Z';
- mbl_sda_b(i) <= i2c_mbl_sda_out(i) when i2c_mbl_sda_oen(i) = '0' else 'Z';
- end generate gen_i2c_tribufs;
--chipscope_icon_1 : chipscope_icon
-- port map (
@@ -535,7 +559,11 @@ begin
generic map (
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
- g_without_network => false)
+ g_without_network => false,
+ g_with_TRU => false,
+ g_with_TATSU => false,
+ g_with_HWDU => false,
+ g_with_PSTATS => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
@@ -565,17 +593,40 @@ begin
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
+ clk_dmtd_divsel_o => clk_dmtd_divsel_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
-- led_link_o => led_link_o,
led_act_o => led_act_o(c_NUM_PORTS-1 downto 0),
- i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
- i2c_mbl_scl_o => i2c_mbl_scl_out,
- i2c_mbl_scl_i => mbl_scl_b,
- i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
- i2c_mbl_sda_o => i2c_mbl_sda_out,
- i2c_mbl_sda_i => mbl_sda_b);
+-- i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
+-- i2c_mbl_scl_o => i2c_mbl_scl_out,
+-- i2c_mbl_scl_i => mbl_scl_b,
+-- i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
+-- i2c_mbl_sda_o => i2c_mbl_sda_out,
+-- i2c_mbl_sda_i => mbl_sda_b
+ i2c_scl_oen_o => i2c_scl_oen,
+ i2c_scl_o => i2c_scl_out,
+ i2c_scl_i => i2c_scl_in,
+ i2c_sda_oen_o => i2c_sda_oen,
+ i2c_sda_o => i2c_sda_out,
+ i2c_sda_i => i2c_sda_in,
+ mb_fan1_pwm_o => mb_fan1_pwm_o,
+ mb_fan2_pwm_o => mb_fan2_pwm_o);
+
+ i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
+ i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
+
+ i2c_scl_in(2) <= sensors_scl_b;
+ i2c_sda_in(2) <= sensors_sda_b;
+
+ gen_i2c_tribufs : for i in 0 to 1 generate
+ mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
+ mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
+ end generate gen_i2c_tribufs;
+
+ sensors_scl_b <= i2c_scl_out(2) when i2c_scl_oen(2) = '0' else 'Z';
+ sensors_sda_b <= i2c_sda_out(2) when i2c_sda_oen(2) = '0' else 'Z';
end Behavioral;
diff --git a/top/scb_18ports/scb_top_synthesis.ucf b/top/scb_18ports/scb_top_synthesis.ucf
index 2d37d4257d80694325fc420f00452fe79f0ed1f4..9d02c42212b3aacc46b61a1c6f5fe77be9ce1700 100644
--- a/top/scb_18ports/scb_top_synthesis.ucf
+++ b/top/scb_18ports/scb_top_synthesis.ucf
@@ -284,8 +284,6 @@ NET "mb_fan2_pwm_o" LOC="D12";
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
-
-
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
@@ -303,10 +301,11 @@ TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_aux_n_i" TNM_NET = fpga_clk_aux_n_i;
TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 5 ns HIGH 50%;
+#TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 8 ns HIGH 50%;
NET "fpga_clk_aux_p_i" TNM_NET = fpga_clk_aux_p_i;
TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 5 ns HIGH 50%;
+#TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 8 ns HIGH 50%;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
-
NET "from_phys[0]_rx_clk" TNM="phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM="phy_rx_clocks";
NET "from_phys[2]_rx_clk" TNM="phy_rx_clocks";
@@ -351,287 +350,288 @@ TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
-INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
+#INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/gen_network_stuff.U_RTU/U_Wrapped_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.U_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/gen_network_stuff.U_RTU/U_Wrapped_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_en_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_rst_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_set_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_pps_valid_sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_BB_Detect/sync_ffs_phase_p/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_BB_Detect/U_Detect_Ref_Pulses/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_sync_ffs_sync_done/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_sync_ffs_sync_en/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_BB_Detect/sync_ffs_phase_p/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_BB_Detect/U_Detect_Ref_Pulses/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_sync_ffs_sync_done/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_sync_ffs_sync_en/sync0" TNM = Ignore_sync_ffs;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
@@ -647,7 +647,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
@@ -673,28 +673,28 @@ TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG;
TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_0" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_1" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_2" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_3" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_4" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_5" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_6" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_7" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_8" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_9" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_10" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_11" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_12" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_13" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_14" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_15" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_16" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_17" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_18" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_19" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_20" TNM = DMTD_TAG_INT;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_21" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_0" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_1" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_2" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_3" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_4" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_5" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_6" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_7" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_8" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_9" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_10" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_11" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_12" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_13" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_14" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_15" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_16" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_17" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_18" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_19" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_20" TNM = DMTD_TAG_INT;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1097,28 +1097,28 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_0" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_1" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_2" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_3" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_4" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_5" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_6" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_7" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_8" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_9" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_10" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_11" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_12" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_13" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_14" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_15" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_16" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_17" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_18" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_19" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_20" TNM = DMTD_TAG_O;
-INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_21" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_0" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_1" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_2" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_3" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_4" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_5" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_6" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_7" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_8" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_9" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_10" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_11" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_12" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_13" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_14" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_15" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_16" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_17" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_18" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_19" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_20" TNM = DMTD_TAG_O;
+#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_21" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1449,7 +1449,6 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
-
TIMESPEC TS_ignore8 = FROM "fpga_clk_ref_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore9 = FROM "phy_rx_clocks" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore18 = FROM "fpga_clk_dmtd_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
@@ -1466,7 +1465,6 @@ TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/07/16
-
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
@@ -1486,4 +1484,44 @@ TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
+
#TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY;
+#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2013/11/06
+NET "gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys_bufr[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[2].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys_bufr[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[3].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[6].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[7].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[8].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[9].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[10].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[11].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[11].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[12].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[12].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[13].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[13].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[14].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[14].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[15].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[15].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[16].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[16].U_PHY/rx_rec_clk_bufin;
+NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
+
+TIMESPEC TS_gen_phys_bufr_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_bufr_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_bufr_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_bufr_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+
+TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_11__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[11].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_12__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[12].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_13__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[13].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_14__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[14].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
+TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
diff --git a/top/scb_18ports/scb_top_synthesis.vhd b/top/scb_18ports/scb_top_synthesis.vhd
index f679c68991a420dc698e48788f7e6507c150b94c..d09d9152e23d2e21f197955d9d1d639f1ebfca00 100644
--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -176,7 +176,7 @@ architecture Behavioral of scb_top_synthesis is
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "0.5ns";
-
+ attribute buffer_type : string;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
@@ -212,6 +212,11 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
+ attribute buffer_type of clk_dmtd : signal is "BUFG";
+ attribute buffer_type of clk_ref : signal is "BUFG";
+ attribute buffer_type of clk_aux : signal is "BUFG";
+ attribute buffer_type of clk_sys : signal is "BUFG";
+
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
@@ -236,7 +241,11 @@ architecture Behavioral of scb_top_synthesis is
generic (
g_num_ports : integer;
g_simulation : boolean;
- g_without_network : boolean);
+ g_without_network : boolean;
+ g_with_TRU : boolean;
+ g_with_TATSU : boolean;
+ g_with_HWDU : boolean;
+ g_with_PSTATS : boolean);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
@@ -266,7 +275,7 @@ architecture Behavioral of scb_top_synthesis is
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
--- uart_sel_o : out std_logic;
+ uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
@@ -591,7 +600,11 @@ begin
generic map (
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
- g_without_network => false)
+ g_without_network => false,
+ g_with_TRU => false,
+ g_with_TATSU => false,
+ g_with_HWDU => true,
+ g_with_PSTATS => false)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
diff --git a/top/scb_8ports/scb_top_synthesis.vhd b/top/scb_8ports/scb_top_synthesis.vhd
index 9daec9a163ac7f9f286e54ca76d071797dec293b..bd68c841b8137ef62f78b31fe8dc103f4128a7fe 100644
--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -177,7 +177,6 @@ architecture Behavioral of scb_top_synthesis is
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
-
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
@@ -237,7 +236,10 @@ architecture Behavioral of scb_top_synthesis is
generic (
g_num_ports : integer;
g_simulation : boolean;
- g_without_network : boolean);
+ g_without_network : boolean;
+ g_with_TRU : boolean;
+ g_with_TATSU : boolean;
+ g_with_HWDU : boolean);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
@@ -592,7 +594,10 @@ begin
generic map (
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
- g_without_network => false)
+ g_without_network => false,
+ g_with_TRU => true,
+ g_with_TATSU => true,
+ g_with_HWDU => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,