diff --git a/testbench/scb_top/main.sv b/testbench/scb_top/main.sv
index cf2a548a23f63c6c587599bd5153afe8fca239fb..0ddad241ad917c15c4fd54e198db6838d3baed67 100644
--- a/testbench/scb_top/main.sv
+++ b/testbench/scb_top/main.sv
@@ -2751,8 +2751,8 @@ module main;
     trans_paths[17]='{17 ,0  , 1 }; // port 17
     
     g_enable_pck_gaps    = 0;
-    g_min_pck_gap        = 0;
-    g_max_pck_gap        = 400;
+    g_min_pck_gap        = 100;
+    g_max_pck_gap        = 120;
     repeat_number        = 10000;//2700; //10
     tries_number         = 1;  
 //     g_force_payload_size = 225-18; // header = 14 bytes | CRC = 4 bytes
@@ -2763,12 +2763,12 @@ module main;
     rx_forward_on_fmatch_full = 1; 
     mac_br               = 1;
     g_is_qvlan           = 0;
-    g_ignore_rx_test_check = 0;
+    g_ignore_rx_test_check = 1;
     g_simple_allocator_unicast_check = 1;
-    
+/*    
     g_do_vlan_config    = 2; // snake EP configuration (tagging proper VLANs on ports
     
-    g_set_untagging     = 2; // untagging
+    g_set_untagging     = 2; // untagging*/
   end
 //*/
  /** ***************************   test scenario 81  ************************************* **/ 
diff --git a/testbench/scb_top/wave.do b/testbench/scb_top/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..bbb18719f3ca4635a94f8f591b0d2fe2884ac656
--- /dev/null
+++ b/testbench/scb_top/wave.do
@@ -0,0 +1,10511 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/clk_i
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(17).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(15).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(16).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(14).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(13).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(12).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(11).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(10).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(9).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(8).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(7).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(6).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(5).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(4).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(3).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(2).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(1).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(0).tx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(17).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(16).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(15).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(14).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(13).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(12).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(11).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(10).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(9).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(8).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(7).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(6).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(5).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(4).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(3).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(2).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(1).rx_data
+add wave -noupdate -group Ports-normal /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(0).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(17).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(16).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(15).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(14).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(13).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(12).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(11).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(10).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(9).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(8).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(7).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(6).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(5).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(4).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(3).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(2).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(1).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(0).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(17).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(16).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(15).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(14).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(13).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(12).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(11).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(10).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(9).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(8).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(7).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(6).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(5).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(4).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(3).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(2).rx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_o(1).tx_data
+add wave -noupdate -group Ports-snake /main/DUT/U_Top/U_Wrapped_SCBCore/phys_i(0).rx_data
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_i
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_i
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_o
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rq_i
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_state
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rq_i
+add wave -noupdate /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_rd
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_wr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/clk_sys_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_MAC_entry
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_mac_ID
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_pcr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_address_granularity
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_handle_only_single_req_per_port
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_interface_mode
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_match_req_fifo_size
+add wave -noupdate -group RTU -group RTU->top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_num_ports
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_port_mask_bits
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_prio_num
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/gnt_fifo_access
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_ack
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_drdy
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_entry
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_fid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_found
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_hash
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_mac
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_start
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/irq_nempty
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/match_req_fifo_cnt
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/mfifo_trigger
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_b_unrec
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_fix_prio
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_learn_en
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/dbg_forwarded_to_port
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/req_i
+add wave -noupdate -group RTU -group RTU->top -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_o(0) -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rmon_events_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_pass_all
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_pass_bpdu
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_prio_val
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/port_idle
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/regs_fromwb
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/regs_towb
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/req_full_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_almost_full
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_d_muxed
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_d_requests
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_empty
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_full
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_full_for_ports
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_qvalid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_read
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_wr_access
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_write_sng
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_ack_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_fifo_read_all_zeros
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rst_n_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rtu2tru_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rtu_gcr_poly_used
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rtu_special_traffic_config
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/tru_enabled_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/tru_req_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/tru_resp_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_data4match
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_entry4fast_match
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_entry4match
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_vid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rmon_events_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_wr_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_in
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_out
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/zeros
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_rd
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_wr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/clk_sys_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_MAC_entry
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_mac_ID
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_pcr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_rd
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_wr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/clk_sys_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_MAC_entry
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_mac_ID
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_pcr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_address_granularity
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_handle_only_single_req_per_port
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_interface_mode
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_match_req_fifo_size
+add wave -noupdate -group RTU -group RTU->top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_num_ports
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_port_mask_bits
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/g_prio_num
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/gnt_fifo_access
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_ack
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_drdy
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_entry
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_fid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_found
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_hash
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_mac
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_start
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/htab_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/irq_nempty
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/match_req_fifo_cnt
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/mfifo_trigger
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_b_unrec
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_fix_prio
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_learn_en
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/dbg_forwarded_to_port
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/req_i
+add wave -noupdate -group RTU -group RTU->top -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_o(0) -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rmon_events_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_pass_all
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_pass_bpdu
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/pcr_prio_val
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/port_idle
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/regs_fromwb
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/regs_towb
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/req_full_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_almost_full
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_d_muxed
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_d_requests
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_empty
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_full
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_full_for_ports
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_qvalid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_read
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_wr_access
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rq_fifo_write_sng
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_ack_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rsp_fifo_read_all_zeros
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rst_n_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rtu2tru_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rtu_gcr_poly_used
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rtu_special_traffic_config
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/tru_enabled_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/tru_req_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/tru_resp_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_data4match
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_entry4fast_match
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_entry4match
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_rd_vid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/rmon_events_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/vlan_tab_wr_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_in
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/wb_out
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/zeros
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_data_o
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_rd
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/aram_main_wr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/clk_sys_i
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_MAC_entry
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_mac_ID
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/current_pcr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_req_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_data
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_rsp_valid
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_addr
+add wave -noupdate -group RTU -group RTU->top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/fast_match_vtab_data
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/clk_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/g_num_ports
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/g_port_mask_bits
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/grant
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_req_data_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_req_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_rsp_data_o
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_rsp_valid_o
+add wave -noupdate -group RTU -group RTU->FastMatch -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/pipeline_grant
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/pipeline_match_rsp
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/pipeline_valid
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/req
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/req_masked
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/req_strobe
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rq_prio_mask
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rsp_fast_match
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rst_n_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_req_stage_0
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_req_stage_1
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_req_stage_g
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_str_config_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_br
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_br_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_ff
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_ff_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_hp
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_hp_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_nf
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_nf_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_ptp
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/tru_enabled_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/tru_req_o
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/tru_rsp_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/vtab_rd_addr_o
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/vtab_rd_entry_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/zeros
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/clk_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/g_num_ports
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/g_port_mask_bits
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/grant
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_req_data_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_req_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_rsp_data_o
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/match_rsp_valid_o
+add wave -noupdate -group RTU -group RTU->FastMatch -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/pipeline_grant
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/pipeline_match_rsp
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/pipeline_valid
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/req
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/req_masked
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/req_strobe
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rq_prio_mask
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rsp_fast_match
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rst_n_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_req_stage_0
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_req_stage_1
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_req_stage_g
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/rtu_str_config_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_br
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_br_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_ff
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_ff_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_hp
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_hp_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_nf
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_nf_d
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/traffic_ptp
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/tru_enabled_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/tru_req_o
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/tru_rsp_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/vtab_rd_addr_o
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/vtab_rd_entry_i
+add wave -noupdate -group RTU -group RTU->FastMatch /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Fast_match/zeros
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/clk_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group Port_8 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/drop
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/hp
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/nf
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_state
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group Port_8 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group Port_8 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/match_required
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rsp
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/zeros
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/clk_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group Port_8 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/drop
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/hp
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/nf
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_state
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group Port_8 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group Port_8 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/match_required
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/rsp
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group Port_8 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(8)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_12 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_12 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/drop
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/hp
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/nf
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_12 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_12 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/drop
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/hp
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/nf
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(12)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rq_i.valid
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_o.valid
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rq_abort_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_abort_i
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/drop
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/hp
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/nf
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_0 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/drop
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/hp
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/nf
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(0)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/drop
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/hp
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/nf
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/drop
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/hp
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/nf
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(1)/U_PortX/zeros
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/g_num_ports
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/clk_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rst_n_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rq_fifo_read_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rq_fifo_empty_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rq_fifo_input_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_write_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_full_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_output_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_start_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_ack_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_found_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_hash_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_mac_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_fid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_drdy_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_entry_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_port_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_src_dst_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_wr_req_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_wr_full_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_wr_empty_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_dmac_lo_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_dmac_hi_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_smac_lo_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_smac_hi_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_vid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_prio_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_pid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_has_vid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_has_prio_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_addr_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_data_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_rd_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_data_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_wr_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/vlan_tab_addr_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/vlan_tab_entry_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_learn_en_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_b_unrec_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_b_unrec_fw_cpu_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_cpu_mask_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_crc_poly_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_smac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_dmac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_has_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/mstate
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_htab_rd_data_ack
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_port_id
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_smac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_dmac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_has_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_fifo_read
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_dst_port_mask
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_drop
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_bpdu
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_input_fid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_dst_reg
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_tab_addr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_tab_data
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_tab_rd
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_port_mask
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_fid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_prio_override
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_bucket_cnt
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_port_mask_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_drop_unmatched_src_ports
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_prio_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_has_prio_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_prio_override_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_cam_addr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_is_bpdu
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_port_mask_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_prio_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_has_prio_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_prio_override_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_addr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_data_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_data_o_delayed
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_wr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_to_shift_left
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/shifted_left
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_dmac_lo
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_dmac_hi
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_smac_lo
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_smac_hi
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_pid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_has_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_dst_sel
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_learned_reg
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_port_id_vector
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_port_number_tmp
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_pass_all
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_learn_en
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_pass_bpdu
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_b_unrec
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_bitsel_msb
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_ufifo_wr_req
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/requesting_port
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_urec_broadcast_mask
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/zeros
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/g_num_ports
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/clk_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rst_n_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rq_fifo_read_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rq_fifo_empty_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rq_fifo_input_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_write_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_full_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rsp_fifo_output_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_start_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_ack_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_found_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_hash_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_mac_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_fid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_drdy_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_entry_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_port_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/htab_src_dst_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_wr_req_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_wr_full_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_wr_empty_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_dmac_lo_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_dmac_hi_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_smac_lo_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_smac_hi_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_vid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_prio_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_pid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_has_vid_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_ufifo_has_prio_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_addr_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_data_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_rd_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_data_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_aram_main_wr_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/vlan_tab_addr_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/vlan_tab_entry_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_learn_en_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_pcr_b_unrec_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_b_unrec_fw_cpu_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_cpu_mask_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/rtu_crc_poly_i
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_smac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_dmac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_has_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/a_rq_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/mstate
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_htab_rd_data_ack
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_port_id
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_smac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_dmac
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_has_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_fifo_read
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_dst_port_mask
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_drop
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rsp_bpdu
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_input_fid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_hash_dst_reg
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_tab_addr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_tab_data
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_tab_rd
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_port_mask
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_fid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_vlan_prio_override
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_bucket_cnt
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_port_mask_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_drop_unmatched_src_ports
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_prio_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_has_prio_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_prio_override_src
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_entry_cam_addr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_is_bpdu
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_port_mask_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_prio_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_has_prio_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_dst_entry_prio_override_dst
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_addr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_data_o
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_data_o_delayed
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_main_wr
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_to_shift_left
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/shifted_left
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_dmac_lo
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_dmac_hi
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_smac_lo
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_smac_hi
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_pid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_has_vid
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_ufifo_has_prio
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_src_dst_sel
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rq_learned_reg
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_port_id_vector
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_port_number_tmp
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_pass_all
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_learn_en
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_pass_bpdu
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_pcr_b_unrec
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_aram_bitsel_msb
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_rtu_ufifo_wr_req
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/requesting_port
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/s_urec_broadcast_mask
+add wave -noupdate -group RTU -group Full_match /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/U_Full_Match/zeros
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/drop
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/prio
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/hp
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/nf
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/dbg_force_fast_match_only
+add wave -noupdate -group RTU -group port_14 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(14)/U_PortX/dbg_force_full_match_only
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_3 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_3 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/drop
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/prio
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/hp
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/nf
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/dbg_force_fast_match_only
+add wave -noupdate -group RTU -group port_3 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(3)/U_PortX/dbg_force_full_match_only
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/drop
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/prio
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/hp
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/nf
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/dbg_force_fast_match_only
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/dbg_force_full_match_only
+add wave -noupdate -group RTU -group port_13 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(13)/U_PortX/new_req_at_full_match_rsp_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_10 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_10 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/new_req_at_full_match_rsp_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/drop
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/prio
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/hp
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/nf
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/dbg_force_fast_match_only
+add wave -noupdate -group RTU -group port_10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(10)/U_PortX/dbg_force_full_match_only
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/g_num_ports
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/g_port_mask_bits
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/g_match_req_fifo_size
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/g_port_index
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/clk_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rst_n_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_idle_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_state
+add wave -noupdate -group RTU -group port_5 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i
+add wave -noupdate -group RTU -group port_5 -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_wr_req_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_wr_data_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_wr_done_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_wr_full_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_rd_data_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_rd_valid_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_wr_req_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_wr_data_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_rd_valid_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_rd_data_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_almost_full_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_full_o
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_str_config_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_gcr_g_ena_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_pcr_pass_bpdu_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_pcr_pass_all_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_pcr_fix_prio_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_pcr_prio_val_i
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_pcr_pass_bpdu
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_pcr_pass_all
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rq_fifo_d
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/src_port_mask
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_and_full_mask
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/mirror_port_dst
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/mirror_port_src_rx
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/mirror_port_src_tx
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/match_required
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_nofw_only
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_in
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_wr_req
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_wr_req
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/none_match_wr_req
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_valid
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_rd_valid
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rq_prio
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rq_has_prio
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_req_d
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_wr_req_d
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/fast_match_wr_req_d
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/delayed_full_match_wr_req
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rq_rsp_cnt
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rsp
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_idle
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/forwarding_mask
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/forwarding_mask_CPU_filtered
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/forwarding_and_mirror_mask
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/forwarding_without_mr_dst_mask
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/drop
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/prio
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/hp
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/nf
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_rsp_port
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_rsp_prio
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_req_in_progress
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_aboard
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/full_match_aboard_d
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/aboard_possible
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/zeros
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/dbg_force_fast_match_only
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/dbg_force_full_match_only
+add wave -noupdate -group RTU -group port_5 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/new_req_at_full_match_rsp_d
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p8->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p12->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p12->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p12->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p12->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p12->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p1->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p1->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p1->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p1->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p1->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p1->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p1->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p1->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p1->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p1->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p1->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p16->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p16->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p0->input_block -radix hexadecimal /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p0->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p0->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_o.stall
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p0->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p0->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p0->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p0->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p0->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p17->ouput_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p17->ouput_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p17->ouput_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p17->ouput_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p17->ouput_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p14->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p14->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p14->output_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p14->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p3->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_num_ports
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_addr_width
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_page_num
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_size_width
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_partial_select_width
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_data_width
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/rst_n_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/clk_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_done_o
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_addr_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_data_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_next_addr_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_next_addr_valid_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_rd_req_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_addr_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read_done_o
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data_o
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/mpm_rpath_addr_i
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/mpm_rpath_data_o
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_request_vec
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec_d0
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec_d1
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_index
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_index_d0
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_request_noempty
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_done
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/in_sel_write
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_ena
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_next_ena
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_addr
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_next_addr
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_data
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_data_valid
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_end_of_list
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/tmp_write_end_of_list
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_addr
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_data
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_ena
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_addr_reg
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_data_reg
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_ena_reg
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_request_vec
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_request_noempty
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec_d0
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec_d1
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_index
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_index_d0
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_valid
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_valid_d0
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read_done
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_ena
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_addr
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_data
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data_out
+add wave -noupdate -group SWcore -group LinkedList -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/zeros
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_num_ports
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_addr_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_page_num
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_size_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_partial_select_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_data_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/rst_n_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/clk_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_done_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_data_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_next_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_next_addr_valid_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_rd_req_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read_done_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/mpm_rpath_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/mpm_rpath_data_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_request_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec_d1
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_index
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_index_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_request_noempty
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_done
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/in_sel_write
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_next_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_next_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_data_valid
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_end_of_list
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/tmp_write_end_of_list
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_addr_reg
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_data_reg
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_ena_reg
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_request_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_request_noempty
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec_d1
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_index
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_index_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_valid
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_valid_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read_done
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data_out
+add wave -noupdate -group SWcore -group LinkedList -group p14-req_vect /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/zeros
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_num_ports
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_addr_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_page_num
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_size_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_partial_select_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/g_data_width
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/rst_n_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/clk_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_done_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_data_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_next_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_next_addr_valid_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_rd_req_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read_done_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/mpm_rpath_addr_i
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/mpm_rpath_data_o
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_request_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_vec_d1
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_index
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_grant_index_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_request_noempty
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/write_done
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/in_sel_write
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_next_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_next_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_data_valid
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_write_end_of_list
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/tmp_write_end_of_list
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_addr_reg
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_data_reg
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_wr_ena_reg
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_request_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_request_noempty
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_vec_d1
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_index
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_index_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_valid
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_grant_valid_d0
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_read_done
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_ena
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_addr
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/ll_free_pck_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/free_pck_data_out
+add wave -noupdate -group SWcore -group LinkedList -group p14-read_valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/LINKED_LIST/zeros
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_data_width
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_ratio
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_page_size
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_num_pages
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_num_ports
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_fifo_size
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/clk_io_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/clk_core_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rst_n_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/wport_d_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/wport_dvalid_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/wport_dlast_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/wport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/wport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/wport_dreq_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_d_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/ll_data_i
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rst_n_core
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/rst_n_io
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/fbm_wr_addr
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/fbm_rd_addr
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/fbm_wr_data
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/fbm_rd_data
+add wave -noupdate -group SWcore -group MPM -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/fbm_we
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_data_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_ratio
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_page_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_num_pages
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_num_ports
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_fifo_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/clk_io_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/clk_core_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_d_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_dvalid_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_dlast_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_dreq_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_data_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_we_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/arb_grant_sreg
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/arb_req
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/arb_grant
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wr_mux_a_in
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wr_mux_d_in
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_we_d
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wr_mux_sel
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_data_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_ratio
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_page_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_num_pages
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_num_ports
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_fifo_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/clk_io_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/clk_core_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_d_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_dvalid_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_dlast_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport_dreq_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_data_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_we_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(17) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(2) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(2).fbm_addr_out {-height 17 -radix unsigned} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(1) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(1).fbm_addr_out {-height 17 -radix unsigned} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(0) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(0).fbm_addr_out {-height 17 -radix unsigned} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate(0).grant_d -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wstate
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport(17) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport(2) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport(1) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport(0) -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wport
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/arb_req
+add wave -noupdate -group SWcore -group MPM -group write_path -group top -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/arb_grant
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wr_mux_a_in
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wr_mux_d_in
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/fbm_we_d
+add wave -noupdate -group SWcore -group MPM -group write_path -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/wr_mux_sel
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_width
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_ratio
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/we_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/align_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/d_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/q_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/side_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/side_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/empty_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/wr_sreg
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/wr_cell
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/real_we
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/q_int
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/wr_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/rd_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/full_int
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/side_comb
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_width
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_ratio
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/we_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/align_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/d_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/q_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/side_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/side_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/empty_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/wr_sreg
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/wr_cell
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/real_we
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/q_int
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/wr_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/rd_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/full_int
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/side_comb
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/mem
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/rd_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/ra_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/we_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/wd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/wa_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/clk_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group input_fifo_0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/g_width
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/g_width
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/clk_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/wa_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/wd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/we_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/ra_i
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/rd_o
+add wave -noupdate -group SWcore -group MPM -group write_path -expand -group cell0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(0)/U_Input_FIFOx/gen_mem_cells(0)/U_Mem/mem
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_ratio
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/we_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/align_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/d_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/q_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/side_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/side_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/empty_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/wr_sreg
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/wr_cell
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/real_we
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/q_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/wr_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/rd_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/full_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/side_comb
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_ratio
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/we_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/align_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/d_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/q_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/side_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/side_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/empty_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/wr_sreg
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/wr_cell
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/real_we
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/q_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/wr_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/rd_addr
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/full_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_1 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(1)/U_Input_FIFOx/side_comb
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/wr_addr_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rd_addr_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/going_full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/empty_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rcb
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/wcb
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/full_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/empty_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/going_full
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/g_size
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rd_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/wr_i
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/wr_addr_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rd_addr_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/going_full_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/empty_o
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/rcb
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/wcb
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/full_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/empty_int
+add wave -noupdate -group SWcore -group MPM -group write_path -group input_fifo_17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Write_Path/gen_input_fifos(17)/U_Input_FIFOx/U_CTRL/going_full
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_num_ports
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_fifo_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/fbm_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/mem_grant_sreg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/mem_grant_sreg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/mem_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/mem_grant
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/ll_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/ll_grant
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/io
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/core
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rd_mux_a_in
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rd_mux_sel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/fbm_data_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/fifos_rst_n_core
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/logic_rst_n_core
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Page_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/side_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/side_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/flush_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rd_count
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/real_rd
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/empty_wide
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/empty_narrow
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/line_flushed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/side_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/side_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/flush_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rd_count
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/real_rd
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/q_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/empty_wide
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/empty_narrow
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_0 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(0)/U_Output_Fifo/line_flushed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Page_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/side_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/side_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/flush_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rd_count
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/real_rd
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/empty_wide
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/empty_narrow
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/line_flushed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/side_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/side_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/flush_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rd_count
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/real_rd
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/q_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/empty_wide
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/empty_narrow
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_1 -expand -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(1)/U_Output_Fifo/line_flushed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Page_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Page_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/side_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/side_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/flush_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rd_count
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/real_rd
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/empty_wide
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/empty_narrow
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/line_flushed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/g_sideband_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rst_n_a_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/clk_wr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/clk_rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/we_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rd_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/side_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/side_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/flush_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/full_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/empty_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rd_count
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/real_rd
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_muxed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_comb
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/q_reg
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/wr_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/rd_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/empty_wide
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/empty_narrow
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group FIFO_17 -group Output_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_fifos(17)/U_Output_Fifo/line_flushed
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_0 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(0)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/cur_ll.size {-height 17 -radix unsigned}} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -expand -group block_1 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(1)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_17 -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(17)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_14 -expand -group IO_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(14)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_partial_select_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_ll_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_max_oob_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_min_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/g_max_packet_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/clk_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rst_n_io_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_d_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_dvalid_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_dlast_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_ack
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_pg_words
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_first
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/d_valid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/last_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_dsel_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_dreq_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_abort_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_pg_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_pg_valid_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_pg_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_data_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/pf_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/pf_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/pf_fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/pf_pg_lines_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/df_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/df_flush_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/df_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/df_d_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/page_state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/cur_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/cur_ll
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fvalid_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_pg_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_pg_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_dsel
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_last
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/fetch_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/df_we_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/last_page
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/dsel_words_total
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/words_xmitted
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/df_rd_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/pf_we_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_req_int
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_grant_d0
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/ll_grant_d1
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/counters_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/data_dsel_valid
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/wait_first_fetched
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/wait_next_valid_ll_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/start_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/min_pck_size_reached
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/d_counter_equal
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/supress_pre_fetch
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/last_pg_start_ptr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/allow_rport_pg_req
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/abort_wait_cnt
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/rport_abort_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -expand -group io_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_IO_Block/long_rst_at_abort
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/g_num_pages
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/g_data_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/g_page_addr_width
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/g_page_size
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/g_ratio
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/clk_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/rst_n_core_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_req_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_grant_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_addr_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/df_full_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/df_we_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/pf_fbm_addr_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/pf_pg_lines_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/pf_empty_i
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/pf_rd_o
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_grant_d
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/state
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_addr
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_remaining_lines
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/page_read
+add wave -noupdate -group SWcore -group MPM -expand -group read_path -group block_5 -group core_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Read_Path/gen_io_core_blocks(5)/U_Core_Block/fbm_req_int
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_data_width
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_size
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_with_byte_enable
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_addr_conflict_resolution
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_init_file
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_dual_clock
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/g_fail_if_file_not_found
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/rst_n_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/clka_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/bwea_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/wea_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/aa_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/da_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/qa_o
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/clkb_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/bweb_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/web_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/ab_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/db_i
+add wave -noupdate -group SWcore -group MPM -group Memory /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_F_B_Memory/qb_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/g_sync_edge
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/clk_i
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/rst_n_i
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/data_i
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/synced_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/npulse_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/ppulse_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/sync0
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/sync1
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/sync2
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/g_sync_edge
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/clk_i
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/rst_n_i
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/data_i
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/synced_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/npulse_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/ppulse_o
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/sync0
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/sync1
+add wave -noupdate -group SWcore -group MPM -group reset_coreclk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MULTIPORT_MEMORY/U_Sync_Reset_Coreclk/sync2
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_num_pages
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_page_addr_width
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_num_ports
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_usecount_width
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/clk_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rst_n_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/force_free_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/set_usecnt_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/pgaddr_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_last_usecnt_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/nomem_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/tmp_dbg_dealloc
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/tmp_page
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group alloc_core /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_blocks
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_page_addr_width
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_num_ports
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_page_num
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_usecount_width
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_max_pck_size
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_page_size
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_special_res_num_pages
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_resource_num
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_resource_num_width
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_num_dbg_vector_width
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/rst_n_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/clk_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_done_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/clk_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_done_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_done_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_done_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_free_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_force_free_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_usecnt_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_alloc_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_last_usecnt_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/nomem_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/resource_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/resource_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_resource_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_resource_valid_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_resource_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_resource_valid_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/rescnt_page_num_i
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_succeeded_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/res_full_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/res_almost_full_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_o
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_alloc
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_free
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_force_free
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_set_usecnt
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_addr_alloc
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_free_last_usecnt
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_done
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_nomem
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_done
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_done
+add wave -noupdate -group SWcore -group new-MemoryManagementU -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_done
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p14->input /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p4->input_port /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p17->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p15->input_block -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p15->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p13->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p10->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/port_state
+add wave -noupdate -group SWcore /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i
+add wave -noupdate -group SWcore -label valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.valid
+add wave -noupdate -group SWcore -label smac /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.smac
+add wave -noupdate -group SWcore -label dmac /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.dmac
+add wave -noupdate -group SWcore -label vid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.vid
+add wave -noupdate -group SWcore -label has_vid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.has_vid
+add wave -noupdate -group SWcore -label prio /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.prio
+add wave -noupdate -group SWcore -label has_prio /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rq_i.has_prio
+add wave -noupdate -group SWcore /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o
+add wave -noupdate -group SWcore -label valid /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o.valid
+add wave -noupdate -group SWcore -label port_mask /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o.port_mask
+add wave -noupdate -group SWcore -label prio /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o.prio
+add wave -noupdate -group SWcore -label drop /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o.drop
+add wave -noupdate -group SWcore -label hp /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_o.hp
+add wave -noupdate -group SWcore /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_RTU/ports(5)/U_PortX/rtu_rsp_ack_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/dbg_pckstart_pageaddr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/dbg_pckinter_pageaddr_o
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/cur_res_info_almsot_full
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/cur_res_info_full
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/mem_full_dump
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_transfer_ready
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_transfer_rtu_valid
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_transfer_wait_sof
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/tp_transfer_set_usecnt
+add wave -noupdate -group SWcore -group p5->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_page_addr_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_num_ports
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_prio_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_usecount_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_input_block_cannot_accept_data
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_page_size
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_partial_select_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_ll_data_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_max_oob_size
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_port_index
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_resource_num
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/g_resource_num_width
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_page_alloc_req_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_page_alloc_done_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_pageaddr_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_pageaddr_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_force_free_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_force_free_done_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_force_free_addr_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_set_usecnt_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_set_usecnt_done_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_usecnt_alloc_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_usecnt_set_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_nomem_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_resource_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_rescnt_page_num_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_set_usecnt_succeeded_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_res_full_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_res_almost_full_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_rsp_valid_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_rsp_ack_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_dst_port_mask_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_hp_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_drop_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_prio_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_data_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_dvalid_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_dlast_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_dreq_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_addr_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_data_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_next_addr_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_next_addr_valid_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_wr_req_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_wr_done_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_transfer_pck_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_transfer_ack_i
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_pageaddr_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_mask_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_hp_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_prio_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_page_in_advance
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_pageaddr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_usecnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_page_alloc_req
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_usecnt_req
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_usecnt_write
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_usecnt_prev
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_usecnt_next
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_usecnt_pgaddr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckinter_page_in_advance
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckinter_pageaddr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckinter_page_alloc_req
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_dst_port_usecnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rtu_rsp_ack
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_prio
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_mask
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_res_info
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_hp
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_usecnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_drop
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_pckstart_pageaddr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/current_pckstart_usecnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_transfer_pck
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_pageaddr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_mask
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_resource
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_hp
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pta_prio
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_data
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_dvalid
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_dlast
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_dlast_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mpm_pg_req_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_dat_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_adr_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_sel_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_cyc_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_stb_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_we_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_stall_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_ack_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_rty_int
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_stall_force_h
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_stall_force_l
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_sel_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_cyc_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_adr_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/snk_stall_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_dvalid
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_dat
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_sof
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_eof
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_err
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_eod
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_eof_normal
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_eof_on_pause
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_sof_allowed
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_sof_delayed
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_dvalid_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_dat_d0
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/in_pck_sof_on_stall
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/finish_rcv_pck
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_force_free_req
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_force_free_addr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/page_word_cnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/transfer_delay_cnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/max_transfer_delay
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/new_pck_first_page
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_entry
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_entry_tmp
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_wr_req
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/ll_data_eof
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_pageaddr_clred
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_sync
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_in_pck_err
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_drop_on_stuck
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_accept_rtu
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_in_pck_error
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_rcv_first_page
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_ll_entry_addr
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rp_ll_entry_size
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/tp_sync
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/tp_need_pckstart_usecnt_set
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/tp_drop
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/tp_stuck
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/tp_transfer_valid
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/lw_sync_first_stage
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/lw_sync_second_stage
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/lw_sync_2nd_stage_chk
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/lw_pckstart_pg_clred
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/pckstart_pg_clred
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/alloc_FSM
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/trans_FSM
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/rcv_p_FSM
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/linkl_FSM
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_resource_out
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_rescnt_page_num
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_res_full
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/mmu_res_almost_full
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/unknown_res_page_cnt
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/res_info_valid
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/res_info
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/res_info_almsot_full
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/res_info_full
+add wave -noupdate -group SWcore -group p2->input_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/dbg_dropped_on_res_full
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_hwdu_output_block_width
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/drop_at_retry
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/send_FSM
+add wave -noupdate -group SWcore -group p5->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/OUTPUT_BLOCK/prep_FSM
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_max_pck_size_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_output_block_per_queue_fifo_size
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_queue_num_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_queue_num
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_prio_num_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_mpm_page_addr_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_mpm_data_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_mpm_partial_select_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_mpm_fetch_next_pg_in_advance
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_mmu_resource_num_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_wb_data_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_wb_addr_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_wb_sel_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_hwdu_output_block_width
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_wb_ob_ignore_ack
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/g_drop_outqueue_head_on_full
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/clk_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rst_n_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pta_transfer_data_valid_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pta_pageaddr_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pta_prio_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pta_hp_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pta_transfer_data_ack_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_d_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/dbg_hwdu_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/tap_out_o
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pta_transfer_data_ack
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rd_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/dp_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ram_rd_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/drop_index
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/drop_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/write_index
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/read_index
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/not_full_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/full_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/not_empty_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/not_empty_and_shaped_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/read_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/read
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rd_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/write_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/write
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/zeros
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_addr_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rd_addr_array
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_data
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rd_data
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free_pgaddr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/pck_start_pgaddr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/free_sent_pck_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/free_sent_pck_req
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/free_dped_pck_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/free_dped_pck_req
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ram_zeros
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ram_ones
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/request_retry
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/out_dat_err
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_addr_memorized
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_addr_memorized_valid
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_dreq
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_abort
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm_pg_valid
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm2wb_dat_int
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm2wb_dat_int_pre
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm2wb_sel_int
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm2wb_adr_int
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mpm2wb_adr_int_pre
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/src_out_int
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/tmp_sel
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/tmp_dat
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/tmp_adr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ack_count
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/set_next_rd_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_en
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_en_reg
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_addr_reg
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wr_data_reg
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rdy_for_rd_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/set_next_mem_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/set_next_dp_addr
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/rd_valid
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/allow_next_newpck_set
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/dp_valid
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free_sent
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ppfm_free_dropped
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/mm_valid
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/cycle_frozen
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/cycle_frozen_cnt
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/current_tx_prio
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/hp_prio_mask
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/zero_prio_mask
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/hp_in_queuing
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/non_hp_txing
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/abord_tx_at_hp
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/drop_at_hp
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/wrf_status_err
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/page_set_in_advance
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/ifg_count
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/cyc_d0
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/drop_at_retry
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/send_FSM
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/prep_FSM
+add wave -noupdate -group SWcore -group p3->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/OUTPUT_BLOCK/scr_i_rty
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/g_page_addr_width
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/g_pck_pg_free_fifo_size
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/g_data_width
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/g_resource_num_width
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/clk_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/rst_n_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ib_force_free_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ib_force_free_done_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ib_force_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ob_free_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ob_free_done_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ob_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ll_read_addr_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ll_read_data_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ll_read_req_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ll_read_valid_data_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_resource_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free_done_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free_last_usecnt_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free_resource_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_force_free_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_force_free_done_i
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_force_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_force_free_resource_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_force_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/state
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ib_force_free_done
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ob_free_done
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_wr
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_data_in
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_full
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_empty
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_data_out
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_rd
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_clean
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/current_page
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/next_page
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ll_read_req
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_force_free
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/mmu_free
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/ones
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/freeing_mode
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/fifo_clear_n
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/eof
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/free_resource
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/free_resource_valid
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/force_free_resource
+add wave -noupdate -group pkg_free_module -group port12 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(12)/LPD/force_free_resource_valid
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/g_page_addr_width
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/g_pck_pg_free_fifo_size
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/g_data_width
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/g_resource_num_width
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/clk_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/rst_n_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_done_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ob_free_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ob_free_done_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ob_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ll_read_addr_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ll_read_data_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ll_read_req_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ll_read_valid_data_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_resource_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free_done_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free_last_usecnt_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free_resource_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_force_free_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_force_free_done_i
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_force_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_force_free_resource_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_force_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/state
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ib_force_free_done
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ob_free_done
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_wr
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_data_in
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_full
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_empty
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_data_out
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_rd
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_clean
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/current_page
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/next_page
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ll_read_req
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_force_free
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/mmu_free
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/ones
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/freeing_mode
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/fifo_clear_n
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/eof
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/free_resource
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/free_resource_valid
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/force_free_resource
+add wave -noupdate -group pkg_free_module -group port0 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(0)/LPD/force_free_resource_valid
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/g_page_addr_width
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/g_pck_pg_free_fifo_size
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/g_data_width
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/g_resource_num_width
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/clk_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/rst_n_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ib_force_free_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ib_force_free_done_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ib_force_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ob_free_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ob_free_done_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ob_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ll_read_addr_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ll_read_data_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ll_read_req_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ll_read_valid_data_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_resource_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free_done_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free_last_usecnt_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free_resource_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_force_free_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_force_free_done_i
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_force_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_force_free_resource_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_force_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/state
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ib_force_free_done
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ob_free_done
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_wr
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_data_in
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_full
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_empty
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_data_out
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_rd
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_clean
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/current_page
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/next_page
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ll_read_req
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_force_free
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/mmu_free
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/ones
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/freeing_mode
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/fifo_clear_n
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/eof
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/free_resource
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/free_resource_valid
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/force_free_resource
+add wave -noupdate -group pkg_free_module -group port10 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(10)/LPD/force_free_resource_valid
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/g_page_addr_width
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/g_pck_pg_free_fifo_size
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/g_data_width
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/g_resource_num_width
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/clk_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/rst_n_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ib_force_free_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ib_force_free_done_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ib_force_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ob_free_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ob_free_done_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ob_free_pgaddr_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ll_read_addr_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ll_read_data_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ll_read_req_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ll_read_valid_data_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_resource_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free_done_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free_last_usecnt_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free_resource_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_force_free_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_force_free_done_i
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_force_free_pgaddr_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_force_free_resource_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_force_free_resource_valid_o
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/state
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ib_force_free_done
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ob_free_done
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_wr
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_data_in
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_full
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_empty
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_data_out
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_rd
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_clean
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/current_page
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/next_page
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ll_read_req
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_force_free
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/mmu_free
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/ones
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/freeing_mode
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/fifo_clear_n
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/eof
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/free_resource
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/free_resource_valid
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/force_free_resource
+add wave -noupdate -group pkg_free_module -expand -group port17 /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/PCK_PAGES_FREEEING_MODULE/lpd_gen(17)/LPD/force_free_resource_valid
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dvalid_i
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dlast_i
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_dreq_o
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_abort_o
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_addr_o
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_valid_o
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_done_i
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/mpm_pg_req_i
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_o
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ppfm_free_pgaddr_o
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ots_output_mask_i
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/ots_output_drop_at_rx_hp_i
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i
+add wave -noupdate -group swcore->p0->output_block -label ack /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i.ack
+add wave -noupdate -group swcore->p0->output_block -label stall /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i.stall
+add wave -noupdate -group swcore->p0->output_block -label err /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i.err
+add wave -noupdate -group swcore->p0->output_block -label rty /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_i.rty
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/s_send_pck
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/s_prep_to_send
+add wave -noupdate -group swcore->p0->output_block /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o
+add wave -noupdate -group swcore->p0->output_block -label adr /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o.adr
+add wave -noupdate -group swcore->p0->output_block -label dat /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o.dat
+add wave -noupdate -group swcore->p0->output_block -label cyc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o.cyc
+add wave -noupdate -group swcore->p0->output_block -label stb /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o.stb
+add wave -noupdate -group swcore->p0->output_block -label we /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o.we
+add wave -noupdate -group swcore->p0->output_block -label sel /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/OUTPUT_BLOCK/src_o.sel
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_vlans
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_dpi_classifier
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rtu
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rx_buffer
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_early_match
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_rx_buffer_size
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_sys_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_rx_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_sys_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fab_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_busy_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_quanta_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_prio_mask_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_buffer_occupation_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rmon_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_full_i
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_abort_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dbg_o
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/state
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gap_cntr
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/counter
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rxdata_saved
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/next_hdr
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/is_pause
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/data_firstword
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/flush_stall
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/stb_int
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_int
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_int
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ack_count
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_out_int
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_sel
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_dat
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_done
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_hp
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_pause
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tclass
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_vid
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tag_done
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_is_tagged
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_hp
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_pause
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d0
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d1
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_class
+add wave -noupdate -group EP_0 -expand -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/g_with_rtu
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/clk_sys_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rst_n_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_abort_o
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/in_header
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_abort
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_fab_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_dreq_o
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_fab_o
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_dreq_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/mbuf_is_pause_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_class_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_vid_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_tag_done_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_is_tagged_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rmon_drp_at_rtu_full_o
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_o
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_full_i
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_o
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/hdr_offset
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/in_packet
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_basic
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_tagged
+add wave -noupdate -group EP_0 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_out
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_vlans
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_timestamper
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_packet_injection
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_force_gap_length
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/clk_sys_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/rst_n_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_fab_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_error_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_busy_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_dreq_i
+add wave -noupdate -group EP_0 -group tx_path -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/snk_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/snk_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_req_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_delay_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_ready_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_flow_enable_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_port_id_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_fid_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ts_value_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_stb_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ack_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txts_timestamp_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txts_timestamp_valid_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_req_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_ready_o
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_packet_sel_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_user_value_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/ep_ctrl_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/regs_i
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/dbg_o
+add wave -noupdate -group EP_0 -group tx_path -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(4) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(3) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(2) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(1) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(0) -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/dreq_pipe
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/vlan_mem_addr
+add wave -noupdate -group EP_0 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/vlan_mem_data
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/rst_n_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/clk_sys_i
+add wave -noupdate -group EP_0 -group tx_pcs -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_fab_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_error_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_busy_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_dreq_o
+add wave -noupdate -group EP_0 -group tx_pcs -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_fab
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/mdio_mcr_pdown_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/mdio_wr_spec_tx_cal_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_en_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_val_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/timestamp_trigger_p_a_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/rmon_tx_underrun
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_clk_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_data_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_k_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_disparity_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_enc_err_i
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/dbg_wr_count_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/dbg_rd_count_o
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_is_k
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_odata_reg
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_catch_disparity
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_state
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_cntr
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_cr_alternate
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_packed_in
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_packed_out
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_empty
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_almost_empty
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_almost_full
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_enough_data
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_wr
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_rd
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_ready
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d0
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d1
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d2
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d3
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d4
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_read_int
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_busy
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_error
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/reset_synced_txclk
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/mdio_mcr_pdown_synced
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/s_one
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_en_synced
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/wr_count
+add wave -noupdate -group EP_0 -group tx_pcs /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/rd_count
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_vlans
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_dpi_classifier
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rtu
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rx_buffer
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_early_match
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_rx_buffer_size
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_sys_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_rx_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_sys_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fab_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_busy_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_quanta_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_prio_mask_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_buffer_occupation_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rmon_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_full_i
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_abort_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dbg_o
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/state
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gap_cntr
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/counter
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rxdata_saved
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/next_hdr
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/is_pause
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/data_firstword
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/flush_stall
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/stb_int
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_int
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_int
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ack_count
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_out_int
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_sel
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_dat
+add wave -noupdate -group EP_0 -group rx_path -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(0) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(7) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(8) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(9) -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(0).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(1).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(2).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(3).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(4).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(5).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(6).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(7).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(8).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(9).sof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(0).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(1).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(2).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(3).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(4).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(5).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(6).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(7).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(8).eof
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(9).eof
+add wave -noupdate -group EP_0 -group rx_path -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_done
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_hp
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_pause
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tclass
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_vid
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tag_done
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_is_tagged
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_hp
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_pause
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d0
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d1
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_class
+add wave -noupdate -group EP_0 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/g_with_packet_injection
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/g_with_timestamper
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/g_force_gap_length
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/clk_sys_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/rst_n_i
+add wave -noupdate -group EP_0 -group tx_header_processor -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/src_fab_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/src_dreq_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/pcs_busy_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/pcs_error_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/counter
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/state
+add wave -noupdate -group EP_0 -group tx_header_processor -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/wb_snk_i
+add wave -noupdate -group EP_0 -group tx_header_processor -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/wb_snk_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_pause_req_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_pause_delay_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_pause_ready_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_flow_enable_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_port_id_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_fid_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_ts_value_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_stb_o
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_ack_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txts_timestamp_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txts_timestamp_valid_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/ep_ctrl_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/regs_i
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_pause_mode
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_pause_delay
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/snk_valid
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/sof_p1
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/eof_p1
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/abort_p1
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/error_p1
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/snk_cyc_d0
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/stored_status
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/oob_state
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/oob
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/wb_out
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/decoded_status
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/abort_now
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/stall_int
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_en
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/ep_ctrl
+add wave -noupdate -group EP_0 -group tx_header_processor /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/bitsel_d
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/clk_sys_i
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/rst_n_i
+add wave -noupdate -group EP_0 -group tx_crc -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/snk_fab_i
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/snk_dreq_o
+add wave -noupdate -group EP_0 -group tx_crc -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/src_fab_o
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/src_dreq_i
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/state
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_gen_reset
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_gen_enable
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_value
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/odd_length
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/embed_valid
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/embed_eof
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/stored_msb
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/in_payload
+add wave -noupdate -group EP_0 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/src_dreq_d0
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/clk_sys_i
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/rst_n_i
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/snk_fab_i
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/snk_dreq_o
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/src_fab_o
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/src_dreq_i
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/inject_mem_addr_i
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/inject_mem_data_o
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/state
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/counter
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_rd_vid
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_wr_vid
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_untag
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_stored_tag
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_stored_ethertype
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/mem_addr_muxed
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/mem_rdata
+add wave -noupdate -group EP_0 -group tx_vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/src_dreq_d0
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/g_size
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/g_with_fc
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/clk_sys_i
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/rst_n_i
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/snk_fab_i
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/snk_dreq_o
+add wave -noupdate -group EP_0 -group rx_buffer -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/src_fab_o
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/src_dreq_i
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/level_o
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/regs_i
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/rmon_o
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_in
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_out
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_usedw
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_reset
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_rd
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_in_valid
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_empty
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_afull
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_drop
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_out_valid
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/q_aempty
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/state
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/fab_to_encode
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/src_fab_int
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/in_prev_addr
+add wave -noupdate -group EP_0 -group rx_buffer /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/out_cur_addr
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_data_width
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_size
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_show_ahead
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_with_empty
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_with_full
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_with_almost_empty
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_with_almost_full
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_with_count
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_almost_empty_threshold
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_almost_full_threshold
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/g_register_flag_outputs
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/rst_n_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/clk_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/d_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/q_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/rd_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/we_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/empty_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/full_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/almost_empty_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/almost_full_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/count_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/g_data_width
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/g_size
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/g_dual_clock
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/g_almost_empty_threshold
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/g_almost_full_threshold
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/g_with_count
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/rst_n_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/clk_wr_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/clk_rd_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/d_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/we_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/q_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/rd_i
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/rd_empty_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/wr_full_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/rd_almost_empty_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/wr_almost_full_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/rd_count_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/wr_count_o
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/di_wide_18
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/do_wide_18
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/di_18
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/do_18
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/dip_18
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/dop_18
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/di_36
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/do_36
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/dip_36
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/dop_36
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/di_wide_36
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/do_wide_36
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/srst
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/srstreg
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/rd_ptr
+add wave -noupdate -group EP_0 -group rx_buffer->buf_fifo->native /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer/U_Rx_Buffer/BUF_FIFO/gen_native/U_Native_FIFO/wr_ptr
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP_3 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_vlans
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_dpi_classifier
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rtu
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rx_buffer
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_early_match
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_rx_buffer_size
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_sys_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_rx_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_sys_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fab_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_busy_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_quanta_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_prio_mask_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_buffer_occupation_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rmon_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_full_i
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dbg_o
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/state
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gap_cntr
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/counter
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rxdata_saved
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/next_hdr
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/is_pause
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/data_firstword
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/flush_stall
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/stb_int
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_int
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_int
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ack_count
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_out_int
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_sel
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_dat
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_done
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_hp
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_pause
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tclass
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_vid
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tag_done
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_is_tagged
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_hp
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_pause
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d0
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d1
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_class
+add wave -noupdate -group EP_3 -group rx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/g_with_rtu
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/clk_sys_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rst_n_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_fab_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_dreq_o
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_fab_o
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_dreq_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/mbuf_is_pause_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_class_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_vid_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_tag_done_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_is_tagged_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rmon_drp_at_rtu_full_o
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_o
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_full_i
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_o
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/hdr_offset
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/in_packet
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_basic
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_tagged
+add wave -noupdate -group EP_3 -group rx-headerExt /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(3)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_out
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_num_pages
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_page_addr_width
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_num_ports
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_usecount_width
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_with_RESOURCE_MGR
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_page_size
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_max_pck_size
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_special_res_num_pages
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_resource_num
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_resource_num_width
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/g_num_dbg_vector_width
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/clk_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rst_n_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/force_free_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/set_usecnt_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_alloc_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_set_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/pgaddr_free_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/pgaddr_usecnt_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/req_vec_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rsp_vec_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_i
+add wave -noupdate -group alloc -label alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_req_d0.alloc
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/nomem_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/real_nomem
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/pgaddr_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_alloc_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_pages
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_last_usecnt_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_usecnt_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_free_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_force_free_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/resource_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/resource_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_resource_valid_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rescnt_page_num_i
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/set_usecnt_succeeded_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_full_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_almost_full_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_double_free_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_double_force_free_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_q_write_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_q_read_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/dbg_initializing_o
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/out_nomem
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rd_ptr_p0
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/wr_ptr_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_pages
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_write_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_read_p0
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_read_d1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/initializing
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_addr_rd_p0
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_rddata_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rescnt_rddata_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/ena_wr_p1_ram1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/ena_wr_p1_ram2
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rddata_p1_ram1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rddata_p1_ram2
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/addr_wr_p1_ram1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/addr_wr_p1_ram2
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_wrdata_p1_ram1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_wrdata_p1_ram2
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rescnt_wrdata_p1_ram1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/rescnt_wrdata_p1_ram2
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/wrdata_p1_ram1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/wrdata_p1_ram2
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_output_addr_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/q_input_addr_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/done_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/ram_ones
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_last_usecnt
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/usecnt_not_zero
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_mgr_alloc
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_mgr_free
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_mgr_res_num
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_mgr_rescnt_set
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/set_usecnt_allowed_p1
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/res_almost_full
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_req_in
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_req_d0
+add wave -noupdate -group alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/alloc_req_d1
+add wave -noupdate -radix unsigned /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_pages
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_page_addr_width
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_num_ports
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_page_num
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_usecount_width
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_max_pck_size
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_page_size
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_special_res_num_pages
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_resource_num
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_resource_num_width
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_num_dbg_vector_width
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/g_with_RESOURCE_MGR
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/rst_n_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/clk_i
+add wave -noupdate -group multiport_alloc -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_i
+add wave -noupdate -group multiport_alloc -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_i
+add wave -noupdate -group multiport_alloc -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_done_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/done_alloc
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/done_usecnt
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/done_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/done_force_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_nomem
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_req_vec
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_rsp_vec
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_alloc
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_force_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_set_usecnt
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_done_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_done_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_done_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_free_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_force_free_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_usecnt_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/usecnt_set_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/usecnt_alloc_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pgaddr_alloc_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_last_usecnt_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/nomem_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/resource_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/resource_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_resource_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_resource_valid_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_resource_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_resource_valid_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/rescnt_page_num_i
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_succeeded_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/res_full_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/res_almost_full_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_o
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ports
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/arb_req
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/arb_grant
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/arb_req_d0
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_usecnt_set
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_usecnt_alloc
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_addr_ucnt_set
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_addr_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_addr_alloc
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_free_last_usecnt
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_done
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/grant_ob_d0
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/grant_ib_d0
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/alloc_done
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/free_done
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/force_free_done
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_done
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_double_force_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_double_free
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_q_read
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_q_write
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/dbg_initializing
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_resource_in
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_alloc_usecnt_resource
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_free_resource
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_force_free_resource
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_resource_out
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_free_resource_valid
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_rescnt_page_num
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_res_full
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_res_almost_full
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/resources_feedback
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/resources_out
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/pg_set_usecnt_succeeded
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/set_usecnt_succeeded
+add wave -noupdate -group multiport_alloc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/MEMORY_MANAGEMENT_UNIT/ALLOC_CORE/free_pages
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/g_with_rtu
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/clk_sys_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rst_n_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_fab_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_dreq_o
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_fab_o
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_dreq_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/mbuf_is_pause_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_class_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_vid_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_tag_done_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_is_tagged_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rmon_drp_at_rtu_full_o
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_o
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_full_i
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_o
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/hdr_offset
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/in_packet
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_basic
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_tagged
+add wave -noupdate -group EP_10 -expand -group rtu_header_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_out
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP_10 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(10)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP5 -group top -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP5 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_vlans
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_dpi_classifier
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rtu
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_rx_buffer
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_with_early_match
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/g_rx_buffer_size
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_sys_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/clk_rx_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_sys_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fab_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_busy_i
+add wave -noupdate -group EP5 -group tx_path -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_wb_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_quanta_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_prio_mask_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_buffer_occupation_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rmon_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/regs_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_full_i
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dbg_o
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/state
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gap_cntr
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/counter
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rxdata_saved
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/next_hdr
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/is_pause
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/data_firstword
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/flush_stall
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/stb_int
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_int
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_int
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ack_count
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/src_out_int
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_sel
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/tmp_dat
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_done
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_hp
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_pause
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/fc_pause_p
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tclass
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_vid
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_tag_done
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/vlan_is_tagged
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/pcs_fifo_almostfull
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_hp
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_pause
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d0
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d1
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_class
+add wave -noupdate -group EP5 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/rtu_rq_valid
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/g_with_rtu
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/clk_sys_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rst_n_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_fab_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_dreq_o
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_fab_o
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_dreq_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/mbuf_is_pause_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_class_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_vid_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_tag_done_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_is_tagged_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rmon_drp_at_rtu_full_o
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_o
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_full_i
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_o
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/hdr_offset
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/in_packet
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_basic
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_tagged
+add wave -noupdate -group EP5 -group rtu_ext_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(5)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_out
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP15 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/clk_sys_i
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/rst_n_i
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/snk_fab_i
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/snk_dreq_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/src_fab_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/src_dreq_i
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/tclass_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/vid_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/tag_done_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/is_tagged_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/rmon_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/regs_i
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/regs_o
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/dreq_mask
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/hdr_offset
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/comb_tag_type
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/tag_type
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/state
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/at_ethertype
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/at_vid
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/at_tpid
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/is_tagged
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/stored_ethertype
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/stored_fab
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/prio_int
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/force_dvalid
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/r_tcar_pcp_map
+add wave -noupdate -group EP15 -expand -group rx_path -group vlan_unit /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/gen_with_vlan_unit/U_vlan_unit/is_tag_inserted
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/g_with_rtu
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/clk_sys_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rst_n_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_fab_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/snk_dreq_o
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_fab_o
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/src_dreq_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/mbuf_is_pause_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_class_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_vid_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_tag_done_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/vlan_is_tagged_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rmon_drp_at_rtu_full_o
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_o
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_full_i
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_o
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/hdr_offset
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/in_packet
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_basic
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_tagged
+add wave -noupdate -group EP15 -expand -group rx_path -group rtu_head_ext /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(15)/U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_RTU_Header_Extract/rtu_rq_valid_out
+add wave -noupdate -group swcore-input-fms -group p0->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p0->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p0->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p0->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(0)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p1->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p1->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p1->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p1->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(1)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p2->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p2->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p2->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p2->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(2)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p3->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p3->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p3->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p3->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(3)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p4->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p4->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p4->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p4->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(4)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -expand -group p5->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -expand -group p5->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -expand -group p5->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -expand -group p5->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(5)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p6->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(6)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p6->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(6)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p6->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(6)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p6->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(6)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p7->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(7)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p7->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(7)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p7->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(7)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p7->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(7)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p8->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p8->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p8->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p8->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(8)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p9->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(9)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p9->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(9)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p9->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(9)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p9->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(9)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p10->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p10->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p10->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p10->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(10)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p11->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(11)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p11->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(11)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p11->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(11)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p11->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(11)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p12->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p12->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p12->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p12->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(12)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p13->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p13->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p13->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p13->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(13)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p14->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p14->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p14->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p14->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(14)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p15->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p15->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p15->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p15->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(15)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p16->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p16->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p16->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p16->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(16)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p17->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p17->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p17->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p17->inblk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(17)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group swcore-input-fms -group p18->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(18)/INPUT_BLOCK/s_page_alloc
+add wave -noupdate -group swcore-input-fms -group p18->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(18)/INPUT_BLOCK/s_transfer_pck
+add wave -noupdate -group swcore-input-fms -group p18->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(18)/INPUT_BLOCK/s_rcv_pck
+add wave -noupdate -group swcore-input-fms -group p18->inBlk /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/U_Swcore/gen_blocks(18)/INPUT_BLOCK/s_ll_write
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_abort_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP_2 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_vlans
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_timestamper
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_packet_injection
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_force_gap_length
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/clk_sys_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/rst_n_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_fab_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_error_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_busy_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_dreq_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/snk_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/snk_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_req_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_delay_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_ready_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_flow_enable_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_port_id_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_fid_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ts_value_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_stb_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ack_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txts_timestamp_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txts_timestamp_valid_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_req_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_ready_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_packet_sel_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_user_value_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/ep_ctrl_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/regs_i
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/dbg_o
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/dreq_pipe
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/vlan_mem_addr
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/vlan_mem_data
+add wave -noupdate -group EP_2 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_stb
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/g_master_use_struct
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/g_master_mode
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/g_master_granularity
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/g_slave_use_struct
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/g_slave_mode
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/g_slave_granularity
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/clk_sys_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/rst_n_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_adr_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_dat_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_sel_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_cyc_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_stb_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_we_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_dat_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_err_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_rty_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_ack_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_stall_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/sl_int_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/slave_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/slave_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_adr_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_dat_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_sel_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_cyc_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_stb_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_we_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_dat_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_err_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_rty_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_ack_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_stall_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/ma_int_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/master_i
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/master_o
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/fsm_state
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/master_in
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/master_out
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/slave_in
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/slave_out
+add wave -noupdate -group EP_2 -group wb_slave /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Slave_adapter/stored_we
+add wave -noupdate -group EP_2 -expand -group tx_inject /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_mode
+add wave -noupdate -group EP_2 -group tx_inj_ctrl /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(2)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_mode
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_interface_mode}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_address_granularity}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_tx_force_gap_length}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_simulation}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_pcs_16bit}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_rx_buffer_size}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_rx_buffer}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_flow_control}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_timestamper}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_dpi_classifier}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_vlans}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_rtu}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_leds}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_dmtd}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_with_packet_injection}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_use_new_rxcrc}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/g_use_new_txcrc}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/clk_ref_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/clk_sys_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/clk_dmtd_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rst_n_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pps_csync_p1_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pps_valid_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_rst_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_loopen_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_enable_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_syncen_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_ref_clk_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_tx_data_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_tx_k_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_tx_disparity_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_tx_enc_err_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_rx_data_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_rx_clk_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_rx_k_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_rx_enc_err_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phy_rx_bitslide_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_tx_clk_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_txd_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_tx_en_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_tx_er_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_rx_clk_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_rxd_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_rx_er_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/gmii_rx_dv_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_dat_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_adr_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_sel_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_cyc_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_stb_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_we_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_stall_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_ack_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_err_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_dat_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_adr_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_sel_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_cyc_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_stb_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_we_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_stall_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_ack_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_err_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/snk_rty_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txtsu_port_id_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txtsu_frame_id_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txtsu_ts_value_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txtsu_ts_incorrect_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txtsu_stb_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txtsu_ack_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_full_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_almost_full_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_strobe_p1_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_abort_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_smac_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_dmac_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_vid_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_has_vid_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_prio_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq_has_prio_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_cyc_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_stb_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_we_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_sel_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_adr_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_dat_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_dat_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_ack_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_stall_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pfilter_pclass_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pfilter_drop_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pfilter_done_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_tx_pause_req_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_tx_pause_delay_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_tx_pause_ready_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_rx_pause_start_p_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_rx_pause_quanta_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_rx_pause_prio_mask_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/fc_rx_buffer_occupation_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/inject_req_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/inject_ready_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/inject_packet_sel_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/inject_user_value_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rmon_events_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/led_link_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/led_act_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/link_kill_i}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/link_up_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/dbg_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/dbg_tx_pcs_wr_count_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/dbg_tx_pcs_rd_count_o}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txpcs_fab}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txpcs_dreq}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txpcs_error}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txpcs_busy}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txoob_fid_value}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txoob_fid_stb}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txpcs_timestamp_trigger_p_a}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txts_timestamp_stb}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txts_timestamp_valid}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txts_timestamp_value}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_timestamp_stb}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_timestamp_trigger_p_a}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_timestamp_valid}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_timestamp_value}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_fab}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_busy}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxpcs_fifo_almostfull}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/regs_fromwb}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/regs_towb}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/regs_towb_ep}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/regs_towb_tsu}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/regs_towb_rpath}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/regs_towb_tpath}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txfra_flow_enable}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxfra_pause_p}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxfra_pause_delay}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txfra_pause_req}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txfra_pause_ready}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txfra_pause_delay}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/link_ok}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/txfra_enable}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rxfra_enable}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/mdio_addr}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/sink_in}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/sink_out}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_in}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/src_out}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rst_n_rx}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rst_n_sys}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rst_n_ref}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_in}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/wb_out}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/extended_ADDR}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phase_meas}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/phase_meas_p}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/validity_cntr}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/r_dmcr_en}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/r_dmcr_n_avg}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rtu_rq}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/dvalid_tx}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/dvalid_rx}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/ep_ctrl}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pfilter_pclass}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pfilter_drop}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pfilter_done}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/tx_pclass}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/pcs_rmon}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rx_path_rmon}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/rmon}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/CONTROL0}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/TRIG0}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/TRIG1}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/TRIG2}
+add wave -noupdate -group sim_ep_0 {/main/DUT/genblk1[0]/genblk1/DUT/TRIG3}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/g_addr_width}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/g_data_width}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/clk_i}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/rst_n_i}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/adr}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/dat_i}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/sel}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/dat_o}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/ack}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/stall}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/err}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/rty}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/cyc}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/stb}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/we}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/last_access_t}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/cyc_prev}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/trans_index}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/first_transaction}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/settings}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/permanent_stall}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/cyc_start}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/cyc_end}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/clk_i}
+add wave -noupdate -group ep_snk_0 {/main/DUT/genblk1[0]/genblk1/U_ep_snk/rst_n_i}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/g_addr_width}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/g_data_width}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/clk_i}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/rst_n_i}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/adr}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/dat_o}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/sel}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/dat_i}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/ack}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/stall}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/err}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/rty}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/cyc}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/stb}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/we}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/clk}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/rst_n}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/last_access_t}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/settings}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/xf_idle}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/ack_cnt_int}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/clk_i}
+add wave -noupdate -group ep_src_0 {/main/DUT/genblk1[0]/genblk1/U_ep_src/rst_n_i}
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_interface_mode
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_address_granularity
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_tx_force_gap_length
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_simulation
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_pcs_16bit
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_rx_buffer_size
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rx_buffer
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_flow_control
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_timestamper
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dpi_classifier
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_vlans
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_rtu
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_leds
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_dmtd
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_with_packet_injection
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_use_new_rxcrc
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/g_use_new_txcrc
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/clk_ref_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/clk_sys_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/clk_dmtd_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pps_csync_p1_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pps_valid_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rst_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_loopen_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_enable_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_syncen_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_ref_clk_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_data_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_k_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_disparity_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_tx_enc_err_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_data_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_clk_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_k_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_enc_err_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phy_rx_bitslide_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_clk_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_txd_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_en_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_tx_er_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_clk_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rxd_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_er_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/gmii_rx_dv_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_dat_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_adr_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_sel_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_cyc_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_stb_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_we_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_stall_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_ack_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_err_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_dat_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_adr_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_sel_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_cyc_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stb_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_we_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_stall_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_ack_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_err_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/snk_rty_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_port_id_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_frame_id_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_value_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_stb_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txtsu_ack_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_full_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_almost_full_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_strobe_p1_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_abort_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_smac_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_dmac_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_vid_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_vid_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_prio_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq_has_prio_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_cyc_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stb_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_we_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_sel_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_adr_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_dat_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_ack_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_stall_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_req_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_delay_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_tx_pause_ready_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_start_p_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_quanta_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_pause_prio_mask_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/fc_rx_buffer_occupation_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/inject_req_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/inject_ready_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/inject_packet_sel_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/inject_user_value_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rmon_events_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/led_link_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/led_act_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/link_kill_i
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/link_up_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_wr_count_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/dbg_tx_pcs_rd_count_o
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_fab
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_dreq
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_error
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_busy
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_value
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txoob_fid_stb
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_stb
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_valid
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txts_timestamp_value
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_stb
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_trigger_p_a
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_valid
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_timestamp_value
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fab
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_busy
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxpcs_fifo_almostfull
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/regs_fromwb
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_ep
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tsu
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_rpath
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/regs_towb_tpath
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_flow_enable
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_p
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_pause_delay
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_req
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_ready
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_pause_delay
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/link_ok
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/txfra_enable
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rxfra_enable
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/mdio_addr
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/sink_in
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/sink_out
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_in
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/src_out
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_rx
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_sys
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rst_n_ref
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_in
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/wb_out
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/extended_ADDR
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/phase_meas_p
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/validity_cntr
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_en
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/r_dmcr_n_avg
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rtu_rq
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_tx
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/dvalid_rx
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/ep_ctrl
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_pclass
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_drop
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pfilter_done
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/tx_pclass
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/pcs_rmon
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rx_path_rmon
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/rmon
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/CONTROL0
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG0
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG1
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG2
+add wave -noupdate -group EP_1 -group top /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/TRIG3
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_vlans
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_timestamper
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_packet_injection
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_with_inj_ctrl
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_force_gap_length
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/g_use_new_crc
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/clk_sys_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/rst_n_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_fab_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_error_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_busy_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/pcs_dreq_i
+add wave -noupdate -group EP_1 -group tx_path -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/snk_i
+add wave -noupdate -group EP_1 -group tx_path -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/snk_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_req_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_delay_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_pause_ready_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fc_flow_enable_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_port_id_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_fid_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ts_value_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_stb_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_ack_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txts_timestamp_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txts_timestamp_valid_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_req_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_ready_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_packet_sel_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_user_value_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/ep_ctrl_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/regs_i
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/regs_o
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/dbg_o
+add wave -noupdate -group EP_1 -group tx_path -expand -subitemconfig {/main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(4) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(3) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(2) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(1) -expand /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe(0) -expand} /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/fab_pipe
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/dreq_pipe
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/vlan_mem_addr
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/vlan_mem_data
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/txtsu_stb
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_req
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_ready
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_packet_sel
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_user_value
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inject_mode
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_req
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_ready
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_packet_sel
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_user_value
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_ena
+add wave -noupdate -group EP_1 -group tx_path /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/inj_ctr_mode
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/g_with_packet_injection
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/g_with_timestamper
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/g_force_gap_length
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/clk_sys_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/rst_n_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/src_fab_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/src_dreq_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/pcs_busy_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/pcs_error_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/wb_snk_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/wb_snk_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_pause_req_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_pause_delay_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_pause_ready_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/fc_flow_enable_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_port_id_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_fid_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_ts_value_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_ts_incorrect_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_stb_o
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txtsu_ack_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txts_timestamp_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/txts_timestamp_valid_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/ep_ctrl_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/regs_i
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/state
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/counter
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_pause_mode
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_pause_delay
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/snk_valid
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/sof_p1
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/eof_p1
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/abort_p1
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/error_p1
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/snk_cyc_d0
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/stored_status
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/oob_state
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/oob
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/wb_out
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/decoded_status
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/abort_now
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/stall_int
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/tx_en
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/ep_ctrl
+add wave -noupdate -group EP_1 -group tx_header /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Header_Processor/bitsel_d
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/clk_sys_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/rst_n_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/snk_fab_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/snk_dreq_o
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/src_fab_o
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/src_dreq_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/inject_mem_addr_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/inject_mem_data_o
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/uram_offset_wr_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/uram_offset_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/uram_data_i
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/state
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/counter
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_rd_vid
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_wr_vid
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_untag
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_untag_reg
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_stored_tag
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/vut_stored_ethertype
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/mem_addr_muxed
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/mem_rdata
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/src_dreq_d0
+add wave -noupdate -group EP_1 -group tx_vlan /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/gen_with_vlan_unit/U_VLAN_Unit/flush_ethtype
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/g_use_new_crc
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/clk_sys_i
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/rst_n_i
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/snk_fab_i
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/snk_dreq_o
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/src_fab_o
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/src_dreq_i
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/dbg_o
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/state
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_gen_reset
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_gen_enable
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_value
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/odd_length
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/embed_valid
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/embed_eof
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/stored_msb
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/in_payload
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/src_dreq_d0
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_p_value
+add wave -noupdate -group EP_1 -group tx_crc /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_Tx_Path/U_Insert_CRC/crc_n_value
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/rst_n_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/clk_sys_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_fab_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_error_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_busy_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/pcs_dreq_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/mdio_mcr_pdown_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/mdio_wr_spec_tx_cal_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_en_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_val_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/timestamp_trigger_p_a_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/rmon_tx_underrun
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_clk_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_data_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_k_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_disparity_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/phy_tx_enc_err_i
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/dbg_wr_count_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/dbg_rd_count_o
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_is_k
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_odata_reg
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_catch_disparity
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_state
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_cntr
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_cr_alternate
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_packed_in
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_packed_out
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_empty
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_almost_empty
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_almost_full
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_enough_data
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_wr
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_rd
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_ready
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d0
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d1
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d2
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d3
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_clear_n_d4
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_read_int
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/fifo_fab
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_busy
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/tx_error
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/reset_synced_txclk
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/mdio_mcr_pdown_synced
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/s_one
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_en_synced
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/wr_count
+add wave -noupdate -group EP_1 -expand -group tx16bit_PCS /main/DUT/U_Top/U_Wrapped_SCBCore/gen_network_stuff/gen_endpoints_and_phys(1)/U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/rd_count
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {270168000000 fs} 1} {{Cursor 7} {292760000000 fs} 1} {{Cursor 8} {270248000000 fs} 1} {{Cursor 4} {268714826620 fs} 1}
+configure wave -namecolwidth 289
+configure wave -valuecolwidth 195
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits fs
+update
+WaveRestoreZoom {0 fs} {728322 ns}