hwdu_wishbone_slave
WR Switch Hardware Debugging Unit
The module is used for reading the value of registers from inside of WR Switch. Usefull for debugging during development.
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control Register
3.2. Value of the requested register
|
→
|
rst_n_i
|
|
Control Register:
|
|
|
→
|
clk_sys_i
|
|
hwdu_cr_adr_o[15:0]
|
⇒
|
|
→
|
wb_adr_i
|
|
hwdu_cr_rd_err_i
|
←
|
|
⇒
|
wb_dat_i[31:0]
|
|
hwdu_cr_rd_en_o
|
→
|
|
⇐
|
wb_dat_o[31:0]
|
|
hwdu_cr_rd_en_i
|
←
|
|
→
|
wb_cyc_i
|
|
hwdu_cr_rd_en_load_o
|
→
|
|
⇒
|
wb_sel_i[3:0]
|
|
|
|
|
→
|
wb_stb_i
|
|
Value of the requested register:
|
|
|
→
|
wb_we_i
|
|
hwdu_reg_val_i[31:0]
|
⇐
|
|
←
|
wb_ack_o
|
|
|
|
|
←
|
wb_stall_o
|
|
|
|
|
HW prefix:
|
hwdu_cr
|
|
HW address:
|
0x0
|
|
C prefix:
|
CR
|
|
C offset:
|
0x0
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
|
RD_EN
|
RD_ERR
|
-
|
-
|
-
|
-
|
-
|
-
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
|
ADR[15:8]
|
|
|
|
|
|
|
|
-
ADR
[read/write]: Address of the register
Which register (among those connected to HWDU) will be read
-
RD_ERR
[read-only]: Read error
read 1: read error, provided address is out of range
read 0: read done successfully
-
RD_EN
[read/write]: Read register value
write 1: read the content
write 0: no effect
read 1: reading in progress
read 0: reading done, register value available
|
HW prefix:
|
hwdu_reg_val
|
|
HW address:
|
0x1
|
|
C prefix:
|
REG_VAL
|
|
C offset:
|
0x4
|
The value of the register under ADR from the Control Register
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
|
REG_VAL[31:24]
|
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
|
REG_VAL[23:16]
|
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
|
REG_VAL[15:8]
|
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
REG_VAL[7:0]
|
|
|
|
|
|
|
|
-
REG_VAL
[read-only]: register value