Skip to content

W
White Rabbit Network Interface Card
Commit 7a337d4c authored by Javier Díaz's avatar Javier Díaz
Browse files
Options

vic-eic interrupts tested, debugged with python scripts

parent 00ce30b6
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2687 additions and 1499 deletions
Manifest.py
View file @ 7a337d4c
......@@ -8,3 +8,5 @@ modules = {"local" :
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized",
"svn" : "http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl"
}
doc/wr-nic.mkd
View file @ 7a337d4c
This diff is collapsed.
modules/wrsw_dio/Manifest.py
View file @ 7a337d4c
files = ["wrsw_dio_wb.vhd",
"wrsw_dio.vhd",
"pulse_gen_pl.vhd",
"immed_pulse_counter.vhd",
"dummy_time.vhd" ]
"xwrsw_dio.vhd",
"pulse_gen_pl.vhd",
"immed_pulse_counter.vhd",
"dummy_time.vhd" ]
modules/wrsw_dio/wrsw_dio.vhd
View file @ 7a337d4c
This diff is collapsed.
modules/wrsw_dio/xwrsw_dio.vhd 0 → 100644
View file @ 7a337d4c
This diff is collapsed.
software_test_dio_core/dio_fmc.py
View file @ 7a337d4c
......@@ -23,6 +23,17 @@ class VIC_irq:
def get_reg(self, adr):
return self.bus.iread(0, self.base + adr, 4)
class wrcore_time:
def __init__(self, bus, base):
self.bus = bus;
self.base = base;
def set_reg(self, adr, value):
self.bus.iwrite(0, self.base + adr, 4, value)
def get_reg(self, adr):
return self.bus.iread(0, self.base + adr, 4)
class CDAC5578:
......@@ -63,10 +74,10 @@ class CDAC5578:
class CFmcDio:
BASE_REGS = 0x300
BASE_GPIO = 0x200
BASE_I2C = 0x100
BASE_ONEWIRE = 0x0
BASE_I2C = 0x100
BASE_GPIO = 0x200
BASE_REGS = 0x300
I2C_ADDR_DAC = 0x48
I2C_ADDR_EEPROM = 0x50
......@@ -132,13 +143,13 @@ class CFmcDio:
return self.ds1820.read_temp(serial_number)
def set_reg(self, adr, value):
self.bus.iwrite(0, 0x60000 + self.BASE_REGS + adr, 4, value)
self.bus.iwrite(0, 0x62000 + self.BASE_REGS + adr, 4, value)
def get_reg(self, adr):
return self.bus.iread(0, 0x60000 + self.BASE_REGS + adr, 4)
return self.bus.iread(0, 0x62000 + self.BASE_REGS + adr, 4)
def get_reg_long(self, adr):
return self.bus.iread(0, 0x60000 + self.BASE_REGS + adr, 8)
return self.bus.iread(0, 0x62000 + self.BASE_REGS + adr, 8)
def wait_irq_spec(self):
return self.bus.irqwait()
......
software_test_dio_core/load.sh
View file @ 7a337d4c
#!/bin/bash
insmod ~/pts/gnurabbit/kernel/rawrabbit.ko vendor=0x10dc device=0x18d
insmod ~/OHWR/wr-nic/software_test_dio_core/rawrabbit.ko vendor=0x10dc device=0x18d
software_test_dio_core/test_pulse.py
View file @ 7a337d4c
This diff is collapsed.
software_test_dio_core/test_pulse_v01.py 0 → 100644
View file @ 7a337d4c
#!/usr/bin/python
#coding: utf8
from ptsexcept import *
from dio_fmc import *
import rr
import os
import sys
import gn4124
import kbhit
"""
Tests DIO core (GEN AND STAMPER PULSE)
"""
def pause():
raw_input("press key\n")
GN4124_CSR = 0x0
def main(default_directory="."):
print "(-------------STARTING TEST-----------------)"
# Configure the FPGA using the program fpga_loader
path_fpga_loader = './fpga_loader'
path_firmware = '../syn/spec/wr_nic_top.bin'
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)
os.system( firmware_loader + ' ' + bitstream )
# Load board library and open the corresponding device
spec = rr.Gennum()
gennum = gn4124.CGN4124(spec, GN4124_CSR)
dio = CFmcDio(spec, 0x62000)
print "(3 devices expected)"
print
print ("FMC temperature: %3.3f°C" % dio.get_temp())
print "(expected room or computer temperature)"
print
# Lemo output configuration
print "(------------CONFIGURING DIO CHANNELS--------------)"
print "Value of LEMOs with all drivers enabled and terminations disabled"
for lemon in range(5):
dio.set_term(lemon, 0)
dio.set_dir(lemon, 1) # enable output
dio.set_in_threshold(lemon,15)
print "Input threshold set to an intermediate level ({}).".format(dio.get_in_threshold(0))
print
print "(------------CONFIGURING INTERRUPTS--------------)"
# DIO Interrupts
print "(DIO Interrupts)"
dio.set_reg(0x64, 0x1f) # Interrupts when the fifos have datas (UTC time from the pulse stamper)
#dio.set_reg(0x64, 0x3ff) # fifos and pulse gen rdy interrupts
mask_irq = dio.get_reg(0x68)
print "MASK IRQ DIO =>", mask_irq
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq
# VIC Interrupts
print "(VIC Interrupts)"
VIC = VIC_irq(spec, 0x60000)
VIC.set_reg(0x0, 0x3) # control register
control_irq_vic = VIC.get_reg(0x0)
print "CONTROL IRQ VIC =>", control_irq_vic
VIC.set_reg(0x8, 0x7) # enable register
mask_irq_vic = VIC.get_reg(0x10)
print "MASK IRQ VIC =>", mask_irq_vic
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
# Simulate interrupts
#VIC.set_reg(0x18, 0x7) # generate soft irq
#status_irq_vic = VIC.get_reg(0x4)
#print "STATUS VIC IRQ AFTER SOFTWARE INTERRUPTS =>", status_irq_vic
# Checking interrupts at pc level
#print "Waiting irq ..."
#spec.irqena()
#gennum.set_interrupt_config()
#a=gennum.wait_irq()
#b=spec.irqwait()
#print "Is this working?", a,b
# Read WRCORE time --> HANG UP THE PC!!!!!!!
#WR_CORE_AD =0x0
#PRI_CROSSBAR_AD=0x00020000 # Second bridge
#SEC_CROSSBAR_AD=0x00000300 # PPS
#time = wrcore_time(spec, (WR_CORE_AD + PRI_CROSSBAR_AD+SEC_CROSSBAR_AD))
#print "eso", time
#seconds= time.get_reg(0x8) NNOOOOOOO!!!!!! 0x00020308
#cycles = time.get_reg(0x4)
#seconds=10
#cycles=0
#print "Time is: ", seconds, "and", cycles*8, "(cycles", cycles, ")"
###################################################################################
# START LEMO OUTPUT DANCING ...
print
print "(------------START LEMO CONFIGURATION--------------)"
#print "Note: The dummy time core is already running after configuring the fpga, therefore you should run this program"
#print "before the configured trigger time below."
# BASIC GPIO FUNCTIONALITY TEST
dio.set_reg(0x3C, 0x00) # channels as GPIOs
for lemon in range(5):
dio.set_dir(lemon, 1) # enable output
dio.set_out(lemon,0)
val=dio.get_in (lemon)
print "Set value for channel", lemon, " to 0, read: ", val
dio.set_out(lemon,1)
val=dio.get_in (lemon)
print "Set value for channel", lemon, " to 1, read: ", val
# Please connect channel 0 and 1 with a lemo wire for this test
dio.set_dir(0, 0) # enable channel 1 output and dissble channel 0
dio.set_dir(1,1)
dio.set_out(1,0)
val=dio.get_in (0)
print "Channel 1 write 0, channel 0 read", val
dio.set_out(1,1)
val=dio.get_in (0)
print "Channel 1 write 1, channel 0 read", val
# Osciloscope test
#dio.set_out(4,1)
#pause()
#dio.set_out(4,0)
#pause()
#dio.set_out(4,1)
#pause()
#dio.set_out(4,0)
#pause()
# TIME-LENGTH PROGRAMMABLE PULSES TESTS
dio.set_reg(0x3C, 0x1f) #Generate a programmable/immediate pulse of different length
# Setting pulse length
dio.set_reg(0x48, 0x1)
dio.set_reg(0x4C, 0x8)
dio.set_reg(0x50, 0x10)
dio.set_reg(0x54, 0x1)
dio.set_reg(0x58, 0x40)
# Time-stamps FIFOs registers address
adr_status_fifo = [0x7c, 0x8c, 0x9c, 0xac, 0xbc]
adr_time = [0x70, 0x80, 0x90, 0xa0, 0xb0] # we just take the lowest 32 bits for the seconds
adr_cycles = [0x78, 0x88, 0x98, 0xa8, 0xb8]
# Flushng fifos from previous game
print
for dio_pulse in range(5): # reading of pulses
print "------Flushing fifos ", dio_pulse, ":"
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
cont = 0
while((status_fifo_reg & 0xff) != 0x0):
time = dio.get_reg_long(adr_time[dio_pulse])
cycles = dio.get_reg(adr_cycles[dio_pulse])
print "Pulse ", cont
print "Seconds DIO dio_pulse =>", time
print "cycles DIO dio_pulse =>", cycles
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
cont = cont + 1
print
###################################################################################################
# Inmmediate output test
print
print "(-----------IMMEDIATE PULSE GENERATION (5 pulses for each DIO)---------------)"
#pause()
for num_pulses in range(5):
dio.set_reg(0x5C, 0x1f) #Generate a pulse of different length
#status_irq = dio.get_reg(0x6c)
##print "STATUS IRQ DIO =>", status_irq
print "5 Immediate pulse of different length has been generated for each channel"
print
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq # 31 means the 5 fifos has data
print
for dio_pulse in range(5): # reading of pulses
print "------Pulses from DIO ", dio_pulse, ":"
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
cont = 0
while((status_fifo_reg & 0xff) != 0x0):
time = dio.get_reg_long(adr_time[dio_pulse])
cycles = dio.get_reg(adr_cycles[dio_pulse])
print "Pulse ", cont
print "Seconds DIO dio_pulse =>", time
print "cycles DIO dio_pulse =>", cycles
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
cont = cont + 1
print
print
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq # we have read the fifo, no data to read => 0
############################################################################
print
print "Starting time-programmable test"
print
print "(------------TIME-TRIGGER BASED OUTPUTS--------------)"
# Programmable output test
dio_rdy = dio.get_reg(0x44)
if dio_rdy != 0x1f:
print "Some pulse_gen module isn't ready to accept next trigger time tag, dio_rdy:", dio_rdy
exit()
#TIME TRIGGERS VALUES FOR EACH CHANNEL
dio.set_reg(0x0, 3) #trig0 seconds_low
dio.set_reg(0x4, 0) #trig0 seconds_high
dio.set_reg(0x8, 0) #trig0 cycles
dio.set_reg(0xc, 5) #trig1 seconds_low
dio.set_reg(0x10, 0) #trig1 seconds_high
dio.set_reg(0x14, 67) #trig1 cycles
dio.set_reg(0x18, 10) #trig2 seconds_low
dio.set_reg(0x1c, 0) #trig2 seconds_high
dio.set_reg(0x20, 430) #trig2 cycles
dio.set_reg(0x24, 12) #trig3 seconds_low
dio.set_reg(0x28, 0) #trig3 seconds_high
dio.set_reg(0x2c, 94) #trig3 cycles
dio.set_reg(0x30, 15) #trig4 seconds_low
dio.set_reg(0x34, 0) #trig4 seconds_high
dio.set_reg(0x38, 98) #trig4 cycles
dio.set_reg(0x40, 0x1f) # channell x trigger strobe
print
for dio_pulse in range(5):
print "Waiting pulse stamper from DIO ", dio_pulse," ...."
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
while((status_fifo_reg & 0xff) != 0x1): #counter = 0x1
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
time = dio.get_reg_long(adr_time[dio_pulse])
cycles = dio.get_reg(adr_cycles[dio_pulse])
print "DIO dio_pulse seconds =>", time
print "DIO dio_pulse cycles =>", cycles
print
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
print
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq
exit()
if __name__ == "__main__":
main(".")
syn/spec/wr_nic.xise
View file @ 7a337d4c
This source diff could not be displayed because it is too large. You can view the blob instead.
top/spec/wr_nic_top.vhd
View file @ 7a337d4c
......@@ -40,6 +40,11 @@
-- 0x00060000: VIC
-- 0x00061000: TxTSU
-- 0x00062000: DIO
-- 0x000: DIO-ONEWIRE
-- 0x100: DIO-I2C
-- 0x200: DIO-GPIO
-- 0x300: DIO-REGISTERS
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -80,8 +85,8 @@ entity wr_nic_top is
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8 -- T.B.V. datasheet write 9
-- GPIO[1] -> GN4124 GPIO9 -- T.B.V. datasheet write 9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
......@@ -475,7 +480,7 @@ architecture rtl of wr_nic_top is
end component;
-- DIO core
component wrsw_dio
component xwrsw_dio
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
......@@ -866,9 +871,9 @@ begin
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
dma_irq_o => open, -- T.B.D. Check it is ok
dma_irq_o => open,
irq_p_i => vic_irq,
irq_p_o => GPIO(0),
irq_p_o => GPIO(1), -- T.B.D. Check if GPIO is 1 or 0
dma_reg_clk_i => clk_sys, -- Look, many signals just take default values if not used
......@@ -1153,7 +1158,7 @@ begin
-----------------------------------
-- DIO core
-----------------------------------
U_dio_core : wrsw_dio
U_dio_core : xwrsw_dio
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment