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Distributed Direct Digital Synthesis over White Rabbit D3S
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  • Setup cern vme

Setup cern vme

Last edited by Eva Calvo Jan 28, 2016
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Setting up DDS demo system on a CERN VME Crate

Requirements:

Hardware:*

  • A VME crate with a MEN A20 CPU
  • 2 SVECs with 2 DDS FMCs installed in slot 1.
  • A WR Switch & fibers.

Software:*

  • An LM32 toolchain to build the realtime software. Until it becomes officially supported, the is one installed in /user/twlostow/apps/gcc-lm32

Setup instructions:

Setting up the repository

  • Note: you must do the following operations from a PC with Internet access, so that Git can fetch the necessary submodules. *
  • Clone the repository of the project and ensure the submodules are up-to-date:

$ git clone git:https://www.ohwr.org/white-rabbit/wr-d3s.git
$ cd wr-d3s
$ git submodule update --init

  • Edit software/applications/wr_d3s/rt/common/wrnode.mk and point it to the correct LM32 compiler location:

CROSS_COMPILE=/user/twlostow/apps/gcc-lm32/bin/lm32-elf-

  • Build the real-time firmware and tools:

$ cd software/
$ make LINUX=/acc/sys/L866/usr/src/kernels/3.6.11-rt30.25.el6rt.x86_64/

Loading the drivers

  • Make sure the SVECs are declared in /etc/transfer.ref. There's no need to declare the mezzanines.
  • From the Front-end: go to the scripts/ subdirectory of the repo and run:

$ sudo ./load-vme-cern.sh

This should output something like:

svec: insmod with lun=0,1 slot=10,12 vme_base=0x500000,0x600000 vector=0xd8,0xd9 fw_name=fmc/svec-golden.bin,fmc/svec-golden.bin vme_am=0x39,0x39 vme_size=0x80000,0x80000
Loading FPGA for SVEC LUN=0
Loading FPGA for SVEC LUN=1
mount: none already mounted or /sys/kernel/debug/ busy
mount: according to mtab, none is already mounted on /sys/kernel/debug
Loading WR Core firmware for SVEC @ lun 0 slot 10
Loading WR Core firmware for SVEC @ lun 1 slot 12

If everything loaded correctly, there should be two WR Nodes visible in the system.

$ lswrnc
wrnc-0302
wrnc-0282

Take note of the device IDs, they will be needed to load the realtime software.

By default, the script assumes there are 2 SVECs in the system. The drivers can be installed for any number of SVEC cards by editing the line:

# SVECs to load the firmware to
SVECS="0 1" - put the LUN list of the SVECs here.

To load your own FPGA firmware, change the path in the following line of the script to the path of your binary:

# FPGA firmware path
FW=/lib/firmware/fmc/test/svec-wr-d3s-test-20150907a.bin

Building and running the realtime software.

The RT software & tools reside in the software/applications/wr_d3s/rt subdirectory:

- d3s/ subdirectory contains the sources of the real-time application (LM32).
- tools subdirectory contains the wr-d3s-ctl tool used to configure the parameters of the frequency distribution (stream ID, frequency, etc.)

These are built automatically with the drivers, in order to rebuild them you may call make in any of the directories above.

In order to load the realtime software:

* edit the software/applications/wr_d3s/rt/d3s/Makefile by putting the IDs of the WR Node devices seen by lswrnc in the previous step. For two SVECs with the IDs presented in this example, the load target should look like this:

load:
    wrnc-loader -D 0x302 -i 0 -f rt-d3s.bin
    wrnc-cpu-restart -D 0x302 -i 0
    wrnc-loader -D 0x282 -i 0 -f rt-d3s.bin
    wrnc-cpu-restart -D 0x282 -i 0
  • (optional) run the wrnc-messages tool in another terminal to see if the embedded CPUs say hello to the debug console:
    $ wrnc-messages -Q
  • load the firmware:
    @ $ cd software/applications/wr_d3s/rt/d3s/Makefile@

And then from the Front-end and with root rights:
@ $ make load @

* the debug console should show something like:

wrnc-0302-cpu-00: Initializing AD9516 PLL...
wrnc-0302-cpu-00: Waiting for lock...[e]
wrnc-0282-cpu-00: Initializing AD9516 PLL...
wrnc-0282-cpu-00: Waiting for lock...[e]
wrnc-0302-cpu-00: RT_D3S firmware initialized.
wrnc-0302-cpu-00: WR link online!
wrnc-0302-cpu-00: WR time ok [lock on]!
wrnc-0282-cpu-00: RT_D3S firmware initialized.
wrnc-0282-cpu-00: WR link online!
wrnc-0302-cpu-00: WR link locked!

Setting up the RF transmission:

Connect the RF source to the RF input of the master card.

Use the wr-d3s-ctl tool in the software/applications/wr_d3s/tools directory to configure RF transmission. For a system with one master (ID = 0x282) and one slave (ID = 0x302), running at 352 MHz the command go as follows:

./wr-d3s-ctl -D 0x282 -C stream master 1234 352e6
./wr-d3s-ctl -D 0x302 -C stream slave 1234 0

The first parameter after the mode is the stream ID, allowing to multiplex several RF signals inside the same WR network. The second parameter is the center frequency in Hz (irrelevant in slave mode).

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