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Distributed Direct Digital Synthesis over White Rabbit D3S
Commit 1bd30289 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: initial commit

parent dc92d265
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dds_regs.vh 0 → 100644
View file @ 1bd30289
`define ADDR_DDS_CR 6'h0
`define DDS_CR_TEST_OFFSET 0
`define DDS_CR_TEST 32'h00000001
`define DDS_CR_SLAVE_OFFSET 1
`define DDS_CR_SLAVE 32'h00000002
`define DDS_CR_MASTER_OFFSET 2
`define DDS_CR_MASTER 32'h00000004
`define DDS_CR_ADC_BB_ENABLE_OFFSET 3
`define DDS_CR_ADC_BB_ENABLE 32'h00000008
`define DDS_CR_CLK_ID_OFFSET 4
`define DDS_CR_CLK_ID 32'h000ffff0
`define ADDR_DDS_GPIOR 6'h4
`define DDS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define DDS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define DDS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
`define DDS_GPIOR_PLL_SYS_RESET_N 32'h00000002
`define DDS_GPIOR_PLL_SCLK_OFFSET 2
`define DDS_GPIOR_PLL_SCLK 32'h00000004
`define DDS_GPIOR_PLL_SDIO_OFFSET 3
`define DDS_GPIOR_PLL_SDIO 32'h00000008
`define DDS_GPIOR_PLL_SDIO_DIR_OFFSET 4
`define DDS_GPIOR_PLL_SDIO_DIR 32'h00000010
`define DDS_GPIOR_PLL_VCXO_RESET_N_OFFSET 5
`define DDS_GPIOR_PLL_VCXO_RESET_N 32'h00000020
`define DDS_GPIOR_PLL_VCXO_CS_N_OFFSET 6
`define DDS_GPIOR_PLL_VCXO_CS_N 32'h00000040
`define DDS_GPIOR_PLL_VCXO_FUNCTION_OFFSET 7
`define DDS_GPIOR_PLL_VCXO_FUNCTION 32'h00000080
`define DDS_GPIOR_PLL_VCXO_SDO_OFFSET 8
`define DDS_GPIOR_PLL_VCXO_SDO 32'h00000100
`define DDS_GPIOR_ADF_CE_OFFSET 9
`define DDS_GPIOR_ADF_CE 32'h00000200
`define DDS_GPIOR_ADF_CLK_OFFSET 10
`define DDS_GPIOR_ADF_CLK 32'h00000400
`define DDS_GPIOR_ADF_LE_OFFSET 11
`define DDS_GPIOR_ADF_LE 32'h00000800
`define DDS_GPIOR_ADF_DATA_OFFSET 12
`define DDS_GPIOR_ADF_DATA 32'h00001000
`define DDS_GPIOR_ADC_SDI_OFFSET 13
`define DDS_GPIOR_ADC_SDI 32'h00002000
`define DDS_GPIOR_ADC_CNV_OFFSET 14
`define DDS_GPIOR_ADC_CNV 32'h00004000
`define DDS_GPIOR_ADC_SCK_OFFSET 15
`define DDS_GPIOR_ADC_SCK 32'h00008000
`define DDS_GPIOR_ADC_SDO_OFFSET 16
`define DDS_GPIOR_ADC_SDO 32'h00010000
`define ADDR_DDS_FREQ_HI 6'h8
`define ADDR_DDS_FREQ_LO 6'hc
`define ADDR_DDS_GAIN 6'h10
`define ADDR_DDS_RSTR 6'h14
`define DDS_RSTR_PLL_RST_OFFSET 0
`define DDS_RSTR_PLL_RST 32'h00000001
`define DDS_RSTR_SW_RST_OFFSET 1
`define DDS_RSTR_SW_RST 32'h00000002
`define ADDR_DDS_I2CR 6'h18
`define DDS_I2CR_SCL_OUT_OFFSET 0
`define DDS_I2CR_SCL_OUT 32'h00000001
`define DDS_I2CR_SDA_OUT_OFFSET 1
`define DDS_I2CR_SDA_OUT 32'h00000002
`define DDS_I2CR_SCL_IN_OFFSET 2
`define DDS_I2CR_SCL_IN 32'h00000004
`define DDS_I2CR_SDA_IN_OFFSET 3
`define DDS_I2CR_SDA_IN 32'h00000008
`define ADDR_DDS_PIR 6'h1c
`define DDS_PIR_KP_OFFSET 0
`define DDS_PIR_KP 32'h0000ffff
`define DDS_PIR_KI_OFFSET 16
`define DDS_PIR_KI 32'hffff0000
`define ADDR_DDS_PD_FIFO_R0 6'h20
`define DDS_PD_FIFO_R0_DATA_OFFSET 0
`define DDS_PD_FIFO_R0_DATA 32'h0000ffff
`define ADDR_DDS_PD_FIFO_CSR 6'h24
`define DDS_PD_FIFO_CSR_FULL_OFFSET 16
`define DDS_PD_FIFO_CSR_FULL 32'h00010000
`define DDS_PD_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_PD_FIFO_CSR_EMPTY 32'h00020000
`define ADDR_DDS_TUNE_FIFO_R0 6'h28
`define DDS_TUNE_FIFO_R0_DATA_OFFSET 0
`define DDS_TUNE_FIFO_R0_DATA 32'hffffffff
`define ADDR_DDS_TUNE_FIFO_CSR 6'h2c
`define DDS_TUNE_FIFO_CSR_FULL_OFFSET 16
`define DDS_TUNE_FIFO_CSR_FULL 32'h00010000
`define DDS_TUNE_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_TUNE_FIFO_CSR_EMPTY 32'h00020000
rtl/Manifest.py
View file @ 1bd30289
files = ["dds_single_channel.v","lfsr_gen.vhd" ]
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "mdsp.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd" ]
modules = {"local":"streamers"}
rtl/ad7980_if.vhd 0 → 100644
View file @ 1bd30289
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dds_wbgen2_pkg.all;
entity ad7980_if is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0);
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic
);
end ad7980_if;
architecture rtl of ad7980_if is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal count : unsigned(7 downto 0);
signal do_acq : std_logic;
type t_state is (WAIT_TRIG, START_CNV, READBACK);
signal state : t_state;
signal d_rdy : std_logic;
begin -- rtl
U_SPI_Master : spi_master
generic map (
g_div_ratio_log2 => 3,
g_num_data_bits => 16)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
start_i => do_acq,
cpol_i => '0',
data_i => x"0000",
data_o => d_o,
drdy_o => d_rdy,
spi_sclk_o => adc_sck_o,
spi_miso_i => adc_sdo_i);
d_valid_o <= d_rdy;
adc_sdi_o <= '1';
p_acquire : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= (others => '0');
adc_cnv_o <= '0';
do_acq <= '0';
state <= WAIT_TRIG;
else
case state is
when WAIT_TRIG =>
if(trig_i = '1') then
count <= (others => '0');
adc_cnv_o <= '1';
state <= START_CNV;
end if;
when START_CNV =>
count<= count +1;
if(count = 100) then
adc_cnv_o <= '0';
do_acq <= '1';
state <= READBACK;
end if;
when READBACK =>
do_acq <= '0';
if(d_rdy = '1') then
state <= WAIT_TRIG;
end if;
end case;
end if;
end if;
end process;
end rtl;
rtl/build_wb.sh 0 → 100755
View file @ 1bd30289
#!/bin/bash
wbgen2 -V dds_wb_slave.vhd -H record -p dds_wbgen2_pkg.vhd -K ../dds_regs.vh -s defines -C dds_regs.h -D doc/dds_regs.html dds_wb_slave.wb
rtl/cic_1024x.vhd 0 → 100644
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This diff is collapsed.
rtl/dds_core.vhd 0 → 100644
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rtl/dds_quad_channel.v 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ps
module dds_quad_channel
(
clk_i,
rst_n_i,
acc_i,
acc_o,
dreq_i,
tune_i,
tune_load_i,
acc_load_i,
y0_o,
y1_o,
y2_o,
y3_o);
parameter integer g_acc_frac_bits = 32;
parameter integer g_output_bits = 14;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 10;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_lut_cell_size = g_lut_sample_bits + g_lut_slope_bits;
input clk_i;
input rst_n_i;
input acc_load_i;
input tune_load_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
output reg [g_acc_frac_bits + g_lut_size_log2 : 0] acc_o;
input [g_acc_frac_bits + g_lut_size_log2 : 0] tune_i;
input dreq_i;
output wire [g_output_bits-1:0] y0_o, y1_o, y2_o, y3_o;
wire [g_lut_size_log2-1:0] lut_addr[0:3];
reg [c_lut_cell_size-1:0] lut_data[0:3];
reg [c_acc_bits-1:0] acc, acc_d0, acc_f[0:3], tune;
wire [g_output_bits-1:0] y[0:3];
always@(posedge clk_i)
begin
if(!rst_n_i)begin
tune <= 0;
acc <= 0;
end else begin
if(tune_load_i)
tune <= tune_i;
if(acc_load_i)
acc <= acc_i;
else if(dreq_i) begin
acc <= acc + tune;
acc_d0 <= acc;
acc_o <= acc;
acc_f[0] <= acc_d0;
acc_f[1] <= acc_d0 + (tune >> 2);
acc_f[2] <= acc_d0 + (tune >> 1);
acc_f[3] <= acc_d0 + (tune >> 2) + (tune >> 1);
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_i)
generate
genvar i;
for(i=0;i<4;i=i+1)
begin
dds_stage
#(
.g_acc_frac_bits(g_acc_frac_bits),
.g_output_bits(g_output_bits),
.g_lut_size_log2(g_lut_size_log2),
.g_dither_init_value(i*1234567)
)
U_Stage_X
(
.clk_i(clk_i),
.rst_n_i(rst_n_i),
.acc_i(acc_f[i]),
.y_o(y[i]),
.dreq_i(dreq_i),
.lut_addr_o(lut_addr[i]),
.lut_data_i(lut_data[i])
);
end // for (i=0;i<4;i++)
endgenerate
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut01[0:2**g_lut_size_log2-1];
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut23[0:2**g_lut_size_log2-1];
`include "lut_init.v"
initial begin
`INIT_LUT(01)
`INIT_LUT(23)
end
always@(posedge clk_i)
lut_data[0] <= lut01[lut_addr[0]];
always@(posedge clk_i)
lut_data[1] <= lut01[lut_addr[1]];
always@(posedge clk_i)
lut_data[2] <= lut23[lut_addr[2]];
always@(posedge clk_i)
lut_data[3] <= lut23[lut_addr[3]];
assign y0_o = y[0];
assign y1_o = y[1];
assign y2_o = y[2];
assign y3_o = y[3];
endmodule // dds_quad_channel
\ No newline at end of file
rtl/dds_stage.v 0 → 100644
View file @ 1bd30289
`timescale 1ns/1ps
module dds_stage
(
clk_i,
rst_n_i,
acc_i,
dreq_i,
y_o,
lut_addr_o,
lut_data_i
);
parameter integer g_acc_frac_bits = 32;
parameter integer g_dither_init_value = 32'h00000001;
parameter integer g_output_bits = 12;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 12;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_dither_bits = (g_lut_sample_bits - g_output_bits - 1);
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_output_shift = g_lut_sample_bits - g_output_bits;
wire signed [c_dither_bits :0 ] dither_in;
input clk_i;
input rst_n_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
input dreq_i;
output reg [g_output_bits-1:0] y_o;
output reg [g_lut_size_log2-1:0] lut_addr_o;
input [g_lut_sample_bits + g_lut_slope_bits - 1:0] lut_data_i;
reg [c_acc_bits-1:0] acc0, acc1, tune;
wire [g_lut_size_log2 : 0] phase;
wire [g_lut_slope_bits-1 : 0] frac;
reg [g_lut_slope_bits-1 : 0] frac_d0, frac_d1, frac_d2, frac_d3;
wire half;
reg [g_lut_size_log2-1:0] addr0, addr1,tmp,tmp2,tmp3;
reg [8:0] sign;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut_in;
wire signed [g_lut_slope_bits-1:0] lut_slope;
reg signed [g_lut_slope_bits-1:0] slope_d0;
wire signed [g_lut_sample_bits-1:0] lut_sample;
reg signed [g_lut_sample_bits-1:0] sample_d0;
reg signed [g_lut_sample_bits-1:0] interp, interp_d0;
reg signed [g_lut_sample_bits-1:0] qv;
reg signed [g_output_bits:0] yt;
wire signed [2*g_lut_slope_bits-1:0] interp_mul;
reg [g_dither_length-1:0] lfsr=g_dither_init_value;
assign lut_slope = lut_in[g_lut_sample_bits + g_lut_slope_bits - 1 : g_lut_sample_bits ];
assign lut_sample = lut_in[g_lut_sample_bits - 1 : 0];
assign phase = acc_i [ g_acc_frac_bits + g_lut_size_log2 - 1 : g_acc_frac_bits - 1];
assign half = acc_i [g_acc_frac_bits + g_lut_size_log2];
assign frac = acc_i [g_acc_frac_bits - 1 : g_acc_frac_bits-g_lut_slope_bits];
always@(posedge clk_i)
begin
if (!rst_n_i) begin
lfsr <= g_dither_init_value;
end else if (dreq_i) begin
if(lfsr[0])
lfsr <= {1'b0, lfsr[g_dither_length-1:1]} ^ g_dither_taps;
else
lfsr <= {1'b0, lfsr[g_dither_length-1:1]};
end
end
wire signed [g_lut_slope_bits:0] interp_frac;
assign interp_frac = {1'b0, frac_d3};
assign dither_in = { lfsr[c_dither_bits+4:5], 1'b0 };
assign interp_mul = lut_slope * interp_frac;
always@(posedge clk_i)
begin
if (!rst_n_i) begin
end else if(dreq_i) begin
addr0 <= acc_i[g_acc_frac_bits + g_lut_size_log2-1 : g_acc_frac_bits];
sign <= {sign[7:0], half };
lut_addr_o <= addr0;
lut_in <= lut_data_i;
frac_d0 <= frac;
frac_d1 <= frac_d0;
frac_d2 <= frac_d1;
frac_d3 <= frac_d2;
interp <= interp_mul >>> (g_lut_slope_bits + g_interp_shift);
sample_d0 <= lut_sample;
qv <= (sample_d0) + (interp) + (dither_in) + 1;
if(sign[5])
yt <= qv >>> (c_output_shift-1);
else
yt <= (-qv) >>> (c_output_shift-1);
if(yt[0])
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)) + 1);
else
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)));
end // if (dreq_i)
end // always@ (posedge clk_i)
endmodule // dds_single_channel
rtl/dds_wb_slave.vhd 0 → 100644
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rtl/dds_wb_slave.wb 0 → 100644
View file @ 1bd30289
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DDS RF distribution WB Slave";
hdl_entity = "dds_wb_slave";
prefix = "dds";
reg {
prefix = "CR";
name = "Control Register";
field {
name = "Enable DDS test mode";
prefix = "TEST";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Enable DDS RF slave mode";
prefix = "SLAVE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Enable DDS RF master mode";
prefix = "MASTER";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "ADC Bitbanged Access Enable";
prefix = "ADC_BB_ENABLE";
type = MONOSTABLE;
};
field {
name = "Broadcast Clock ID";
description = "Send/Receive clocks matching given ID";
prefix = "CLK_ID";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
reg {
prefix = "GPIOR";
name = "GPIO register";
field {
name = "System PLL CS";
prefix = "PLL_SYS_CS_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "System Reset";
prefix = "PLL_SYS_RESET_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL SCLK (shared)";
prefix = "PLL_SCLK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL SDIO (shared)";
prefix = "PLL_SDIO";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "PLL SDIO direction (shared)";
prefix = "PLL_SDIO_DIR";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Reset";
prefix = "PLL_VCXO_RESET_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Chip Select";
prefix = "PLL_VCXO_CS_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Function";
prefix = "PLL_VCXO_FUNCTION";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL SDO";
prefix = "PLL_VCXO_SDO";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "ADF4002 Chip Enable";
prefix = "ADF_CE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Clock";
prefix = "ADF_CLK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Latch Enable";
prefix = "ADF_LE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Data";
prefix = "ADF_DATA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Data Out";
prefix = "ADC_SDI";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Convert Strobe";
prefix = "ADC_CNV";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Serial Clock";
prefix = "ADC_SCK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Data In";
prefix = "ADC_SDO";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
fifo_reg {
name = "PD ADC Test FIFO (test mode)";
prefix = "PD_FIFO";
size = 512;
direction = CORE_TO_BUS;
clock = "clk_ref_i";
flags_bus = { FIFO_EMPTY, FIFO_FULL };
flags_dev = { FIFO_EMPTY, FIFO_FULL };
field {
name = "ADC data";
prefix = "DATA";
size = 16;
type = SLV;
};
};
fifo_reg {
name = "DDS Tuning FIFO (test mode)";
prefix = "TUNE_FIFO";
size = 512;
flags_bus = { FIFO_EMPTY, FIFO_FULL };
flags_dev = { FIFO_EMPTY };
direction = BUS_TO_CORE;
clock = "clk_ref_i";
field {
name = "DDS tune word";
prefix = "DATA";
size = 32;
type = SLV;
};
};
reg {
name = "DDS Center frequency hi";
prefix = "FREQ_HI";
field {
name = "Center freq HI";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DDS Center frequency lo";
prefix = "FREQ_LO";
field {
name = "Center freq LO";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DDS Gain";
prefix = "GAIN";
field {
name = "DDS gain (4.12 unsigned)";
size = 16;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "RSTR";
field {
name = "FPGA REF/Serdes PLL Reset";
prefix = "PLL_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FPGA DDS Logic software reset";
prefix = "SW_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "I2C bitbanged IO register";
prefix = "I2CR";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
reset_value = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "PI register";
prefix = "PIR";
field {
name = "KP";
prefix = "KP";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
field {
name = "KI";
prefix = "KI";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
};
\ No newline at end of file
rtl/dds_wbgen2_pkg.vhd 0 → 100644
View file @ 1bd30289
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for DDS RF distribution WB Slave
---------------------------------------------------------------------------------------
-- File : dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from dds_wb_slave.wb
-- Created : Fri May 10 01:11:43 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package dds_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dds_in_registers is record
gpior_pll_sdio_i : std_logic;
gpior_pll_vcxo_sdo_i : std_logic;
gpior_adc_sdo_i : std_logic;
pd_fifo_wr_req_i : std_logic;
pd_fifo_data_i : std_logic_vector(15 downto 0);
tune_fifo_rd_req_i : std_logic;
i2cr_scl_in_i : std_logic;
i2cr_sda_in_i : std_logic;
end record;
constant c_dds_in_registers_init_value: t_dds_in_registers := (
gpior_pll_sdio_i => '0',
gpior_pll_vcxo_sdo_i => '0',
gpior_adc_sdo_i => '0',
pd_fifo_wr_req_i => '0',
pd_fifo_data_i => (others => '0'),
tune_fifo_rd_req_i => '0',
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0'
);
-- Output registers (WB slave -> user design)
type t_dds_out_registers is record
cr_test_o : std_logic;
cr_slave_o : std_logic;
cr_master_o : std_logic;
cr_adc_bb_enable_o : std_logic;
cr_clk_id_o : std_logic_vector(15 downto 0);
gpior_pll_sys_cs_n_o : std_logic;
gpior_pll_sys_reset_n_o : std_logic;
gpior_pll_sclk_o : std_logic;
gpior_pll_sdio_o : std_logic;
gpior_pll_sdio_load_o : std_logic;
gpior_pll_sdio_dir_o : std_logic;
gpior_pll_vcxo_reset_n_o : std_logic;
gpior_pll_vcxo_cs_n_o : std_logic;
gpior_pll_vcxo_function_o : std_logic;
gpior_adf_ce_o : std_logic;
gpior_adf_clk_o : std_logic;
gpior_adf_le_o : std_logic;
gpior_adf_data_o : std_logic;
gpior_adc_sdi_o : std_logic;
gpior_adc_cnv_o : std_logic;
gpior_adc_sck_o : std_logic;
pd_fifo_wr_full_o : std_logic;
pd_fifo_wr_empty_o : std_logic;
tune_fifo_rd_empty_o : std_logic;
tune_fifo_data_o : std_logic_vector(31 downto 0);
freq_hi_o : std_logic_vector(31 downto 0);
freq_lo_o : std_logic_vector(31 downto 0);
gain_o : std_logic_vector(15 downto 0);
rstr_pll_rst_o : std_logic;
rstr_sw_rst_o : std_logic;
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
pir_kp_o : std_logic_vector(15 downto 0);
pir_ki_o : std_logic_vector(15 downto 0);
end record;
constant c_dds_out_registers_init_value: t_dds_out_registers := (
cr_test_o => '0',
cr_slave_o => '0',
cr_master_o => '0',
cr_adc_bb_enable_o => '0',
cr_clk_id_o => (others => '0'),
gpior_pll_sys_cs_n_o => '0',
gpior_pll_sys_reset_n_o => '0',
gpior_pll_sclk_o => '0',
gpior_pll_sdio_o => '0',
gpior_pll_sdio_load_o => '0',
gpior_pll_sdio_dir_o => '0',
gpior_pll_vcxo_reset_n_o => '0',
gpior_pll_vcxo_cs_n_o => '0',
gpior_pll_vcxo_function_o => '0',
gpior_adf_ce_o => '0',
gpior_adf_clk_o => '0',
gpior_adf_le_o => '0',
gpior_adf_data_o => '0',
gpior_adc_sdi_o => '0',
gpior_adc_cnv_o => '0',
gpior_adc_sck_o => '0',
pd_fifo_wr_full_o => '0',
pd_fifo_wr_empty_o => '0',
tune_fifo_rd_empty_o => '0',
tune_fifo_data_o => (others => '0'),
freq_hi_o => (others => '0'),
freq_lo_o => (others => '0'),
gain_o => (others => '0'),
rstr_pll_rst_o => '0',
rstr_sw_rst_o => '0',
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
pir_kp_o => (others => '0'),
pir_ki_o => (others => '0')
);
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body dds_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_dds_in_registers) return t_dds_in_registers is
variable tmp: t_dds_in_registers;
begin
tmp.gpior_pll_sdio_i := f_x_to_zero(left.gpior_pll_sdio_i) or f_x_to_zero(right.gpior_pll_sdio_i);
tmp.gpior_pll_vcxo_sdo_i := f_x_to_zero(left.gpior_pll_vcxo_sdo_i) or f_x_to_zero(right.gpior_pll_vcxo_sdo_i);
tmp.gpior_adc_sdo_i := f_x_to_zero(left.gpior_adc_sdo_i) or f_x_to_zero(right.gpior_adc_sdo_i);
tmp.pd_fifo_wr_req_i := f_x_to_zero(left.pd_fifo_wr_req_i) or f_x_to_zero(right.pd_fifo_wr_req_i);
tmp.pd_fifo_data_i := f_x_to_zero(left.pd_fifo_data_i) or f_x_to_zero(right.pd_fifo_data_i);
tmp.tune_fifo_rd_req_i := f_x_to_zero(left.tune_fifo_rd_req_i) or f_x_to_zero(right.tune_fifo_rd_req_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
return tmp;
end function;
end package body;
rtl/lut_init.v 0 → 100644
View file @ 1bd30289
This diff is collapsed.
rtl/mac_test.v 0 → 100644
View file @ 1bd30289
module mac_test(
input clk_i,
input rst_n_i,
input signed [63:0] acc_i,
input [1:0] op_i,
input signed [31:0] a_i,
input signed [31:0] b_i,
output signed [63:0] q_o);
reg signed [63:0] acc0, acc1, acc2, m0, d0;
`define op_mul 2'b00
`define op_mac 2'b01
`define op_load 2'b10
`define op_trunc 2'b11
reg [1:0] s2_op, s3_op, s4_op;
always@(posedge clk_i)
begin
case(op_i)
`op_mac: m0 <= a_i * b_i;
`op_mul: m0 <= a_i * b_i;
`op_load: d0 <= acc_i;
default: m0 <= a_i * b_i;
endcase // case (op_i)
s2_op <= op_i;
end // always@ (posedge clk_i)
always@(posedge clk_i)
begin
s3_op <= s2_op;
case(s2_op)
`op_mac: acc0 <= acc0 + m0;
`op_load: acc0 <= d0;
default: acc0 <= m0;
endcase // case (s2_op)
end
always@(posedge clk_i)
begin
s4_op <= s3_op;
acc1 <=acc0;
end
always@(posedge clk_i)
if(s4_op == `op_trunc)
acc2 <= acc1 >> 30;
else
acc2 <= acc1;
assign q_o = acc2;
endmodule // mac_test
\ No newline at end of file
rtl/max5870_serializer.vhd 0 → 100644
View file @ 1bd30289
-- file: max5870_serializer.vhd
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity max5870_serializer is
generic
(-- width of the data for the system
sys_w : integer := 14;
-- width of the data for the device
dev_w : integer := 56);
port
(
-- From the device out to the system
DATA_OUT_FROM_DEVICE : in std_logic_vector(dev_w-1 downto 0);
DATA_OUT_TO_PINS_P : out std_logic_vector(sys_w-1 downto 0);
DATA_OUT_TO_PINS_N : out std_logic_vector(sys_w-1 downto 0);
-- Clock and reset signals
CLK_IN : in std_logic; -- Fast clock from PLL/MMCM
CLK_DIV_IN : in std_logic; -- Slow clock from PLL/MMCM
LOCKED_IN : in std_logic;
LOCKED_OUT : out std_logic;
CLK_RESET : in std_logic; -- Reset signal for Clock circuit
IO_RESET : in std_logic); -- Reset signal for IO circuit
end max5870_serializer;
architecture xilinx of max5870_serializer is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "max5870_serializer,selectio_wiz_v3_2,{component_name=max5870_serializer,bus_dir=OUTPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=14,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFPLL,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=NOT_APP,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVCMOS18,v6_clk_sig_type=DIFF}";
constant clock_enable : std_logic := '1';
signal unused : std_logic;
signal clk_in_int_buf : std_logic;
signal clk_div_in_int : std_logic;
-- Before the buffer
signal data_out_to_pins_int : std_logic_vector(sys_w-1 downto 0);
-- Between the delay and serdes
signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
constant num_serial_bits : integer := dev_w/sys_w;
type serdarr is array (0 to 7) of std_logic_vector(sys_w-1 downto 0);
-- Array to use intermediately from the serdes to the internal
-- devices. bus "0" is the leftmost bus
-- * fills in from higher order
signal oserdes_d : serdarr := (( others => (others => '0')));
signal serdesstrobe : std_logic;
signal ocascade_ms_d : std_logic_vector(sys_w-1 downto 0);
signal ocascade_ms_t : std_logic_vector(sys_w-1 downto 0);
signal ocascade_sm_d : std_logic_vector(sys_w-1 downto 0);
signal ocascade_sm_t : std_logic_vector(sys_w-1 downto 0);
begin
-- Create the clock logic
bufpll_inst : BUFPLL
generic map (
DIVIDE => 4)
port map (
IOCLK => clk_in_int_buf,
LOCK => LOCKED_OUT,
SERDESSTROBE => serdesstrobe,
GCLK => CLK_DIV_IN, -- GCLK pin must be driven by BUFG
LOCKED => LOCKED_IN,
PLLIN => CLK_IN);
-- We have multiple bits- step over every bit, instantiating the required elements
pins: for pin_count in 0 to sys_w-1 generate
begin
-- Instantiate the buffers
----------------------------------
-- Instantiate a buffer for every bit of the data bus
obufds_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => DATA_OUT_TO_PINS_P (pin_count),
OB => DATA_OUT_TO_PINS_N (pin_count),
I => data_out_to_pins_int(pin_count));
-- Pass through the delay
-----------------------------------
data_out_to_pins_int(pin_count) <= data_out_to_pins_predelay(pin_count);
-- Instantiate the serdes primitive
----------------------------------
-- declare the oserdes
oserdes2_master : OSERDES2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_OT => "SDR",
TRAIN_PATTERN => 0,
DATA_WIDTH => 4,
SERDES_MODE => "NONE",
OUTPUT_MODE => "SINGLE_ENDED")
port map (
D1 => oserdes_d(3)(pin_count),
D2 => oserdes_d(2)(pin_count),
D3 => oserdes_d(1)(pin_count),
D4 => oserdes_d(0)(pin_count),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '1',
SHIFTIN2 => '1',
SHIFTIN3 => '1',
SHIFTIN4 => '1',
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TRAIN => '0',
OCE => clock_enable,
CLK0 => clk_in_int_buf,
CLK1 => '0',
CLKDIV => CLK_DIV_IN,
OQ => data_out_to_pins_predelay(pin_count),
TQ => open,
IOCE => serdesstrobe,
TCE => clock_enable,
RST => IO_RESET);
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- This places the first data in time on the right
oserdes_d(4-slice_count-1) <=
DATA_OUT_FROM_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w);
-- To place the first data in time on the left, use the
-- following code, instead
-- oserdes_d(slice_count) <=
-- DATA_OUT_FROM_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w);
end generate out_slices;
end generate pins;
end xilinx;
rtl/mdsp.v 0 → 100644
View file @ 1bd30289
This diff is collapsed.
rtl/pi_control.v 0 → 100644
View file @ 1bd30289
module pi_control(
input clk_i,
input rst_n_i,
input d_valid_i,
input [15:0] d_i,
output reg q_valid_o,
output reg signed [15:0] q_o,
input signed [15:0] ki_i,
input signed [15:0] kp_i
);
parameter g_goal = 32768;
parameter g_acc_shift = 6;
reg signed [39:0] acc;
reg signed [15:0] err,d0,d1;
reg [4:0] stage;
reg clip_plus;
reg clip_minus;
wire signed [17:0] ds;
assign ds = {3'b0, d_i} - g_goal;
always@(posedge clk_i)
if(!rst_n_i) begin
stage[0] <= 0;
acc <= 0;
end else begin
stage[0] <= d_valid_i;
if(d_valid_i) begin
$display("%d %d", ds <0, !clip_minus);
if(clip_plus && ds<0)
acc <= acc + ds;
else if(clip_minus && ds>0)
acc <= acc + ds;
else if (!clip_plus && !clip_minus)
acc <= acc + ds;
d0 <= ds;
end
end
reg signed [39 - g_acc_shift : 0] acc0;
always@(posedge clk_i)
if(!rst_n_i) begin
stage[1] <= 0;
end else begin
acc0 <= acc >> g_acc_shift;
d1<=d0;
stage[1] <= stage[0];
end
reg signed [23:0] term_p, term_i, sum;
wire signed [24 + 30 - 1 : 0] mul_p, mul_i;
assign mul_i = acc0 * ki_i;
assign mul_p = d1 * kp_i;
always@(posedge clk_i)
if(!rst_n_i) begin
stage[2] <= 0;
end else begin
stage[2]<=stage[1];
term_i <= mul_i >> 16;
term_p <= mul_p >> 16;
end
always@(posedge clk_i)
if(!rst_n_i) begin
stage[3] <= 0;
end else begin
sum <= term_p + term_i;
stage[3] <= stage[2];
end
always@(posedge clk_i)
if(!rst_n_i) begin
q_valid_o <= 0;
clip_plus <=0;
clip_minus <= 0;
end else begin
if(stage[3])
begin
if(sum < -32767) begin
clip_minus <= 1;
clip_plus<= 0;
q_o <= -32767;
end else if(sum > 32767) begin
clip_minus <= 0;
clip_plus<= 1;
q_o <= 32767;
end else begin
clip_minus <= 0;
clip_plus<= 0;
q_o <= sum;
end
end
q_valid_o <= stage[3];
end
endmodule
\ No newline at end of file
rtl/spi_master.vhd 0 → 100644
View file @ 1bd30289
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-05-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spi_master;
architecture behavioral of spi_master is
signal divider : unsigned(11 downto 0);
signal tick : std_logic;
signal sreg : std_logic_vector(g_num_data_bits-1 downto 0);
signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
begin -- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
divider <= (others => '0');
else
if(start_i = '1' or tick = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
end if;
end if;
end process;
tick <= divider(g_div_ratio_log2);
-- Main state machine. Executes SPI transfers
p_main_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
sclk <= '0';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
counter <= (others => '0');
drdy_o <= '0';
else
case state is
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_mosi_o <= data_i(sreg'high);
end if;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when TX_CS =>
if tick = '1' then
state <= TX_DAT1;
end if;
-- Outputs subsequent bits to MOSI line.
when TX_DAT1 =>
if(tick = '1') then
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
-- Flips the SCLK (active edge)
when TX_SCK1 =>
if(tick = '1') then
sclk <= not sclk;
counter <= counter + 1;
state <= TX_DAT2;
end if;
-- Shifts in bits read from the slave
when TX_DAT2 =>
if(tick = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when TX_SCK2 =>
if(tick = '1') then
sclk <= not sclk;
if(counter = g_num_data_bits) then
state <= TX_CS2;
else
state <= TX_DAT1;
end if;
end if;
-- Generates a gap for de-assertoin of CS line
when TX_CS2 =>
if(tick = '1') then
state <= TX_GAP;
data_o <= rx_sreg;
drdy_o <= '1';
end if;
when TX_GAP =>
drdy_o <= '0';
if (tick = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
ready_o <= '1' when (state = IDLE and start_i = '0') else '0';
-- SCLK polarity control
spi_sclk_o <= sclk xor cpol_i;
end behavioral;
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files = [ "xtx_streamer.vhd", "tx_streamer.vhd", "xrx_streamer.vhd", "rx_streamer.vhd", "gc_escape_inserter.vhd", "gc_escape_detector.vhd", "dropping_buffer.vhd","streamers_pkg.vhd" ]
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syn/spec/Manifest.py 0 → 100644
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target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_rf_demo.xise"
modules = { "local" : [ "../../top" ] }
files = "wrc.ram"
\ No newline at end of file
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testbench/dds_single/main.sv
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testbench/dds_single/wave.do
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action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../rtl" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim"
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make
vlog -sv main.sv +incdir+../../sim
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 10us
wave zoomfull
radix -hex
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action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../top" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
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-0.00038385 -0.0013273 -0.0015635 0.00091054 0.0047773 0.0039991 -0.0042284 -0.010424 -0.001365 0.016826 0.01661 -0.013276 -0.036778 -0.0081087 0.051718 0.054753 -0.038602 -0.12613 -0.049535 0.20453 0.43998 0.43998 0.20453 -0.049535 -0.12613 -0.038602 0.054753 0.051718 -0.0081087 -0.036778 -0.013276 0.01661 0.016826 -0.001365 -0.010424 -0.0042284 0.0039991 0.0047773 0.00091054 -0.0015635 -0.0013273 -0.00038385
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files = ["mem_model.vhd", "textutil.vhd", "gn412x_bfm.vhd", "util.vhd"]
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