Q: Loading the FPGA bitstream seems to work, but executing spec-cl or spec-vuart results in a segmentation fault. What am I doing wrong?
A: First of all make sure you run the spec-cl or spec-vuart as root
(e.g. using sudo). If you have more than one SPEC board in your
computer please check the spec-sw documentation for the parameters
specifying which board spec-cl and spec-vuart should
Q: I'm trying to run WR PTP Core on my personal FPGA boards and the MAC address for each of them is the same.
A: WR PTP Core uses the ID of digital 1-wire thermometer available on
SPEC board to generate unique MAC address for each board. If you use
some other board instead of SPEC there are high changes that you don't
have such thermometer. Then, your MAC address is default, but you can
change it manually with "mac set " wrpc shell
Q: How can I feed WR PTP Core running on SPEC board with 1-PPS and 10MHz signals?
A: First of all you need to have your
SPEC carrying a Digital IO FMC
board (DIO). The DIO has
several LEMO connectors you will be using. You just need to plug your
10MHz signal to LEMO connector no.5 and 1-PPS signal to LEMO connector
no.4. After setting the WR PTP Core mode to GrandMaster (please check
WRPC building manual for
instructions on how to do this) it will synchronize its internal clock
to your reference and will distribute it to the Slave.
On the other side, on the SPEC running in Slave mode you can connect
LEMO no.1 to get 1-PPS output signal aligned to 1-PPS from
Master/GrandMaster. There is no output for the 10 MHz signal (we believe
the signal driver used on the DIO is not suited for
Q: Is it possible to generate a 10MHz reference from a SPEC FMC-DIO card synchronized to a white rabbit switch?
You cannot use the two oscillators on the
SPEC to generate this clock as
they are needed for WR synchronization. One of them is the local 125MHz
clock being synchronized to WR Master, and the other is DMTD offset
clock needed for phase measurements. If you need to generate 10MHz from
your node you need to use Fine Delay
Q: How can I synthesize WRPC gateware to run on SPEC in standalone mode?
copy the wrc.ram file generated during the wrpc software compilation
set the generic parameter of xwr_core component in
g_dpram_initf => "wrc.ram"
Q: Is alpha parameter a fixed constant in the WRPC-code somewhere or is it somehow estimated from measurement?
Q: Synthesis without wrc.ram takes less time, how can I embed WR PTP Core software binary into the synthesized bitstream ?
A: You can use data2mem to combine the configuration file (.bit with
"empty" RAM) with an "elf" file. As a result you will get a ".bit" file
with RAM blocks filled with your code. You'll need the placement of the
RAM blocks that were generated by the place&route tool of Xilinx. This
is the "-bd.bmm" file. An example CMD script
attached (Note that this example uses two different instances of the
Another tricky thing may be to create a ".bmm" file. The Xilinx tools do
not provide a template (although the tool has got all the knowledge) so
you should prepare one manually. Luckily this is a one time operation
(as long as the memory size is not changed). Attached You'll find a
sample ".bmm" file
the same example design). The tricky bit is that the synthesis tool
creates the final names of the BRAMs. The topology of the memory (how
the BRAMs are composed to build the complete memory array) also may
differ between sysnthesis tools.
These are the steps performed with Xilinx XST design flow:
1. Synthesize design with wr_core parameter g_dpram_initf=""
2. Look in design.pcf file (or use PlanAhead) to guess ram instance
3. Fix instance prefix in fpga.bmm
4. Add ngdbuild option: -bm fpga.bmm
5. Implement as usual, get bitfile with empty ram
6. Compile wrpc-sw software and get wrc.elf
7. data2mem -bm fpga_bd.bmm -bd wrc.elf -bt work/fvme2tmwr.bit -o b
Q: Can I use WR PTP Core as a regular IEEE1588 Slave?
A: Yes, it is possible starting with version v2.1
of the WR PTP Core which uses PPSI as a default WR PTP engine. See also
FAQ Not now, but we are working on it. Currently the WR PTP Core can be
the Master for non-WR, regular IEEE1588 device, but cannot synchronize
itself to a non-WR Master. However, next release of WRPC software will
allow to configure also regular IEEE1588 Slave and Master.
Q: Can the WR Core receive data from a standard Ethernet Switch?
A: Yes. If your application does not require timing, you may use a
standard Gigabit Ethernet switch; the WR core will simply pass packets
through. The WR Core will not need to wait for any synchronization
packets before start receiving data. The data is independent of
WR PTP core internals
Q: Why is the PLL locking the local clock to the physical link clock implemented with the help of an LM32 processor and is it not just implemented in hardware?
A: Three reasons:
Because control algorithms for PLLs are not so simple
Q: I'm trying to figure out how to add timestamps to samples from an ADC (25Ms/s) on a standalone Specv4 board.
A: Just latch the values of the WRPC outputs tm_tai and tm_cycles.
tm_tai is the current number of TAI seconds, tm_cycles is the number
of 8 ns ticks since the beginning of the current second. When
tm_cycles reaches 124999999, tm_tai counter is incremented and
tm_cycles goes back to 0.
Note that these counters run in the WR reference clock domain
(clk_ref). If the signal to latch the timestamp comes from a different
clock domain, you can use the gc_pulse_synchronizer module from the
general-cores library to pass it to clk_ref
Q: How can I phase align a non-125 MHz clock locked to WR 125 MHz reference?
_Original question: I'm integrating White Rabbit in a distributed DAQ
system runing at
41.667 MHz. There are clock signals originating from WR 125 MHz main
clock and divided by 3 using sy89229 with async reset. The phase of
divided clock is synchronized by resetting the divider after WR is
locked using 1-pps signal (and tm_tai % 3 == 0). The drawback is an
interruption of divided clock while reset.
Does anyone has an idea how to synchronize derived clock phase with
1-pps using softpll adjustment?_
h3: A: This feature is planned for 2015 to be included in the official
WR PTP core release and the upcoming release of FmcAdc100M with WR
The idea is to produce a PPS signal from the 41.667 MHz clock and sample
it with the WR PPS signal. it's a trick that we already use in recent
SoftPLL versions for locking to a 10 MHz external reference. The phase
of the aux 125 MHz clock is swept (either by linear sweep or by
divide-and-conquer) until a transition is observed in the PPS signal -
this will mean that both PPSes are in phase (+- the jitter). The extra
benefit is capability of fine phase tuning of the divided clock (of