Frequently Asked Questions
About the use of the PTP core
Q: Loading the FPGA bitstream seems to work, but executing spec-cl or spec-vuart results in a segmentation fault. What am I doing wrong ?
A: First of all make sure you run the spec-cl or spec-vuart as root (e.g. using sudo). If you have more than one SPEC board in your computer please check the spec-sw documentation for the parameters specifying which board spec-cl and spec-vuart should use.
Q: I'm trying to run WR PTP Core on my personal FPGA boards and the MAC address for each of them is the same.
A: WR PTP Core uses the ID of digital 1-wire thermometer available on SPEC board to generate unique MAC address for each board. If you use some other board instead of SPEC there are high changes that you don't have such thermometer. Then, your MAC address is default, but you can change it manually with "mac set " wrpc shell command.
Q: How can I feed WR PTP Core running on SPEC board with 1-PPS and 10MHz signals ?
A: First of all you need to have your SPEC carrying a Digital IO FMC board (DIO). The DIO has several LEMO connectors you will be using. You just need to plug your 10MHz signal to LEMO connector no.5 and 1-PPS signal to LEMO connector no.4. After setting the WR PTP Core mode to GrandMaster (please check WRPC building manual for instructions on how to do this) it will synchronize its internal clock to your reference and will distribute it to the Slave.
On the other side, on the SPEC running in Slave mode you can connect LEMO no.1 to get 1-PPS output signal aligned to 1-PPS from Master/GrandMaster. There is no output for the 10 MHz signal (we believe the signal driver used on the DIO is not suited for it).
Q: Can I use WR PTP Core as a regular IEEE1588 Slave ?
A: Not now, but we are working on it. Currently the WR PTP Core can be the Master for non-WR, regular IEEE1588 device, but cannot synchronize itself to a non-WR Master. However, next release of WRPC software will allow to configure also regular IEEE1588 Slave and Master.
Q: How can I synthesize WRPC gateware to run on SPEC in standalone mode ?
A:
- copy the wrc.ram file generated during the wrpc software compilation to syn/spec_1_1/wr_core_demo/.
- set the generic parameter of xwr_core component in
top/spec_1_1/wr_core_demo/spec_top.vhd
g_dpram_initf => "wrc.ram" - build new gateware
About the internals of the PTP core
Q: Why is the PLL locking the local clock to the physical link clock implemented with the help of an LM32 processor and is it not just implemented in hardware?
Three reasons:
- Because control algorithms for PLLs are not so simple
- Because HDL is difficult to debug
- Because SoftPLL takes much less space
Read the full story in the document Why the SoftPLL is not a HardPLL...
4 March 2013