• Maciej Lipinski's avatar
    wr_streamers: fixed bug that prevented timestamps from being latched · caa2e084
    Maciej Lipinski authored
    In the mode in which data is provided to wr_streamers with clk_ref_i,
    the timestamps are captured with the clk_ref_i clock. The input data
    then crosses domains via FIFO to clk_sys_i clock. The timestamp is
    used by FSM in the clk_sys_i domain. The pulse from the timestamper
    was expected to happen when the frame is already started to be
    generated by the FSM, thus the latch of the tag_valid pulse
    (indicating the timestamp was generated) was reseted in the IDLE
    state of this FSM. This is OK when the input data and the FSM
    are in the same clock domain. IF there is asynch FIFO in between,
    it can happen that the timestamp is generated still in the IDLE
    state of the FSM... I've changed the reset of the latch to happen
    after the timestamp is embedded in the header (i.e. in the
    FRAME_SEQ_ID state).
    caa2e084
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