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Maciej Lipinski authored
This was previously implemented but got lost when the fixed latency instreamers was re-done. The idea is to compensate for internal delays, so that the tx/rx_valid signals are as close to the configured latency as possible. Corrected simulation accordingly: the simulation also corrected for delays.
b34eac40
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| .. | ||
| fabric | ||
| timing | ||
| wr_dacs | ||
| wr_eca | ||
| wr_endpoint | ||
| wr_mini_nic | ||
| wr_nic | ||
| wr_pps_gen | ||
| wr_si57x_interface | ||
| wr_softpll_ng | ||
| wr_streamers | ||
| wr_tbi_phy | ||
| wr_tlu | ||
| wr_txtsu | ||
| wrc_core | ||
| Manifest.py |