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Grzegorz Daniluk authored
This constraint is needed only when DMTD samples 125m refclock (clock has to be fed to D input of a flip-flop). However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher. This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D input of a flip-flop. This constraint would be needed e.g. for Kintex, where refclock is 62.5MHz and we don't use g_divide_input_by_2.
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Manifest.py | ||
spec_reset_gen.vhd | ||
spec_top.ucf | ||
spec_top.vhd |