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Dimitris Lampridis authored
This allows to use the same top level vhd for different synthesis targets. Example, we can use the spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.
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Makefile | ||
Manifest.py | ||
svec_wr_ref.xise | ||
svec_wr_ref_top.ucf |