Currently WR PTP Core exposes directly its full internal address space over external Wishbone interface. This requires a huge memory window being allocated from the designs that instantiate it. In vast majority of cases these applications using WR PTP Core are interested only in reading diagnostics registers.

TODO: add Wishbone address translation module that would "hide" the whole LM32 memory space from external WB interface. Provide registers in Syscon WB peripheral for accessing LM32 memory indirectly so that updating LM32 binary is still possible over Wishbone.