This constraint is needed only when DMTD samples 125m refclock (clock has to be
fed to D input of a flip-flop). However, in case of SPEC we use
g_divide_input_by_2 generic in the dmtd_with_deglitcher. This re-generates
62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D input of a
flip-flop.
This constraint would be needed e.g. for Kintex, where refclock is 62.5MHz and
we don't use g_divide_input_by_2.

the WR Switch so that later we can merge.

- this new module contains the PLLs, buffers, PHY and DAC arbiter that
  would be usually copied in the top_level of each design
- it was created to make integration of WRPC in user's design easier and
  cleaner
- it is expected to be extended with more families in which case, only
  the PHY is expected to change
- similar module will be created for Altera

- merged two pkg files (wr_streamers and wr_transmission) into one, i.e.
  a moved the stuff from wr_transmission into wr_streamers and removed
  wr_transmission_pkg.vhd file
- added simulation header in proper place, i.e. ./sim/
- modified build_wb.sh script adapting it to "kind-of convesion" used in wr-cores

- xwr_transmission is a container for rx and tx streamers that might be
  generally useful in non-Btrain projects. it was initially developed
  for Btrain
- it was imported from the following repo/branch/commit
  ssh://git@gitlab.cern.ch:7999/BTrain-TEAM/PS-BTrain-over-WhiteRabbit.git
  ML-addressReviewFeedback
  cfc0fc0eeb1f81f80154a2a30027c1e6df5d0171
- it was imported with history following steps in:
  http://stackoverflow.com/questions/1365541/how-to-move-files-from-one-git-repo-to-another-not-a-clone-preserving-history

Before, the output data would be maintained after to valid_o goes LOW. this causes two problems
- main problem: if there is only single output word, rx_first_p1_o and rx_last_p1_o are
  maintained HIGH, they are generally expected to be pulses
- side problem: the data is maintained - it is OK, but it is supposed to be valid anyway
  only when valid_o is HIGH
So, now the data_o is set to zeros when valid is not HIGH. this should prevent
anyone from relying on the fact that data is maintaned after valid_o goes LOW and
it makes rx_first_p1_o and rx_last_p1_o to be pulses

this is a patch that updates both, the streamers code in wr-cores and
the instantation of streamers. a separate commit just in case that this
is not a good idea.

This is to follow the naming convention and easy coding, if you know that a
signal is a single-cycle pulse, you don't need to worry about edge detection

This is to follow naming convetion for single-cycle pulse signal
This change concern all but the wr_streamers stuff that is in wr-cores.
The change of stuff inside wr-cores will be in the following and
separate commit

This ext_pll_10_to_125m component is part of xilinx platform-dependent
folder. It is used in spec_top entities. Since it was not in the package,
it had to be declared in top files which is not perfect. So, its
declaration was added to the pkg.

t was hard to get fully coherent statistics, especially if they were changing
fast (e.g. 250kHz in btrain). Setting snapshot bit to high copies at the same
instant all the counters to separate registers. as long as snapshot bit is high,
these registers are exposed to WB and SNMP. so one can read it as long as it
takes and the data is still coherent.

Conflicts:

	hdl/rtl/WRtransmission/wr_transmission_wb.vhd
	hdl/rtl/WRtransmission/wr_transmission_wbgen2_pkg.vhd