- 11 Dec, 2019 1 commit
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Tomasz Wlostowski authored
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- 02 Dec, 2019 1 commit
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Tomasz Wlostowski authored
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- 18 Oct, 2019 1 commit
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Tomasz Wlostowski authored
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- 14 Oct, 2019 1 commit
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Tomasz Wlostowski authored
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- 30 Apr, 2019 1 commit
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Dimitris Lampridis authored
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- 26 Apr, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 23 Apr, 2019 6 commits
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Dimitris Lampridis authored
hdl: introduce "g_verbose" generic to control the printing of information messages during simulation. This affects in particular the messages about loading of LM32 software, as well as the messages printed by the wishbone crossbar, listing all attached slaves. If omitted, the default value is "TRUE", in order to maintain backward compatibility.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL. According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select CLK10/CLK11. This is done in order to ensure backward compatibility with previous versions of the Xilinx platform support package.
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- 11 Mar, 2019 10 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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- 08 Mar, 2019 1 commit
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Tomasz Wlostowski authored
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- 06 Mar, 2019 16 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Otherwise, counter gets crazy when watchdog resets the swcore and feeds all the endpoints and NIC with ack=1.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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