- 29 Sep, 2020 1 commit
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Grzegorz Daniluk authored
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- 16 Sep, 2020 1 commit
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Grzegorz Daniluk authored
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- 28 Jan, 2020 3 commits
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Pascal Bos authored
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Peter Jansweijer authored
upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd
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Peter Jansweijer authored
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- 23 May, 2019 1 commit
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Maciej Lipinski authored
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- 14 May, 2019 1 commit
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Maciej Lipinski authored
The streamers demo was using very old top. With the updated of resets, etc, it stopped working (at least the testbench did stop). So, I finally updated this top to work (in the testbench at least) with the new BSP. This required a major re-do of the top. I left from the old as much as I could. The new top is based on the spec_ref_design. This was tested only for simulation (testbech/wr_streamers/streamers-on-spec_trigger-distribution). A commit with updates to simulation follows.
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- 26 Apr, 2019 1 commit
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Dimitris Lampridis authored
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- 21 Jan, 2019 12 commits
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li hongming authored
change the function of LEDs: the front end LEDs display the status of link and sync. the on-board LEDS display the act of link and PPS.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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li hongming authored
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Grzegorz Daniluk authored
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li hongming authored
Solve compile bug in ucf file.
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li hongming authored
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li hongming authored
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li hongming authored
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Grzegorz Daniluk authored
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Vraliens authored
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Vraliens authored
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- 03 Dec, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
This allows to use the same top level vhd for different synthesis targets. Example, we can use the spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.
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- 16 Oct, 2018 3 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
I prepared it based on SPEC's board support, I forgot to update vxs package name
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Maciej Lipinski authored
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- 27 Jul, 2018 1 commit
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Dimitris Lampridis authored
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- 20 Mar, 2018 1 commit
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Dimitris Lampridis authored
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- 15 Dec, 2017 1 commit
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Grzegorz Daniluk authored
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- 13 Dec, 2017 6 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
updates kintex7 phy name to reflect new peter_xilinx_phys convention add clbv3 reference design files last commit also needs artix7 support in xwrc_platform_xilinx.vhd added BullsEye connections CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd CLBv3: implementation files (including bmm) CLBv3: Clean up Conflicts: platform/xilinx/xwrc_platform_xilinx.vhd
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Peter Jansweijer authored
added clbv2_ref_design files added initial clbv2_ref_design ucf file removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16 Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i) updates kintex7 phy name to reflect new peter_xilinx_phys convention last commit also needs artix7 support in xwrc_platform_xilinx.vhd CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly. CLBv2: point proper bram file CLBv2: implementation (including bmm) CLBv2 reference design cleaned CLBv2: updated (hdlmake made) Xilinx ISE project file
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- 08 Dec, 2017 1 commit
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Grzegorz Daniluk authored
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- 30 Nov, 2017 1 commit
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Grzegorz Daniluk authored
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- 24 Nov, 2017 2 commits
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Maciej Lipinski authored
The streamer has a new start-up delay counter. this delay needs to be shorter for simulation. the fact that we are running simulation was not passed to the Tx streamer, now it is passed.
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Maciej Lipinski authored
by default, the bram content for synthesis is specified. it is only overriden by simulation. In this way, if the top can be both, simulated and synthesized.
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- 18 Aug, 2017 1 commit
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Grzegorz Daniluk authored
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- 30 Jun, 2017 1 commit
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Grzegorz Daniluk authored
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