1. 18 Jan, 2021 1 commit
  2. 16 Sep, 2020 1 commit
  3. 14 Sep, 2020 1 commit
  4. 09 Apr, 2020 1 commit
    • Maciej Lipinski's avatar
      [CUTE] move oserdes_4_to_1 to board/cute (temporary solution) · c6a8b74d
      Maciej Lipinski authored
      oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/
      that include generic modules. This prevented the Altera-based
      design from building. Ultimately, the module needs to be moved
      to some more appropriate place, possibly to
      general-cores/platform/xilinx. To be decided. A temporary solution
      is to have it in board/cute, since it is only used by in the
      xwrc_board_cute.
      c6a8b74d
  5. 28 Jan, 2020 3 commits
  6. 30 Apr, 2019 1 commit
  7. 26 Apr, 2019 1 commit
  8. 22 Jan, 2019 1 commit
    • li hongming's avatar
      Make the 500MHz clock output from PLL_BASE(clkout1). · 2e037cba
      li hongming authored
      The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL
      (CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a
      BUFG (O) when using ENABLE_SYNC (FALSE)."
      
      I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but
      the 10MHz output is still missing. So I have to change the setting of
      "cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from
      CLKOUT2.
      2e037cba
  9. 21 Jan, 2019 5 commits
  10. 03 Dec, 2018 3 commits
  11. 29 Oct, 2018 1 commit
    • Dimitris Lampridis's avatar
      hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing (re-done) · b6dfc740
      Dimitris Lampridis authored
      Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a,
      later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the
      fiber.
      
      The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking
      into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk
      side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source
      for both clock domains of the rx path.
      
      Tested on an SPEC, works.
      b6dfc740
  12. 16 Oct, 2018 2 commits
    • Maciej Lipinski's avatar
    • Maciej Lipinski's avatar
      [VXS support] Synthesis for VXS · 6426d212
      Maciej Lipinski authored
      added ISE project file (*xise) because synthesis of VXS require
      special configuration, otherwise ISE returns internal error.
      This special configuration is added XST command line option:
      " -use_new_parser yes". It can be added by clicking the top
      hierarhy file (vxs_wr_ref_top.vhd) in the "Design Manager", the
      right-click on "Synthesis -XST" in "Processes" window, from
      drop menu chose "Process Properties - Synthesis Options" and
      then input " -use_new_parser yes" on "Other XST Command Line
      Options"
      6426d212
  13. 27 Jul, 2018 1 commit
  14. 18 Dec, 2017 2 commits
  15. 13 Dec, 2017 3 commits
    • Grzegorz Daniluk's avatar
    • Peter Jansweijer's avatar
      clbv3 reference design files · 522c6cbd
      Peter Jansweijer authored
      updates kintex7 phy name to reflect new peter_xilinx_phys convention
      add clbv3 reference design files
      last commit also needs artix7 support in xwrc_platform_xilinx.vhd
      added BullsEye connections
      CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd
      CLBv3: implementation files (including bmm)
      CLBv3: Clean up
      
      Conflicts:
      	platform/xilinx/xwrc_platform_xilinx.vhd
      522c6cbd
    • Peter Jansweijer's avatar
      clbv2 reference design files · d2f24245
      Peter Jansweijer authored
      added clbv2_ref_design files
      added initial clbv2_ref_design ucf file
      removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization
      removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16
      Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design
      clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i)
      updates kintex7 phy name to reflect new peter_xilinx_phys convention
      last commit also needs artix7 support in xwrc_platform_xilinx.vhd
      CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly.
      CLBv2: point proper bram file
      CLBv2: implementation (including bmm)
      CLBv2 reference design cleaned
      CLBv2: updated (hdlmake made) Xilinx ISE project file
      d2f24245
  16. 24 Nov, 2017 2 commits
  17. 18 Aug, 2017 2 commits
  18. 17 Aug, 2017 1 commit
  19. 07 Jul, 2017 1 commit
  20. 14 Mar, 2017 1 commit
  21. 27 Feb, 2017 1 commit
  22. 24 Feb, 2017 1 commit
  23. 21 Feb, 2017 1 commit
  24. 17 Feb, 2017 2 commits
  25. 14 Feb, 2017 1 commit