1. 15 Sep, 2020 3 commits
  2. 14 Sep, 2020 3 commits
  3. 13 May, 2020 1 commit
  4. 29 Apr, 2020 1 commit
  5. 25 Apr, 2020 1 commit
  6. 23 Apr, 2020 1 commit
    • Maciej Lipinski's avatar
      [streamers] correction of internal delays for fixed-latency · b34eac40
      Maciej Lipinski authored
      This was previously implemented but got lost when the fixed latency
      instreamers was re-done. The idea is to compensate for internal
      delays, so that the tx/rx_valid signals are as close to the
      configured latency as possible.
      Corrected simulation accordingly: the simulation also corrected for
  7. 22 Apr, 2020 1 commit
  8. 21 Apr, 2020 1 commit
    • Maciej Lipinski's avatar
      [streamers] bugfix of streamers simulation · f56b734e
      Maciej Lipinski authored
      For simulation, the second duration is forced to be shorter with the
      generic g_sim_cycle_counter_range. The problem is that the tai/cycle
      counters are still counting full seconds, the trick was done only
      when calculating the delay in function f_cycles_counter_range()
      in fixed_latency_ts_match.vhd. This worked fine unless the timestamps
      were at the edge of the "shorter" second and fixed-latency was
      enabled. In such case, it happened that the time of releasing
      data from streamers was calcualted for TAI+1, yet TAI was incremented
      after the "true" second, not the shorter one. So, the simulation
      was stuck.
      To avoid messing up with PPS gen in which the tai/cycles are
      generated, for simulation the tai/cycle values are overriden
      in the xwr_streamer top module. This "alternative" TAI time
      is counted from the time when time_valid goes HIGH.
      This solution should work for streamers, provided that tx/rx
      instances have the time_valid go HIGH more or less at the same time.
      As far as I can tell, this is usually the case.
  9. 09 Apr, 2020 1 commit
    • Maciej Lipinski's avatar
      [CUTE] move oserdes_4_to_1 to board/cute (temporary solution) · c6a8b74d
      Maciej Lipinski authored
      oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/
      that include generic modules. This prevented the Altera-based
      design from building. Ultimately, the module needs to be moved
      to some more appropriate place, possibly to
      general-cores/platform/xilinx. To be decided. A temporary solution
      is to have it in board/cute, since it is only used by in the
  10. 08 Apr, 2020 1 commit
  11. 07 Apr, 2020 4 commits
    • Maciej Lipinski's avatar
      [cute/top] added synchronizer bringing pll_aux_locked to clk_pll_125m clock domain · 4e70a456
      Maciej Lipinski authored
      It seems that pll_aux_locked is in clk_sys clock domain. When
      synthesising cute for BTrain I had timing errors in the 10MHz
      generation process. This commit fixes the timing issues.
    • Maciej Lipinski's avatar
      [wr-streamers] bugfix and added reset of stats after (re-)start and synch · 79f5b749
      Maciej Lipinski authored
      1) bugfix:
         - tm_time_valid_i signal from ref_clk domain was used in sys_clk
           to gate statistics in xrx_streamers_stats.vhd - likely this gating
           was not needed because statistics are done when rcvd_latency_valid_i
           is true and this should be true only when time is valid, anyway
         - added gc_sync_ffs to synchronize tm_time_valid_i to sys_clk
           (added in xrtx_streamers_stats.vhd
      2) new feature
         - added initial reset of statistics when the WR node is first
           synchronized after powerup/reset.
         - this is useful so that we have a valid reset timestamp without
           a need for a management tool to reset them. So far, when a device
           was started, the reset timestamp was zero, so without additional
           action of reseting stats, it was not possible to know when the
           stats were started
    • Maciej Lipinski's avatar
      [wr-streamers] increased sampling period of ts_restore_tai · b5769e38
      Maciej Lipinski authored
      TAI time is sampled from clk_ref to clk_sys domain.
      Apparently, such sampling sometimes takes more than
      the configured 20 periods. Likely, this is not a problem,
      but the updated gc_synchronizer2 now complains. So, I
      increased the sampling time to 30 periods.
    • Maciej Lipinski's avatar
      [softpll] Fix clk_ext_mul_i input when g_num_exts=0 · 462beb7c
      Maciej Lipinski authored
      When g_num_exts=0, the input of xwr_softpll_ng
      clk_ext_mul_i        : in std_logic_vector(g_num_exts-1 downto 0);
      was of wrong range, i.e. std_logic_vector(-1 to 0).
      Function f_nonzero_vector() was added to generate
      std_logic_vector(0 to 0) in the case when g_num_exts=0.
  12. 03 Apr, 2020 1 commit
  13. 30 Jan, 2020 1 commit
  14. 28 Jan, 2020 5 commits
  15. 20 Jan, 2020 1 commit
  16. 17 Dec, 2019 6 commits
  17. 09 Dec, 2019 1 commit
  18. 12 Nov, 2019 1 commit
  19. 30 Aug, 2019 6 commits