Commits · peter_210422_align10mhz · Projects / White Rabbit core collection · Open Hardware Repository

22 Apr, 2021 1 commit
- remove aligned_10mhz_o and restore PPS on Spare BullsEye · 25f431c5
  
  Peter Jansweijer authored Apr 22, 2021
  
  25f431c5
12 Apr, 2021 4 commits
- removed even_odd_det · 309a4703
  Peter Jansweijer authored Apr 12, 2021
  
  309a4703
- move pll_62m5_500m, gen_10MHz, even_odd_det and probe_10mhz to spec7 board level · 99f1c964
  Peter Jansweijer authored Apr 12, 2021
  
  99f1c964
- add probe_10mhz · 4839d8bf
  Peter Jansweijer authored Apr 12, 2021
  
  4839d8bf
- TEST: PPS_o via BullsEye Spare (circumvent re-clock) · a2cadc84
  Peter Jansweijer authored Apr 06, 2021
  
  a2cadc84
24 Mar, 2021 14 commits
- add separate HPSEC XDC file · 4ca8c819
  Peter Jansweijer authored Mar 24, 2021
  
  4ca8c819
- harmonize design names (use HPSEC instead of WRITE) · d90a63fa
  Peter Jansweijer authored Mar 24, 2021
  
  d90a63fa
- Added AUXiliary I2C bus for general purpose use of I2C devices on FMC cards · 25f2f0d3
  Peter Jansweijer authored Jan 21, 2021
  
  25f2f0d3
- comment: Peripheral interconnect => base_addr · a1d5726f
  Peter Jansweijer authored Mar 24, 2021
  
  a1d5726f
- spec7_design uses g_ram_address_space_size_kb => 256 · cbeee4b9
  Peter Jansweijer authored Jan 06, 2021
  
  cbeee4b9
- board/common: allow to select legacy (128kB)/increased (256kB) LM32 RAM address… · b4fb3606
  Peter Jansweijer authored Jan 06, 2021
```
board/common: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)
```
  b4fb3606
- gen_10mhz avoid lut in reset path and add multicycle constraint due to tight 500 mhz timing. · 584fd322
  Peter Jansweijer authored Oct 30, 2020
  
  584fd322
- preload wrc_v5_spec7.bram during synthesis · 1d60f9a9
  Peter Jansweijer authored Oct 07, 2020
  
  1d60f9a9
- Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32 · 758a2910
  Nayib Boukadida authored Sep 09, 2020
  
  758a2910
- add SPEC7 design files · 71583a47
  Peter Jansweijer authored Oct 05, 2020
  
  71583a47
- wrc_core: connect phy sampled clock, also when using g_records_for_phy · cc673d1b
  Peter Jansweijer authored Aug 04, 2020
  
  cc673d1b
- xwrc_board_common: expose SoftPLL's g_use_sampled_ref_clocks generic & associated interface · 91eb6396
  Peter Jansweijer authored Aug 04, 2020
  
  91eb6396
- add rx_sampled_clk to type t_phy_8bits_to_wrc and t_phy_16bits_to_wrc · 8571d366
  Peter Jansweijer authored Aug 04, 2020
  
  8571d366
- add family7-gtx-lp files · bdf607d9
  Peter Jansweijer authored Aug 04, 2020
  
  bdf607d9
26 Jan, 2021 2 commits
- wr_si57x_interface: fix the FSM so that it REALLY freezes the VCO control value during update... · b0ba6baa
  Tomasz Wlostowski authored Jan 26, 2021
  
  b0ba6baa
- wr_si57x_interface: add BUSY flag and full N1/HSDIV configuration to register block · 1435aa3e
  Tomasz Wlostowski authored Jan 26, 2021
  
  1435aa3e
18 Jan, 2021 2 commits
- syn/pxie_fmc_ref_design: add missing README file · fb25a444
  Grzegorz Daniluk authored Jan 18, 2021
  
  fb25a444
- wr_core: hold LM32 reset active when the CPU doesn't have a preloaded firmware · c63228b6
  Tomasz Wlostowski authored Jan 18, 2021
  
  c63228b6
12 Jan, 2021 1 commit
- platform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE3 · bba3432e
  Tomasz Wlostowski authored Nov 06, 2020
  
  bba3432e
06 Jan, 2021 1 commit
- ip_cores: update vme64x-core to latest master · ebe554ec
  Grzegorz Daniluk authored Jan 06, 2021
  
  ebe554ec
15 Dec, 2020 1 commit
- bin/wrc_pxie.bram: update address space · 38ed0cdf
  Grzegorz Daniluk authored Dec 15, 2020
  
  38ed0cdf
09 Dec, 2020 1 commit
- wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address… · dedbf241
  Tomasz Wlostowski authored Dec 09, 2020
```
wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)
```
  dedbf241
02 Oct, 2020 1 commit
- update general-cores to fix vuart · 28191b5a
  Grzegorz Daniluk authored Oct 02, 2020
  
  28191b5a
29 Sep, 2020 2 commits
- spec,svec top: remove sdb and remap WRPC at 0x0 · 514ce141
  Grzegorz Daniluk authored Sep 29, 2020
  
  514ce141
- wrc_core: swap aux WB and diags in secondary crossbar · c96b4047
  Grzegorz Daniluk authored Sep 16, 2020
  
  c96b4047
16 Sep, 2020 10 commits
- platform/xilinx: select appropriate platform based on the FPGA family, not synthesis tool · d1d1cc49
  Grzegorz Daniluk authored Sep 16, 2020
  
  d1d1cc49
- CI: add pxie_ref_design vivado synthesis · f7aafcbd
  Grzegorz Daniluk authored Sep 04, 2020
  
  f7aafcbd
- platform/xilinx: split platform for vivado to a separate file not to break ise… · 53de0e6b
  Grzegorz Daniluk authored Sep 03, 2020
```
platform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitives
```
  53de0e6b
- board/spec: fix async reset bug introduced in commit 10772350 · a5fde2b1
  Grzegorz Daniluk authored Aug 25, 2020
  
  a5fde2b1
- adding LM32 binary for PXIe FMC carrier with ZU7 · 7a4a9875
  Grzegorz Daniluk authored Aug 21, 2020
  
  7a4a9875
- board/pxie-fmc: adding std_logic wrapper · 6394f6c6
  Grzegorz Daniluk authored Aug 20, 2020
  
  6394f6c6
- adding BSP for PXIe-FMC board with Xilinx ZU7 · f1a2fe27
  Grzegorz Daniluk authored Aug 17, 2020
  
  f1a2fe27
- platform/xilinx: adding support for Zynq US+ · 57c9e69e
  Grzegorz Daniluk authored Aug 17, 2020
  
  57c9e69e
- platform/xilinx: global clk_sys signal declaration so that it's available between generate blocks · e20b26ab
  Grzegorz Daniluk authored Aug 17, 2020
  
  e20b26ab
- platform/xilinx: remove unnecesary files for Ultrascale family · 1272b672
  Grzegorz Daniluk authored Sep 16, 2020
  
  1272b672