Commits · f4748f9ee2c4153601e2e0ede69567288e11ada6 · Projects / White Rabbit core collection

03 Dec, 2018 2 commits
- hdl: add auto-generated SDB meta info to SPEC and SVEC ref designs · 0d636aa5
  Dimitris Lampridis authored Nov 30, 2018
  
  0d636aa5
- hdl: move Xilinx UCF files for SPEC and SVEC into the syn/ folder. · 5d49a112
  Dimitris Lampridis authored Nov 30, 2018
```
This allows to use the same top level vhd for different synthesis targets. Example, we can use the
spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.
```
  5d49a112
27 Jul, 2018 1 commit
- syn: use board manifest for spec, svec and vfchd ref designs · 02873972
  Dimitris Lampridis authored Jul 27, 2018
  
  02873972
17 Feb, 2017 1 commit
- top/svec: introduce SVEC reference design · 0d3046df
  Dimitris Lampridis authored Feb 17, 2017
  
  0d3046df