- 28 Jan, 2020 2 commits
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Peter Jansweijer authored
add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout) wrc_phy16_direct_dmtd.bram build with: wrpc-sw.git peter_direct_dmtd SHA 50f1c0e ppsi.git peter_direct_dmtd SHA bf5f6de
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Peter Jansweijer authored
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- 20 Jan, 2020 1 commit
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Tomasz Wlostowski authored
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- 17 Dec, 2019 6 commits
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Grzegorz Daniluk authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
- Add generic parameter for the SDB info of the auxiliary interface of the WRPC. - Export pps_csync and pps_valid ports from the WRPC.
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Miguel Jimenez Lopez authored
wr_nic_wrapper: Fix copyright issues.
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Miguel Jimenez Lopez authored
Fix a place & route error related to the OBUF used for PPS output signal.
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- 09 Dec, 2019 1 commit
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Grzegorz Daniluk authored
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- 12 Nov, 2019 1 commit
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Tomasz Wlostowski authored
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- 30 Aug, 2019 16 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
It's used only locally in dmtd sampler. We don't have enough global clock nets in Virtex6 for 18-port version of WRS.
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 20 Aug, 2019 1 commit
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Grzegorz Daniluk authored
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- 13 Aug, 2019 1 commit
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Grzegorz Daniluk authored
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- 08 Aug, 2019 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Mattia Rizzi authored
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- 14 Jun, 2019 1 commit
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Grzegorz Daniluk authored
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- 05 Jun, 2019 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 31 May, 2019 2 commits
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Peter Jansweijer authored
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Peter Jansweijer authored
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- 24 May, 2019 3 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
In the mode in which data is provided to wr_streamers with clk_ref_i, the timestamps are captured with the clk_ref_i clock. The input data then crosses domains via FIFO to clk_sys_i clock. The timestamp is used by FSM in the clk_sys_i domain. The pulse from the timestamper was expected to happen when the frame is already started to be generated by the FSM, thus the latch of the tag_valid pulse (indicating the timestamp was generated) was reseted in the IDLE state of this FSM. This is OK when the input data and the FSM are in the same clock domain. IF there is asynch FIFO in between, it can happen that the timestamp is generated still in the IDLE state of the FSM... I've changed the reset of the latch to happen after the timestamp is embedded in the header (i.e. in the FRAME_SEQ_ID state).
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