- 16 Oct, 2018 6 commits
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Maciej Lipinski authored
added ISE project file (*xise) because synthesis of VXS require special configuration, otherwise ISE returns internal error. This special configuration is added XST command line option: " -use_new_parser yes". It can be added by clicking the top hierarhy file (vxs_wr_ref_top.vhd) in the "Design Manager", the right-click on "Synthesis -XST" in "Processes" window, from drop menu chose "Process Properties - Synthesis Options" and then input " -use_new_parser yes" on "Other XST Command Line Options"
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Grzegorz Daniluk authored
This reverts commit b3389d12.
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Grzegorz Daniluk authored
This reverts commit 9810ef9a.
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- 22 Aug, 2018 1 commit
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Grzegorz Daniluk authored
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- 17 Aug, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 06 Aug, 2018 1 commit
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Tomasz Wlostowski authored
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- 30 Jul, 2018 1 commit
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Dimitris Lampridis authored
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- 27 Jul, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 04 Jul, 2018 1 commit
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Tomasz Wlostowski authored
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- 03 Jul, 2018 1 commit
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Tomasz Wlostowski authored
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- 20 Mar, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 19 Mar, 2018 1 commit
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Dimitris Lampridis authored
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- 22 Feb, 2018 1 commit
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Dimitris Lampridis authored
platform/xilinx: fix bug where reference clock was not propagated with g_USE_DEFAULT_PLLS was set to false
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- 18 Dec, 2017 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 15 Dec, 2017 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 14 Dec, 2017 3 commits
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Grzegorz Daniluk authored
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Maciej Lipinski authored
no frames are transmitted/received, it only checked correctness of transmission added timeout to throw an error when no frames is received for an unacceptable time
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Grzegorz Daniluk authored
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- 13 Dec, 2017 12 commits
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Peter Jansweijer authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
updates kintex7 phy name to reflect new peter_xilinx_phys convention add clbv3 reference design files last commit also needs artix7 support in xwrc_platform_xilinx.vhd added BullsEye connections CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd CLBv3: implementation files (including bmm) CLBv3: Clean up Conflicts: platform/xilinx/xwrc_platform_xilinx.vhd
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Peter Jansweijer authored
added clbv2_ref_design files added initial clbv2_ref_design ucf file removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16 Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i) updates kintex7 phy name to reflect new peter_xilinx_phys convention last commit also needs artix7 support in xwrc_platform_xilinx.vhd CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly. CLBv2: point proper bram file CLBv2: implementation (including bmm) CLBv2 reference design cleaned CLBv2: updated (hdlmake made) Xilinx ISE project file
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Peter Jansweijer authored
(cherry picked from commit 6d689ad2)
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