Commits · 38ed0cdffa95d6bc9e3e88348cae1e8561feb245 · Projects / White Rabbit core collection · Open Hardware Repository

15 Dec, 2020 1 commit
- bin/wrc_pxie.bram: update address space · 38ed0cdf
  Grzegorz Daniluk authored Dec 15, 2020
  
  38ed0cdf
09 Dec, 2020 1 commit
- wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address… · dedbf241
  Tomasz Wlostowski authored Dec 09, 2020
```
wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)
```
  dedbf241
02 Oct, 2020 1 commit
- update general-cores to fix vuart · 28191b5a
  Grzegorz Daniluk authored Oct 02, 2020
  
  28191b5a
29 Sep, 2020 2 commits
- spec,svec top: remove sdb and remap WRPC at 0x0 · 514ce141
  Grzegorz Daniluk authored Sep 29, 2020
  
  514ce141
- wrc_core: swap aux WB and diags in secondary crossbar · c96b4047
  Grzegorz Daniluk authored Sep 16, 2020
  
  c96b4047
16 Sep, 2020 10 commits
- platform/xilinx: select appropriate platform based on the FPGA family, not synthesis tool · d1d1cc49
  Grzegorz Daniluk authored Sep 16, 2020
  
  d1d1cc49
- CI: add pxie_ref_design vivado synthesis · f7aafcbd
  Grzegorz Daniluk authored Sep 04, 2020
  
  f7aafcbd
- platform/xilinx: split platform for vivado to a separate file not to break ise… · 53de0e6b
  Grzegorz Daniluk authored Sep 03, 2020
```
platform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitives
```
  53de0e6b
- board/spec: fix async reset bug introduced in commit 10772350 · a5fde2b1
  Grzegorz Daniluk authored Aug 25, 2020
  
  a5fde2b1
- adding LM32 binary for PXIe FMC carrier with ZU7 · 7a4a9875
  Grzegorz Daniluk authored Aug 21, 2020
  
  7a4a9875
- board/pxie-fmc: adding std_logic wrapper · 6394f6c6
  Grzegorz Daniluk authored Aug 20, 2020
  
  6394f6c6
- adding BSP for PXIe-FMC board with Xilinx ZU7 · f1a2fe27
  Grzegorz Daniluk authored Aug 17, 2020
  
  f1a2fe27
- platform/xilinx: adding support for Zynq US+ · 57c9e69e
  Grzegorz Daniluk authored Aug 17, 2020
  
  57c9e69e
- platform/xilinx: global clk_sys signal declaration so that it's available between generate blocks · e20b26ab
  Grzegorz Daniluk authored Aug 17, 2020
  
  e20b26ab
- platform/xilinx: remove unnecesary files for Ultrascale family · 1272b672
  Grzegorz Daniluk authored Sep 16, 2020
  
  1272b672
15 Sep, 2020 25 commits
- modules/wrc_core: bring back link_ok_o functionality · 0fbb5a20
  Grzegorz Daniluk authored Sep 14, 2020
  
  0fbb5a20
- platform/xilinx: Manifest indentation fix, no technical change · a023a6be
  Grzegorz Daniluk authored Sep 11, 2020
  
  a023a6be
- platform/xilinx: revert to Vivado-generated wrapper for GTHE3 · c9cc5cab
  Tomasz Wlostowski authored Jul 17, 2020
  
  c9cc5cab
- wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counter · 97ecba2b
  Tomasz Wlostowski authored Jul 03, 2020
  
  97ecba2b
- wr_gthe3_phy_family7: possible fix for failing link up detection after disconnecting the fiber · 6d55fbc4
  Tomasz Wlostowski authored Jun 12, 2020
  
  6d55fbc4
- wr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force… · 900b6812
  Tomasz Wlostowski authored May 13, 2020
```
wr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force link down event in the PCS
```
  900b6812
- wr_core: expose UART FIFO configuration to wr_core generics · f5304283
  Tomasz Wlostowski authored Aug 27, 2020
  
  f5304283
- wrc_core: expose PHY LPC interface · 561f5733
  Tomasz Wlostowski authored Apr 27, 2020
  
  561f5733
- platform: pre-validated version of kintex-7 lpdc phy · c5199f95
  Tomasz Wlostowski authored Sep 25, 2019
  
  c5199f95
- wrc_core: increase LM32 code/data address space to 256 kB · b6cb633a
  Tomasz Wlostowski authored Sep 25, 2019
  
  b6cb633a
- wr_softpll_ng: expose g_with_debug_fifo bit through Wishbone · 630b5268
  Tomasz Wlostowski authored Sep 25, 2019
  
  630b5268
- kintex7-lp: stuck on losing-the-2nd-word issue, going back to 1.25 native tx path · 5c7c211f
  Tomasz Wlostowski authored Jun 26, 2019
  
  5c7c211f
- wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies,… · 5e088128
  Tomasz Wlostowski authored Jun 19, 2019
```
wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resets
```
  5e088128
- wrc_core: increase AUX address space to 32 kB in SDB descriptor · 1f3c0302
  Tomasz Wlostowski authored Jun 19, 2019
  
  1f3c0302
- dmtd_sampler: initialize clock divider flip-flop, added to Manifest · 618d4f6d
  Tomasz Wlostowski authored Jun 19, 2019
  
  618d4f6d
- wr_gtx_phy_kintex7_lp: wip · 41b25aba
  Tomasz Wlostowski authored Jun 14, 2019
  
  41b25aba
- wr_gtx_phy_kintex7_lp: gave up with RX oversampling... · 4b0e3748
  Tomasz Wlostowski authored Jun 13, 2019
  
  4b0e3748
- kintex7-lp: WIP on oversampled version, not sure if it will be needed with the QPLL · 5c6e5607
  Tomasz Wlostowski authored Jun 12, 2019
  
  5c6e5607
- kintex7_lp: hacking oversampled version of the transceiver · 18ba0078
  Tomasz Wlostowski authored Jun 06, 2019
  
  18ba0078
- wr_softpll_ng: Enabled internal frequency reference for oscillator diagnostics · 28502290
  Tomasz Wlostowski authored Feb 14, 2018
  
  28502290
- wr_gtx_phy_kintex7_lp: removed some unused signals · 33a90903
  Tomasz Wlostowski authored May 25, 2019
  
  33a90903
- wr_core: expose SoftPLL's g_use_sampled_ref_clocks generic & associated interface · fcc50b04
  Tomasz Wlostowski authored May 25, 2019
  
  fcc50b04
- wr_softpll_ng: added support for external DDMTD sampler · 5363943e
  Tomasz Wlostowski authored Jul 07, 2017
  
  5363943e
- platform: phase-stable GTXE2 wrapper (Kintex7), initial version · 4e9d0763
  Tomasz Wlostowski authored Mar 29, 2019
  
  4e9d0763
- platform: hacking the GTXE2 wrapper · 678491f4
  Tomasz Wlostowski authored Feb 26, 2019
  
  678491f4