- 17 Feb, 2017 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 16 Feb, 2017 4 commits
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 14 Feb, 2017 19 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
wrc.bram compiled from commit (wrpc-sw repo): 61dfdc2 wrpc sim: missing pl_cnt assignment
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
for details how it works now. Short description of changes - frames are generated in two places: LM32 and main.sv - frames from LM32 are looped back in main.sv - frames from main.sv go through WRPC and are looped back by wrf_loopback - frames generated by main.sv have randome size, Inter-frame gap is randome for one bunch of sent frames, and fixed low for stress in another bunch of sent frames. - frames from LM32 are sent as fast as possible, which is sloooow - frames from LM32 have codes to indicate to the simulation problems of reception of previous frame (no other easy way for information to pass from LM32 to main.sv - all frames have seqID which is verified in main.sv - warnings are thrown when * wrong seqID is detected by main.sv * when ERROR code is sent by LM32, can be on seqID mismatch, or rx function error NOTE: the software for LM32 is now compiled by proper make config in wrpc-sw (see wrpc-sw/config): wrpc_sim_defconfig
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Maciej Lipinski authored
the script NOTE: you need to run make before do run.do ...
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
- in the Endpoint of WRPC, the autonegotiation is enabled - in the Endpoint of simulation, the autonegotiation was disabled - This mismatch of configuration prevented stuff from working. Fixed by enabling autonegotiation in simulation
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Maciej Lipinski authored
- the connection of rx/tx to PHY was wrong, there was (very likely unintentional) a loop between tx and rx of PHY. - since there is the (intentional) loop between sink and source of wrpc, frames sent by WRPC SW (LM32) were looping endlessly.
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Maciej Lipinski authored
- align code - remove commented stuff - make some basic comments
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Grzegorz Daniluk authored
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Dimitris Lampridis authored
By default, the bit is zero (masked), which means that PPS signal output is masked when the link status is not ok. This is useful to pervent spurious PPS when in GM or SLAVE mode and the link goes down. When the bit is set, then a PPS is always generated (as long as the PPS valid bit in the ESCR register is set). This is useful in free-running master mode.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Grzegorz Daniluk authored
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- 26 Jan, 2017 4 commits
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Adam Wujek authored
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Compiled from wrpc-sw: 1c028e8e Merge branch 'minic_fifo' into proposed_master
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Grzegorz Daniluk authored
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- 25 Jan, 2017 4 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
This also removes Xilinx ISE synthesis warnings like: wr-cores\platform\xilinx\wr_gtp_phy\wr_gtp_phy_spartan6.vhd" Line 246: <bufio2> remains a black-box since it has no binding entity.
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- 24 Jan, 2017 5 commits
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Grzegorz Daniluk authored
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Adam Wujek authored
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 20 Jan, 2017 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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