White Rabbit core collection:054200a6d34ff4597ea7a18433cbabe037f3c101 commitshttps://ohwr.org/project/wr-cores/commits/054200a6d34ff4597ea7a18433cbabe037f3c1012021-04-19T09:14:15Zhttps://ohwr.org/project/wr-cores/commit/054200a6d34ff4597ea7a18433cbabe037f3c101wr_gthe4_phy_family7_xilinx_ip: enable LPM transceiver mode. See UG576 page 2072021-04-19T09:14:15ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/b0ba6baaa31e00beeb77e08dac547ff331a553d3wr_si57x_interface: fix the FSM so that it REALLY freezes the VCO control val...2021-01-26T16:44:00ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/1435aa3e881248e9c7fe068aac5fe2ffa2ec25fdwr_si57x_interface: add BUSY flag and full N1/HSDIV configuration to register...2021-01-26T16:44:00ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/fb25a444c3d06e01671ad2926a13582efb83ab77syn/pxie_fmc_ref_design: add missing README file2021-01-18T10:52:46ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/c63228b608b3f550d442051648b5e2b27cfe8925wr_core: hold LM32 reset active when the CPU doesn't have a preloaded firmware2021-01-18T10:44:59ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/bba3432e9fe65595d745d20a218e2bc60ed22a33platform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE32021-01-12T14:02:03ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/ebe554ecd0c9bb9314c91eaf79ba233e68b21a8aip_cores: update vme64x-core to latest master2021-01-06T09:34:08ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/38ed0cdffa95d6bc9e3e88348cae1e8561feb245bin/wrc_pxie.bram: update address space2020-12-15T07:21:33ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/dedbf24144915a9c5107027958516ea597ba0086wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address…2020-12-09T16:47:59ZTomasz Wlostowskitomasz.wlostowski@cern.chwr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)
https://ohwr.org/project/wr-cores/commit/28191b5ad27dbdf2593865e61a5d013a30d65a95update general-cores to fix vuart2020-10-02T07:43:49ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/514ce141c3afd006a5fd2a49bdba5327a147afcbspec,svec top: remove sdb and remap WRPC at 0x02020-09-29T12:14:46ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/c96b40476167026135462729ef7e2d0c26fb3561wrc_core: swap aux WB and diags in secondary crossbar2020-09-29T12:14:46ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/d1d1cc497419d396371f2da4ff1b8288101b216aplatform/xilinx: select appropriate platform based on the FPGA family, not sy...2020-09-16T12:16:17ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/f7aafcbdf6e6d341e0d21fd6fe0d7b56cbd46c3cCI: add pxie_ref_design vivado synthesis2020-09-16T09:24:21ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/53de0e6b911c80d8b809b5a2059882fa2f4a2957platform/xilinx: split platform for vivado to a separate file not to break ise…2020-09-16T09:22:07ZGrzegorz Danilukgrzegorz.daniluk@cern.chplatform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitives
https://ohwr.org/project/wr-cores/commit/a5fde2b1c66226c14ea41768b2b87fbaf9f8b499board/spec: fix async reset bug introduced in commit 10772352020-09-16T09:18:16ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/7a4a98759493a4143462e803a7045d53577d689dadding LM32 binary for PXIe FMC carrier with ZU72020-09-16T09:18:16ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/6394f6c6f6ca70a6b297c90fee8b480c177df91bboard/pxie-fmc: adding std_logic wrapper2020-09-16T09:18:16ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/f1a2fe276a048f37221f00b5315fd779c26bd97cadding BSP for PXIe-FMC board with Xilinx ZU72020-09-16T09:18:16ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/57c9e69e198053fc505c33b17d6776a4dbecfbeeplatform/xilinx: adding support for Zynq US+2020-09-16T09:18:16ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/e20b26ab884b93d948fb4b107733092054a03613platform/xilinx: global clk_sys signal declaration so that it's available bet...2020-09-16T09:18:16ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/1272b672403e84edbde36965847805c304814b76platform/xilinx: remove unnecesary files for Ultrascale family2020-09-16T07:00:34ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/0fbb5a2042669b26f25002d256efff7743d988bemodules/wrc_core: bring back link_ok_o functionality2020-09-15T13:23:53ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/a023a6bec237a49298e1f6e4d87ed326e8b1984bplatform/xilinx: Manifest indentation fix, no technical change2020-09-15T13:23:53ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/wr-cores/commit/c9cc5cab4a1b0868391d32726c017816f4749a62platform/xilinx: revert to Vivado-generated wrapper for GTHE32020-09-15T13:23:53ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/97ecba2bcd528a01d5ea19585e04a00c07fba522wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bit...2020-09-15T13:23:53ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/6d55fbc4ac11f78c2adda2be840502e96bdeece4wr_gthe3_phy_family7: possible fix for failing link up detection after discon...2020-09-15T13:23:53ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/900b6812e57ec35db81670fd2bfecc2a489d963dwr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force…2020-09-15T13:23:53ZTomasz Wlostowskitomasz.wlostowski@cern.chwr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force link down event in the PCS
https://ohwr.org/project/wr-cores/commit/f530428394876247bc2f5fcf0f92b74cfc3209a4wr_core: expose UART FIFO configuration to wr_core generics2020-09-15T13:23:53ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/561f5733529b83b81516424bf8dc96ac09694363wrc_core: expose PHY LPC interface2020-09-15T13:23:53ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/c5199f95abc6a3a03c8ff0d2db7f9586af135af0platform: pre-validated version of kintex-7 lpdc phy2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/b6cb633a6d5584d848781732fab0c41cb915b651wrc_core: increase LM32 code/data address space to 256 kB2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/630b52687c9898b64544cfbabbd2822f7d426860wr_softpll_ng: expose g_with_debug_fifo bit through Wishbone2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/5c7c211fb8c4c626aa1691883387f74b3a666b2bkintex7-lp: stuck on losing-the-2nd-word issue, going back to 1.25 native tx ...2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/5e0881282f4c0ba6d938e298edcf78e11039c376wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies,…2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chwr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resets
https://ohwr.org/project/wr-cores/commit/1f3c0302624726b6519c14deb6cda555d83b3800wrc_core: increase AUX address space to 32 kB in SDB descriptor2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/618d4f6d647aafc794c1eb2d71976eb4c8240cdedmtd_sampler: initialize clock divider flip-flop, added to Manifest2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/41b25aba917ec99a22706374456c67d49dbf7a43wr_gtx_phy_kintex7_lp: wip2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/4b0e3748648511d4d7dcc31b72417ebb17ad2eddwr_gtx_phy_kintex7_lp: gave up with RX oversampling...2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/wr-cores/commit/5c6e5607565ee3d759d3c4fc318ec58fe89b7a1bkintex7-lp: WIP on oversampled version, not sure if it will be needed with th...2020-09-15T13:23:53ZTomasz Włostowskitomasz.wlostowski@cern.ch