oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/
that include generic modules. This prevented the Altera-based
design from building. Ultimately, the module needs to be moved
to some more appropriate place, possibly to
general-cores/platform/xilinx. To be decided. A temporary solution
is to have it in board/cute, since it is only used by in the
xwrc_board_cute.

upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd

The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL
(CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a
BUFG (O) when using ENABLE_SYNC (FALSE)."

I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but
the 10MHz output is still missing. So I have to change the setting of
"cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from
CLKOUT2.

    change the function of LEDs:
      the front end LEDs display the status of link and sync.
      the on-board LEDS display the act of link and PPS.

syn: remove Makefiles, they are auto-generated and contain paths that are not exportable to other users (such as the location of the Xilinx ISE tools)

This allows to use the same top level vhd for different synthesis targets. Example, we can use the
spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.

Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a,
later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the
fiber.

The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking
into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk
side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source
for both clock domains of the rx path.

Tested on an SPEC, works.

added ISE project file (*xise) because synthesis of VXS require
special configuration, otherwise ISE returns internal error.
This special configuration is added XST command line option:
" -use_new_parser yes". It can be added by clicking the top
hierarhy file (vxs_wr_ref_top.vhd) in the "Design Manager", the
right-click on "Synthesis -XST" in "Processes" window, from
drop menu chose "Process Properties - Synthesis Options" and
then input " -use_new_parser yes" on "Other XST Command Line
Options"

updates kintex7 phy name to reflect new peter_xilinx_phys convention
add clbv3 reference design files
last commit also needs artix7 support in xwrc_platform_xilinx.vhd
added BullsEye connections
CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd
CLBv3: implementation files (including bmm)
CLBv3: Clean up

Conflicts:
	platform/xilinx/xwrc_platform_xilinx.vhd

added clbv2_ref_design files
added initial clbv2_ref_design ucf file
removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization
removed external wishbone busses (not used for clbv2_ref_design), free running clk_125m_pllref needed for reset synchronization, phy16
Merge branch 'peter_clbv2_ref_design' of ohwr.org:hdl-core-lib/wr-cores into peter_clbv2_ref_design
clk_20m_vcxo_i free running clock for reset gen. (thus no need for separate 125 MHz fpga input; remove clk_125m_pllref_p/n_i)
updates kintex7 phy name to reflect new peter_xilinx_phys convention
last commit also needs artix7 support in xwrc_platform_xilinx.vhd
CLBv2: reference clock is 62.5 MHz for 16 bit PHYs. Changed naming convention accordingly.
CLBv2: point proper bram file
CLBv2: implementation (including bmm)
CLBv2 reference design cleaned
CLBv2: updated (hdlmake made) Xilinx ISE project file

syn/vfchd: prevent quartus flow messages printed to stderr during core generation from stopping the synthesis process