added gc_async_counter_diff to general-cores, thus
updating the submodules

hdl: introduce "g_verbose" generic to control the printing of information messages during simulation.

This affects in particular the messages about loading of LM32 software, as well as the messages printed by the wishbone crossbar, listing all attached slaves.

If omitted, the default value is "TRUE", in order to maintain backward compatibility.

hdl: bump general-cores, vme64x-core and gn4124-core to latest version in preparation for updating the SPEC and SVEC reference designs

Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a,
later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the
fiber.

The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking
into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk
side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source
for both clock domains of the rx path.

Tested on an SPEC, works.

This reverts commit b3389d12.