1. 24 May, 2019 1 commit
    • Maciej Lipinski's avatar
      wr_streamers: fixed bug that caused flush_p1_i to be missed. · 03448da1
      Maciej Lipinski authored
      In case the data was received in clk_ref_i domain, the flush_p1_i
      was also received in the clk_ref_i domain. However, it was used
      in an FSM that works in the clk_sys_i domain. This could cause
      problems, for example missing the flash_p1_i pulses, thus frames
      not being sent when requested. It was easily seen in the
      spec_fixed_latency-demo testbench. In principle, the tx_flush_p1_i
      does not need to come with data, can be asynchronous to data.
      It should be a pulse, yet it can happen that it is constantly high
      (see Tom's testbench of fixed-latency mode). Thus in cross-domain
      use case :
      1. first the pulse is extended to to cycles
      2. thanks to this, the gc_sync_ffs module can be used to
         pass the signal to clk_sys clock domain, whether it is a
         pulse or not.
      03448da1
  2. 23 May, 2019 4 commits
  3. 22 May, 2019 5 commits
  4. 21 May, 2019 3 commits
  5. 20 May, 2019 1 commit
  6. 16 May, 2019 18 commits
  7. 14 May, 2019 6 commits
    • Tomasz Wlostowski's avatar
    • Maciej Lipinski's avatar
      board_common: provide g_clk_ref_rate to wr streamers based on g_pcs_16bit · ee41b569
      Maciej Lipinski authored
      Provide the rate of the WR Reference Clock based on the information
      about the width of the PCS word. It is assumed to be related:
      * 16bit word with 62.5MHz clock
      *  8bit word with  125MHz clock
      ee41b569
    • Maciej Lipinski's avatar
      wr_streamers: added g_clk_ref_rate to wr_streamers · 9a9fb3b6
      Maciej Lipinski authored
      WR Streamers need to be used with WR Reference clock of 62.5MHz,
      adding generic to specify what ref_clk is used (125MHz by default,
      or 62.5MHz)
      9a9fb3b6
    • Maciej Lipinski's avatar
      [modules/timing]:added generic to provide the ref_clk rate · 4c9a10cb
      Maciej Lipinski authored
      The generic g_ref_clk_rate was dummy, i.e. never used. The module
      pulse_stamper is used with input reference clock (and tm_cycles_i)
      of 125MHz and 62.5MHz clock, in the wr_streamers. Added possibility
      to define what clock is used (default 125MHz or 62.5MHz). In any
      case, the output timestamp is of cycle period of 8ns.
      4c9a10cb
    • Maciej Lipinski's avatar
      [wr_streamers_demo] Update of the testbench for steamers. · aa36aa47
      Maciej Lipinski authored
      This follows update of the top in: top/spec_1_1/wr_streamers_demo
      that is used by this testbench. After the updated of the top, few
      changes were needed in the simulation:
      - update of inputs/outputs in the main
      - addition of a (dummy) synthesis_description.vhd (this is generated
        when synthesising, yet needed for compilation in simulation. Since,
        the data in this file is not really important in simulation, no
        need for generation of the file, dummy version is OK
      - waveform updated
      aa36aa47
    • Maciej Lipinski's avatar
      [wr_streamers_demo] Updated the streamers demo to work Boards Support Package · 15403bb0
      Maciej Lipinski authored
      The streamers demo was using very old top. With the updated of resets,
      etc, it stopped working (at least the testbench did stop). So, I finally
      updated this top to work (in the testbench at least) with the new BSP.
      This required a major re-do of the top. I left from the old as much
      as I could. The new top is based on the spec_ref_design. This was
      tested only for simulation
      (testbech/wr_streamers/streamers-on-spec_trigger-distribution).
      A commit with updates to simulation follows.
      15403bb0
  8. 09 May, 2019 1 commit
  9. 30 Apr, 2019 1 commit