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White Rabbit core collection
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fe9d4661
Commit
fe9d4661
authored
Mar 04, 2020
by
Peter Jansweijer
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fix: txts_o and rxtx_o in clk_ref domain instead of clk_sy domain.
parent
4e39ff0f
Pipeline
#153
failed with stages
in 2 minutes and 1 second
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ep_timestamping_unit.vhd
modules/wr_endpoint/ep_timestamping_unit.vhd
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modules/wr_endpoint/ep_timestamping_unit.vhd
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fe9d4661
...
...
@@ -371,6 +371,18 @@ begin -- syn
npulse_o
=>
tx_ts_done
,
ppulse_o
=>
open
);
-- timestamping "txts_o" is same as "done" signal above, but in clk_ref domain
txts_gen
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
rst_n_ref_i
,
data_i
=>
tx_sync_delay
(
0
),
synced_o
=>
open
,
npulse_o
=>
txts_o
,
ppulse_o
=>
open
);
-- timestamping "done" signals sync chains (clk_rx -> clk_sys)
rx_done_gen
:
gc_sync_ffs
generic
map
(
...
...
@@ -383,8 +395,18 @@ begin -- syn
npulse_o
=>
rx_ts_done
,
ppulse_o
=>
open
);
txts_o
<=
tx_ts_done
;
-- 2013-Nov-28 peterj added for debugging/calibration
rxts_o
<=
rx_ts_done
;
-- 2013-Nov-28 peterj added for debugging/calibration
-- timestamping "rxts_o" is same as "done" signal above, but in clk_ref domain
rxts_gen
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
rst_n_ref_i
,
data_i
=>
rx_sync_delay
(
0
),
synced_o
=>
open
,
npulse_o
=>
rxts_o
,
ppulse_o
=>
open
);
p_output_rx_ts
:
process
(
clk_rx_i
)
begin
...
...
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