Commit f8e30f3a authored by Dimitris Lampridis's avatar Dimitris Lampridis

platform/altera: update Arria5 PHY with newer version, add default WR PLLs and…

platform/altera: update Arria5 PHY with newer version, add default WR PLLs and introduce Altera WR platform wrapper

- Use the built-in 8b10b encoding/decoding provided by the Altera arria5_phy megafunction. This removes the need for
  the custom encoders/decoders, most of the processes at the end of the top-level vhd file, as well as the need for
  the tx_clk_i port and the two generics.

- Repurpose drop_link_i to reset the two megafunctions (arria5_phy_reconf and arria5_phy).

- Removed the Altera clock controllers. The system works fine without them and they only add skew to the clocks.

- Add tx_clk_o port so that we can pass the tx clock to the phy_ref_clk_i of WR PTP core.

- Introduce 8- and 16-bit PCS variants

- Introduce default PLLs for WR:
  * 1x DMTD PLL:  20MHz clock input, 62.5MHz clock output
  * 1x SYS  PLL: 125MHz clock input, 125MHz, 62.5MHz clock outputs
  * 1x EXT  PLL:  10MHz clock input, 125MHz clock output

- Reset all blocks properly and make sure that phy_ready is syncrhonised to phy_rx_clk
parent 1eb93833
if target=="altera":
modules = {"local" : "altera"}
elif target=="xilinx":
modules = {"local" : "xilinx"}
\ No newline at end of file
modules = {"local" : "xilinx"}
......@@ -3,6 +3,7 @@ def __helper():
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
return dirs
files = [ "altera_pkg.vhd" ]
files = [ "wr_altera_pkg.vhd", "xwrc_platform_altera.vhd" ]
modules = {"local": __helper() }
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wr_altera_pkg is
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
port (
clk_reconf_i : in std_logic;
clk_pll_i : in std_logic;
clk_cru_i : in std_logic;
clk_free_i : in std_logic;
rst_i : in std_logic;
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component wr_arria5_phy is
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
port (
clk_reconf_i : in std_logic;
clk_phy_i : in std_logic;
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
end wr_altera_pkg;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.endpoint_pkg.all;
package wr_altera_pkg is
component xwrc_platform_altera is
generic (
g_fpga_family : string := "arria5";
g_with_external_clock_input : boolean := FALSE;
g_use_default_plls : boolean := TRUE;
g_pcs_16bit : boolean := FALSE);
port (
areset_n_i : in std_logic := '1';
clk_10m_ext_i : in std_logic := '0';
clk_20m_vcxo_i : in std_logic := '0';
clk_125m_pllref_i : in std_logic := '0';
clk_62m5_dmtd_i : in std_logic := '0';
clk_dmtd_locked_i : in std_logic := '1';
clk_62m5_sys_i : in std_logic := '0';
clk_sys_locked_i : in std_logic := '1';
clk_125m_ref_i : in std_logic := '0';
clk_125m_ext_i : in std_logic := '0';
clk_ext_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
sfp_tx_o : out std_logic;
sfp_rx_i : in std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_los_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
ext_ref_mul_o : out std_logic;
ext_ref_mul_locked_o : out std_logic;
ext_ref_mul_stopped_o : out std_logic;
ext_ref_rst_i : in std_logic := '0');
end component xwrc_platform_altera;
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
port (
clk_reconf_i : in std_logic;
clk_pll_i : in std_logic;
clk_cru_i : in std_logic;
clk_free_i : in std_logic;
rst_i : in std_logic;
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component wr_arria5_phy is
generic (
g_pcs_16bit : boolean := FALSE);
port (
clk_reconf_i : in std_logic;
clk_phy_i : in std_logic;
ready_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
tx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
rx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component arria5_phy_reconf is
port (
reconfig_busy : out std_logic;
mgmt_clk_clk : in std_logic := '0';
mgmt_rst_reset : in std_logic := '0';
reconfig_mgmt_address : in std_logic_vector(6 downto 0) := (others => '0');
reconfig_mgmt_read : in std_logic := '0';
reconfig_mgmt_readdata : out std_logic_vector(31 downto 0);
reconfig_mgmt_waitrequest : out std_logic;
reconfig_mgmt_write : in std_logic := '0';
reconfig_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
reconfig_to_xcvr : out std_logic_vector(139 downto 0);
reconfig_from_xcvr : in std_logic_vector(91 downto 0) := (others => '0'));
end component;
component arria5_phy8 is
port (
phy_mgmt_clk : in std_logic := '0';
phy_mgmt_clk_reset : in std_logic := '0';
phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0');
phy_mgmt_read : in std_logic := '0';
phy_mgmt_readdata : out std_logic_vector(31 downto 0);
phy_mgmt_waitrequest : out std_logic;
phy_mgmt_write : in std_logic := '0';
phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
tx_ready : out std_logic;
rx_ready : out std_logic;
pll_ref_clk : in std_logic_vector(0 downto 0) := (others => '0');
tx_serial_data : out std_logic_vector(0 downto 0);
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0) := (others => '0');
pll_locked : out std_logic_vector(0 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
rx_runningdisp : out std_logic_vector(0 downto 0);
rx_disperr : out std_logic_vector(0 downto 0);
rx_errdetect : out std_logic_vector(0 downto 0);
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
rx_clkout : out std_logic_vector(0 downto 0);
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => '0');
tx_datak : in std_logic_vector(0 downto 0) := (others => '0');
rx_parallel_data : out std_logic_vector(7 downto 0);
rx_datak : out std_logic_vector(0 downto 0);
reconfig_from_xcvr : out std_logic_vector(91 downto 0);
reconfig_to_xcvr : in std_logic_vector(139 downto 0) := (others => '0'));
end component;
component arria5_phy16 is
port (
phy_mgmt_clk : in std_logic := '0';
phy_mgmt_clk_reset : in std_logic := '0';
phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0');
phy_mgmt_read : in std_logic := '0';
phy_mgmt_readdata : out std_logic_vector(31 downto 0);
phy_mgmt_waitrequest : out std_logic;
phy_mgmt_write : in std_logic := '0';
phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
tx_ready : out std_logic;
rx_ready : out std_logic;
pll_ref_clk : in std_logic_vector(0 downto 0) := (others => '0');
tx_serial_data : out std_logic_vector(0 downto 0);
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0) := (others => '0');
pll_locked : out std_logic_vector(0 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
rx_runningdisp : out std_logic_vector(1 downto 0);
rx_disperr : out std_logic_vector(1 downto 0);
rx_errdetect : out std_logic_vector(1 downto 0);
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
rx_clkout : out std_logic_vector(0 downto 0);
tx_parallel_data : in std_logic_vector(15 downto 0) := (others => '0');
tx_datak : in std_logic_vector(1 downto 0) := (others => '0');
rx_parallel_data : out std_logic_vector(15 downto 0);
rx_datak : out std_logic_vector(1 downto 0);
reconfig_from_xcvr : out std_logic_vector(91 downto 0);
reconfig_to_xcvr : in std_logic_vector(139 downto 0) := (others => '0'));
end component;
component arria5_dmtd_pll_default is
port (
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
locked : out std_logic);
end component;
component arria5_sys_pll_default is
port (
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
outclk_1 : out std_logic;
locked : out std_logic);
end component;
component arria5_ext_ref_pll_default is
port (
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
locked : out std_logic);
end component arria5_ext_ref_pll_default;
end wr_altera_pkg;
# Quartus droppings
greybox_tmp/
# Arria5 PHY
arria5_phy/
arria5_phy_sim/
arria5_phy.bsf
arria5_phy.cmp
arria5_phy.ppf
arria5_phy.qip
arria5_phy.sip
arria5_phy.spd
arria5_phy.vhd
arria5_phy_sim.f
# Arria5 PHY reconfig
arria5_phy_reconf/
arria5_phy_reconf_sim/
arria5_phy_reconf.bsf
arria5_phy_reconf.cmp
arria5_phy_reconf.ppf
arria5_phy_reconf.qip
arria5_phy_reconf.sip
arria5_phy_reconf.spd
arria5_phy_reconf.vhd
arria5_phy_reconf_sim.f
*
!*.txt
!*.tcl
!Manifest.py
files = [
"wr_arria5_phy.vhd",
"wr_arria5_phy.qip",
]
"wr_arria5_phy.vhd",
]
-- megafunction wizard: %Deterministic Latency PHY v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="16.0" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="operation_mode" value="Duplex" />
-- Retrieval info: <generic name="lanes" value="1" />
-- Retrieval info: <generic name="gui_deser_factor" value="16" />
-- Retrieval info: <generic name="gui_pcs_pma_width" value="PARAM_DEFAULT" />
-- Retrieval info: <generic name="gui_pll_type" value="CMU" />
-- Retrieval info: <generic name="data_rate" value="1.25 Gbps" />
-- Retrieval info: <generic name="gui_base_data_rate" value="1228.8 Mbps" />
-- Retrieval info: <generic name="gui_pll_refclk_freq" value="62.5 MHz" />
-- Retrieval info: <generic name="en_cdrref_support" value="0" />
-- Retrieval info: <generic name="gui_pll_feedback_path" value="true" />
-- Retrieval info: <generic name="use_double_data_mode" value="DEPRECATED" />
-- Retrieval info: <generic name="word_aligner_mode" value="manual" />
-- Retrieval info: <generic name="gui_tx_bitslip_enable" value="true" />
-- Retrieval info: <generic name="gui_enable_run_length" value="false" />
-- Retrieval info: <generic name="run_length_violation_checking" value="40" />
-- Retrieval info: <generic name="gui_use_wa_status" value="false" />
-- Retrieval info: <generic name="gui_use_8b10b_status" value="true" />
-- Retrieval info: <generic name="gui_use_status" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_enable_pll_reconfig" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_refclk_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_main_pll_index" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_mgmt_clk_in_hz" value="250000000" />
-- Retrieval info: <generic name="gui_split_interfaces" value="0" />
-- Retrieval info: <generic name="gui_embedded_reset" value="1" />
-- Retrieval info: <generic name="channel_interface" value="0" />
-- Retrieval info: </instance>
-- megafunction wizard: %Deterministic Latency PHY v13.1%
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="13.1" >
-- megafunction wizard: %Deterministic Latency PHY v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="16.0" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="operation_mode" value="Duplex" />
-- Retrieval info: <generic name="lanes" value="1" />
-- Retrieval info: <generic name="gui_deser_factor" value="10" />
-- Retrieval info: <generic name="gui_deser_factor" value="8" />
-- Retrieval info: <generic name="gui_pcs_pma_width" value="PARAM_DEFAULT" />
-- Retrieval info: <generic name="gui_pll_type" value="CMU" />
-- Retrieval info: <generic name="data_rate" value="1.25 Gbps" />
......@@ -17,13 +18,13 @@
-- Retrieval info: <generic name="gui_enable_run_length" value="false" />
-- Retrieval info: <generic name="run_length_violation_checking" value="40" />
-- Retrieval info: <generic name="gui_use_wa_status" value="false" />
-- Retrieval info: <generic name="gui_use_8b10b_status" value="false" />
-- Retrieval info: <generic name="gui_use_8b10b_status" value="true" />
-- Retrieval info: <generic name="gui_use_status" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_enable_pll_reconfig" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_refclk_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_main_pll_index" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_refclk_freq" value="0 MHz" />
......@@ -48,6 +49,4 @@
-- Retrieval info: <generic name="gui_split_interfaces" value="0" />
-- Retrieval info: <generic name="gui_embedded_reset" value="1" />
-- Retrieval info: <generic name="channel_interface" value="0" />
-- Retrieval info: <generic name="AUTO_PHY_MGMT_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: <generic name="AUTO_PLL_REF_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
-- megafunction wizard: %Transceiver Reconfiguration Controller v13.1%
-- Retrieval info: <instance entity-name="alt_xcvr_reconfig" version="13.1" >
-- megafunction wizard: %Transceiver Reconfiguration Controller v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="alt_xcvr_reconfig" version="16.0" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="number_of_reconfig_interfaces" value="2" />
-- Retrieval info: <generic name="gui_split_sizes" value="" />
......@@ -14,5 +15,4 @@
-- Retrieval info: <generic name="enable_mif" value="0" />
-- Retrieval info: <generic name="gui_enable_pll" value="0" />
-- Retrieval info: <generic name="gui_cal_status_port" value="false" />
-- Retrieval info: <generic name="AUTO_MGMT_CLK_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_phy.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_phy_reconf.qip"]
qmegawiz { arria5_phy arria5_phy_reconf }
qmegawiz { arria5_phy8 arria5_phy16 arria5_phy_reconf }
-------------------------------------------------------------------------------
-- Title : Deterministic Altera PHY wrapper - Arria 5
-- Project : White Rabbit Switch
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_arria5_phy.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Authors : Wesley W. Terpstra
-- Dimitrios lampridis
-- Company : GSI, CERN
-- Created : 2013-05-14
-- Last update: 2013-05-14
-- Platform : FPGA-generic
-- Last update: 2017-02-01
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single channel wrapper for deterministic PHY
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 GSI / Wesley W. Terpstra
-- Copyright (c) 2016-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -33,11 +35,6 @@
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-12 1.0 terpstra Rewrote using deterministic mode
-- 2013-08-22 1.1 terpstra Now runs on arria5 hardware
-------------------------------------------------------------------------------
library ieee;
......@@ -45,145 +42,95 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.wr_altera_pkg.all;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
use work.altera_networks_pkg.all;
entity wr_arria5_phy is
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
g_pcs_16bit : boolean := FALSE);
port (
clk_reconf_i : in std_logic; -- 100 MHz
clk_phy_i : in std_logic; -- feeds transmitter CMU and CRU
locked_o : out std_logic; -- Is the rx_rbclk valid?
loopen_i : in std_logic; -- local loopback enable (Tx->Rx), active hi
drop_link_i : in std_logic; -- Kill the link?
tx_clk_i : in std_logic; -- clock used for TX data; MUST HAVE FIXED PHASE wrt. clk_phy_i
tx_data_i : in std_logic_vector(7 downto 0); -- data input (8 bits, not 8b10b-encoded)
tx_k_i : in std_logic; -- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_disparity_o : out std_logic; -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
tx_enc_err_o : out std_logic; -- error encoding
rx_rbclk_o : out std_logic; -- RX recovered clock
rx_data_o : out std_logic_vector(7 downto 0); -- 8b10b-decoded data output.
rx_k_o : out std_logic; -- 1 when the byte on rx_data_o is a control code
rx_enc_err_o : out std_logic; -- encoding error indication
rx_bitslide_o : out std_logic_vector(3 downto 0); -- RX bitslide indication, indicating the delay of the RX path of the transceiver (in UIs). Must be valid when rx_data_o is valid.
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
-- Clock for PHY reconfiguration core. Must be between 75MHz and 125MHz.
clk_reconf_i : in std_logic;
-- Clock for PHY. 125MHz when PCS is 8bit, 62.5MHz when PCS is 16bit.
clk_phy_i : in std_logic;
-- PLL locked, RX/TX ready, PHY reconfiguration complete
ready_o : out std_logic;
-- Enable local loopback (Tx->Rx)
loopen_i : in std_logic;
-- Drop the link
drop_link_i : in std_logic;
-- Copy of clock used for TX data
tx_clk_o : out std_logic;
-- Data to transmit (8/16 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
tx_disparity_o : out std_logic;
-- TX encoding error
tx_enc_err_o : out std_logic;
-- RX recovered clock
rx_rbclk_o : out std_logic;
-- Received data (8/16 bits, not 8b10b-encoded)
rx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
-- RX encoding error
rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when rx_data_o is valid.
rx_bitslide_o : out std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
-- Transceiver serial data I/O
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end wr_arria5_phy;
architecture rtl of wr_arria5_phy is
component arria5_phy_reconf
port(
reconfig_busy : out std_logic;
mgmt_clk_clk : in std_logic;
mgmt_rst_reset : in std_logic;
reconfig_mgmt_address : in std_logic_vector(6 downto 0);
reconfig_mgmt_read : in std_logic;
reconfig_mgmt_readdata : out std_logic_vector(31 downto 0);
reconfig_mgmt_waitrequest : out std_logic;
reconfig_mgmt_write : in std_logic;
reconfig_mgmt_writedata : in std_logic_vector(31 downto 0);
reconfig_to_xcvr : out std_logic_vector(139 downto 0);
reconfig_from_xcvr : in std_logic_vector(91 downto 0));
end component;
component arria5_phy
port(
phy_mgmt_clk : in std_logic;
phy_mgmt_clk_reset : in std_logic;
phy_mgmt_address : in std_logic_vector(8 downto 0);
phy_mgmt_read : in std_logic;
phy_mgmt_readdata : out std_logic_vector(31 downto 0);
phy_mgmt_waitrequest : out std_logic;
phy_mgmt_write : in std_logic;
phy_mgmt_writedata : in std_logic_vector(31 downto 0);
tx_ready : out std_logic;
rx_ready : out std_logic;
pll_ref_clk : in std_logic_vector(0 downto 0);
tx_serial_data : out std_logic_vector(0 downto 0);
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0);
pll_locked : out std_logic_vector(0 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0);
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
rx_clkout : out std_logic_vector(0 downto 0);
tx_parallel_data : in std_logic_vector(9 downto 0);
rx_parallel_data : out std_logic_vector(9 downto 0);
reconfig_from_xcvr : out std_logic_vector(91 downto 0);
reconfig_to_xcvr : in std_logic_vector(139 downto 0));
end component;
component dec_8b10b
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
in_10b_i : in std_logic_vector(9 downto 0);
ctrl_o : out std_logic;
code_err_o : out std_logic;
rdisp_err_o : out std_logic;
out_8b_o : out std_logic_vector(7 downto 0));
end component;
component enc_8b10b
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ctrl_i : in std_logic;
in_8b_i : in std_logic_vector(7 downto 0);
err_o : out std_logic;
dispar_o : out std_logic;
out_10b_o : out std_logic_vector(9 downto 0));
end component;
signal clk_rx_gxb : std_logic; -- external fabric
signal clk_rx : std_logic; -- regional clock
signal clk_tx_gxb : std_logic; -- external fabric
signal clk_tx : std_logic; -- regional clock
signal rx_rbclk : std_logic;
signal pll_locked : std_logic;
signal rx_ready : std_logic;
signal tx_ready : std_logic;
signal phy_ready : std_logic;
signal reconfig_busy : std_logic;
signal tx_8b10b_rstn : std_logic_vector(2 downto 0); -- tx domain
signal rx_8b10b_rstn : std_logic_vector(2 downto 0); -- rx domain
signal rx_disperr : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal rx_errdetect : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal rx_bitslide : std_logic_vector(4 downto 0);
signal xcvr_to_reconfig : std_logic_vector(91 downto 0);
signal reconfig_to_xcvr : std_logic_vector(139 downto 0);
signal rx_bitslipboundaryselectout : std_logic_vector (4 downto 0);
signal rx_gxb_dataout : std_logic_vector (9 downto 0); -- signal out of GXB
signal rx_reg_dataout : std_logic_vector (9 downto 0); -- regional clocked FPGA register (clk_rx)
signal tx_enc_datain : std_logic_vector (9 downto 0); -- registered encoder output (tx_clk_i)
signal tx_reg_datain : std_logic_vector (9 downto 0); -- transfer register from fabric (tx_clk_i)
signal tx_gxb_datain : std_logic_vector (9 downto 0); -- transfer register to GXB (clk_tx)
signal rst_reconf : std_logic;
signal rst_reconf_ext : std_logic;
begin
rx_rbclk_o <= clk_rx;
U_RxClkout : single_region
-- management reset sync and pulse extension
-- should be at least 2 mgmt_clk cycles according to Altera PHY docs
mgmt_rst_sync : gc_sync_ffs
port map (
inclk => clk_rx_gxb,
outclk => clk_rx);
U_TxClk : single_region
clk_i => clk_reconf_i,
rst_n_i => '1',
data_i => drop_link_i,
synced_o => rst_reconf);
mgmt_rst_extend_pulse : gc_extend_pulse
generic map (
g_width => 4)
port map (
inclk => clk_tx_gxb,
outclk => clk_tx);
clk_i => clk_reconf_i,
rst_n_i => '1',
pulse_i => rst_reconf,
extended_o => rst_reconf_ext);
-- Altera PHY calibration block
U_Reconf : arria5_phy_reconf
port map (
reconfig_busy => reconfig_busy,
mgmt_clk_clk => clk_reconf_i,
mgmt_rst_reset => '0',
mgmt_rst_reset => rst_reconf_ext,
reconfig_mgmt_address => (others => '0'),
reconfig_mgmt_read => '0',
reconfig_mgmt_readdata => open,
......@@ -193,104 +140,93 @@ begin
reconfig_to_xcvr => reconfig_to_xcvr,
reconfig_from_xcvr => xcvr_to_reconfig);
--- The serializer and byte aligner
U_The_PHY : arria5_phy
-- Altera PHY with 8bit PCS
gen_arria5_phy8 : if (g_pcs_16bit = FALSE) generate
U_The_PHY : arria5_phy8
port map (
phy_mgmt_clk => clk_reconf_i,
phy_mgmt_clk_reset => rst_reconf_ext,
phy_mgmt_address => "010000101", -- 0x085
phy_mgmt_read => '0',
phy_mgmt_readdata => open,
phy_mgmt_waitrequest => open,
phy_mgmt_write => '1',
phy_mgmt_writedata => (0 => '1', others => '0'),
tx_ready => tx_ready,
rx_ready => rx_ready,
pll_ref_clk(0) => clk_phy_i,
tx_serial_data(0) => pad_txp_o,
tx_bitslipboundaryselect => (others => '0'),
pll_locked(0) => pll_locked,
rx_serial_data(0) => pad_rxp_i,
rx_runningdisp => open,
rx_disperr => rx_disperr,
rx_errdetect => rx_errdetect,
rx_bitslipboundaryselectout => rx_bitslide,
tx_clkout(0) => tx_clk_o,
rx_clkout(0) => rx_rbclk,
tx_parallel_data => tx_data_i,
tx_datak => tx_k_i,
rx_parallel_data => rx_data_o,
rx_datak => rx_k_o,
reconfig_from_xcvr => xcvr_to_reconfig,
reconfig_to_xcvr => reconfig_to_xcvr);
rx_enc_err_o <= rx_disperr(0) or rx_errdetect(0);
end generate gen_arria5_phy8;
-- Altera PHY with 16bit PCS
gen_arria5_phy16 : if (g_pcs_16bit = TRUE) generate
U_The_PHY : arria5_phy16
port map (
phy_mgmt_clk => clk_reconf_i,
phy_mgmt_clk_reset => rst_reconf_ext,
phy_mgmt_address => "010000101", -- 0x085
phy_mgmt_read => '0',
phy_mgmt_readdata => open,
phy_mgmt_waitrequest => open,
phy_mgmt_write => '1',
phy_mgmt_writedata => (0 => '1', others => '0'),
tx_ready => tx_ready,
rx_ready => rx_ready,
pll_ref_clk(0) => clk_phy_i,
tx_serial_data(0) => pad_txp_o,
tx_bitslipboundaryselect => (others => '0'),
pll_locked(0) => pll_locked,
rx_serial_data(0) => pad_rxp_i,
rx_runningdisp => open,
rx_disperr => rx_disperr,
rx_errdetect => rx_errdetect,
rx_bitslipboundaryselectout => rx_bitslide,
tx_clkout(0) => tx_clk_o,
rx_clkout(0) => rx_rbclk,
tx_parallel_data => tx_data_i,
tx_datak => tx_k_i,
rx_parallel_data => rx_data_o,
rx_datak => rx_k_o,
reconfig_from_xcvr => xcvr_to_reconfig,
reconfig_to_xcvr => reconfig_to_xcvr);
rx_enc_err_o <= rx_disperr(0) or rx_errdetect(0) or
rx_disperr(1) or rx_errdetect(1);
end generate gen_arria5_phy16;
rx_rbclk_o <= rx_rbclk;
phy_ready <= pll_locked and tx_ready and rx_ready and not reconfig_busy;
-- synchronize ready to rx clock
cmp_gc_sync_ffs_phy_ready : gc_sync_ffs
port map (
phy_mgmt_clk => clk_reconf_i,
phy_mgmt_clk_reset => '0',
phy_mgmt_address => "010000101", -- 0x085
phy_mgmt_read => '0',
phy_mgmt_readdata => open,
phy_mgmt_waitrequest => open,
phy_mgmt_write => '1',
phy_mgmt_writedata => (0 => '1', others => '0'),
tx_ready => tx_ready,
rx_ready => rx_ready,
pll_ref_clk(0) => clk_phy_i,
tx_serial_data(0) => pad_txp_o,
tx_bitslipboundaryselect => (others => '0'),
pll_locked(0) => pll_locked,
rx_serial_data(0) => pad_rxp_i,
rx_bitslipboundaryselectout => rx_bitslipboundaryselectout,
tx_clkout(0) => clk_tx_gxb,
rx_clkout(0) => clk_rx_gxb,
tx_parallel_data => tx_gxb_datain,
rx_parallel_data => rx_gxb_dataout,
reconfig_from_xcvr => xcvr_to_reconfig,
reconfig_to_xcvr => reconfig_to_xcvr);
-- Encode the TX data
encoder : enc_8b10b
port map(
clk_i => tx_clk_i,
rst_n_i => tx_8b10b_rstn(0),
ctrl_i => tx_k_i,
in_8b_i => tx_data_i,
err_o => tx_enc_err_o,
dispar_o => tx_disparity_o,
out_10b_o => tx_enc_datain);
-- Decode the RX data
decoder : dec_8b10b
port map(
clk_i => clk_rx,
rst_n_i => rx_8b10b_rstn(0),
in_10b_i => rx_reg_dataout,
ctrl_o => rx_k_o,
code_err_o => rx_enc_err_o,
rdisp_err_o => open,
out_8b_o => rx_data_o);
locked_o <= pll_locked and tx_ready and not reconfig_busy;
-- Generate reset for 8b10b encoder
p_pll_reset : process(tx_clk_i) is
begin
if rising_edge(tx_clk_i) then
tx_8b10b_rstn <= (not drop_link_i and tx_ready) & tx_8b10b_rstn(tx_8b10b_rstn'left downto 1);
end if;
end process;
-- Generate reset for the 8b10b decoder and ep_sync_detect
-- should use global version of clk_rx
p_rx_reset : process(clk_rx) is
begin
if rising_edge(clk_rx) then
rx_8b10b_rstn <= (not drop_link_i and rx_ready) & rx_8b10b_rstn(rx_8b10b_rstn'left downto 1);
end if;
end process;
-- Cross clock domain from tx_clk_i to clk_tx
-- These clocks must be phase aligned
-- Registers tx_reg_datain and tx_gxb_datain must be logic locked
-- to the same ALM, preferrably directly beside the GXB.
p_tx_path0 : process(tx_clk_i) is
begin
if tx_clk_i'event and tx_clk_i = (not g_tx_latch_edge) then
tx_reg_datain <= tx_enc_datain;
end if;
end process;
p_tx_path1 : process(clk_tx) is
begin
if clk_tx'event and clk_tx = g_tx_latch_edge then
tx_gxb_datain <= tx_reg_datain;
end if;
end process;
-- Additional register to improve timings
p_rx_path : process(clk_rx) is
begin
if clk_rx'event and clk_rx = g_rx_latch_edge then
rx_reg_dataout <= rx_gxb_dataout;
end if;
end process;
-- Slow registered signals out of the GXB
p_rx_regs : process(clk_rx) is
begin
if rising_edge(clk_rx) then
rx_bitslide_o <= rx_bitslipboundaryselectout(3 downto 0);
end if;
end process;
clk_i => rx_rbclk,
rst_n_i => '1',
data_i => phy_ready,
synced_o => ready_o);
rx_bitslide_o <= rx_bitslide(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
-- [TODO] DL: not sure how to get these yet
tx_disparity_o <= '0';
tx_enc_err_o <= '0';
end rtl;
-- megafunction wizard: %Altera PLL v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_pll" version="16.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="device" value="5AGTFC7H3F35I3" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="20.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="62.5" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- megafunction wizard: %Altera PLL v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_pll" version="16.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="device" value="5AGTFC7H3F35I3" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="10.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="125.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- megafunction wizard: %Altera PLL v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_pll" version="16.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="device" value="5AGTFC7H3F35I3" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="125.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="2" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="62.5" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="125.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
qmegawiz { arria5_dmtd_pll_default arria5_ext_ref_pll_default arria5_sys_pll_default }
-------------------------------------------------------------------------------
-- Title : Altera-specific components required by WR PTP Core
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_platform_altera.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-11-21
-- Last update: 2017-02-16
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This module instantiates platform-specific modules that are
-- needed by the WR PTP Core (WRPC) to interface hardware on Altera FPGA.
-- In particular it contains the Altera transceiver PHY and PLLs.
-------------------------------------------------------------------------------
-- Copyright (c) 2016-2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.endpoint_pkg.all;
use work.gencores_pkg.all;
use work.wr_altera_pkg.all;
entity xwrc_platform_altera is
generic
(
-- Define the family/model of Altera FPGA
-- (supported: for now only arria5)
g_fpga_family : string := "arria5";
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := FALSE;
-- Set to FALSE if you want to instantiate your own PLLs
g_use_default_plls : boolean := TRUE;
-- Set to TRUE to use 16bit PCS (currently unsupported)
g_pcs_16bit : boolean := FALSE
);
port (
---------------------------------------------------------------------------
-- Asynchronous reset (active low)
---------------------------------------------------------------------------
areset_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
---------------------------------------------------------------------------
clk_10m_ext_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Clock inputs for default PLLs (g_use_default_plls = TRUE)
---------------------------------------------------------------------------
-- 20MHz VCXO clock
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz PLL reference
clk_125m_pllref_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
---------------------------------------------------------------------------
-- 62.5MHz DMTD offset clock and lock status
clk_62m5_dmtd_i : in std_logic := '0';
clk_dmtd_locked_i : in std_logic := '1';
-- 62.5MHz Main system clock and lock status
clk_62m5_sys_i : in std_logic := '0';
clk_sys_locked_i : in std_logic := '1';
-- 125MHz Reference clock
clk_125m_ref_i : in std_logic := '0';
-- 125MHz derived from 10MHz external reference and lock status
-- (when g_with_external_clock_input = TRUE)
clk_125m_ext_i : in std_logic := '0';
clk_ext_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
---------------------------------------------------------------------------
-- SFP
---------------------------------------------------------------------------
sfp_tx_o : out std_logic;
sfp_rx_i : in std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_los_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
---------------------------------------------------------------------------
--Interface to WR PTP Core (WRPC)
---------------------------------------------------------------------------
-- PLL outputs
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
-- PHY
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
-- External reference
ext_ref_mul_o : out std_logic;
ext_ref_mul_locked_o : out std_logic;
ext_ref_mul_stopped_o : out std_logic;
ext_ref_rst_i : in std_logic := '0'
);
end entity xwrc_platform_altera;
architecture rtl of xwrc_platform_altera is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- PLLs
signal phy_clk : std_logic;
signal clk_pll_sys : std_logic;
signal clk_pll_ref : std_logic;
signal pll_arst : std_logic;
-- PHY
signal phy_ready : std_logic;
signal phy_loopen : std_logic;
signal phy_rst : std_logic;
signal phy_tx_clk : std_logic;
signal phy_tx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_rbclk : std_logic;
signal phy_rx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Check for unsupported features and/or misconfiguration
-----------------------------------------------------------------------------
gen_unknown_fpga : if (g_fpga_family /= "arria5") generate
assert FALSE
report "Altera FPGA family [" & g_fpga_family & "] is not supported"
severity ERROR;
end generate gen_unknown_fpga;
gen_unsupported_pcs : if (g_pcs_16bit = TRUE) generate
assert FALSE
report "16bit PCS not yet supported"
severity ERROR;
end generate gen_unsupported_pcs;
-----------------------------------------------------------------------------
-- Clock PLLs
-----------------------------------------------------------------------------
-- active high async reset for PLLs
pll_arst <= not areset_n_i;
gen_default_plls : if (g_use_default_plls = TRUE) generate
-- Default PLL setup consists of two PLLs.
-- One takes a 125MHz clock signal as input and produces:
-- a) 62.5MHz WR PTP core main system clock
-- b) 125MHz WR PTP core reference clock
-- The other PLL takes a 20MHz clock signal as input and produces
-- the 62.5MHz DMTD clock.
--
-- A third PLL is instantiated if also g_with_external_clock_input = TRUE.
-- In that case, a 10MHz external reference is multiplied to generate a
-- 125MHz reference clock
gen_arria5_default_plls : if (g_fpga_family = "arria5") generate
signal pll_sys_locked : std_logic;
signal pll_dmtd_locked : std_logic;
begin --gen_arria5_default_plls
cmp_sys_clk_pll : arria5_sys_pll_default
port map (
refclk => clk_125m_pllref_i,
rst => pll_arst,
outclk_0 => clk_pll_sys,
outclk_1 => clk_pll_ref,
locked => pll_sys_locked);
cmp_dmtd_clk_pll : arria5_dmtd_pll_default
port map (
refclk => clk_20m_vcxo_i,
rst => pll_arst,
outclk_0 => clk_62m5_dmtd_o,
locked => pll_dmtd_locked);
clk_62m5_sys_o <= clk_pll_sys;
clk_125m_ref_o <= clk_pll_ref;
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
gen_arria5_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
signal pll_ext_rst : std_logic;
begin --gen_arria5_ext_ref_pll
cmp_ext_ref_pll : arria5_ext_ref_pll_default
port map (
refclk => clk_10m_ext_i,
rst => pll_ext_rst,
outclk_0 => ext_ref_mul_o,
locked => ext_ref_mul_locked_o);
cmp_extend_ext_reset : gc_extend_pulse
generic map (
g_width => 1000)
port map (
clk_i => clk_pll_sys,
rst_n_i => pll_sys_locked,
pulse_i => ext_ref_rst_i,
extended_o => pll_ext_rst);
end generate gen_arria5_ext_ref_pll;
-- not provided by Altera PLL
ext_ref_mul_stopped_o <= '0';
end generate gen_arria5_default_plls;
end generate gen_default_plls;
-- If external PLLs are used, just copy clock inputs to outputs
gen_custom_plls : if (g_use_default_plls = FALSE) generate
clk_62m5_sys_o <= clk_62m5_sys_i;
clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
clk_125m_ref_o <= clk_125m_ref_i;
clk_pll_sys <= clk_62m5_sys_i;
clk_pll_ref <= clk_125m_ref_i;
pll_locked_o <= clk_sys_locked_i and clk_dmtd_locked_i;
ext_ref_mul_o <= clk_125m_ext_i;
ext_ref_mul_locked_o <= clk_ext_locked_i;
ext_ref_mul_stopped_o <= clk_ext_stopped_i;
end generate gen_custom_plls;
-- always pass ext reference reset input to output, even when not used
clk_ext_rst_o <= ext_ref_rst_i;
-----------------------------------------------------------------------------
-- Transceiver PHY
-----------------------------------------------------------------------------
gen_arria5_phy : if (g_fpga_family = "arria5") generate
cmp_phy : wr_arria5_phy
generic map (
g_pcs_16bit => g_pcs_16bit)
port map (
clk_reconf_i => clk_pll_ref,
clk_phy_i => phy_clk,
ready_o => phy_ready,
loopen_i => phy_loopen,
drop_link_i => phy_rst,
tx_clk_o => phy_tx_clk,
tx_data_i => phy_tx_data,
tx_k_i => phy_tx_k,
tx_disparity_o => phy_tx_disparity,
tx_enc_err_o => phy_tx_enc_err,
rx_rbclk_o => phy_rx_rbclk,
rx_data_o => phy_rx_data,
rx_k_o => phy_rx_k,
rx_enc_err_o => phy_rx_enc_err,
rx_bitslide_o => phy_rx_bitslide,
pad_txp_o => sfp_tx_o,
pad_rxp_i => sfp_rx_i);
end generate gen_arria5_phy;
gen_pcs_8bit : if (g_pcs_16bit = FALSE) generate
phy_clk <= clk_pll_ref;
phy_loopen <= phy8_i.loopen;
phy_rst <= phy8_i.rst;
phy_tx_data <= phy8_i.tx_data;
phy_tx_k <= phy8_i.tx_k;
sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
phy8_o.ref_clk <= phy_tx_clk;
phy8_o.tx_disparity <= phy_tx_disparity;
phy8_o.tx_enc_err <= phy_tx_enc_err;
phy8_o.rx_clk <= phy_rx_rbclk;
phy8_o.rx_data <= phy_rx_data;
phy8_o.rx_k <= phy_rx_k;
phy8_o.rx_enc_err <= phy_rx_enc_err;
phy8_o.rx_bitslide <= phy_rx_bitslide;
phy8_o.rdy <= phy_ready;
phy8_o.sfp_tx_fault <= sfp_tx_fault_i;
phy8_o.sfp_los <= sfp_los_i;
phy16_o <= c_dummy_phy16_to_wrc;
end generate gen_pcs_8bit;
gen_pcs_16bit : if (g_pcs_16bit = TRUE) generate
phy_clk <= clk_pll_sys;
phy_loopen <= phy16_i.loopen;
phy_rst <= phy16_i.rst;
phy_tx_data <= phy16_i.tx_data;
phy_tx_k <= phy16_i.tx_k;
sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
phy16_o.ref_clk <= phy_tx_clk;
phy16_o.tx_disparity <= phy_tx_disparity;
phy16_o.tx_enc_err <= phy_tx_enc_err;
phy16_o.rx_clk <= phy_rx_rbclk;
phy16_o.rx_data <= phy_rx_data;
phy16_o.rx_k <= phy_rx_k;
phy16_o.rx_enc_err <= phy_rx_enc_err;
phy16_o.rx_bitslide <= phy_rx_bitslide;
phy16_o.rdy <= phy_ready;
phy16_o.sfp_tx_fault <= sfp_tx_fault_i;
phy16_o.sfp_los <= sfp_los_i;
phy8_o <= c_dummy_phy8_to_wrc;
end generate gen_pcs_16bit;
end architecture rtl;
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