Commit f8e30f3a authored by Dimitris Lampridis's avatar Dimitris Lampridis

platform/altera: update Arria5 PHY with newer version, add default WR PLLs and…

platform/altera: update Arria5 PHY with newer version, add default WR PLLs and introduce Altera WR platform wrapper

- Use the built-in 8b10b encoding/decoding provided by the Altera arria5_phy megafunction. This removes the need for
  the custom encoders/decoders, most of the processes at the end of the top-level vhd file, as well as the need for
  the tx_clk_i port and the two generics.

- Repurpose drop_link_i to reset the two megafunctions (arria5_phy_reconf and arria5_phy).

- Removed the Altera clock controllers. The system works fine without them and they only add skew to the clocks.

- Add tx_clk_o port so that we can pass the tx clock to the phy_ref_clk_i of WR PTP core.

- Introduce 8- and 16-bit PCS variants

- Introduce default PLLs for WR:
  * 1x DMTD PLL:  20MHz clock input, 62.5MHz clock output
  * 1x SYS  PLL: 125MHz clock input, 125MHz, 62.5MHz clock outputs
  * 1x EXT  PLL:  10MHz clock input, 125MHz clock output

- Reset all blocks properly and make sure that phy_ready is syncrhonised to phy_rx_clk
parent 1eb93833
if target=="altera":
modules = {"local" : "altera"}
elif target=="xilinx":
modules = {"local" : "xilinx"}
\ No newline at end of file
modules = {"local" : "xilinx"}
......@@ -3,6 +3,7 @@ def __helper():
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
return dirs
files = [ "altera_pkg.vhd" ]
files = [ "wr_altera_pkg.vhd", "xwrc_platform_altera.vhd" ]
modules = {"local": __helper() }
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wr_altera_pkg is
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
port (
clk_reconf_i : in std_logic;
clk_pll_i : in std_logic;
clk_cru_i : in std_logic;
clk_free_i : in std_logic;
rst_i : in std_logic;
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component wr_arria5_phy is
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
port (
clk_reconf_i : in std_logic;
clk_phy_i : in std_logic;
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
end wr_altera_pkg;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.endpoint_pkg.all;
package wr_altera_pkg is
component xwrc_platform_altera is
generic (
g_fpga_family : string := "arria5";
g_with_external_clock_input : boolean := FALSE;
g_use_default_plls : boolean := TRUE;
g_pcs_16bit : boolean := FALSE);
port (
areset_n_i : in std_logic := '1';
clk_10m_ext_i : in std_logic := '0';
clk_20m_vcxo_i : in std_logic := '0';
clk_125m_pllref_i : in std_logic := '0';
clk_62m5_dmtd_i : in std_logic := '0';
clk_dmtd_locked_i : in std_logic := '1';
clk_62m5_sys_i : in std_logic := '0';
clk_sys_locked_i : in std_logic := '1';
clk_125m_ref_i : in std_logic := '0';
clk_125m_ext_i : in std_logic := '0';
clk_ext_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
sfp_tx_o : out std_logic;
sfp_rx_i : in std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_los_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
phy8_o : out t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
phy16_o : out t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
ext_ref_mul_o : out std_logic;
ext_ref_mul_locked_o : out std_logic;
ext_ref_mul_stopped_o : out std_logic;
ext_ref_rst_i : in std_logic := '0');
end component xwrc_platform_altera;
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
g_rx_latch_edge : std_logic := '0');
port (
clk_reconf_i : in std_logic;
clk_pll_i : in std_logic;
clk_cru_i : in std_logic;
clk_free_i : in std_logic;
rst_i : in std_logic;
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component wr_arria5_phy is
generic (
g_pcs_16bit : boolean := FALSE);
port (
clk_reconf_i : in std_logic;
clk_phy_i : in std_logic;
ready_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
tx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
rx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
component arria5_phy_reconf is
port (
reconfig_busy : out std_logic;
mgmt_clk_clk : in std_logic := '0';
mgmt_rst_reset : in std_logic := '0';
reconfig_mgmt_address : in std_logic_vector(6 downto 0) := (others => '0');
reconfig_mgmt_read : in std_logic := '0';
reconfig_mgmt_readdata : out std_logic_vector(31 downto 0);
reconfig_mgmt_waitrequest : out std_logic;
reconfig_mgmt_write : in std_logic := '0';
reconfig_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
reconfig_to_xcvr : out std_logic_vector(139 downto 0);
reconfig_from_xcvr : in std_logic_vector(91 downto 0) := (others => '0'));
end component;
component arria5_phy8 is
port (
phy_mgmt_clk : in std_logic := '0';
phy_mgmt_clk_reset : in std_logic := '0';
phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0');
phy_mgmt_read : in std_logic := '0';
phy_mgmt_readdata : out std_logic_vector(31 downto 0);
phy_mgmt_waitrequest : out std_logic;
phy_mgmt_write : in std_logic := '0';
phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
tx_ready : out std_logic;
rx_ready : out std_logic;
pll_ref_clk : in std_logic_vector(0 downto 0) := (others => '0');
tx_serial_data : out std_logic_vector(0 downto 0);
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0) := (others => '0');
pll_locked : out std_logic_vector(0 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
rx_runningdisp : out std_logic_vector(0 downto 0);
rx_disperr : out std_logic_vector(0 downto 0);
rx_errdetect : out std_logic_vector(0 downto 0);
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
rx_clkout : out std_logic_vector(0 downto 0);
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => '0');
tx_datak : in std_logic_vector(0 downto 0) := (others => '0');
rx_parallel_data : out std_logic_vector(7 downto 0);
rx_datak : out std_logic_vector(0 downto 0);
reconfig_from_xcvr : out std_logic_vector(91 downto 0);
reconfig_to_xcvr : in std_logic_vector(139 downto 0) := (others => '0'));
end component;
component arria5_phy16 is
port (
phy_mgmt_clk : in std_logic := '0';
phy_mgmt_clk_reset : in std_logic := '0';
phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0');
phy_mgmt_read : in std_logic := '0';
phy_mgmt_readdata : out std_logic_vector(31 downto 0);
phy_mgmt_waitrequest : out std_logic;
phy_mgmt_write : in std_logic := '0';
phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
tx_ready : out std_logic;
rx_ready : out std_logic;
pll_ref_clk : in std_logic_vector(0 downto 0) := (others => '0');
tx_serial_data : out std_logic_vector(0 downto 0);
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0) := (others => '0');
pll_locked : out std_logic_vector(0 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
rx_runningdisp : out std_logic_vector(1 downto 0);
rx_disperr : out std_logic_vector(1 downto 0);
rx_errdetect : out std_logic_vector(1 downto 0);
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
rx_clkout : out std_logic_vector(0 downto 0);
tx_parallel_data : in std_logic_vector(15 downto 0) := (others => '0');
tx_datak : in std_logic_vector(1 downto 0) := (others => '0');
rx_parallel_data : out std_logic_vector(15 downto 0);
rx_datak : out std_logic_vector(1 downto 0);
reconfig_from_xcvr : out std_logic_vector(91 downto 0);
reconfig_to_xcvr : in std_logic_vector(139 downto 0) := (others => '0'));
end component;
component arria5_dmtd_pll_default is
port (
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
locked : out std_logic);
end component;
component arria5_sys_pll_default is
port (
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
outclk_1 : out std_logic;
locked : out std_logic);
end component;
component arria5_ext_ref_pll_default is
port (
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
locked : out std_logic);
end component arria5_ext_ref_pll_default;
end wr_altera_pkg;
# Quartus droppings
greybox_tmp/
# Arria5 PHY
arria5_phy/
arria5_phy_sim/
arria5_phy.bsf
arria5_phy.cmp
arria5_phy.ppf
arria5_phy.qip
arria5_phy.sip
arria5_phy.spd
arria5_phy.vhd
arria5_phy_sim.f
# Arria5 PHY reconfig
arria5_phy_reconf/
arria5_phy_reconf_sim/
arria5_phy_reconf.bsf
arria5_phy_reconf.cmp
arria5_phy_reconf.ppf
arria5_phy_reconf.qip
arria5_phy_reconf.sip
arria5_phy_reconf.spd
arria5_phy_reconf.vhd
arria5_phy_reconf_sim.f
*
!*.txt
!*.tcl
!Manifest.py
files = [
"wr_arria5_phy.vhd",
"wr_arria5_phy.qip",
]
"wr_arria5_phy.vhd",
]
-- megafunction wizard: %Deterministic Latency PHY v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="16.0" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="operation_mode" value="Duplex" />
-- Retrieval info: <generic name="lanes" value="1" />
-- Retrieval info: <generic name="gui_deser_factor" value="16" />
-- Retrieval info: <generic name="gui_pcs_pma_width" value="PARAM_DEFAULT" />
-- Retrieval info: <generic name="gui_pll_type" value="CMU" />
-- Retrieval info: <generic name="data_rate" value="1.25 Gbps" />
-- Retrieval info: <generic name="gui_base_data_rate" value="1228.8 Mbps" />
-- Retrieval info: <generic name="gui_pll_refclk_freq" value="62.5 MHz" />
-- Retrieval info: <generic name="en_cdrref_support" value="0" />
-- Retrieval info: <generic name="gui_pll_feedback_path" value="true" />
-- Retrieval info: <generic name="use_double_data_mode" value="DEPRECATED" />
-- Retrieval info: <generic name="word_aligner_mode" value="manual" />
-- Retrieval info: <generic name="gui_tx_bitslip_enable" value="true" />
-- Retrieval info: <generic name="gui_enable_run_length" value="false" />
-- Retrieval info: <generic name="run_length_violation_checking" value="40" />
-- Retrieval info: <generic name="gui_use_wa_status" value="false" />
-- Retrieval info: <generic name="gui_use_8b10b_status" value="true" />
-- Retrieval info: <generic name="gui_use_status" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_enable_pll_reconfig" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_refclk_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_main_pll_index" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll1_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll2_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_refclk_freq" value="0 MHz" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll3_clk_network" value="x1" />
-- Retrieval info: <generic name="gui_mgmt_clk_in_hz" value="250000000" />
-- Retrieval info: <generic name="gui_split_interfaces" value="0" />
-- Retrieval info: <generic name="gui_embedded_reset" value="1" />
-- Retrieval info: <generic name="channel_interface" value="0" />
-- Retrieval info: </instance>
-- megafunction wizard: %Deterministic Latency PHY v13.1%
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="13.1" >
-- megafunction wizard: %Deterministic Latency PHY v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="16.0" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="operation_mode" value="Duplex" />
-- Retrieval info: <generic name="lanes" value="1" />
-- Retrieval info: <generic name="gui_deser_factor" value="10" />
-- Retrieval info: <generic name="gui_deser_factor" value="8" />
-- Retrieval info: <generic name="gui_pcs_pma_width" value="PARAM_DEFAULT" />
-- Retrieval info: <generic name="gui_pll_type" value="CMU" />
-- Retrieval info: <generic name="data_rate" value="1.25 Gbps" />
......@@ -17,13 +18,13 @@
-- Retrieval info: <generic name="gui_enable_run_length" value="false" />
-- Retrieval info: <generic name="run_length_violation_checking" value="40" />
-- Retrieval info: <generic name="gui_use_wa_status" value="false" />
-- Retrieval info: <generic name="gui_use_8b10b_status" value="false" />
-- Retrieval info: <generic name="gui_use_8b10b_status" value="true" />
-- Retrieval info: <generic name="gui_use_status" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_enable_pll_reconfig" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_refclk_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_main_pll_index" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_pll_type" value="CMU" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_data_rate" value="0 Mbps" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_refclk_freq" value="0 MHz" />
......@@ -48,6 +49,4 @@
-- Retrieval info: <generic name="gui_split_interfaces" value="0" />
-- Retrieval info: <generic name="gui_embedded_reset" value="1" />
-- Retrieval info: <generic name="channel_interface" value="0" />
-- Retrieval info: <generic name="AUTO_PHY_MGMT_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: <generic name="AUTO_PLL_REF_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
-- megafunction wizard: %Transceiver Reconfiguration Controller v13.1%
-- Retrieval info: <instance entity-name="alt_xcvr_reconfig" version="13.1" >
-- megafunction wizard: %Transceiver Reconfiguration Controller v16.0%
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <instance entity-name="alt_xcvr_reconfig" version="16.0" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="number_of_reconfig_interfaces" value="2" />
-- Retrieval info: <generic name="gui_split_sizes" value="" />
......@@ -14,5 +15,4 @@
-- Retrieval info: <generic name="enable_mif" value="0" />
-- Retrieval info: <generic name="gui_enable_pll" value="0" />
-- Retrieval info: <generic name="gui_cal_status_port" value="false" />
-- Retrieval info: <generic name="AUTO_MGMT_CLK_CLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_phy.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_phy_reconf.qip"]
qmegawiz { arria5_phy arria5_phy_reconf }
qmegawiz { arria5_phy8 arria5_phy16 arria5_phy_reconf }
qmegawiz { arria5_dmtd_pll_default arria5_ext_ref_pll_default arria5_sys_pll_default }
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