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f73f8239
Commit
f73f8239
authored
Sep 13, 2018
by
Grzegorz Daniluk
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pps_gen: add bit to control WRS 1-PPS in termination - required for WRS
parent
b54d81db
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6 changed files
with
54 additions
and
13 deletions
+54
-13
pps_gen_regs.h
modules/wr_pps_gen/pps_gen_regs.h
+10
-6
pps_gen_wb.vhd
modules/wr_pps_gen/pps_gen_wb.vhd
+21
-4
pps_gen_wb.wb
modules/wr_pps_gen/pps_gen_wb.wb
+12
-0
wr_pps_gen.vhd
modules/wr_pps_gen/wr_pps_gen.vhd
+6
-3
xwr_pps_gen.vhd
modules/wr_pps_gen/xwr_pps_gen.vhd
+3
-0
pps_gen_regs.v
sim/pps_gen_regs.v
+2
-0
No files found.
modules/wr_pps_gen/pps_gen_regs.h
View file @
f73f8239
...
...
@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Wed
Aug 16 22:41:09 2017
* Created : Wed
Jun 5 16:28:58 2019
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
...
...
@@ -14,11 +14,7 @@
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
...
...
@@ -28,7 +24,7 @@
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_MASK(offset, size) (((1
ULL
<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
...
...
@@ -87,6 +83,9 @@
/* definitions for field: Set nanoseconds counter in reg: External sync control register */
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Enable PPS_IN 50Ohm termination in reg: External sync control register */
#define PPSG_ESCR_PPS_IN_TERM WBGEN2_GEN_MASK(6, 1)
PACKED
struct
PPSG_WB
{
/* [0x0]: REG Control Register */
uint32_t
CR
;
...
...
@@ -106,4 +105,9 @@ PACKED struct PPSG_WB {
uint32_t
ESCR
;
};
#define PPSG_PERIPH_PREFIX "ppsg"
#define PPSG_PERIPH_NAME "WR Switch PPS generator and RTC"
#define PPSG_PERIPH_DESC WBGEN2_DESC("Unit generating PPS signals and acting as a UTC real-time clock")
#endif
modules/wr_pps_gen/pps_gen_wb.vhd
View file @
f73f8239
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created : Wed
Aug 16 22:41:09 2017
-- Created : Wed
Jun 5 16:28:58 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
...
...
@@ -68,7 +68,9 @@ entity pps_gen_wb is
-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
ppsg_escr_sec_set_o
:
out
std_logic
;
-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
ppsg_escr_nsec_set_o
:
out
std_logic
ppsg_escr_nsec_set_o
:
out
std_logic
;
-- Port for BIT field: 'Enable PPS_IN 50Ohm termination' in reg: 'External sync control register'
ppsg_escr_pps_in_term_o
:
out
std_logic
);
end
pps_gen_wb
;
...
...
@@ -151,15 +153,26 @@ signal ppsg_escr_nsec_set_int_delay : std_logic ;
signal
ppsg_escr_nsec_set_sync0
:
std_logic
;
signal
ppsg_escr_nsec_set_sync1
:
std_logic
;
signal
ppsg_escr_nsec_set_sync2
:
std_logic
;
signal
ppsg_escr_pps_in_term_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
...
...
@@ -205,6 +218,7 @@ begin
ppsg_escr_sec_set_int_delay
<=
'0'
;
ppsg_escr_nsec_set_int
<=
'0'
;
ppsg_escr_nsec_set_int_delay
<=
'0'
;
ppsg_escr_pps_in_term_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -478,6 +492,7 @@ begin
ppsg_escr_sec_set_int_delay
<=
wrdata_reg
(
4
);
ppsg_escr_nsec_set_int
<=
wrdata_reg
(
5
);
ppsg_escr_nsec_set_int_delay
<=
wrdata_reg
(
5
);
ppsg_escr_pps_in_term_int
<=
wrdata_reg
(
6
);
end
if
;
if
(
wb_we_i
=
'0'
)
then
rddata_reg
(
0
)
<=
'X'
;
...
...
@@ -491,7 +506,7 @@ begin
rddata_reg
(
3
)
<=
ppsg_escr_tm_valid_int
;
rddata_reg
(
4
)
<=
'0'
;
rddata_reg
(
5
)
<=
'0'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
6
)
<=
ppsg_escr_pps_in_term_int
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
...
...
@@ -813,6 +828,8 @@ begin
end
process
;
-- Enable PPS_IN 50Ohm termination
ppsg_escr_pps_in_term_o
<=
ppsg_escr_pps_in_term_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
modules/wr_pps_gen/pps_gen_wb.wb
View file @
f73f8239
...
...
@@ -220,5 +220,17 @@ peripheral {
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "Enable PPS_IN 50Ohm termination";
description = "write 1: enable 50ohm termination for 1-PPS input \
write 0: disable 50ohm termination for 1-PPS input \
read 1: 50ohm termination for 1-PPS input enabled \
read 0: 50ohm termination for 1-PPS input disabled";
prefix = "PPS_IN_TERM";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wr_pps_gen/wr_pps_gen.vhd
View file @
f73f8239
...
...
@@ -79,7 +79,8 @@ entity wr_pps_gen is
-- External PPS input. Warning! This signal is treated as synchronous to
-- the clk_ref_i (or the external 10 MHz reference) to prevent sync chain
-- delay uncertainities. Setup/hold times must be respected!
pps_in_i
:
in
std_logic
;
pps_in_i
:
in
std_logic
;
ppsin_term_o
:
out
std_logic
;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o
:
out
std_logic
;
...
...
@@ -137,7 +138,8 @@ architecture behavioral of wr_pps_gen is
ppsg_escr_tm_valid_o
:
out
std_logic
;
ppsg_escr_sec_set_o
:
out
std_logic
;
ppsg_escr_nsec_set_o
:
out
std_logic
;
ppsg_escr_pps_unmask_o
:
out
std_logic
);
ppsg_escr_pps_unmask_o
:
out
std_logic
;
ppsg_escr_pps_in_term_o
:
out
std_logic
);
end
component
pps_gen_wb
;
-- Wisbone slave signals
...
...
@@ -495,7 +497,8 @@ begin -- behavioral
ppsg_escr_tm_valid_o
=>
ppsg_escr_tm_valid
,
ppsg_escr_sec_set_o
=>
ppsg_escr_sec_set
,
ppsg_escr_nsec_set_o
=>
ppsg_escr_nsec_set
,
ppsg_escr_pps_unmask_o
=>
ppsg_escr_pps_unmask
);
ppsg_escr_pps_unmask_o
=>
ppsg_escr_pps_unmask
,
ppsg_escr_pps_in_term_o
=>
ppsin_term_o
);
-- drive unused signals
wb_out
.
rty
<=
'0'
;
...
...
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @
f73f8239
...
...
@@ -67,6 +67,7 @@ entity xwr_pps_gen is
link_ok_i
:
in
std_logic
;
pps_in_i
:
in
std_logic
;
ppsin_term_o
:
out
std_logic
;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o
:
out
std_logic
;
...
...
@@ -108,6 +109,7 @@ architecture behavioral of xwr_pps_gen is
wb_stall_o
:
out
std_logic
;
link_ok_i
:
in
std_logic
;
pps_in_i
:
in
std_logic
;
ppsin_term_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
...
...
@@ -145,6 +147,7 @@ begin -- behavioral
wb_stall_o
=>
slave_o
.
stall
,
link_ok_i
=>
link_ok_i
,
pps_in_i
=>
pps_in_i
,
ppsin_term_o
=>
ppsin_term_o
,
pps_csync_o
=>
pps_csync_o
,
pps_out_o
=>
pps_out_o
,
pps_led_o
=>
pps_led_o
,
...
...
sim/pps_gen_regs.v
View file @
f73f8239
...
...
@@ -28,3 +28,5 @@
`define
PPSG_ESCR_SEC_SET 32
'
h00000010
`define
PPSG_ESCR_NSEC_SET_OFFSET 5
`define
PPSG_ESCR_NSEC_SET 32
'
h00000020
`define
PPSG_ESCR_PPS_IN_TERM_OFFSET 6
`define
PPSG_ESCR_PPS_IN_TERM 32
'
h00000040
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