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White Rabbit core collection
Commit f2e9c962 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_gthe3_phy_family7: possible fix for failing link up detection after disconnecting the fiber

parent 41a01556
Pipeline #276 failed with stages
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      platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_phy_family7.vhd
      View file @ f2e9c962
      ......@@ -124,6 +124,7 @@ architecture rtl of wr_gthe3_phy_family7 is
      signal RXBYTEISALIGNED : std_logic;
      signal RXCOMMADET : std_logic;
      signal RXCTRL0 : std_logic_vector(15 downto 0);
      signal RXCTRL3 : std_logic_vector(7 downto 0);
      signal RXDATA : std_logic_vector(127 downto 0);
      signal RXOUTCLK : std_logic;
      signal RXPHALIGNDONE : std_logic;
      ......@@ -155,6 +156,7 @@ architecture rtl of wr_gthe3_phy_family7 is
      signal rx_data_int : std_logic_vector(15 downto 0);
      signal rx_k_int : std_logic_vector(1 downto 0);
      signal rx_err_int : std_logic_vector(1 downto 0);
      signal serdes_ready_txusrclk, serdes_ready_rxusrclk : std_logic;
      ......@@ -181,6 +183,14 @@ architecture rtl of wr_gthe3_phy_family7 is
      return true;
      end function;
      attribute mark_debug : string;
      attribute mark_debug of rx_buffer_bypass_done : signal is "TRUE";
      attribute mark_debug of RXCDRLOCK : signal is "TRUE";
      attribute mark_debug of RXRESETDONE : signal is "TRUE";
      attribute mark_debug of RXSYNCDONE : signal is "TRUE";
      attribute mark_debug of RXPMARESETDONE : signal is "TRUE";
      attribute mark_debug of serdes_ready : signal is "TRUE";
      begin
      ......@@ -196,6 +206,7 @@ begin
      TXDATA(127 downto 16) <= (others => '0');
      rx_k_int <= RXCTRL0(1 downto 0);
      rx_err_int <= RXCTRL3(1 downto 0);
      rx_data_int <= RXDATA(15 downto 0);
      U_Bitslide : entity work.gtp_bitslide
      ......@@ -315,7 +326,7 @@ begin
      data_i => serdes_ready,
      synced_o => serdes_ready_txusrclk);
      serdes_ready <= reset_done and rx_buffer_bypass_done and tx_buffer_bypass_done and RXCDRLOCK and RXRESETDONE and TXRESETDONE and TXSYNCDONE and RXSYNCDONE and RXPMARESETDONE and TXPMARESETDONE;
      serdes_ready <= reset_done and rx_buffer_bypass_done and tx_buffer_bypass_done and RXRESETDONE and TXRESETDONE and TXSYNCDONE and RXSYNCDONE and RXPMARESETDONE and TXPMARESETDONE;
      -- tx_active -> userclk_tx_reset and deassert tx_active on rst master, deassert after few cycles of
      -- txusrclk2. same for rx_active.
      ......@@ -356,6 +367,7 @@ begin
      RXBYTEISALIGNED => RXBYTEISALIGNED,
      RXCOMMADET => RXCOMMADET,
      RXCTRL0 => RXCTRL0,
      rxctrl3 => rxctrl3,
      RXDATA => RXDATA,
      RXOUTCLK => RXOUTCLK,
      RXPHALIGNDONE => RXPHALIGNDONE,
      ......@@ -399,7 +411,7 @@ begin
      rx_k_o <= (others => '0');
      rx_enc_err_o <= '1';
      elsif rising_edge(RXUSRCLK2) then
      if(serdes_ready_rxusrclk = '1' and rx_synced = '1') then
      if(serdes_ready_rxusrclk = '1' and rx_synced = '1' and rx_err_int = "00") then
      rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
      rx_k_o <= rx_k_int(0) & rx_k_int(1);
      rx_enc_err_o <= '0'; --rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
      ......@@ -435,7 +447,7 @@ begin
      end generate gen_synthesis;
      rdy_o <= serdes_ready and rx_synced;
      rdy_o <= serdes_ready;
      tx_locked_o <= serdes_ready;
      tx_enc_err_o <= '0';
      ......
      platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_wrapper.vhd
      View file @ f2e9c962
      ......@@ -22,6 +22,9 @@ entity wr_gthe3_wrapper is
      RXBYTEISALIGNED : out std_logic;
      RXCOMMADET : out std_logic;
      RXCTRL0 : out std_logic_vector(15 downto 0);
      RXCTRL1 : out std_logic_vector(15 downto 0);
      RXCTRL2 : out std_logic_vector(7 downto 0);
      RXCTRL3 : out std_logic_vector(7 downto 0);
      RXDATA : out std_logic_vector(127 downto 0);
      RXOUTCLK : out std_logic;
      RXPHALIGNDONE : out std_logic;
      ......@@ -1211,9 +1214,9 @@ begin
      RXCOMSASDET => open,
      RXCOMWAKEDET => open,
      RXCTRL0 => RXCTRL0,
      RXCTRL1 => open,
      RXCTRL2 => open,
      RXCTRL3 => open,
      RXCTRL1 => RXCTRL1,
      RXCTRL2 => RXCTRL2,
      RXCTRL3 => RXCTRL3,
      RXDATA => RXDATA,
      RXDATAEXTENDRSVD => open,
      RXDATAVALID => open,
      ......
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