Commit ee7df2a8 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra

altera: move gsi-specific PLLs to bel_projects

parent 36e07425
def __helper():
dirs = []
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy", "arria5_pll"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy", "arria2_pll"])
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
return dirs
files = [ "altera_pkg.vhd", "altera_butis.vhd", "altera_phase.vhd", "altera_reset.vhd" ]
files = [ "altera_pkg.vhd" ]
modules = {"local": __helper() }
-------------------------------------------------------------------------------
-- Title : Butis Altera clock alignment
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : altera_butis.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-08-23
-- Last update: 2013-08-23
-- Platform : Altera
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Aligns a 200 MHz clock to the PPS
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 GSI / Wesley W. Terpstra
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-08-23 1.0 terpstra First stab at state machine
-- 2013-09-24 1.1 terpstra Move phase shifting to a general purpose core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wr_altera_pkg.all;
entity altera_butis is
port(
clk_ref_i : in std_logic;
clk_25m_i : in std_logic;
pps_i : in std_logic;
phase_o : out phase_offset);
end altera_butis;
-- It is not possible to reliably align 200MHz and 125MHz directly.
-- The problem is that periods of 8ns and 5ns have a gcd=1ns.
-- So, any attempt to measure one clock with the other will have
-- some edges which are within 0.5ns of each other. Too fast.
--
-- Instead, we take the following approach:
-- Setup the PLL to output 125MHz, 200MHz, and 25MHz clocks.
-- Require that all are phase aligned when the PLL is locked.
-- This means that every 40ns they have a common rising edge.
-- Once we find the PPS on the 125MHz clock, latch it's (mod 5*8ns) period.
-- Now, compare a 25 MHz toggling flip-flop to the position of the PPS.
-- We can safely inspect the 12.5 MHz toggle signal in the 125MHz domain.
-- It will look like five '1's then five '0's, repeating.
-- We KNOW that the rising (and falling) edge of the toggle line-up
-- with the 200MHz clock, because the PLL starts up locked this way.
-- Thus, whatever shift would line up the 25MHz signal will also line
-- up the 200MHz signal. Output this to the PLL phase controller.
architecture rtl of altera_butis is
signal toggle_25m : std_logic;
signal clk25_shift : std_logic_vector(4 downto 0);
signal clk25_reg : std_logic_vector(4 downto 0);
signal pps_count : unsigned(2 downto 0);
signal r_pps : std_logic;
begin
toggle : process(clk_25m_i) is
begin
if rising_edge(clk_25m_i) then
toggle_25m <= not toggle_25m;
end if;
end process;
sample : process(clk_ref_i) is
begin
if rising_edge(clk_ref_i) then
clk25_shift <= clk25_shift(clk25_shift'length-2 downto 0) & toggle_25m;
r_pps <= pps_i;
if (pps_i = '1' and r_pps = '0') or pps_count = 0 then
pps_count <= to_unsigned(4, pps_count'length);
else
pps_count <= pps_count - 1;
end if;
if pps_count = 0 then
clk25_reg <= clk25_shift;
end if;
end if;
end process;
-- Phase offsets are 1/8th VCO. At 1GHZ, we need 8 steps to move 1ns.
phase : process(clk_ref_i) is
begin
if rising_edge(clk_ref_i) then
case clk25_reg is
when "00000" => phase_o <= to_unsigned((0*8 mod 5)*8, phase_o'length);
when "00001" => phase_o <= to_unsigned((1*8 mod 5)*8, phase_o'length);
when "00011" => phase_o <= to_unsigned((2*8 mod 5)*8, phase_o'length);
when "00111" => phase_o <= to_unsigned((3*8 mod 5)*8, phase_o'length);
when "01111" => phase_o <= to_unsigned((4*8 mod 5)*8, phase_o'length);
when "11111" => phase_o <= to_unsigned((0*8 mod 5)*8, phase_o'length);
when "11110" => phase_o <= to_unsigned((1*8 mod 5)*8, phase_o'length);
when "11100" => phase_o <= to_unsigned((2*8 mod 5)*8, phase_o'length);
when "11000" => phase_o <= to_unsigned((3*8 mod 5)*8, phase_o'length);
when "10000" => phase_o <= to_unsigned((4*8 mod 5)*8, phase_o'length);
when others => phase_o <= (others => '-'); -- impossible; optimize however
end case;
end if;
end process;
end rtl;
This diff is collapsed.
......@@ -4,122 +4,6 @@ use ieee.numeric_std.all;
package wr_altera_pkg is
subtype phase_offset is unsigned(9 downto 0);
type phase_offset_vector is array(natural range <>) of phase_offset;
type natural_vector is array(natural range <>) of natural;
component altera_reset is
generic(
g_plls : natural := 4;
g_clocks : natural := 2;
g_areset : natural := 1024; -- length of pll_arst_o
g_stable : natural := 1024); -- duration locked must be stable
port(
clk_free_i : in std_logic; -- external free running clock
rstn_i : in std_logic; -- external reset button
pll_lock_i : in std_logic_vector(g_plls-1 downto 0);
pll_arst_o : out std_logic;
clocks_i : in std_logic_vector(g_clocks-1 downto 0);
rstn_o : out std_logic_vector(g_clocks-1 downto 0));
end component;
component dmtd_pll is -- arria2
port(
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 20 MHz
c0 : out std_logic; -- 62.5 MHz
locked : out std_logic);
end component;
component dmtd_pll5 is -- arria5
port(
refclk : in std_logic := 'X'; -- 20 MHz
outclk_0 : out std_logic; -- 62.5 MHz
rst : in std_logic := 'X';
locked : out std_logic);
end component;
component ref_pll is -- arria2
port(
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 125 MHz
c0 : out std_logic; -- 125 MHz
c1 : out std_logic; -- 200 MHz
c2 : out std_logic; -- 25 MHz
locked : out std_logic;
scanclk : in std_logic;
phasecounterselect : in std_logic_vector(3 downto 0);
phasestep : in std_logic;
phaseupdown : in std_logic;
phasedone : out std_logic);
end component;
component ref_pll5 is -- arria5
port(
refclk : in std_logic := 'X'; -- 125 MHz
outclk_0 : out std_logic; -- 125 MHz
outclk_1 : out std_logic; -- 200 MHz
outclk_2 : out std_logic; -- 25 MHz
outclk_3 : out std_logic; --1000 MHz
outclk_4 : out std_logic; -- 125 MHz, 1/8 duty cycle, -1.5ns phase
rst : in std_logic := 'X';
locked : out std_logic;
scanclk : in std_logic;
cntsel : in std_logic_vector(4 downto 0);
phase_en : in std_logic;
updn : in std_logic;
phase_done : out std_logic);
end component;
component sys_pll is -- arria2
port(
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 125 MHz
c0 : out std_logic; -- 62.5 MHz
c1 : out std_logic; -- 50 MHz (flash+reconfig)
c2 : out std_logic; -- 20 MHz (display+scubus)
c3 : out std_logic; -- 10 MHz (remote update)
locked : out std_logic);
end component;
component sys_pll5 is -- arria5
port(
refclk : in std_logic := 'X'; -- 125 MHz
outclk_0 : out std_logic; -- 62.5 MHz
outclk_1 : out std_logic; -- 100 MHz (flash+reconfig)
outclk_2 : out std_logic; -- 20 MHz (display+scubus)
outclk_3 : out std_logic; -- 10 MHz (remote update)
rst : in std_logic := 'X';
locked : out std_logic);
end component;
component altera_phase is
generic(
g_select_bits : natural;
g_outputs : natural;
g_base : integer; -- base phase shift relative to input
g_vco_freq : natural;
g_output_freq : natural_vector;
g_output_select : natural_vector);
port(
clk_i : in std_logic;
rstn_i : in std_logic; -- phase counters were zero'd
clks_i : in std_logic_vector(g_outputs-1 downto 0);
rstn_o : out std_logic_vector(g_outputs-1 downto 0);
offset_i : in phase_offset_vector(g_outputs-1 downto 0);
phasedone_i : in std_logic;
phasesel_o : out std_logic_vector(g_select_bits-1 downto 0);
phasestep_o : out std_logic);
end component;
component altera_butis is
port(
clk_ref_i : in std_logic;
clk_25m_i : in std_logic;
pps_i : in std_logic;
phase_o : out phase_offset);
end component;
component wr_arria2_phy
generic (
g_tx_latch_edge : std_logic := '1';
......
-------------------------------------------------------------------------------
-- Title : Cleanly reset PLLs at power-on
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : altera_reset.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-08-23
-- Last update: 2013-08-23
-- Platform : Altera
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Synchronize PLLs and generate reset lines
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 GSI / Wesley W. Terpstra
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-16 1.0 terpstra First version
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
entity altera_reset is
generic(
g_plls : natural := 4;
g_clocks : natural := 2;
g_areset : natural := 1024; -- length of pll_arst_o
g_stable : natural := 1024); -- duration locked must be stable
port(
clk_free_i : in std_logic; -- external free running clock
rstn_i : in std_logic; -- external reset button
pll_lock_i : in std_logic_vector(g_plls-1 downto 0);
pll_arst_o : out std_logic; -- reset analog lock
clocks_i : in std_logic_vector(g_clocks-1 downto 0);
rstn_o : out std_logic_vector(g_clocks-1 downto 0));
end altera_reset;
architecture rtl of altera_reset is
function f_max(a : natural; b : natural) return natural is
begin
if a > b then return a; else return b; end if;
end function;
constant ones : std_logic_vector(g_plls-1 downto 0) := (others => '1');
constant count_bits : natural := f_ceil_log2(f_max(g_areset, g_stable));
subtype t_count is unsigned(count_bits-1 downto 0);
subtype t_sync is std_logic_vector(2 downto 0);
type t_sync_array is array (natural range <>) of t_sync;
-- async
signal s_locked : std_logic;
-- clk_free registers
signal locked : t_sync := (others => '0');
signal stable : boolean := false; -- counter expired
signal reset : std_logic := '1'; -- async reset of PLL (g_areset)
signal waiting : std_logic := '1'; -- waiting for g_stable (g_stable)
signal count : t_count := to_unsigned(g_areset-1, t_count'length);
-- clocks_i registers
signal nresets : t_sync_array(g_clocks-1 downto 0) := (others => (others => '0'));
-- We ensure timing between these nodes via the state machine
attribute altera_attribute : string;
attribute altera_attribute OF rtl : architecture is
("-name SDC_STATEMENT ""set_false_path -to {*|altera_reset:*|locked[2]}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_reset:*|waiting} -to {*|altera_reset:*|nresets*}""");
begin
s_locked <= rstn_i when (pll_lock_i = ones) else '0';
-- Reset PLLs and wait till all have locked.
-- If any PLL loses lock, reset all of them.
main : process(clk_free_i) is
begin
if rising_edge(clk_free_i) then
locked <= s_locked & locked(locked'left downto 1);
stable <= count = 1;
-- We don't use a traditional state machine here.
-- This code has to be clk_free_i glitch safe!
-- Every case has at most 6 inputs (ie: fits in one 6-LUT)
-- (reset, waiting, stable, locked(0), count(i-1))
if reset = '1' then
if stable then
reset <= '0';
waiting <= '1';
count <= to_unsigned(g_stable-1, t_count'length);
else
reset <= '1';
waiting <= '1';
count <= count - 1;
end if;
elsif waiting = '1' then
if locked(0) = '0' then
reset <= '0';
waiting <= '1';
count <= to_unsigned(g_stable-1, t_count'length);
elsif stable then
reset <= '0';
waiting <= '0';
count <= (others => '-');
else
reset <= '0';
waiting <= '1';
count <= count - 1;
end if;
else
if locked(0) = '0' then
reset <= '1';
waiting <= '1';
count <= to_unsigned(g_areset-1, t_count'length);
else
reset <= '0';
count <= (others => '-');
end if;
end if;
end if;
end process;
pll_arst_o <= reset;
-- Generate per-clock reset lines
resets : for i in g_clocks-1 downto 0 generate
rstn_o(i) <= nresets(i)(0);
reset : process(waiting, clocks_i(i)) is
begin
if waiting = '1' then
nresets(i) <= (others => '0');
elsif rising_edge(clocks_i(i)) then
nresets(i) <= '1' & nresets(i)(t_sync'left downto 1);
end if;
end process;
end generate;
end rtl;
dmtd_pll.cmp
dmtd_pll.ppf
dmtd_pll.qip
dmtd_pll.vhd
ref_pll.cmp
ref_pll.ppf
ref_pll.qip
ref_pll.vhd
sys_pll.cmp
sys_pll.ppf
sys_pll.qip
sys_pll.vhd
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "sys_pll.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "ref_pll.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "dmtd_pll.qip"]
qmegawiz { sys_pll ref_pll dmtd_pll }
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "62.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "20.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "62.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "dmtd_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "50000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
-- Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmtd_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmtd_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmtd_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmtd_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmtd_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmtd_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
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dmtd_pll5.bsf
dmtd_pll5.cmp
dmtd_pll5.ppf
dmtd_pll5.qip
dmtd_pll5.sip
dmtd_pll5.spd
dmtd_pll5.vhd
dmtd_pll5_sim.f
dmtd_pll5/
dmtd_pll5_sim/
ref_pll5.bsf
ref_pll5.cmp
ref_pll5.ppf
ref_pll5.qip
ref_pll5.sip
ref_pll5.spd
ref_pll5.vhd
ref_pll5_sim.f
ref_pll5/
ref_pll5_sim/
sys_pll5.bsf
sys_pll5.cmp
sys_pll5.ppf
sys_pll5.qip
sys_pll5.sip
sys_pll5.spd
sys_pll5.vhd
sys_pll5_sim.f
sys_pll5/
sys_pll5_sim/
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "sys_pll5.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "ref_pll5.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "dmtd_pll5.qip"]
qmegawiz { sys_pll5 ref_pll5 dmtd_pll5 }
This diff is collapsed.
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This diff is collapsed.
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