add sit5359 interface files

e197b6c2 · Peter Jansweijer · 7655749b · e197b6c2 · e197b6c2 · e197b6c2
Commit e197b6c2 authored Jan 10, 2022 by Peter Jansweijer
8 changed files
--- a/modules/Manifest.py
+++ b/modules/Manifest.py
@@ -9,6 +9,7 @@ modules =  {
        "wr_pps_gen",
        "wr_dacs",
        "wr_si57x_interface",
+        "wr_sit5359_interface",
        "wr_eca",
        "wr_tlu",
        "wrc_core",

--- a/modules/wr_sit5359_interface/Manifest.py
+++ b/modules/wr_sit5359_interface/Manifest.py
+files = ["sit5359_regs_pkg.vhd",
+         "sit5359_if_wb.vhd",
+         "wr_sit5359_interface.vhd",
+         "xwr_sit5359_interface.vhd"]
+
--- a/modules/wr_sit5359_interface/build_wb.sh
+++ b/modules/wr_sit5359_interface/build_wb.sh
+#!/bin/bash
+
+mkdir -p doc
+wbgen2.exe -D ./doc/sit5359_id_wb.html -C sit5359_regs.h -p sit5359_regs_pkg.vhd -H record -V sit5359_if_wb.vhd --cstyle defines --lang vhdl sit5359_if_wb.wb
\ No newline at end of file
--- a/modules/wr_sit5359_interface/sit5359_if_wb.vhd
+++ b/modules/wr_sit5359_interface/sit5359_if_wb.vhd
--- a/modules/wr_sit5359_interface/sit5359_if_wb.wb
+++ b/modules/wr_sit5359_interface/sit5359_if_wb.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+	 name = "SiTime 5359 interface";
+	 hdl_entity = "sit5359_if_wb";
+	 prefix = "sit5359";
+
+
+	 reg {
+      name = "Control Register";
+      prefix = "CR";
+			field {
+         name = "Sit5359 I2C Address";
+         size = 8;
+         type = SLV;
+				 prefix = "I2C_ADDR";
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+			field {
+		 name = "I2C Clock Divider (1 I2C bit = 4*(CLK_DIV+1)*clk_sys-period)";
+				 prefix = "CLK_DIV";
+         size = 8;
+         type = SLV;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+			field {
+         name = "Sit5359 SPLL input enable";
+				 prefix = "SPLL_EN";
+         type = BIT;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+			field {
+         name = "Sit5359 Oscillator Output Enable";
+				 prefix = "OSC_OE";
+         type = BIT;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+};
+	 
+   reg {
+      name = "GPIO Set/Readback Register";
+      prefix = "GPSR";
+
+
+      field {
+         name = "Sit5359 I2C bitbanged SCL";
+         prefix = "scl";
+         description = "write 1: Set FMC SCL line to 1 (pullup)\
+                        read : returns the current status of the SCL line.";
+         type = BIT;
+         access_bus = READ_WRITE;
+         access_dev = READ_WRITE;
+         load = LOAD_EXT;
+      };
+
+      field {
+         name = "Sit5359 I2C bitbanged SDA";
+         prefix = "sda";
+         description = "write 1: Set FMC SDA line to 1 (pullup)\
+                        read : returns the current status of the SCL line.";
+         type = BIT;
+         access_bus = READ_WRITE;
+         access_dev = READ_WRITE;
+         load = LOAD_EXT;
+      };
+   };
+
+reg {
+      name = "GPIO Clear Register";
+      prefix = "GPCR";
+
+   
+      field {
+         name = "Sit5359 I2C bitbanged SCL";
+         prefix = "scl";
+         description = "write 1: Set SCL line to 0\
+                        read : returns the current status of the SCL line.";
+         type = MONOSTABLE;
+      };
+
+      field {
+         name = "Sit5359 I2C bitbanged SDA";
+         prefix = "sda";
+         description = "write 1: Set SDA line to 0\
+                        read : returns the current status of the SCL line.";
+         type = MONOSTABLE;
+      };
+   };
+};
--- a/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd
+++ b/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for SiTime 5359 interface
+---------------------------------------------------------------------------------------
+-- File           : sit5359_regs_pkg.vhd
+-- Author         : auto-generated by wbgen2 from sit5359_if_wb.wb
+-- Created        : 01/11/22 17:31:58
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sit5359_if_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package sit5359_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_sit5359_in_registers is record
+    gpsr_scl_i                               : std_logic;
+    gpsr_sda_i                               : std_logic;
+    end record;
+  
+  constant c_sit5359_in_registers_init_value: t_sit5359_in_registers := (
+    gpsr_scl_i => '0',
+    gpsr_sda_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_sit5359_out_registers is record
+      cr_i2c_addr_o                            : std_logic_vector(7 downto 0);
+      cr_clk_div_o                             : std_logic_vector(7 downto 0);
+      cr_spll_en_o                             : std_logic;
+      cr_osc_oe_o                              : std_logic;
+      gpsr_scl_o                               : std_logic;
+      gpsr_scl_load_o                          : std_logic;
+      gpsr_sda_o                               : std_logic;
+      gpsr_sda_load_o                          : std_logic;
+      gpcr_scl_o                               : std_logic;
+      gpcr_sda_o                               : std_logic;
+      end record;
+    
+    constant c_sit5359_out_registers_init_value: t_sit5359_out_registers := (
+      cr_i2c_addr_o => (others => '0'),
+      cr_clk_div_o => (others => '0'),
+      cr_spll_en_o => '0',
+      cr_osc_oe_o => '0',
+      gpsr_scl_o => '0',
+      gpsr_scl_load_o => '0',
+      gpsr_sda_o => '0',
+      gpsr_sda_load_o => '0',
+      gpcr_scl_o => '0',
+      gpcr_sda_o => '0'
+      );
+    function "or" (left, right: t_sit5359_in_registers) return t_sit5359_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body sit5359_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_sit5359_in_registers) return t_sit5359_in_registers is
+variable tmp: t_sit5359_in_registers;
+begin
+tmp.gpsr_scl_i := f_x_to_zero(left.gpsr_scl_i) or f_x_to_zero(right.gpsr_scl_i);
+tmp.gpsr_sda_i := f_x_to_zero(left.gpsr_sda_i) or f_x_to_zero(right.gpsr_sda_i);
+return tmp;
+end function;
+end package body;
--- a/modules/wr_sit5359_interface/wr_sit5359_interface.vhd
+++ b/modules/wr_sit5359_interface/wr_sit5359_interface.vhd
--- a/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd
+++ b/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd
+-------------------------------------------------------------------------------
+-- Title      : SiTime Sit5359 oscillator I2C controller
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : xwr_sit5359_interface.vhd
+-- Author     : Peter Jansweijer (inspired by Tomasz Wlostowski)
+-- Company    : Nikhef/CERN BE-Co-HT
+-- Created    : 2022-01-10
+-- Last update: 2022-01-10
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description: Wrapper for wr_sit5359_interface using Wishbone records in
+-- entity interface. See wr_sit5359_interface.vhd for description.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+entity xwr_sit5359_interface is
+  generic (
+    g_simulation : integer := 0);
+  port (
+    clk_sys_i         : in  std_logic;
+    rst_n_i           : in  std_logic;
+    
+    tm_dac_value_i    : in  std_logic_vector(15 downto 0) := (others => '0');
+    tm_dac_value_wr_i : in  std_logic                     := '0';
+    
+    scl_pad_oen_o     : out std_logic;
+    sda_pad_oen_o     : out std_logic;
+    scl_pad_i         : in  std_logic;
+    sda_pad_i         : in  std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out
+    );
+end xwr_sit5359_interface;
+
+architecture wrapper of xwr_sit5359_interface is
+
+  component wr_sit5359_interface
+    generic (
+      g_simulation : integer);
+    port (
+      clk_sys_i         : in  std_logic;
+      rst_n_i           : in  std_logic;
+      tm_dac_value_i    : in  std_logic_vector(15 downto 0)                           := (others => '0');
+      tm_dac_value_wr_i : in  std_logic                                               := '0';
+      scl_pad_oen_o     : out std_logic;
+      sda_pad_oen_o     : out std_logic;
+      scl_pad_i         : in  std_logic;
+      sda_pad_i         : in  std_logic;
+      wb_adr_i          : in  std_logic_vector(c_wishbone_address_width-1 downto 0)   := (others => '0');
+      wb_dat_i          : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
+      wb_dat_o          : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_sel_i          : in  std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
+      wb_we_i           : in  std_logic                                               := '0';
+      wb_cyc_i          : in  std_logic                                               := '0';
+      wb_stb_i          : in  std_logic                                               := '0';
+      wb_ack_o          : out std_logic;
+      wb_err_o          : out std_logic;
+      wb_stall_o        : out std_logic);
+  end component;
+  
+begin  -- wrapper
+
+  U_Wrapped_sit5359 : wr_sit5359_interface
+    generic map (
+      g_simulation => g_simulation)
+    port map (
+      clk_sys_i         => clk_sys_i,
+      rst_n_i           => rst_n_i,
+      tm_dac_value_i    => tm_dac_value_i,
+      tm_dac_value_wr_i => tm_dac_value_wr_i,
+      scl_pad_oen_o     => scl_pad_oen_o,
+      sda_pad_oen_o     => sda_pad_oen_o,
+      scl_pad_i         => scl_pad_i,
+      sda_pad_i         => sda_pad_i,
+      wb_adr_i          => slave_i.adr,
+      wb_dat_i          => slave_i.dat,
+      wb_dat_o          => slave_o.dat,
+      wb_sel_i          => slave_i.sel,
+      wb_we_i           => slave_i.we,
+      wb_cyc_i          => slave_i.cyc,
+      wb_stb_i          => slave_i.stb,
+      wb_ack_o          => slave_o.ack,
+      wb_err_o          => slave_o.err,
+      wb_stall_o        => slave_o.stall);
+
+
+end wrapper;