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White Rabbit core collection
Commit e01a4c8b authored by A. Hahn's avatar A. Hahn
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wr_arria2_phy: enc_8b10b => gc_enc_8b10b, dec_8b10b => gc_dec_8b10b

parent 657036fa
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    platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
    View file @ e01a4c8b
    ......@@ -129,7 +129,7 @@ architecture rtl of wr_arria2_phy is
    reconfig_togxb : out std_logic_vector (3 downto 0));
    end component;
    component dec_8b10b
    component gc_dec_8b10b
    port (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    ......@@ -140,7 +140,7 @@ architecture rtl of wr_arria2_phy is
    out_8b_o : out std_logic_vector(7 downto 0));
    end component;
    component enc_8b10b
    component gc_enc_8b10b
    port (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    ......@@ -251,7 +251,7 @@ begin
    tx_datain => tx_gxb_datain);
    -- Encode the TX data
    encoder : enc_8b10b
    encoder : gc_enc_8b10b
    port map(
    clk_i => tx_clk_i,
    rst_n_i => tx_8b10b_rstn(0),
    ......@@ -262,7 +262,7 @@ begin
    out_10b_o => tx_enc_datain);
    -- Decode the RX data
    decoder : dec_8b10b
    decoder : gc_dec_8b10b
    port map(
    clk_i => clk_rx,
    rst_n_i => rx_8b10b_rstn(0),
    ......
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