rx_bitslide_o:outstd_logic_vector(3downto0);-- RX bitslide indication, indicating the delay of the RX path of the transceiver (in UIs). Must be valid when rx_data_o is valid.
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@@ -128,8 +128,8 @@ architecture rtl of wr_arria2_phy is
busy:outstd_logic;
reconfig_togxb:outstd_logic_vector(3downto0));
endcomponent;
componentdec_8b10b
componentgc_dec_8b10b
port(
clk_i:instd_logic;
rst_n_i:instd_logic;
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@@ -140,7 +140,7 @@ architecture rtl of wr_arria2_phy is
out_8b_o:outstd_logic_vector(7downto0));
endcomponent;
componentenc_8b10b
componentgc_enc_8b10b
port(
clk_i:instd_logic;
rst_n_i:instd_logic;
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@@ -157,43 +157,43 @@ architecture rtl of wr_arria2_phy is