Commit ce621186 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski

wr_streamers: bring back fixed latency mode for data clock != ref clock

parent b9f7e3e6
...@@ -123,14 +123,18 @@ architecture rtl of fixed_latency_delay is ...@@ -123,14 +123,18 @@ architecture rtl of fixed_latency_delay is
signal fifo_valid : std_logic; signal fifo_valid : std_logic;
signal rx_valid : std_logic; signal rx_valid : std_logic;
signal delay_arm : std_logic; signal delay_arm_p : std_logic;
signal delay_match : std_logic; signal delay_match_p : std_logic;
signal delay_miss : std_logic; signal delay_miss_p : std_logic;
signal delay_timeout : std_logic; signal delay_timeout_p : std_logic;
signal fifo_target_ts_error : std_logic; signal fifo_target_ts_error : std_logic;
signal fifo_target_ts_tai : std_logic_vector(39 downto 0); signal fifo_target_ts_tai : std_logic_vector(39 downto 0);
signal fifo_target_ts_cycles : std_logic_vector(27 downto 0); signal fifo_target_ts_cycles : std_logic_vector(27 downto 0);
signal clk_data : std_logic;
signal rst_n_data : std_logic;
begin begin
...@@ -141,11 +145,8 @@ begin ...@@ -141,11 +145,8 @@ begin
data_i => rst_n_i, data_i => rst_n_i,
synced_o => rst_n_ref); synced_o => rst_n_ref);
-- clk_data <= clk_sys_i when g_use_ref_clock_for_data = 0 else clk_ref_i; clk_data <= clk_sys_i when g_use_ref_clock_for_data = 0 else clk_ref_i;
-- rst_n_data <= rst_n_i when g_use_ref_clock_for_data = 0 else rst_n_ref; rst_n_data <= rst_n_i when g_use_ref_clock_for_data = 0 else rst_n_ref;
-- clk_data <= clk_ref_i;
-- rst_n_data <= rst_n_ref;
dbuf_d(g_data_width-1 downto 0) <= d_data_i; dbuf_d(g_data_width-1 downto 0) <= d_data_i;
dbuf_d(g_data_width) <= d_last_i; dbuf_d(g_data_width) <= d_last_i;
...@@ -187,15 +188,15 @@ begin ...@@ -187,15 +188,15 @@ begin
d_i => dbuf_q, d_i => dbuf_q,
we_i => dbuf_q_valid, we_i => dbuf_q_valid,
wr_full_o => wr_full, wr_full_o => wr_full,
clk_rd_i => clk_ref_i, clk_rd_i => clk_data,
q_o => fifo_q, q_o => fifo_q,
rd_i => fifo_rd, rd_i => fifo_rd,
rd_empty_o => fifo_empty); rd_empty_o => fifo_empty);
p_fsm_seq: process(clk_ref_i) p_fsm_seq: process(clk_data)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_data) then
if rst_n_ref = '0' then if rst_n_data = '0' then
state <= IDLE; state <= IDLE;
fifo_valid <= '0'; fifo_valid <= '0';
else else
...@@ -226,7 +227,7 @@ begin ...@@ -226,7 +227,7 @@ begin
when TS_WAIT_MATCH => when TS_WAIT_MATCH =>
if delay_miss = '1' or delay_match = '1' or delay_timeout = '1' then if delay_miss_p = '1' or delay_match_p = '1' or delay_timeout_p = '1' then
if fifo_last = '1' and fifo_empty = '0' then if fifo_last = '1' and fifo_empty = '0' then
state <= TS_SETUP_MATCH; state <= TS_SETUP_MATCH;
else else
...@@ -255,11 +256,14 @@ begin ...@@ -255,11 +256,14 @@ begin
generic map ( generic map (
g_clk_ref_rate => g_clk_ref_rate, g_clk_ref_rate => g_clk_ref_rate,
g_sim_cycle_counter_range => g_sim_cycle_counter_range, g_sim_cycle_counter_range => g_sim_cycle_counter_range,
g_simulation => g_simulation) g_simulation => g_simulation,
g_use_ref_clock_for_data => g_use_ref_clock_for_data)
port map ( port map (
clk_i => clk_ref_i, clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref, clk_data_i => clk_data,
arm_i => delay_arm, rst_ref_n_i => rst_n_ref,
rst_data_n_i => rst_n_data,
arm_p_i => delay_arm_p,
ts_tai_i => fifo_target_ts_tai, ts_tai_i => fifo_target_ts_tai,
ts_cycles_i => fifo_target_ts_cycles, ts_cycles_i => fifo_target_ts_cycles,
ts_latency_i => rx_streamer_cfg_i.fixed_latency, ts_latency_i => rx_streamer_cfg_i.fixed_latency,
...@@ -267,36 +271,36 @@ begin ...@@ -267,36 +271,36 @@ begin
tm_time_valid_i => tm_time_valid_i, tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i, tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i, tm_cycles_i => tm_cycles_i,
timeout_o => delay_timeout, timeout_p_o => delay_timeout_p,
match_o => delay_match, match_p_o => delay_match_p,
late_o => delay_miss); late_p_o => delay_miss_p);
p_fsm_comb: process(state, rx_dreq_i, fifo_empty, delay_miss, fifo_last, delay_match, delay_timeout, fifo_target_ts_en, fifo_valid) p_fsm_comb: process(state, rx_dreq_i, fifo_empty, delay_miss_p, fifo_last, delay_match_p, delay_timeout_p, fifo_target_ts_en, fifo_valid)
begin begin
case state is case state is
when IDLE => when IDLE =>
delay_arm <= '0'; delay_arm_p <= '0';
fifo_rd <= not fifo_empty; fifo_rd <= not fifo_empty;
rx_valid <= '0'; rx_valid <= '0';
rx_late_o <= '0'; rx_late_o <= '0';
rx_timeout_o <= '0'; rx_timeout_o <= '0';
when TS_SETUP_MATCH => when TS_SETUP_MATCH =>
delay_arm <= fifo_valid and fifo_target_ts_en; delay_arm_p <= fifo_valid and fifo_target_ts_en;
fifo_rd <= '0'; fifo_rd <= '0';
rx_valid <= '0'; rx_valid <= '0';
rx_late_o <= '0'; rx_late_o <= '0';
rx_timeout_o <= '0'; rx_timeout_o <= '0';
when TS_WAIT_MATCH => when TS_WAIT_MATCH =>
delay_arm <= '0'; delay_arm_p <= '0';
fifo_rd <= (delay_match or delay_miss or delay_timeout) and not fifo_empty; fifo_rd <= (delay_match_p or delay_miss_p or delay_timeout_p) and not fifo_empty;
rx_valid <= delay_match or delay_miss; rx_valid <= delay_match_p or delay_miss_p;
rx_late_o <= delay_miss; rx_late_o <= delay_miss_p;
rx_timeout_o <= delay_timeout; rx_timeout_o <= delay_timeout_p;
when SEND => when SEND =>
delay_arm <= '0'; delay_arm_p <= '0';
fifo_rd <= (rx_dreq_i or (fifo_last and fifo_valid)) and not fifo_empty; fifo_rd <= (rx_dreq_i or (fifo_last and fifo_valid)) and not fifo_empty;
rx_valid <= fifo_valid; rx_valid <= fifo_valid;
rx_late_o <= '0'; rx_late_o <= '0';
...@@ -308,29 +312,29 @@ begin ...@@ -308,29 +312,29 @@ begin
U_Sync_RXMatch_Pulse : gc_pulse_synchronizer2 U_Sync_RXMatch_Pulse : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_ref_i, clk_in_i => clk_data,
rst_in_n_i => rst_n_ref, rst_in_n_i => rst_n_data,
clk_out_i => clk_sys_i, clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_i, rst_out_n_i => rst_n_i,
d_p_i => delay_match, d_p_i => delay_match_p,
q_p_o => stat_match_p1_o); q_p_o => stat_match_p1_o);
U_Sync_RXLate_Pulse : gc_pulse_synchronizer2 U_Sync_RXLate_Pulse : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_ref_i, clk_in_i => clk_data,
rst_in_n_i => rst_n_ref, rst_in_n_i => rst_n_data,
clk_out_i => clk_sys_i, clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_i, rst_out_n_i => rst_n_i,
d_p_i => delay_miss, d_p_i => delay_miss_p,
q_p_o => stat_late_p1_o); q_p_o => stat_late_p1_o);
U_Sync_RXTimeout_Pulse : gc_pulse_synchronizer2 U_Sync_RXTimeout_Pulse : gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_ref_i, clk_in_i => clk_data,
rst_in_n_i => rst_n_ref, rst_in_n_i => rst_n_data,
clk_out_i => clk_sys_i, clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_i, rst_out_n_i => rst_n_i,
d_p_i => delay_timeout, d_p_i => delay_timeout_p,
q_p_o => stat_timeout_p1_o); q_p_o => stat_timeout_p1_o);
fifo_data <= fifo_q(g_data_width-1 downto 0); fifo_data <= fifo_q(g_data_width-1 downto 0);
......
...@@ -45,15 +45,18 @@ entity fixed_latency_ts_match is ...@@ -45,15 +45,18 @@ entity fixed_latency_ts_match is
generic generic
(g_clk_ref_rate : integer; (g_clk_ref_rate : integer;
g_simulation : integer := 0; g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000000 g_sim_cycle_counter_range : integer := 125000000;
g_use_ref_clock_for_data : integer := 0
); );
port port
( (
clk_i : in std_logic; clk_ref_i : in std_logic;
rst_n_i : in std_logic; clk_data_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_data_n_i : in std_logic;
arm_i : in std_logic; arm_p_i : in std_logic;
ts_tai_i : in std_logic_vector(39 downto 0); ts_tai_i : in std_logic_vector(39 downto 0);
ts_cycles_i : in std_logic_vector(27 downto 0); ts_cycles_i : in std_logic_vector(27 downto 0);
...@@ -69,11 +72,9 @@ entity fixed_latency_ts_match is ...@@ -69,11 +72,9 @@ entity fixed_latency_ts_match is
-- Fractional part of the second (in clk_ref_i cycles) -- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000"; tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
match_o : out std_logic; match_p_o : out std_logic;
late_o : out std_logic; late_p_o : out std_logic;
timeout_o : out std_logic timeout_p_o : out std_logic
); );
end entity; end entity;
...@@ -101,6 +102,11 @@ architecture rtl of fixed_latency_ts_match is ...@@ -101,6 +102,11 @@ architecture rtl of fixed_latency_ts_match is
signal ts_timeout_cycles : unsigned(28 downto 0); signal ts_timeout_cycles : unsigned(28 downto 0);
signal ts_timeout_tai : unsigned(39 downto 0); signal ts_timeout_tai : unsigned(39 downto 0);
signal ts_adjusted_cycles_latched : unsigned(28 downto 0);
signal ts_adjusted_tai_latched : unsigned(39 downto 0);
signal ts_timeout_cycles_latched : unsigned(28 downto 0);
signal ts_timeout_tai_latched : unsigned(39 downto 0);
signal tm_cycles_scaled : unsigned(28 downto 0); signal tm_cycles_scaled : unsigned(28 downto 0);
signal ts_latency_scaled : unsigned(28 downto 0); signal ts_latency_scaled : unsigned(28 downto 0);
signal ts_timeout_scaled : unsigned(28 downto 0); signal ts_timeout_scaled : unsigned(28 downto 0);
...@@ -111,30 +117,16 @@ architecture rtl of fixed_latency_ts_match is ...@@ -111,30 +117,16 @@ architecture rtl of fixed_latency_ts_match is
signal match, late, timeout : std_logic; signal match, late, timeout : std_logic;
signal state : t_state; signal state : t_state;
signal trig : std_logic; signal trig : std_logic;
signal arm_synced_p, arm_synced_p_d : std_logic;
signal wait_cnt : unsigned(23 downto 0); signal wait_cnt : unsigned(23 downto 0);
attribute mark_debug : string;
attribute mark_debug of ts_adjusted_cycles : signal is "TRUE";
attribute mark_debug of ts_adjusted_tai : signal is "TRUE";
attribute mark_debug of ts_timeout_cycles : signal is "TRUE";
attribute mark_debug of ts_timeout_tai : signal is "TRUE";
attribute mark_debug of tm_cycles_scaled_d : signal is "TRUE";
attribute mark_debug of tm_tai_d : signal is "TRUE";
attribute mark_debug of state : signal is "TRUE";
attribute mark_debug of match : signal is "TRUE";
attribute mark_debug of late : signal is "TRUE";
attribute mark_debug of timeout : signal is "TRUE";
attribute mark_debug of trig : signal is "TRUE";
begin begin
process(clk_i) process(clk_ref_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_ref_i) then
tm_cycles_scaled_d <= tm_cycles_scaled; tm_cycles_scaled_d <= tm_cycles_scaled;
tm_tai_d <= unsigned(tm_tai_i); tm_tai_d <= unsigned(tm_tai_i);
end if; end if;
...@@ -157,10 +149,10 @@ begin ...@@ -157,10 +149,10 @@ begin
end process; end process;
process(clk_i) process(clk_ref_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_ref_i) then
if rst_n_i = '0' then if rst_ref_n_i = '0' then
wait_cnt <= (others => '0'); wait_cnt <= (others => '0');
trig <= '0'; trig <= '0';
else else
...@@ -184,10 +176,10 @@ begin ...@@ -184,10 +176,10 @@ begin
process(clk_i) process(clk_ref_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_ref_i) then
if rst_n_i = '0' then if rst_ref_n_i = '0' then
late <= '0'; late <= '0';
match <= '0'; match <= '0';
State <= IDLE; State <= IDLE;
...@@ -200,13 +192,11 @@ begin ...@@ -200,13 +192,11 @@ begin
late <= '0'; late <= '0';
timeout <= '0'; timeout <= '0';
if arm_i = '1' then if arm_synced_p_d = '1' then
ts_adjusted_cycles <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_scaled), 29); ts_adjusted_tai <= ts_adjusted_tai_latched;
ts_adjusted_tai <= resize(unsigned(ts_tai_i), 40); ts_adjusted_cycles <= ts_adjusted_cycles_latched;
ts_timeout_tai <= ts_timeout_tai_latched;
ts_timeout_cycles <= resize(unsigned(ts_cycles_i) + unsigned(ts_timeout_scaled), 29); ts_timeout_cycles <= ts_timeout_cycles_latched;
ts_timeout_tai <= resize(unsigned(ts_tai_i), 40);
State <= WRAP_ADJ_TS; State <= WRAP_ADJ_TS;
end if; end if;
...@@ -262,8 +252,87 @@ begin ...@@ -262,8 +252,87 @@ begin
end if; end if;
end process; end process;
match_o <= match; gen_data_synchronous_to_wr : if g_use_ref_clock_for_data /= 0 generate
late_o <= late; match_p_o <= match;
timeout_o <= timeout; late_p_o <= late;
timeout_p_o <= timeout;
arm_synced_p <= arm_p_i;
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
arm_synced_p_d <= arm_synced_p;
if arm_synced_p = '1' then
ts_adjusted_cycles_latched <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_scaled), 29);
ts_adjusted_tai_latched <= resize(unsigned(ts_tai_i), 40);
ts_timeout_cycles_latched <= resize(unsigned(ts_cycles_i) + unsigned(ts_timeout_scaled), 29);
ts_timeout_tai_latched <= resize(unsigned(ts_tai_i), 40);
end if;
end if;
end process;
end generate;
gen_data_asynchronous_to_wr : if g_use_ref_clock_for_data = 0 generate
U_Sync1: entity work.gc_pulse_synchronizer2
port map (
clk_in_i => clk_data_i,
clk_out_i => clk_ref_i,
rst_in_n_i => rst_data_n_i,
rst_out_n_i => rst_ref_n_i,
d_ready_o => open,
d_p_i => arm_p_i,
q_p_o => arm_synced_p_d);
U_Sync2: entity work.gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
clk_out_i => clk_data_i,
rst_in_n_i => rst_ref_n_i,
rst_out_n_i => rst_data_n_i,
d_ready_o => open,
d_p_i => match,
q_p_o => match_p_o);
U_Sync3: entity work.gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
clk_out_i => clk_data_i,
rst_in_n_i => rst_ref_n_i,
rst_out_n_i => rst_data_n_i,
d_ready_o => open,
d_p_i => late,
q_p_o => late_p_o);
U_Sync4: entity work.gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
clk_out_i => clk_data_i,
rst_in_n_i => rst_ref_n_i,
rst_out_n_i => rst_data_n_i,
d_ready_o => open,
d_p_i => timeout,
q_p_o => timeout_p_o);
process(clk_data_i)
begin
if rising_edge(clk_data_i) then
if arm_p_i = '1' then
ts_adjusted_cycles_latched <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_scaled), 29);
ts_adjusted_tai_latched <= resize(unsigned(ts_tai_i), 40);
ts_timeout_cycles_latched <= resize(unsigned(ts_cycles_i) + unsigned(ts_timeout_scaled), 29);
ts_timeout_tai_latched <= resize(unsigned(ts_tai_i), 40);
end if;
end if;
end process;
end generate;
end rtl; end rtl;
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