Commit c4795908 authored by A. Hahn's avatar A. Hahn

merge: arria 10 gsi wr-v4.2

parents 2d2878e8 c1419c81
......@@ -16,6 +16,6 @@ doc/
*.bin
*.elf
*.ucdb
Makefile
*.xml
Makefile
xgui/
files = [ "enc_8b10b.vhd",
"wr_tbi_phy.vhd",
"disparity_gen_pkg.vhd" ];
files = [ "enc_8b10b.vhd",
"dec_8b10b.vhd",
"wr_tbi_phy.vhd",
"disparity_gen_pkg.vhd" ];
......@@ -12,25 +12,25 @@
-------------------------------------------------------------------------------
-- Description:
-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
--
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -131,7 +131,7 @@ architecture struct of wrc_periph is
signal cntr_div : unsigned(23 downto 0);
signal cntr_tics : unsigned(31 downto 0);
signal cntr_overflow : std_logic;
signal rst_wrc_n_o_reg : std_logic := '1';
signal diag_adr : unsigned(15 downto 0);
signal diag_dat : std_logic_vector(31 downto 0);
......@@ -140,6 +140,24 @@ architecture struct of wrc_periph is
signal wrpc_diag_regs_in : t_wrc_diags_in_registers;
signal wrpc_diag_regs_out : t_wrc_diags_out_registers;
component wrc_syscon_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end component;
begin
rst_wrc_n_o <= rst_n_i and rst_wrc_n_o_reg;
......@@ -153,13 +171,13 @@ begin
if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
rst_wrc_n_o_reg <= not sysc_regs_o.rstr_rst_o;
end if;
end if;
rst_net_n_o <= not sysc_regs_o.gpsr_net_rst_o;
end if;
end if;
end if;
end if;
end process;
-------------------------------------
-- LEDs
-------------------------------------
......@@ -396,7 +414,7 @@ begin
----------------------------------------
-- SYSCON
----------------------------------------
SYSCON : entity work.wrc_syscon_wb
SYSCON : wrc_syscon_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......
def __helper():
dirs = []
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
if syn_device[:3] == "10a": dirs.extend(["wr_arria10_phy"])
if syn_device[:1] == "5": dirs.extend(["wr_arria5_phy"])
if syn_device[:4] == "ep2a": dirs.extend(["wr_arria2_phy"])
return dirs
files = [ "wr_altera_pkg.vhd", "xwrc_platform_altera.vhd" ]
......
This diff is collapsed.
*.sopcinfo
*.xml
*.rpt
*.rpt.1
*.qicache
*.qip
*.html
def __helper():
dirs = []
if syn_device[:4] == "10as": dirs.extend(["wr_arria10_phy"])
if syn_device[:7] == "10ax027": dirs.extend(["wr_arria10_scu4_phy"])
if syn_device[:7] == "10ax066": dirs.extend(["wr_arria10_phy"])
if syn_device[:7] == "10ax115": dirs.extend(["wr_arria10_e3p1_phy"])
return dirs
files = [ "wr_arria10_phy.vhd" ]
modules = {"local": __helper() }
# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst wr_arria10_e3p1_atx_pll -pg 1 -lvl 1 -y 40 -regy -20
preplace inst wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0 -pg 1 -lvl 1 -y 30
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_powerdown,(SLAVE)wr_arria10_e3p1_atx_pll.pll_powerdown) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(MASTER)xcvr_atx_pll_a10_0.tx_serial_clk,(MASTER)wr_arria10_e3p1_atx_pll.tx_serial_clk) 1 1 1 N
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_locked,(SLAVE)wr_arria10_e3p1_atx_pll.pll_locked) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_cal_busy,(SLAVE)wr_arria10_e3p1_atx_pll.pll_cal_busy) 1 0 1 NJ
preplace netloc EXPORT<net_container>wr_arria10_e3p1_atx_pll</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_refclk0,(SLAVE)wr_arria10_e3p1_atx_pll.pll_refclk0) 1 0 1 NJ
levelinfo -pg 1 0 90 430
levelinfo -hier wr_arria10_e3p1_atx_pll 100 130 320
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element xcvr_atx_pll_a10_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="pll_cal_busy"
internal="xcvr_atx_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
internal="xcvr_atx_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_atx_pll_a10_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_refclk0"
internal="xcvr_atx_pll_a10_0.pll_refclk0"
type="clock"
dir="end">
<port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="tx_serial_clk"
internal="xcvr_atx_pll_a10_0.tx_serial_clk"
type="hssi_serial_clock"
dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" />
</interface>
<module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
version="16.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="medium" />
<parameter name="device" value="10AX115S2F45I2SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="enable_ext_lockdetect_ports" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="generate_docs" value="0" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="mcgb_div" value="1" />
<parameter name="message_level" value="error" />
<parameter name="pma_width" value="64" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
<parameter name="rcfg_profile_data3" value="" />
<parameter name="rcfg_profile_data4" value="" />
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="125.0" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="156.25" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="2000000000" />
<parameter name="set_l_cascade_counter" value="15" />
<parameter name="set_l_cascade_predivider" value="1" />
<parameter name="set_l_counter" value="16" />
<parameter name="set_m_counter" value="24" />
<parameter name="set_manual_reference_clock_frequency" value="200.0" />
<parameter name="set_output_clock_frequency" value="625.0" />
<parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_ref_clk_div" value="1" />
<parameter name="set_user_identifier" value="0" />
<parameter name="silicon_rev" value="false" />
<parameter name="support_mode" value="user_mode" />
<parameter name="test_mode" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element xcvr_atx_pll_a10_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45I1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="pll_cal_busy"
internal="xcvr_atx_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
internal="xcvr_atx_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_atx_pll_a10_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_refclk0"
internal="xcvr_atx_pll_a10_0.pll_refclk0"
type="clock"
dir="end">
<port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="tx_serial_clk"
internal="xcvr_atx_pll_a10_0.tx_serial_clk"
type="hssi_serial_clock"
dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" />
</interface>
<module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
version="18.1"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="medium" />
<parameter name="device" value="10AX115S2F45I1SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="enable_ext_lockdetect_ports" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="generate_docs" value="0" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="mcgb_div" value="1" />
<parameter name="message_level" value="error" />
<parameter name="pma_width" value="64" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
<parameter name="rcfg_profile_data3" value="" />
<parameter name="rcfg_profile_data4" value="" />
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="125.0" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="156.25" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="2000000000" />
<parameter name="set_l_cascade_counter" value="15" />
<parameter name="set_l_cascade_predivider" value="1" />
<parameter name="set_l_counter" value="16" />
<parameter name="set_m_counter" value="24" />
<parameter name="set_manual_reference_clock_frequency" value="200.0" />
<parameter name="set_output_clock_frequency" value="2500.0" />
<parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_ref_clk_div" value="1" />
<parameter name="set_user_identifier" value="0" />
<parameter name="silicon_rev" value="false" />
<parameter name="support_mode" value="user_mode" />
<parameter name="test_mode" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
package a10_avmm_h;
// localparam to define unused bus
localparam RD_UNUSED = 8'h0;
// localparams for common capability registers
localparam A10_XR_ADDR_ID_0 = 9'h0;
localparam A10_XR_ADDR_ID_1 = 9'h1;
localparam A10_XR_ADDR_ID_2 = 9'h2;
localparam A10_XR_ADDR_ID_3 = 9'h3;
localparam A10_XR_ADDR_STATUS_EN = 9'h4;
localparam A10_XR_ADDR_CONTROL_EN = 9'h5;
// Reserve Address 9'h6 to 9'hF for common capablities
// native phy capability
localparam A10_XR_ADDR_NAT_CHNLS = 9'h10;
localparam A10_XR_ADDR_NAT_CHNL_NUM = 9'h11;
localparam A10_XR_ADDR_NAT_DUPLEX = 9'h12;
localparam A10_XR_ADDR_NAT_PRBS_EN = 9'h13;
localparam A10_XR_ADDR_NAT_ODI_EN = 9'h14;
// pll ip capability
localparam A10_XR_ADDR_PLL_MCGB_EN = 9'h10;
// localparams for csr for pll locked and cal busy
localparam A10_XR_ADDR_GP_PLL_LOCK = 9'h80;
localparam A10_XR_OFFSET_GP_LOCK = 0;
localparam A10_XR_OFFSET_GP_CAL_BUSY = 1;
localparam A10_XR_OFFSET_GP_AVMM_BUSY = 2;
localparam A10_XR_OFFSET_LOCK_UNUSED = 3;
localparam A10_XR_LOCK_UNUSED_LEN = 5;
// localparams for pll powerdown
localparam A10_XR_ADDR_GP_PLL_RST = 9'hE0;
localparam A10_XR_OFFSET_PLL_RST = 0;
localparam A10_XR_OFFSET_PLL_RST_OVR = 1;
localparam A10_XR_OFFSET_PLL_RST_UNUSED = 2;
localparam A10_XR_PLL_RST_UNUSED_LEN = 6;
// localparams for csr for lock to ref and lock to data
localparam A10_XR_ADDR_GP_RD_LTR = 9'h80;
localparam A10_XR_OFFSET_RD_LTD = 0;
localparam A10_XR_OFFSET_RD_LTR = 1;
localparam A10_XR_OFFSET_LTR_UNUSED = 2;
localparam A10_XR_LTR_UNUSED_LEN = 6;
// localparams for csr for cal busy
localparam A10_XR_ADDR_GP_CAL_BUSY = 9'h81;
localparam A10_XR_OFFSET_TX_CAL_BUSY = 0;
localparam A10_XR_OFFSET_RX_CAL_BUSY = 1;
localparam A10_XR_OFFSET_AVMM_BUSY = 2;
localparam A10_XR_OFFSET_CAL_DUMMY = 3;
localparam A10_XR_OFFSET_TX_CAL_MASK = 4;
localparam A10_XR_OFFSET_RX_CAL_MASK = 5;
localparam A10_XR_OFFSET_CAL_UNUSED = 6;
localparam A10_XR_CAL_UNUSED_LEN = 2;
// localparams for setting lock to ref and lock to data
localparam A10_XR_ADDR_GP_SET_LTR = 9'hE0;
localparam A10_XR_OFFSET_SET_LTD = 0;
localparam A10_XR_OFFSET_SET_LTR = 1;
localparam A10_XR_OFFSET_SET_LTD_OVR = 2;
localparam A10_XR_OFFSET_SET_LTR_OVR = 3;
localparam A10_XR_OFFSET_SET_LTR_UNUSED = 4;
localparam A10_XR_SET_LTR_UNUSED_LEN = 4;
// localparams for setting loopback
localparam A10_XR_ADDR_GP_LPBK = 9'hE1;
localparam A10_XR_OFFSET_LPBK = 0;
localparam A10_XR_OFFSET_LPBK_UNUSED = 1;
localparam A10_XR_LPBK_UNUSED_LEN = 7;
// localparams for setting channel resets
localparam A10_XR_ADDR_CHNL_RESET = 9'hE2;
localparam A10_XR_OFFSET_RX_ANA = 0;
localparam A10_XR_OFFSET_RX_DIG = 1;
localparam A10_XR_OFFSET_TX_ANA = 2;
localparam A10_XR_OFFSET_TX_DIG = 3;
localparam A10_XR_OFFSET_RX_ANA_OVR = 4;
localparam A10_XR_OFFSET_RX_DIG_OVR = 5;
localparam A10_XR_OFFSET_TX_ANA_OVR = 6;
localparam A10_XR_OFFSET_TX_DIG_OVR = 7;
// localparams for prbs addresses
localparam A10_XR_ADDR_PRBS_CTRL = 9'h100;
localparam A10_XR_ADDR_PRBS_ERR_0 = 9'h101;
localparam A10_XR_ADDR_PRBS_ERR_1 = 9'h102;
localparam A10_XR_ADDR_PRBS_ERR_2 = 9'h103;
localparam A10_XR_ADDR_PRBS_ERR_3 = 9'h104;
localparam A10_XR_ADDR_PRBS_ERR_4 = 9'h105;
localparam A10_XR_ADDR_PRBS_ERR_5 = 9'h106;
localparam A10_XR_ADDR_PRBS_ERR_6 = 9'h107;
localparam A10_XR_ADDR_PRBS_BIT_0 = 9'h10D;
localparam A10_XR_ADDR_PRBS_BIT_1 = 9'h10E;
localparam A10_XR_ADDR_PRBS_BIT_2 = 9'h10F;
localparam A10_XR_ADDR_PRBS_BIT_3 = 9'h110;
localparam A10_XR_ADDR_PRBS_BIT_4 = 9'h111;
localparam A10_XR_ADDR_PRBS_BIT_5 = 9'h112;
localparam A10_XR_ADDR_PRBS_BIT_6 = 9'h113;
// localparams for prbs bit offsets
localparam A10_XR_OFFSET_PRBS_EN = 0;
localparam A10_XR_OFFSET_PRBS_RESET = 1;
localparam A10_XR_OFFSET_PRBS_SNAP = 2;
localparam A10_XR_OFFSET_PRBS_DONE = 3;
localparam A10_XR_OFFSET_PRBS_UNUSED = 4;
localparam A10_XR_PRBS_UNUSED_LEN = 4;
// localparams for odi addresses
localparam A10_XR_ADDR_ODI_CTRL = 9'h120;
localparam A10_XR_ADDR_ODI_ERR_0 = 9'h121;
localparam A10_XR_ADDR_ODI_ERR_1 = 9'h122;
localparam A10_XR_ADDR_ODI_ERR_2 = 9'h123;
localparam A10_XR_ADDR_ODI_ERR_3 = 9'h124;
localparam A10_XR_ADDR_ODI_ERR_4 = 9'h125;
localparam A10_XR_ADDR_ODI_ERR_5 = 9'h126;
localparam A10_XR_ADDR_ODI_ERR_6 = 9'h127;
localparam A10_XR_ADDR_ODI_BIT_0 = 9'h12D;
localparam A10_XR_ADDR_ODI_BIT_1 = 9'h12E;
localparam A10_XR_ADDR_ODI_BIT_2 = 9'h12F;
localparam A10_XR_ADDR_ODI_BIT_3 = 9'h130;
localparam A10_XR_ADDR_ODI_BIT_4 = 9'h131;
localparam A10_XR_ADDR_ODI_BIT_5 = 9'h132;
localparam A10_XR_ADDR_ODI_BIT_6 = 9'h133;
// localparams for odi bit offsets
localparam A10_XR_OFFSET_ODI_EN = 0;
localparam A10_XR_OFFSET_ODI_RESET = 1;
localparam A10_XR_OFFSET_ODI_SNAP = 2;
localparam A10_XR_OFFSET_ODI_DONE = 3;
localparam A10_XR_OFFSET_ODI_UNUSED = 4;
localparam A10_XR_ODI_UNUSED_LEN = 4;
// localparams for embedded reconfig addresses
// Control reg and offsets
localparam A10_XR_ADDR_EMBED_RCFG_CTRL = 9'h140;
localparam A10_XR_OFFSET_EMBED_RCFG_CFG_SEL = 0;
localparam A10_XR_EMBED_RCFG_CFG_SEL_LEN = 6; //bits [5:0] are alloted for cfg_sel even though GUI currently only supports upto 8 profiles.
localparam A10_XR_OFFSET_EMBED_RCFG_BCAST_EN = 6;
localparam A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD = 7;
// Status reg and offsets
localparam A10_XR_ADDR_EMBED_RCFG_STATUS = 9'h141;
localparam A10_XR_OFFSET_EMBED_RCFG_STRM_BUSY = 0;
endpackage
./twentynm_xcvr_avmm.sv
./alt_xcvr_resync.sv
./alt_xcvr_arbiter.sv
./a10_avmm_h.sv
./altera_xcvr_native_a10_functions_h.sv
./alt_xcvr_atx_pll_rcfg_arb.sv
./a10_xcvr_atx_pll.sv
./alt_xcvr_pll_embedded_debug.sv
./alt_xcvr_pll_avmm_csr.sv
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Clocked priority encoder with state
//
// On each clock cycle, updates state to show which request is granted.
// Most recent grant holder is always the highest priority.
// If current grant holder is not making a request, while others are,
// then new grant holder is always the requester with lowest bit number.
// If no requests, current grant holder retains grant state
// $Header$
`timescale 1 ns / 1 ns
module alt_xcvr_arbiter #(
parameter width = 2
) (
input wire clock,
input wire [width-1:0] req, // req[n] requests for this cycle
output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
);
wire idle; // idle when no requests
wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
// Note: current grantee is always highest priority for next grant
wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
assign keep = req & grant; // current grantee is always highest priority for next grant
assign idle = ~| req; // idle when no requests
initial begin
grant = 0;
end
// grant next state depends on current grant and take priority
always @(posedge clock) begin
grant <=
// synthesis translate_off
(grant === {width{1'bx}})? {width{1'b0}} :
// synthesis translate_on
keep // if current grantee is requesting, gets to keep grant
| ({width{idle}} & grant) // if no requests, grant state remains unchanged
| take; // take applies only if current grantee is not requesting
end
// 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
assign take[0] = req[0]
& (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
genvar i;
generate
for (i=1; i < width; i = i + 1) begin : arb
assign take[i] = req[i]
& (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
& (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
end
endgenerate
endmodule
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps/1 ps
module alt_xcvr_atx_pll_rcfg_arb #(
parameter total_masters = 3,
parameter interfaces = 1,
parameter address_width = 10,
parameter data_width = 32
) (
// Basic AVMM inputs
input [interfaces-1:0] reconfig_clk,
input [interfaces-1:0] reconfig_reset,
// User AVMM input
input [interfaces-1:0] user_read,
input [interfaces-1:0] user_write,
input [interfaces*address_width-1:0] user_address,
input [interfaces*data_width-1:0] user_writedata,
input [interfaces-1:0] user_read_write,
output [interfaces-1:0] user_waitrequest,
// Reconfig Steamer AVMM input
input [interfaces-1:0] strm_read,
input [interfaces-1:0] strm_write,
input [interfaces*address_width-1:0] strm_address,
input [interfaces*data_width-1:0] strm_writedata,
input [interfaces-1:0] strm_read_write,
output [interfaces-1:0] strm_waitrequest,
// ADME AVMM input
input [interfaces-1:0] jtag_read,
input [interfaces-1:0] jtag_write,
input [interfaces*address_width-1:0] jtag_address,
input [interfaces*data_width-1:0] jtag_writedata,
input [interfaces-1:0] jtag_read_write,
output [interfaces-1:0] jtag_waitrequest,
// AVMM output the interface and the CSR
input [interfaces-1:0] avmm_waitrequest,
output [interfaces-1:0] avmm_read,
output [interfaces-1:0] avmm_write,
output [interfaces*address_width-1:0] avmm_address,
output [interfaces*data_width-1:0] avmm_writedata
);
// General wires
wire [interfaces*total_masters-1:0] grant;
wire [interfaces-1:0] strm_grants;
wire [interfaces-1:0] user_read_write_lcl;
// Variables for the generate loops
genvar ig; // For bus widths
genvar jg; // For interfaces
generate for(jg=0;jg<interfaces;jg=jg+1) begin: g_arb
/*********************************************************************/
// case: 309705
// Simulation fix. When the user inputs drive x at the beginning of simulation,
// then even after a reset, the grant will have been assigned a value of x.
// since there is a loopback in the RTL, the value will continue to be x,
// and gets reflected on avmm_readdata and avmm_waitrequest. once an avmm master
// requests a read or write, the x value for grant will correct itself.
/**********************************************************************/
assign user_read_write_lcl[jg] =
// synthesis translate_off
(user_read_write[jg] === 1'bx) ? 1'b0 :
// synthesis translate_on
user_read_write[jg];
/**********************************************************************/
// Per Instance instantiations and assignments
// Priority in decreasing order is embedded reconfig -> user AVMM -> JTAG
/**********************************************************************/
alt_xcvr_arbiter #(
.width (total_masters)
) arbiter_inst (
.clock (reconfig_clk[jg]),
.req ({jtag_read_write[jg], user_read_write_lcl[jg], strm_read_write[jg]}),
.grant (grant[jg*total_masters+:total_masters])
);
// Assign the grant signal
assign strm_grants[jg] = grant[jg*total_masters];
// Use the grant as a mask for the various read and writes signals
// if you OR them all together, it will generate the read/write request if any are high
// For streamer write/read condition - if broadcasting, wait for all interfaces to receive grant before asserting write/read
assign avmm_write[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_write[jg], user_write[jg], ((~&strm_write | &strm_grants) & strm_write[jg])});
assign avmm_read[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_read[jg], user_read[jg], ((~&strm_read | &strm_grants) & strm_read[jg])});
// Split the wait request, and if the grant is asserted to any one master, assert wait request to all others
assign {jtag_waitrequest[jg], user_waitrequest[jg], strm_waitrequest[jg]} = (~grant[jg*total_masters+:total_masters] | {total_masters{avmm_waitrequest[jg]}});
// Since these are buses, the logic must be done in a bit-wise fashion; hence the for loop
// Generate the address for the bus width
for(ig=0; ig<address_width;ig=ig+1) begin: g_avmm_address
assign avmm_address[jg*address_width + ig] = |(grant[jg*total_masters+:total_masters] & {jtag_address[jg*address_width + ig], user_address[jg*address_width + ig], strm_address[jg*address_width + ig]});
end // End g_avmm_address
// Generate the write data for the bus width
for(ig=0; ig<data_width;ig=ig+1) begin: g_avmm_writdata
assign avmm_writedata[jg*data_width+ ig] = |(grant[jg*total_masters+:total_masters] & {jtag_writedata[jg*data_width + ig], user_writedata[jg*data_width + ig], strm_writedata[jg*data_width + ig]});
end // End g_avmm_writedata
end //End for interface-wise for loop
endgenerate // End generate
endmodule
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_xcvr_pll_embedded_debug #(
parameter dbg_capability_reg_enable = 0,
parameter dbg_user_identifier = 0,
parameter dbg_stat_soft_logic_enable = 0,
parameter dbg_ctrl_soft_logic_enable = 0,
parameter en_master_cgb = 0
) (
// avmm signals
input avmm_clk,
input avmm_reset,
input [8:0] avmm_address,
input [7:0] avmm_writedata,
input avmm_write,
input avmm_read,
output [7:0] avmm_readdata,
output avmm_waitrequest,
// input signals from the core
input in_pll_powerdown,
input in_pll_locked,
input in_pll_cal_busy,
input in_avmm_busy,
// output signals to the ip
output out_pll_powerdown
);
wire prbs_done_sync;
wire csr_prbs_snapshot;
wire csr_prbs_count_en;
wire csr_prbs_reset;
wire [47:0] prbs_err_count;
wire [47:0] prbs_bit_count;
alt_xcvr_pll_avmm_csr #(
.dbg_capability_reg_enable ( dbg_capability_reg_enable ),
.dbg_user_identifier ( dbg_user_identifier ),
.dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
.dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
.en_master_cgb ( en_master_cgb)
) embedded_debug_soft_csr (
// avmm signals
.avmm_clk (avmm_clk),
.avmm_reset (avmm_reset),
.avmm_address (avmm_address),
.avmm_writedata (avmm_writedata),
.avmm_write (avmm_write),
.avmm_read (avmm_read),
.avmm_readdata (avmm_readdata),
.avmm_waitrequest (avmm_waitrequest),
// input status signals from the channel
.pll_powerdown (in_pll_powerdown),
.pll_locked (in_pll_locked),
.pll_cal_busy (in_pll_cal_busy),
.avmm_busy (in_avmm_busy),
// output control signals
.csr_pll_powerdown (out_pll_powerdown)
);
endmodule
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Module: alt_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
// INIT_VALUE
// - Specifies the initial values of the synchronization registers.
//
// Apply embedded false path timing constraint
(* altera_attribute = "-name SDC_STATEMENT \"set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}\"" *)
`timescale 1ps/1ps
module alt_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming. Must be >1
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0, // See description above
parameter INIT_VALUE = 0
) (
input wire clk,
input wire reset,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
(* altera_attribute = "disable_da_rule=D103" *)
reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
assign q[ig] = sync_r[INT_LEN-1]; // Output signal
always @(posedge clk or posedge reset)
if(reset)
sync_r <= L_INIT_VALUE;
else
sync_r <= {sync_r[INT_LEN-2:0],d_in};
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r = L_INIT_VALUE[0];
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Common functions for Arria 10 Native PHY IP
//
`timescale 1 ps/1 ps
package altera_xcvr_native_a10_functions_h;
localparam MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10 = 128;
localparam MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10 = 64;
localparam integer MAX_CHARS_ALT_XCVR_NATIVE_A10 = 86; // To accomodate LONG parameter lists.
////////////////////////////////////////////////////////////////////
// Return the number of bits required to represent an integer
// E.g. 0->1; 1->1; 2->2; 3->2 ... 31->5; 32->6
//
function integer clogb2_alt_xcvr_native_a10;
input integer input_num;
begin
for (clogb2_alt_xcvr_native_a10=0; input_num>0; clogb2_alt_xcvr_native_a10=clogb2_alt_xcvr_native_a10+1)
input_num = input_num >> 1;
if(clogb2_alt_xcvr_native_a10 == 0)
clogb2_alt_xcvr_native_a10 = 1;
end
endfunction
////////////////////////////////////////////////////////////////////
// Used to calculate the value of the "hssi_10g_tx_pcs_comp_cnt"
// parameter for a givin channel in a bonded configuration
//
// @param channels - Number of channels in the interface
// @param pcs_bonding_master - PCS master channel index
// @param channel_index - Index of channel within interface to determine
// parameter value for.
//
// @return An integer value for the parameter "hssi_10g_tx_pcs_comp_cnt".
function [7:0] get_comp_cnt_alt_xcvr_native_a10;
input integer channels;
input integer pcs_bonding_master;
input integer channel_index;
integer max_index;
integer comp_cnt;
begin
// Determine the index of the master
max_index = (pcs_bonding_master > (channels - pcs_bonding_master)) ? pcs_bonding_master
: (channels-pcs_bonding_master);
// Determine the index of this channel
if (channel_index == pcs_bonding_master)
comp_cnt = max_index;
else if (channel_index < pcs_bonding_master)
comp_cnt = max_index - (pcs_bonding_master - channel_index);
else
comp_cnt = max_index - (channel_index - pcs_bonding_master);
// Convert index to count value
comp_cnt = comp_cnt * 2;
get_comp_cnt_alt_xcvr_native_a10 = comp_cnt[7:0];
end
endfunction
////////////////////////////////////////////////////////////////////
// Used to calculate the value of the distance of current channel to mcgb
//
// @param pcs_bonding_master - PCS master channel index
// @param channel_index - Index of channel within interface to determine
// parameter value for.
//
// @return An 4 bits value for the parameter lower 3 showing distance, if MSB 1 then the current channel is above the mcgb
function [3:0] get_mcgb_location_alt_xcvr_native_a10(
input integer pcs_bonding_master,
input integer channel_index
);
integer distance;
begin
if (channel_index < pcs_bonding_master) begin
distance = pcs_bonding_master-channel_index;
get_mcgb_location_alt_xcvr_native_a10 = {1'b1,distance[2:0]};
end else begin
distance = channel_index-pcs_bonding_master;
get_mcgb_location_alt_xcvr_native_a10 = {1'b0,distance[2:0]};
end
end
endfunction
function automatic [MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10-1:0] str_2_bin_alt_xcvr_native_a10;
input [MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10*8-1:0] instring;
integer this_char;
integer i;
begin
// Initialize accumulator
str_2_bin_alt_xcvr_native_a10 = {MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10{1'b0}};
for(i=MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10-1;i>=0;i=i-1) begin
this_char = instring[i*8+:8];
// Add value of this digit
if(this_char >= 48 && this_char <= 57)
str_2_bin_alt_xcvr_native_a10 = (str_2_bin_alt_xcvr_native_a10 * 10) + (this_char - 48);
end
end
endfunction
////////////////////////////////////////////////////////////////////
// Adds an offets to 'scrambler seed' per channel for interlaken as:
// (58'h123456789abcde + user_seed + (24'h826a3*lane_number))
// see FB 138336 for details
//
// @param protocol_hint - only interlaken matters
// @param user_seed - 58 bit base seed to be modified per channel
// @param lane_number - Index of channel within interface to determine
// parameter value for.
//
// @return 58 bits scrambler seed for the channel
function [57:0] set_10g_scrm_seed_user_alt_xcvr_native_a10 (
input [8*MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10:1] protocol_hint,
input [57:0] user_seed,
input integer lane_number
);
set_10g_scrm_seed_user_alt_xcvr_native_a10 = (protocol_hint == "interlaken_mode") ? (58'h123456789abcde + user_seed + (24'h826a3*lane_number)) : user_seed;
endfunction
////////////////////////////////////////////////////////////////////
// Convert an integer to a string
function [MAX_CHARS_ALT_XCVR_NATIVE_A10*8-1:0] int2str_alt_xcvr_native_a10(
input integer in_int
);
integer i;
integer this_char;
i = 0;
int2str_alt_xcvr_native_a10 = "";
do
begin
this_char = (in_int % 10) + 48;
int2str_alt_xcvr_native_a10[i*8+:8] = this_char[7:0];
i=i+1;
in_int = in_int / 10;
end
while(in_int > 0);
endfunction
endpackage
./twentynm_xcvr_avmm.sv
./alt_xcvr_resync.sv
./alt_xcvr_arbiter.sv
./a10_avmm_h.sv
./altera_xcvr_native_a10_functions_h.sv
./alt_xcvr_atx_pll_rcfg_arb.sv
./a10_xcvr_atx_pll.sv
./alt_xcvr_pll_embedded_debug.sv
./alt_xcvr_pll_avmm_csr.sv
// Copyright (C) 2018 Intel Corporation. All rights reserved.
// This simulation model contains highly confidential and
// proprietary information of Intel and is being provided
// in accordance with and subject to the protections of the
// applicable Intel Program License Subscription Agreement
// which governs its use and disclosure. Your use of Intel
// Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions,
// and any output files any of the foregoing (including device
// programming or simulation files), and any associated
// documentation or information are expressly subject to the
// terms and conditions of the Intel Program License Subscription
// Agreement, the Intel Quartus Prime License Agreement, the
// Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is
// for the sole purpose of simulating designs for use exclusively
// in logic devices manufactured by Intel and sold by Intel or
// its authorized distributors. Please refer to the applicable
// agreement for further details. Intel products and services
// are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
// Intel assumes no responsibility or liability arising out of the
// application or use of this simulation model.
// ACDS 18.1std
// ALTERA_TIMESTAMP:Thu Sep 13 01:35:04 PDT 2018
// encrypted_file_type : local_encrypted
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6e"
`pragma protect author = "Altera"
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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ey++PWhyOjangq0CwH9dIAIJv0tOQMOClKdst5WxgNc=
`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 2976)
YS5mUtE6M/T991SP8VQvvNsJA4VcZQn2Hts5BUnTJj2GwzItvWSuA5naHA4Iiyyq
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`pragma protect end_protected
./mentor/twentynm_xcvr_avmm.sv
./mentor/alt_xcvr_resync.sv
./mentor/alt_xcvr_arbiter.sv
./a10_avmm_h.sv
./altera_xcvr_native_a10_functions_h.sv
./mentor/alt_xcvr_atx_pll_rcfg_arb.sv
./mentor/a10_xcvr_atx_pll.sv
./mentor/alt_xcvr_pll_embedded_debug.sv
./mentor/alt_xcvr_pll_avmm_csr.sv
./twentynm_xcvr_avmm.sv
./alt_xcvr_resync.sv
./alt_xcvr_arbiter.sv
./a10_avmm_h.sv
./altera_xcvr_native_a10_functions_h.sv
./alt_xcvr_atx_pll_rcfg_arb.sv
./a10_xcvr_atx_pll.sv
./alt_xcvr_pll_embedded_debug.sv
./alt_xcvr_pll_avmm_csr.sv
./twentynm_xcvr_avmm.sv
./alt_xcvr_resync.sv
./alt_xcvr_arbiter.sv
./a10_avmm_h.sv
./altera_xcvr_native_a10_functions_h.sv
./alt_xcvr_atx_pll_rcfg_arb.sv
./a10_xcvr_atx_pll.sv
./alt_xcvr_pll_embedded_debug.sv
./alt_xcvr_pll_avmm_csr.sv
config wr_arria10_e3p1_atx_pll_cfg;
design wr_arria10_e3p1_atx_pll;
instance wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0 use wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua;
endconfig
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