Commit c418861a authored by li hongming's avatar li hongming Committed by Grzegorz Daniluk

change the pin location of ext_clk for cute-wr-dpV2.2

    change the function of LEDs:
      the front end LEDs display the status of link and sync.
      the on-board LEDS display the act of link and PPS.
parent 78a0b31e
...@@ -78,6 +78,7 @@ ...@@ -78,6 +78,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -1207,9 +1208,6 @@ ...@@ -1207,9 +1208,6 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="290"/> <association xil_pn:name="Implementation" xil_pn:seqID="290"/>
</file> </file>
<file xil_pn:name="../../board/cute/cute_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="291"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="292"/> <association xil_pn:name="Implementation" xil_pn:seqID="292"/>
</file> </file>
......
...@@ -111,7 +111,6 @@ net "plldac_sclk" loc = c2;net "plldac_sclk" iostandard = lvcmos33; ...@@ -111,7 +111,6 @@ net "plldac_sclk" loc = c2;net "plldac_sclk" iostandard = lvcmos33;
net "plldac_sync_n" loc = d1;net "plldac_sync_n" iostandard = lvcmos33; net "plldac_sync_n" loc = d1;net "plldac_sync_n" iostandard = lvcmos33;
net "plldac_load_n" loc = d2;net "plldac_load_n" iostandard = lvcmos33; net "plldac_load_n" loc = d2;net "plldac_load_n" iostandard = lvcmos33;
net "ext_clk" loc = f2;net "ext_clk" iostandard = lvcmos33;
net "sfp1_led" loc = g3;net "sfp1_led" iostandard = lvcmos33; net "sfp1_led" loc = g3;net "sfp1_led" iostandard = lvcmos33;
net "sfp0_led" loc = k4;net "sfp0_led" iostandard = lvcmos33; net "sfp0_led" loc = k4;net "sfp0_led" iostandard = lvcmos33;
net "sfp0_los" loc = g1;net "sfp0_los" iostandard = lvcmos33; net "sfp0_los" loc = g1;net "sfp0_los" iostandard = lvcmos33;
...@@ -157,4 +156,8 @@ TIMESPEC TS_u_wr_core_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch_gtp_clkout_i ...@@ -157,4 +156,8 @@ TIMESPEC TS_u_wr_core_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch_gtp_clkout_i
inst "pps_out" iob = force; inst "pps_out" iob = force;
net "pps_out" drive = 24 | slew = fast; net "pps_out" drive = 24 | slew = fast;
#cute-wr-dp V2.1
#net "ext_clk" loc = f2;net "ext_clk" iostandard = lvcmos33;
#cute-wr-dp V2.2
net "ext_clk" loc = k3;net "ext_clk" iostandard = lvcmos33;
net "ext_clk" drive = 24 | slew = fast; net "ext_clk" drive = 24 | slew = fast;
...@@ -189,8 +189,10 @@ architecture rtl of cute_wr_ref_top is ...@@ -189,8 +189,10 @@ architecture rtl of cute_wr_ref_top is
attribute maxdelay : string; attribute maxdelay : string;
attribute maxdelay of pps_csync : signal is "500 ps"; attribute maxdelay of pps_csync : signal is "500 ps";
signal tm_tai : std_logic_vector(39 downto 0); signal tm_tai : std_logic_vector(39 downto 0);
signal tm_tai_valid : std_logic; signal tm_time_valid : std_logic;
signal tm_tai_valid_d1 : std_logic; signal tm_link_up : std_logic;
signal pps_led : std_logic;
signal led_act : std_logic;
-- Wishbone buse(s) from masters attached to crossbar -- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(0 downto 0); signal cnx_master_out : t_wishbone_master_out_array(0 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(0 downto 0); signal cnx_master_in : t_wishbone_master_in_array(0 downto 0);
...@@ -285,17 +287,17 @@ begin ...@@ -285,17 +287,17 @@ begin
wb_eth_master_o => cnx_master_out(0), wb_eth_master_o => cnx_master_out(0),
wb_eth_master_i => cnx_master_in(0), wb_eth_master_i => cnx_master_in(0),
tm_link_up_o => open, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_tai_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
tm_cycles_o => open, tm_cycles_o => open,
led_act_o => sfp0_led, led_act_o => led_act,
led_link_o => sfp1_led, led_link_o => open,
pps_p_o => pps_out, pps_p_o => pps_out,
pps_led_o => usr_led1, pps_led_o => pps_led,
pps_csync_o => pps_csync, pps_csync_o => pps_csync,
link_ok_o => usr_led2); link_ok_o => open);
cnx_slave_in <= cnx_master_out; cnx_slave_in <= cnx_master_out;
cnx_master_in <= cnx_slave_out; cnx_master_in <= cnx_slave_out;
...@@ -320,4 +322,10 @@ begin ...@@ -320,4 +322,10 @@ begin
one_wire <= '0' when onewire_oen_o = '1' else 'Z'; one_wire <= '0' when onewire_oen_o = '1' else 'Z';
onewire_i <= one_wire; onewire_i <= one_wire;
sfp0_led <= not led_act;
sfp1_led <= not pps_led;
usr_led1 <= not tm_time_valid;
usr_led2 <= not tm_link_up;
end rtl; end rtl;
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