Commit c2bc0d5e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wrc_core: expose PHY LPC interface

parent 963536bb
Pipeline #218 failed with stages
in 2 minutes
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2019-07-24
-- Last update: 2020-03-30
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -163,8 +163,8 @@ entity wr_core is
phy_sfp_tx_disable_o : out std_logic;
phy_rx_rbclk_sampled_i : in std_logic;
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0);
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
-- PHY I/F record-based
......@@ -785,9 +785,9 @@ begin
phy_rx_k_i => phy_rx_k_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy_debug_o => phy_debug_o,
phy_debug_i => phy_debug_i,
phy_lpc_stat_i => phy_lpc_stat_i,
phy_lpc_ctrl_o => phy_lpc_ctrl_o,
phy8_o => phy8_o,
phy8_i => phy8_i,
phy16_o => phy16_o,
......@@ -816,7 +816,7 @@ begin
led_act_o => led_act_o);
led_link_o <= ep_led_link;
link_ok_o <= ep_led_link;
link_ok_o <= '1'; --ep_led_link;
tm_link_up_o <= ep_led_link;
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2019-06-17
-- Last update: 2020-03-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -426,8 +426,9 @@ package wrcore_pkg is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_rx_rbclk_sampled_i : in std_logic := '0';
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0) := x"0000";
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0) := x"0000";
-----------------------------------------
-- PHY I/f - record-based
......@@ -601,8 +602,8 @@ package wrcore_pkg is
phy_sfp_tx_disable_o : out std_logic;
phy_rx_rbclk_sampled_i : in std_logic := '0';
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0) := x"0000";
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0) := x"0000";
-----------------------------------------
-- PHY I/f - record-based
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2019-03-29
-- Last update: 2020-03-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -155,8 +155,8 @@ entity xwr_core is
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0);
phy_lpc_stat_i : in std_logic_vector(15 downto 0);
phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
phy_rst_o : out std_logic;
phy_rdy_i : in std_logic := '1';
......@@ -340,8 +340,8 @@ begin
phy_rdy_i => phy_rdy_i,
phy_loopen_o => phy_loopen_o,
phy_loopen_vec_o => phy_loopen_vec_o,
phy_debug_o => phy_debug_o,
phy_debug_i => phy_debug_i,
phy_lpc_ctrl_o => phy_lpc_ctrl_o,
phy_lpc_stat_i => phy_lpc_stat_i,
phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
phy_sfp_los_i => phy_sfp_los_i,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment