virtex5: bypass internal PHY 8b10b decoder + improved alignment detect/reset

bf13e6b9 · Tomasz Wlostowski · 7da2290b · bf13e6b9 · bf13e6b9 · bf13e6b9
Commit bf13e6b9 authored Dec 07, 2020 by Tomasz Wlostowski
4 changed files
--- a/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/platform/xilinx/wr_gtp_phy/Manifest.py
@@ -20,7 +20,9 @@ elif (syn_device[0:4].upper()=="XC5V"): # Virtex5
    files.extend(["virtex5/wr_gtp_phy_virtex5.vhd",
        "virtex5/whiterabbit_gtp_wrapper_tile_virtex5.vhd",
        "spartan6/gtp_phase_align.vhd",
-        "virtex5/v5_gtp_align_detect.vhd"])
+        "virtex5/v5_gtp_align_detect.vhd",
+        "virtex5/v5_gtp_comma_detect.vhd"
+    ])
 elif (syn_device[0:4].upper()=="XC7A"): # Family 7 GTP (Artix7)
    files.extend(["family7-gtp/wr_gtp_phy_family7.vhd",
        "family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd",

--- a/platform/xilinx/wr_gtp_phy/virtex5/v5_gtp_comma_detect.vhd
+++ b/platform/xilinx/wr_gtp_phy/virtex5/v5_gtp_comma_detect.vhd
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity v5_gtp_comma_detect is
+  port (
+    clk_rx_i : in std_logic;
+    rst_n_i  : in std_logic;
+
+    rx_data_raw_i : in std_logic_vector(9 downto 0);
+
+    rx_is_comma_o : out std_logic;
+    link_up_o : out std_logic;
+    aligned_o : out std_logic
+    );
+
+end v5_gtp_comma_detect;
+
+architecture rtl of v5_gtp_comma_detect is
+
+  type t_state is (SYNC_LOST, SYNC_CHECK, SYNC_ACQUIRED);
+
+  constant c_IDLE_LENGTH_UP   : integer := 500;
+  constant c_IDLE_LENGTH_LOSS : integer := 1000;
+
+  constant c_COMMA_SHIFT_WE_WANT : integer := 0;
+-- fixme
+
+  signal rx_data_d0     : std_logic_vector(9 downto 0);
+  signal rx_data_merged : std_logic_vector(19 downto 0);
+
+  signal first_comma : std_logic_vector(4 downto 0);
+  signal cnt         : unsigned(15 downto 0);
+  signal state       : t_state;
+  signal comma_found : std_logic_vector(9 downto 0);
+
+  
+  function f_onehot_encode (x : std_logic_vector; output_bits : integer)return std_logic_vector is
+    variable rv : std_logic_vector(output_bits-1 downto 0);
+  begin
+    for i in 0 to x'length-1 loop
+      if x(i) = '1' then
+        rv := std_logic_vector(to_unsigned(i, output_bits));
+        return rv;
+      end if;
+    end loop;
+
+    return std_logic_vector(to_unsigned(0, output_bits));
+  end f_onehot_encode;
+
+  constant c_K28_5_PLUS : std_logic_vector(9 downto 0) := "1100000101"; --"1010000011";
+
+  signal comma_pos            : std_logic_vector(4 downto 0);
+  signal prev_comma_pos       : std_logic_vector(4 downto 0);
+  signal prev_comma_pos_valid : std_logic;
+  signal comma_pos_valid      : std_logic;
+  signal link_up : std_logic;
+  signal link_aligned : std_logic;
+  
+begin
+
+
+  process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_i = '0' then
+        comma_found <= (others => '0');
+      else
+        rx_data_d0                  <= rx_data_raw_i;
+        rx_data_merged(19 downto 0) <= rx_data_d0 & rx_data_raw_i;
+        for i in 0 to 9 loop
+          if rx_data_merged(i + 9 downto i) = c_K28_5_PLUS or
+            rx_data_merged(i + 9 downto i) = (not c_K28_5_PLUS) then
+            comma_found(i) <= '1';
+          else
+            comma_found(i) <= '0';
+          end if;
+        end loop;
+
+        comma_pos <= f_onehot_encode(comma_found, comma_pos'length);
+
+        if unsigned(comma_found) /= 0 then
+          comma_pos_valid <= '1';
+        else
+          comma_pos_valid <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_rx_i)
+  begin
+    if rising_edge(clk_rx_i) then
+      if rst_n_i = '0' then
+        link_aligned <= '0';
+      else
+        if comma_pos_valid = '1' then
+          if unsigned(comma_pos) = c_COMMA_SHIFT_WE_WANT then
+            link_aligned <= '1';
+          else
+            link_aligned <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  rx_is_comma_o <= '1' when unsigned(comma_found) /= 0 else '0';
+
+  aligned_o <= link_aligned;
+  link_up_o <= link_up;
+  
+end rtl;
+
--- a/platform/xilinx/wr_gtp_phy/virtex5/whiterabbit_gtp_wrapper_tile_virtex5.vhd
+++ b/platform/xilinx/wr_gtp_phy/virtex5/whiterabbit_gtp_wrapper_tile_virtex5.vhd
@@ -532,8 +532,8 @@ begin
        RXCHARISK0(0)                   =>      RXCHARISK0_OUT,
        RXCHARISK1(1)                   =>      rxcharisk1_float_i,
        RXCHARISK1(0)                   =>      RXCHARISK1_OUT,
-        RXDEC8B10BUSE0                  =>      tied_to_vcc_i,
-        RXDEC8B10BUSE1                  =>      tied_to_vcc_i,
+        RXDEC8B10BUSE0                  =>      '0',
+        RXDEC8B10BUSE1                  =>      '0',
        RXDISPERR0(1)                   =>      rxdisperr0_float_i,
        RXDISPERR0(0)                   =>      RXDISPERR0_OUT,
        RXDISPERR1(1)                   =>      rxdisperr1_float_i,

--- a/platform/xilinx/wr_gtp_phy/virtex5/wr_gtp_phy_virtex5.vhd
+++ b/platform/xilinx/wr_gtp_phy/virtex5/wr_gtp_phy_virtex5.vhd