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White Rabbit core collection
Commit bcf8ff2b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_core: expose UART FIFO configuration to wr_core generics

parent c2bc0d5e
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      modules/wrc_core/wr_core.vhd
      View file @ bcf8ff2b
      ......@@ -6,7 +6,7 @@
      -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
      -- Company : CERN (BE-CO-HT)
      -- Created : 2011-02-02
      -- Last update: 2020-03-30
      -- Last update: 2020-08-19
      -- Platform : FPGA-generics
      -- Standard : VHDL
      -------------------------------------------------------------------------------
      ......@@ -83,6 +83,9 @@ entity wr_core is
      g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
      g_phys_uart : boolean := true;
      g_virtual_uart : boolean := true;
      g_with_phys_uart_fifo : boolean := false;
      g_phys_uart_tx_fifo_size : integer := 1024;
      g_phys_uart_rx_fifo_size : integer := 1024;
      g_aux_clks : integer := 0;
      g_rx_buffer_size : integer := 1024;
      g_tx_runt_padding : boolean := true;
      ......@@ -912,6 +915,9 @@ begin
      g_virtual_uart => g_virtual_uart,
      g_mem_words => g_dpram_size,
      g_vuart_fifo_size => g_vuart_fifo_size,
      g_with_phys_uart_fifo => g_with_phys_uart_fifo,
      g_phys_uart_tx_fifo_size => g_phys_uart_tx_fifo_size,
      g_phys_uart_rx_fifo_size => g_phys_uart_rx_fifo_size,
      g_diag_id => g_diag_id,
      g_diag_ver => g_diag_ver,
      g_diag_ro_size => g_diag_ro_size,
      ......
      modules/wrc_core/wrc_periph.vhd
      View file @ bcf8ff2b
      ......@@ -6,7 +6,7 @@
      -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
      -- Company : CERN (BE-CO-HT)
      -- Created : 2011-04-04
      -- Last update: 2018-03-08
      -- Last update: 2020-08-19
      -- Platform : FPGA-generics
      -- Standard : VHDL
      -------------------------------------------------------------------------------
      ......@@ -51,6 +51,9 @@ entity wrc_periph is
      g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
      g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
      g_phys_uart : boolean := true;
      g_with_phys_uart_fifo : boolean := false;
      g_phys_uart_tx_fifo_size : integer := 1024;
      g_phys_uart_rx_fifo_size : integer := 1024;
      g_virtual_uart : boolean := false;
      g_cntr_period : integer := 62500;
      g_mem_words : integer := 16384; --in 32-bit words
      ......@@ -424,7 +427,10 @@ begin
      g_with_physical_uart => g_phys_uart,
      g_interface_mode => PIPELINED,
      g_address_granularity => BYTE,
      g_vuart_fifo_size => g_vuart_fifo_size
      g_vuart_fifo_size => g_vuart_fifo_size,
      g_WITH_PHYSICAL_UART_FIFO => g_with_phys_uart_fifo,
      g_TX_FIFO_SIZE => g_phys_uart_tx_fifo_size,
      g_RX_FIFO_SIZE => g_phys_uart_rx_fifo_size
      )
      port map(
      clk_sys_i => clk_sys_i,
      ......
      modules/wrc_core/wrcore_pkg.vhd
      View file @ bcf8ff2b
      ......@@ -6,7 +6,7 @@
      -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
      -- Company : CERN (BE-CO-HT)
      -- Created : 2011-05-11
      -- Last update: 2020-03-11
      -- Last update: 2020-08-19
      -- Platform : FPGA-generics
      -- Standard : VHDL
      -------------------------------------------------------------------------------
      ......@@ -253,7 +253,10 @@ package wrcore_pkg is
      g_diag_id : integer := 0;
      g_diag_ver : integer := 0;
      g_diag_ro_size : integer := 0;
      g_diag_rw_size : integer := 0
      g_diag_rw_size : integer := 0;
      g_with_phys_uart_fifo : boolean := false;
      g_phys_uart_tx_fifo_size : integer := 1024;
      g_phys_uart_rx_fifo_size : integer := 1024
      );
      port(
      clk_sys_i : in std_logic;
      ......@@ -368,7 +371,11 @@ package wrcore_pkg is
      g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
      g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
      g_phys_uart : boolean := true;
      g_with_phys_uart_fifo : boolean := false;
      g_phys_uart_tx_fifo_size : integer := 1024;
      g_phys_uart_rx_fifo_size : integer := 1024;
      g_virtual_uart : boolean := true;
      g_with_external_clock_input : boolean := true;
      g_aux_clks : integer := 0;
      g_ep_rxbuf_size : integer := 1024;
      ......@@ -519,6 +526,9 @@ package wrcore_pkg is
      g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
      g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
      g_phys_uart : boolean := true;
      g_with_phys_uart_fifo : boolean := false;
      g_phys_uart_tx_fifo_size : integer := 1024;
      g_phys_uart_rx_fifo_size : integer := 1024;
      g_virtual_uart : boolean := true;
      g_aux_clks : integer := 0;
      g_rx_buffer_size : integer := 1024;
      ......
      modules/wrc_core/xwr_core.vhd
      View file @ bcf8ff2b
      ......@@ -6,7 +6,7 @@
      -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
      -- Company : CERN (BE-CO-HT)
      -- Created : 2011-02-02
      -- Last update: 2020-03-11
      -- Last update: 2020-08-19
      -- Platform : FPGA-generics
      -- Standard : VHDL
      -------------------------------------------------------------------------------
      ......@@ -81,6 +81,9 @@ entity xwr_core is
      g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
      g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
      g_phys_uart : boolean := true;
      g_with_phys_uart_fifo : boolean := false;
      g_phys_uart_tx_fifo_size : integer := 1024;
      g_phys_uart_rx_fifo_size : integer := 1024;
      g_virtual_uart : boolean := true;
      g_aux_clks : integer := 0;
      g_ep_rxbuf_size : integer := 1024;
      ......@@ -287,6 +290,9 @@ begin
      g_flash_secsz_kb => g_flash_secsz_kb,
      g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
      g_phys_uart => g_phys_uart,
      g_with_phys_uart_fifo => g_with_phys_uart_fifo,
      g_phys_uart_tx_fifo_size => g_phys_uart_tx_fifo_size,
      g_phys_uart_rx_fifo_size => g_phys_uart_rx_fifo_size,
      g_virtual_uart => g_virtual_uart,
      g_rx_buffer_size => g_ep_rxbuf_size,
      g_tx_runt_padding => g_tx_runt_padding,
      ......
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