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White Rabbit core collection
Commit b2edc7ba authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_minic: added structized wrapper + updated Manifest

parent 0f14c50b
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modules/wr_mini_nic/Manifest.py
View file @ b2edc7ba
files = [ "minic_packet_buffer.vhd",
"minic_wb_slave.vhd",
"minic_wbgen2_pkg.vhd",
"wr_mini_nic.vhd" ];
"wr_mini_nic.vhd",
"xwr_mini_nic.vhd" ];
modules/wr_mini_nic/xwr_mini_nic.vhd 0 → 100644
View file @ b2edc7ba
library ieee;
use ieee.std_logic_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
entity xwr_mini_nic is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_memsize_log2 : integer := 14;
g_buffer_little_endian : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- System memory i/f
-------------------------------------------------------------------------------
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
-------------------------------------------------------------------------------
-- Pipelined Wishbone interface
-------------------------------------------------------------------------------
-- WBP Master (TX)
src_o: out t_wrf_source_out;
src_i: in t_wrf_source_in;
-- WBP Slave (RX)
snk_o: out t_wrf_sink_out;
snk_i: in t_wrf_sink_in;
-------------------------------------------------------------------------------
-- TXTSU i/f
-------------------------------------------------------------------------------
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone slave
-------------------------------------------------------------------------------
wb_i: in t_wishbone_slave_in;
wb_o: out t_wishbone_slave_out
);
end xwr_mini_nic;
architecture wrapper of xwr_mini_nic is
component wr_mini_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_err_i : in std_logic;
src_ack_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_ack_o : out std_logic;
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic);
end component;
begin -- wrapper
wr_mini_nic_1: wr_mini_nic
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_memsize_log2 => g_memsize_log2,
g_buffer_little_endian => g_buffer_little_endian)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
mem_data_o => mem_data_o,
mem_addr_o => mem_addr_o,
mem_data_i => mem_data_i,
mem_wr_o => mem_wr_o,
src_dat_o => src_o.dat,
src_adr_o => src_o.adr,
src_sel_o => src_o.sel,
src_cyc_o => src_o.cyc,
src_stb_o => src_o.stb,
src_we_o => src_o.we,
src_stall_i => src_i.stall,
src_err_i => src_i.err,
src_ack_i => src_i.ack,
snk_dat_i => snk_i.dat,
snk_adr_i => snk_i.adr,
snk_sel_i => snk_i.sel,
snk_cyc_i => snk_i.cyc,
snk_stb_i => snk_i.stb,
snk_we_i => snk_i.we,
snk_stall_o => snk_o.stall,
snk_err_o => snk_o.err,
snk_ack_o => snk_o.ack,
txtsu_port_id_i => txtsu_port_id_i,
txtsu_frame_id_i => txtsu_frame_id_i,
txtsu_tsval_i => txtsu_tsval_i,
txtsu_valid_i => txtsu_valid_i,
txtsu_ack_o => txtsu_ack_o,
wb_cyc_i => wb_i.cyc,
wb_stb_i => wb_i.stb,
wb_we_i => wb_i.we,
wb_sel_i => wb_i.sel,
wb_adr_i => wb_i.adr,
wb_dat_i => wb_i.dat,
wb_dat_o => wb_o.dat,
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
wb_irq_o => wb_o.int);
end wrapper;
modules/wrc_core/Manifest.py 0 → 100644
View file @ b2edc7ba
files = [ "wr_core.vhd",
"wrc_dpram.vhd",
"wrcore_pkg.vhd",
"wrc_periph.vhd",
"wb_reset.vhd" ];
fetchto = "../../ip_cores"
modules/wrc_lm32/Manifest.py
View file @ b2edc7ba
......@@ -10,5 +10,8 @@ files = [ "wrc_lm32.vhd",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_interrupt.v",
"lm32_dp_ram.v"
"lm32_dp_ram.v",
"lm32_debug.v",
"lm32_jtag.v",
"jtag_wb.v"
];
\ No newline at end of file
modules/wrc_lm32/jtag_wb.v 0 → 100644
View file @ b2edc7ba
/* Added by GSI to support debug over wishbone */
`define ACK_DELAY 8 /* Give the JTAG core time to latch after a write */
module jtag_wb (
clk_i,
DAT_I,
ADR_I,
CYC_I,
SEL_I,
STB_I,
WE_I,
reg_d,
reg_addr_d,
ACK_O,
STALL_O,
DAT_O,
reg_update,
reg_q,
reg_addr_q,
jtck,
jrstn
);
input clk_i;
input [`LM32_WORD_RNG] DAT_I;
input [`LM32_WORD_RNG] ADR_I;
input CYC_I;
input [`LM32_BYTE_SELECT_RNG] SEL_I;
input STB_I;
input WE_I;
input [7:0] reg_d;
input [2:0] reg_addr_d;
output ACK_O;
output STALL_O;
output [`LM32_WORD_RNG] DAT_O;
output reg_update;
output [7:0] reg_q;
output [2:0] reg_addr_q;
output jtck;
output jrstn;
reg [7:0] reg_q;
reg [2:0] reg_addr_q;
reg [`ACK_DELAY-1:0] ack_shift;
assign reg_update = (CYC_I == `TRUE) &&
(STB_I == `TRUE) &&
(WE_I == `TRUE);
assign DAT_O[31:11] = 21'h0;
assign DAT_O[10:3] = reg_d;
assign DAT_O[2:0] = reg_addr_d;
assign jtck = clk_i;
assign jrstn = 1;
assign ACK_O = ack_shift[0];
assign STALL_O = |ack_shift[`ACK_DELAY-1:1];
always @(posedge clk_i)
begin
ack_shift <=
{CYC_I == `TRUE && STB_I == `TRUE && STALL_O == `FALSE,
ack_shift[`ACK_DELAY-1:1]};
if (reg_update == `TRUE)
begin
reg_q <= DAT_I[10:3];
reg_addr_q <= DAT_I[2:0];
end
end
endmodule
modules/wrc_lm32/lm32_interrupt.v
View file @ b2edc7ba
......@@ -191,12 +191,18 @@ endgenerate
// Sequential Logic
/////////////////////////////////////////////////////
`define IE_DELAY 10
reg [`IE_DELAY:0] eie_delay = 0;
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
......@@ -206,6 +212,8 @@ begin
`endif
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
else
begin
......@@ -234,9 +242,20 @@ begin
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
if(eie_delay[0])
ie <= eie;
eie_delay <= {1'b0, eie_delay[`IE_DELAY:1]};
if (eret_q_x == `TRUE) begin
// Restore interrupt enable
eie_delay[`IE_DELAY] <= `TRUE;
eie_delay[`IE_DELAY-1:0] <= 0;
end
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
......@@ -266,7 +285,7 @@ else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
......@@ -275,6 +294,7 @@ begin
bie <= `FALSE;
`endif
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
else
begin
......@@ -303,9 +323,18 @@ begin
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
if(eie_delay[0])
ie <= eie;
eie_delay <= {1'b0, eie_delay[`IE_DELAY:1]};
if (eret_q_x == `TRUE) begin
// Restore interrupt enable
eie_delay[`IE_DELAY] <= `TRUE;
eie_delay[`IE_DELAY-1:0] <= 0;
end
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
......
modules/wrc_lm32/lm32_top.v
View file @ b2edc7ba
......@@ -51,6 +51,14 @@ module lm32_top (
I_ACK_I,
I_ERR_I,
I_RTY_I,
`endif
`ifdef CFG_JWB_ENABLED
J_DAT_I,
J_ADR_I,
J_CYC_I,
J_SEL_I,
J_STB_I,
J_WE_I,
`endif
// Data Wishbone master
D_DAT_I,
......@@ -75,6 +83,10 @@ module lm32_top (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
`endif
`ifdef CFG_JWB_ENABLED
J_ACK_O,
J_DAT_O,
`endif
// Data Wishbone master
D_DAT_O,
......@@ -85,7 +97,10 @@ module lm32_top (
D_WE_O,
D_CTI_O,
D_LOCK_O,
D_BTE_O
D_BTE_O,
trace_pc_o,
trace_eret_o,
trace_pc_valid_o
);
/////////////////////////////////////////////////////
......@@ -111,6 +126,15 @@ input I_ERR_I; // Instruction Wishbone interfac
input I_RTY_I; // Instruction Wishbone interface retry
`endif
`ifdef CFG_JWB_ENABLED
input [`LM32_WORD_RNG] J_DAT_I;
input [`LM32_WORD_RNG] J_ADR_I;
input J_CYC_I;
input [`LM32_BYTE_SELECT_RNG] J_SEL_I;
input J_STB_I;
input J_WE_I;
`endif
input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
input D_ACK_I; // Data Wishbone interface acknowledgement
input D_ERR_I; // Data Wishbone interface error
......@@ -152,6 +176,13 @@ output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interfac
wire [`LM32_BTYPE_RNG] I_BTE_O;
`endif
`ifdef CFG_JWB_ENABLED
output J_ACK_O;
wire J_ACK_O;
output [`LM32_WORD_RNG] J_DAT_O;
wire [`LM32_WORD_RNG] J_DAT_O;
`endif
output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
wire [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
......@@ -199,6 +230,21 @@ wire trace_bret; // Indicates a bret instruction
`endif
`endif
output [31:0] trace_pc_o;
output trace_pc_valid_o;
output trace_eret_o;
`ifdef CFG_TRACE_ENABLED
assign trace_eret_o = trace_eret;
assign trace_pc_o =trace_pc;
assign trace_pc_valid_o = trace_pc_valid;
`else
assign trace_eret_o = 0;
assign trace_pc_o = 0;
assign trace_pc_valid_o = 0;
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
......@@ -290,6 +336,29 @@ lm32_cpu cpu (
);
`ifdef CFG_JTAG_ENABLED
`ifdef CFG_JWB_ENABLED
jtag_wb jtag_wb (
// ----- Inputs -----
.clk_i (clk_i),
.DAT_I (J_DAT_I),
.ADR_I (J_ADR_I),
.CYC_I (J_CYC_I),
.SEL_I (J_SEL_I),
.STB_I (J_STB_I),
.WE_I (J_WE_I),
.reg_d (jtag_reg_d),
.reg_addr_d (jtag_reg_addr_d),
// ----- Outputs -----
.ACK_O (J_ACK_O),
.STALL_O (open),
.DAT_O (J_DAT_O),
.reg_update (jtag_update),
.reg_q (jtag_reg_q),
.reg_addr_q (jtag_reg_addr_q),
.jtck (jtck),
.jrstn (jrstn)
);
`else
// JTAG cores
jtag_cores jtag_cores (
// ----- Inputs -----
......@@ -303,5 +372,6 @@ jtag_cores jtag_cores (
.jrstn (jrstn)
);
`endif
`endif
endmodule
modules/wrc_lm32/system_conf.v
View file @ b2edc7ba
......@@ -36,12 +36,15 @@
//`define CFG_DCACHE_LIMIT 32'h7fffffff
// Enable Debugging
//`define CFG_JTAG_ENABLED
//`define CFG_JTAG_UART_ENABLED
//`define CFG_DEBUG_ENABLED
//`define CFG_HW_DEBUG_ENABLED
//`define CFG_BREAKPOINTS 32'h0
//`define CFG_WATCHPOINTS 32'h0
`define CFG_TRACE_ENABLED
`define CFG_JTAG_ENABLED
`define CFG_JTAG_UART_ENABLED
`define CFG_DEBUG_ENABLED
`define CFG_HW_DEBUG_ENABLED
`define CFG_BREAKPOINTS 32'h4
`define CFG_WATCHPOINTS 32'h4
`define CFG_JWB_ENABLED
`define CFG_INTERRUPTS_ENABLED
//`define CFG_BUS_ERRORS_ENABLED
......
modules/wrc_lm32/wrc_lm32.vhd
View file @ b2edc7ba
......@@ -18,6 +18,8 @@ entity wrc_lm32 is
iwb_dat_i : in std_logic_vector(31 downto 0);
iwb_cyc_o : out std_logic;
iwb_stb_o : out std_logic;
iwb_sel_o : out std_logic_vector(3 downto 0);
iwb_we_o : out std_logic;
iwb_ack_i : in std_logic;
dwb_adr_o : out std_logic_vector(g_addr_width-1 downto 0);
......@@ -27,7 +29,20 @@ entity wrc_lm32 is
dwb_stb_o : out std_logic;
dwb_sel_o : out std_logic_vector(3 downto 0);
dwb_we_o : out std_logic;
dwb_ack_i : in std_logic
dwb_ack_i : in std_logic;
jwb_adr_i : in std_logic_vector(g_addr_width-1 downto 0);
jwb_dat_i : in std_logic_vector(31 downto 0);
jwb_dat_o : out std_logic_vector(31 downto 0);
jwb_cyc_i : in std_logic;
jwb_stb_i : in std_logic;
jwb_sel_i : in std_logic_vector(3 downto 0);
jwb_we_i : in std_logic;
jwb_ack_o : out std_logic;
trace_pc_o: out std_logic_vector(31 downto 0);
trace_pc_valid_o: out std_logic;
trace_eret_o:out std_logic
);
end wrc_lm32;
......@@ -42,6 +57,12 @@ architecture rtl of wrc_lm32 is
I_ACK_I : in std_logic;
I_ERR_I : in std_logic;
I_RTY_I : in std_logic;
J_DAT_I : in std_logic_vector(31 downto 0);
J_ADR_I : in std_logic_vector(31 downto 0);
J_CYC_I : in std_logic;
J_SEL_I : in std_logic_vector(3 downto 0);
J_STB_I : in std_logic;
J_WE_I : in std_logic;
D_DAT_I : in std_logic_vector(31 downto 0);
D_ACK_I : in std_logic;
D_ERR_I : in std_logic;
......@@ -55,6 +76,8 @@ architecture rtl of wrc_lm32 is
I_CTI_O : out std_logic_vector(2 downto 0);
I_LOCK_O : out std_logic;
I_BTE_O : out std_logic_vector(1 downto 0);
J_ACK_O : out std_logic;
J_DAT_O : out std_logic_vector(31 downto 0);
D_DAT_O : out std_logic_vector(31 downto 0);
D_ADR_O : out std_logic_vector(31 downto 0);
D_CYC_O : out std_logic;
......@@ -63,16 +86,20 @@ architecture rtl of wrc_lm32 is
D_WE_O : out std_logic;
D_CTI_O : out std_logic_vector(2 downto 0);
D_LOCK_O : out std_logic;
D_BTE_O : out std_logic_vector(1 downto 0));
D_BTE_O : out std_logic_vector(1 downto 0);
trace_pc_o : out std_logic_vector(31 downto 0);
trace_pc_valid_o : out std_logic;
trace_eret_o: out std_logic);
end component lm32_top;
signal rst : std_logic;
signal iwb_adr_int : std_logic_vector(31 downto 0);
signal dwb_adr_int : std_logic_vector(31 downto 0);
signal jwb_adr_int : std_logic_vector(31 downto 0);
signal irqs_vec : std_logic_vector(31 downto 0);
signal dwb_data_int : std_logic_vector(31 downto 0);
begin
irqs_vec(g_num_irqs-1 downto 0) <= irq_i;
......@@ -90,6 +117,12 @@ begin
I_ACK_I => iwb_ack_i,
I_ERR_I => '0',
I_RTY_I => '0',
J_DAT_I => jwb_dat_i,
J_ADR_I => jwb_adr_int,
J_CYC_I => jwb_cyc_i,
J_SEL_I => jwb_sel_i,
J_STB_I => jwb_stb_i,
J_WE_I => jwb_we_i,
D_DAT_I => dwb_data_int,
D_ACK_I => dwb_ack_i,
D_ERR_I => '0',
......@@ -97,12 +130,14 @@ begin
I_DAT_O => iwb_dat_o,
I_ADR_O => iwb_adr_int,
I_CYC_O => iwb_cyc_o,
I_SEL_O => open,
I_SEL_O => iwb_sel_o,
I_STB_O => iwb_stb_o,
I_WE_O => open,
I_WE_O => iwb_we_o,
I_CTI_O => open,
I_LOCK_O => open,
I_BTE_O => open,
J_DAT_O => jwb_dat_o,
J_ACK_O => jwb_ack_o,
D_DAT_O => dwb_dat_o,
D_ADR_O => dwb_adr_int,
D_CYC_O => dwb_cyc_o,
......@@ -111,11 +146,18 @@ begin
D_WE_O => dwb_we_o,
D_CTI_O => open,
D_LOCK_O => open,
D_BTE_O => open);
D_BTE_O => open,
trace_pc_o => trace_pc_o,
trace_pc_valid_o => trace_pc_valid_o,
trace_eret_o => trace_eret_o);
iwb_adr_o <= iwb_adr_int(g_addr_width+1 downto 2);
dwb_adr_o <= dwb_adr_int(g_addr_width+1 downto 2);
jwb_adr_int(31 downto g_addr_width+2) <= (others => '0');
jwb_adr_int(g_addr_width+1 downto 2) <= jwb_adr_i;
jwb_adr_int(1 downto 0) <= (others => '0');
process(dwb_dat_i)
begin
......
platform/xilinx/chipscope/Manifest.py 0 → 100644
View file @ b2edc7ba
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
platform/xilinx/chipscope/chipscope_icon.ngc 0 → 100644
View file @ b2edc7ba
This diff is collapsed.
platform/xilinx/chipscope/chipscope_ila.ngc 0 → 100644
View file @ b2edc7ba
This diff is collapsed.
syn/spec_1_1/wr_core_demo/Manifest.py 0 → 100644
View file @ b2edc7ba
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_top_wrc.xise"
modules = { "local" : [ "../../../top/spec_1_1/wr_core_demo", "../../../platform/xilinx/chipscope" ] }
testbench/wrc_core/main_tb/Manifest.py 0 → 100644
View file @ b2edc7ba
action = "simulation"
fetchto = "../../../ip_cores"
vlog_opt = "+incdir+../../../sim"
files = [ "main.sv", "wb_gpio_port_notristates.vhd" ]
modules = { "local" : "../../.." };
testbench/wrc_core/main_tb/main.sv 0 → 100644
View file @ b2edc7ba
`timescale 1ns/1ps
`include "if_wishbone.sv"
`include "endpoint_regs.v"
`include "endpoint_mdio.v"
`include "tbi_utils.sv"
`timescale 1ps/1ps
`define EP_QMODE_ACCESS 0
`define EP_QMODE_TRUNK 1
`define EP_QMODE_UNQ 3
// Clock periods (in picoseconds)
const int c_RBCLK_PERIOD = 8001;
const int c_REFCLK_PERIOD = 8000;
`define ADDR_RST_GEN 'h62000
module main;
wire clk_ref;
wire clk_sys;
wire rst_n;
IWishbone WB
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
tbi_clock_rst_gen
#(
.g_rbclk_period(8002))
clkgen(
.clk_ref_o(clk_ref),
.clk_sys_o(clk_sys),
.phy_rbclk_o(phy_rbclk),
.rst_n_o(rst_n)
);
wire clk_sys_dly;
assign #10 clk_sys_dly = clk_sys;
wire [7:0]phy_tx_data ;
wire phy_tx_k ;
wire phy_tx_disparity ;
wire phy_tx_enc_err ;
wire [7:0]phy_rx_data ;
wire phy_rx_rbclk ;
wire phy_rx_k ;
wire phy_rx_enc_err ;
wire [3:0]phy_rx_bitslide ;
wire phy_rst ;
wire phy_loopen;
wr_core #(
.g_simulation (1),
.g_virtual_uart(1),
.g_ep_rxbuf_size_log2 (12),
.g_dpram_initf ("/home/slayer/wrpc-sw/hello.ram"),
.g_dpram_size (16384),
.g_num_gpio (8)
)
DUT (
.clk_sys_i (clk_sys),
.clk_dmtd_i (clk_ref),
.clk_ref_i (clk_ref),
.rst_n_i (rst_n),
.pps_p_o (),
.dac_hpll_load_p1_o (),
.dac_hpll_data_o (),
.dac_dpll_load_p1_o (),
.dac_dpll_data_o (),
.gpio_o (),
.uart_rxd_i (1'b0),
.uart_txd_o (),
.wb_addr_i (WB.adr[17:0]),
.wb_data_i (WB.dat_o),
.wb_data_o (WB.dat_i),
.wb_sel_i (4'b1111),
.wb_we_i (WB.we),
.wb_cyc_i (WB.cyc),
.wb_stb_i (WB.stb),
.wb_ack_o (WB.ack),
.phy_ref_clk_i(clk_ref),
.phy_tx_data_o(phy_tx_data),
.phy_tx_k_o(phy_tx_k),
.phy_tx_disparity_i(phy_tx_disparity),
.phy_tx_enc_err_i(phy_tx_enc_err),
.phy_rx_data_i(phy_rx_data),
.phy_rx_rbclk_i(phy_rx_rbclk),
.phy_rx_k_i(phy_rx_k),
.phy_rx_enc_err_i(phy_rx_enc_err),
.phy_rx_bitslide_i(phy_rx_bitslide),
.phy_rst_o(phy_rst),
.phy_loopen_o(phy_lo),
.genrest_n ()
);
wr_gtp_phy_spartan6
#(
.g_simulation(1),
.g_ch0_use_refclk_out (0),
.g_ch1_use_refclk_out (0)
) PHY
(
.ch0_ref_clk_i(clk_ref),
.ch0_ref_clk_o(),
.ch0_tx_data_i(8'h00),
.ch0_tx_k_i(1'b0),
.ch0_tx_disparity_o(),
.ch0_tx_enc_err_o(),
.ch0_rx_rbclk_o(),
.ch0_rx_data_o(),
.ch0_rx_k_o(),
.ch0_rx_enc_err_o(),
.ch0_rx_bitslide_o(),
.ch0_rst_i(1'b0),
.ch0_loopen_i(1'b0),
.ch1_ref_clk_i(clk_ref),
.ch1_ref_clk_o(),
.ch1_tx_data_i(phy_tx_data),
.ch1_tx_k_i(phy_tx_k),
.ch1_tx_disparity_o(phy_tx_disparity),
.ch1_tx_enc_err_o(phy_tx_enc_err),
.ch1_rx_data_o(phy_rx_data),
.ch1_rx_rbclk_o(phy_rx_rbclk),
.ch1_rx_k_o(phy_rx_k),
.ch1_rx_enc_err_o(phy_rx_enc_err),
.ch1_rx_bitslide_o(phy_rx_bitslide),
.ch1_rst_i(phy_rst),
.ch1_loopen_i(phy_lo),
.pad_txn0_o(),
.pad_txp0_o(),
.pad_rxn0_i(1'b0),
.pad_rxp0_i(1'b0),
.pad_txn1_o(sfp_txn_o),
.pad_txp1_o(sfp_txp_o),
.pad_rxn1_i(sfp_rxn_i),
.pad_rxp1_i(sfp_rxp_i));
assign sfp_rxp_i = sfp_txp_o;
assign sfp_rxn_i = sfp_txn_o;
initial begin
@(posedge rst_n);
repeat(3) @(posedge clk_sys);
WB.write32('h40000, 1);
WB.write32('h40010, 'hdead);
forever begin
reg[31:0] rval;
repeat(100) @(posedge clk_sys);
WB.read32('h40000, rval);
if(rval[3]) begin
WB.read32('h40004, rval);
$display("Got TAG: %d", rval);
end
end
end
endmodule // main
top/spec_1_1/wr_core_demo/Manifest.py 0 → 100644
View file @ b2edc7ba
files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "wb_gpio_port_notristates.vhd"]
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../../"],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
}
top/spec_1_1/wr_core_demo/spec_serial_dac.vhd 0 → 100644
View file @ b2edc7ba
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spec_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8;
g_num_cs_select : integer := 2
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic
);
end spec_serial_dac;
architecture syn of spec_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
begin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(1); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(2); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(3); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(4); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(5); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(6); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(7); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(8); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_reg <= cs_sel_i;
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
gen_cs_out : for i in 0 to g_num_cs_select-1 generate
dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
end generate gen_cs_out;
dac_sclk_o <= iDacClk;
end syn;
top/spec_1_1/wr_core_demo/spec_serial_dac_arb.vhd 0 → 100644
View file @ b2edc7ba
library ieee;
use ieee.std_logic_1164.all;
entity spec_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end spec_serial_dac_arb;
architecture behavioral of spec_serial_dac_arb is
component spec_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer;
g_num_cs_select : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
U_DAC : spec_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits,
g_num_cs_select => 2)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cs_sel_i => dac_cs_sel,
load_i => dac_load,
sclk_divsel_i => "001",
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
dac_cs_sel <= (others => '0');
state <= WAIT_DATA;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when WAIT_DATA =>
if(d1_ready = '1') then
dac_cs_sel <= "01";
dac_data <= d1;
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_cs_sel <= "10";
dac_data <= d2;
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
top/spec_1_1/wr_core_demo/spec_top.ucf 0 → 100644
View file @ b2edc7ba
This diff is collapsed.
top/spec_1_1/wr_core_demo/spec_top.vhd 0 → 100644
View file @ b2edc7ba
This diff is collapsed.
top/spec_1_1/wr_core_demo/wb_gpio_port_notristates.vhd 0 → 100644
View file @ b2edc7ba
------------------------------------------------------------------------------
-- Title : Wishbone GPIO port
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-04-06
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Bidirectional GPIO port of configurable width (1 to 32 bits).
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_gpio_port_notristates is
generic(g_num_pins : natural := 8 -- number of GPIO pins
);
port(
-- System reset, active low
sys_rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
-- GPIO pin vector
gpio_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_dir_o : out std_logic_vector(g_num_pins-1 downto 0)
);
end wb_gpio_port_notristates;
architecture behavioral of wb_gpio_port_notristates is
constant c_GPIO_REG_CODR : std_logic_vector(2 downto 0) := "000"; -- *reg* clear output register
constant c_GPIO_REG_SODR : std_logic_vector(2 downto 0) := "001"; -- *reg* set output register
constant c_GPIO_REG_DDR : std_logic_vector(2 downto 0) := "010"; -- *reg* data direction register
constant c_GPIO_REG_PSR : std_logic_vector(2 downto 0) := "011"; -- *reg* pin state register
signal out_reg, in_reg, dir_reg : std_logic_vector(g_num_pins-1 downto 0);
signal gpio_in_synced : std_logic_vector(g_num_pins-1 downto 0);
signal ack_int : std_logic;
begin
GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
INPUT_SYNC : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => sys_rst_n_i,
clk_i => wb_clk_i,
data_i => gpio_i(i),
synced_o => gpio_in_synced(i),
npulse_o => open
);
end generate GEN_SYNC_FFS;
process (wb_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dir_reg <= (others => '0');
out_reg <= (others => '0');
ack_int <= '0';
wb_data_o(g_num_pins-1 downto 0) <= (others => '0');
elsif rising_edge(wb_clk_i) then
if(ack_int = '1') then
ack_int <= '0';
elsif(wb_cyc_i = '1') and (wb_sel_i = '1') and (wb_stb_i = '1') then
if(wb_we_i = '1') then
case wb_addr_i(2 downto 0) is
when c_GPIO_REG_SODR =>
out_reg <= out_reg or wb_data_i(g_num_pins-1 downto 0);
ack_int <= '1';
when c_GPIO_REG_CODR =>
out_reg <= out_reg and (not wb_data_i(g_num_pins-1 downto 0));
ack_int <= '1';
when c_GPIO_REG_DDR =>
dir_reg <= wb_data_i(g_num_pins-1 downto 0);
ack_int <= '1';
when others =>
ack_int <= '1';
end case;
else
case wb_addr_i(2 downto 0) is
when c_GPIO_REG_DDR =>
wb_data_o(g_num_pins-1 downto 0) <= dir_reg;
ack_int <= '1';
when c_GPIO_REG_PSR =>
wb_data_o(g_num_pins-1 downto 0) <= gpio_in_synced;
ack_int <= '1';
when others =>
ack_int <= '1';
end case;
end if;
else
ack_int <= '0';
end if;
end if;
end process;
gpio_dir_o <= dir_reg;
gpio_o <= out_reg;
wb_ack_o <= ack_int;
end behavioral;
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