added GSI'S Scalable Control Unit demo design (initial commit)

9dfd9435 · Tomasz Wlostowski · 5d852cc7 · 9dfd9435 · 9dfd9435 · 9dfd9435
Commit 9dfd9435 authored Feb 10, 2012 by Tomasz Wlostowski
6 changed files
--- a/syn/gsi_scu/wr_core_demo/Manifest.py
+++ b/syn/gsi_scu/wr_core_demo/Manifest.py
+target = "altera"
+action = "synthesis"
+
+fetchto = "../../../ip_cores"
+
+syn_device = "ep2agx125ef"
+syn_grade = "c5"
+syn_package = "29"
+syn_top = "exploder_ng"
+syn_project = "exploder_ng"
+
+modules = {"local" : [ "../../../", "../../../top/gsi_scu/wr_core_demo"]}
+
+				 
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--- a/syn/gsi_scu/wr_core_demo/exploder_ng.qsf
+++ b/syn/gsi_scu/wr_core_demo/exploder_ng.qsf
--- a/top/gsi_scu/wr_core_demo/Manifest.py
+++ b/top/gsi_scu/wr_core_demo/Manifest.py
+modules = {"local" : "../../../modules/mini_bone"}
+files = ["exploder_ng.vhd", "pow_reset.vhd"]
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--- a/top/gsi_scu/wr_core_demo/exploder_ng.vhd
+++ b/top/gsi_scu/wr_core_demo/exploder_ng.vhd
--- a/top/gsi_scu/wr_core_demo/pow_reset.vhd
+++ b/top/gsi_scu/wr_core_demo/pow_reset.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pow_reset is
+  port (
+    clk    : in  std_logic;             -- 125Mhz
+    nreset : buffer std_logic
+    );
+end entity;
+
+architecture pow_reset_arch of pow_reset is
+  
+  signal powerOn : unsigned(6 downto 0) := "0000000";  -- 7Bit for 1ms nrst
+  
+begin
+     
+     nres : process(Clk)
+     begin
+       if Clk'event and Clk = '1' then
+         if nreset = '0' then
+           powerOn <= powerOn + 1;
+       end if;
+
+       nReset <= std_logic(powerOn(powerON'high));
+     end if;
+end process;
+
+end architecture;
+
--- a/top/readme_platforms.txt
+++ b/top/readme_platforms.txt
+Available device plaftorms (so far):
+------------------------------------
+
+gsi_scu - GSI's Scalable Control Unit (SCU), based on Altera ArriaII-GX (EP2AGX125)
+spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
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